CN114664728A - Method for forming semiconductor structure - Google Patents

Abstract

A method for forming a semiconductor structure, the method comprising: carrying out ion doping on the core layer of the second area, wherein the ion doping is suitable for improving the etching resistance of the core layer, and the core layer positioned in the second area is used as an etching resistance layer; forming a first groove penetrating through at least part of the core layer of the first area along the first direction, and reserving part of the core layer of the first area on two sides of the first groove in the second direction to be used as a sacrificial layer; forming a side wall on the side wall of the first groove, so that the side wall positioned on the side wall of the first groove is encircled to form a first groove; removing the sacrificial layer and forming a second groove in the anti-etching layer; a dividing layer extending along the second direction is formed in any one or two of the first groove and the second groove, and the dividing layer divides the corresponding groove along the first direction; and etching the target layer below the first groove and the second groove by taking the anti-etching layer, the side wall and the partition layer as masks to form a target pattern. The embodiment of the invention is beneficial to further compressing the pitch between the target graphics.

Description

Method for forming semiconductor structure

Technical Field

The embodiment of the invention relates to the field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure.

Background

With the rapid growth of the semiconductor Integrated Circuit (IC) industry, semiconductor technology is driven by moore's law to move towards smaller process nodes, so that the Integrated circuit is developed towards smaller size, higher circuit precision and higher circuit complexity.

In the course of integrated circuit development, as functional density (i.e., the number of interconnect structures per chip) generally increases, the geometric size (i.e., the minimum component size that can be produced by the process steps) also decreases, which correspondingly increases the difficulty and complexity of integrated circuit fabrication.

At present, with the shrinking of technology nodes, it is a challenge how to improve the matching between the pattern formed on the wafer and the target pattern.

Disclosure of Invention

Embodiments of the present invention provide a method for forming a semiconductor structure, which further compresses a pitch between target patterns.

To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate comprising a target layer for forming a target pattern; forming a core layer on the substrate, including a first region and a second region surrounding the first region; carrying out first ion doping on the core layer of the second region, wherein the first ion doping is suitable for improving the etching resistance of the core layer, and the core layer which is positioned in the second region and doped with ions is used as an etching resistance layer; forming a first groove penetrating through at least part of the core layer of the first area along a first direction, wherein the direction perpendicular to the first direction is a second direction, and in the second direction, part of the core layer of the first area is reserved on two sides of the first groove and is used as a sacrificial layer; forming a side wall on the side wall of the first groove, so that the side wall positioned on the side wall of the first groove is surrounded into a first groove; after first ion doping is carried out and the side wall is formed, the sacrificial layer is removed, and a second groove is formed in the anti-etching layer; a dividing layer extending along the second direction is formed in any one or two of the first groove and the second groove, and the dividing layer divides the corresponding groove along the first direction; and etching the target layer below the first groove and the second groove by taking the anti-etching layer, the side wall and the partition layer as masks to form a target pattern.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:

in the method for forming a semiconductor structure provided by the embodiment of the present invention, a core layer of the second region is doped with first ions, which is suitable for improving the etching resistance of the core layer, the core layer doped with ions in the second region serves as an anti-etching layer, and in the step of forming the first trench, part of the core layer of the first region is retained on two sides of the first trench in the second direction to serve as a sacrificial layer, that is, the first region crosses the first trench in the second direction, and a side wall is formed on a side wall of the first trench, so that the side wall on the side wall of the first trench encloses a first groove, and the second groove formed by removing the sacrificial layer is correspondingly located on two sides of the first groove; compared with the size of the second groove, the size of the first area is larger, which is easy to meet the requirement of the photoetching process condition, and the part of the first area, which is overlapped with the first groove, is removed for defining the shape and the size of the second groove, so that the embodiment of the invention utilizes the superposition of the first area pattern and the first groove pattern to enable the second groove to achieve smaller size, the space (space) between the second groove and the first groove is defined by the thickness of the side wall, the first groove and the second groove are easy to meet the designed minimum space, and further, under the limit condition that the photoetching process is not changed, the invention is beneficial to enabling the target pattern to achieve smaller critical size, and further compressing the pitch (pitch) between the target patterns to meet the requirements of high density and high integration degree of the integrated circuit, and small change of the existing process, The process complexity is low, and the photoetching process friendliness is high. In addition, a dividing layer extending along the second direction is formed in any one or two of the first groove and the second groove, and the dividing layer divides the corresponding grooves along the first direction, so that a smaller distance is realized between adjacent grooves along the first direction, and further, the target pattern can be favorably realized at a Head To Head (HTH) position by a smaller line end distance, and the design freedom of the target pattern is improved.

Drawings

Fig. 1 to 20 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure according to an embodiment of the present invention;

FIGS. 21-22 are top views of steps in another embodiment of a method for forming a semiconductor structure of the present invention;

FIGS. 23-24 are top views of steps in a method of forming a semiconductor structure in accordance with another embodiment of the present invention;

fig. 25 to 27 are top views corresponding to steps in yet another embodiment of a method for forming a semiconductor structure according to the present invention.

Detailed Description

As can be seen from the background art, it is a challenge to improve the matching between the pattern formed on the wafer and the target pattern while the technology nodes are being scaled down.

In order to solve the technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, which is beneficial to implementing a smaller critical dimension of a target pattern and further compressing a pitch between the target patterns without changing a limit condition of a photolithography process, so as to meet requirements of high density and high integration of an integrated circuit, and has the advantages of small change of an existing process, low process complexity, and high photolithography process friendliness. In addition, a dividing layer extending along the second direction is formed in any one or two of the first groove and the second groove, and the dividing layer divides the corresponding grooves along the first direction, so that a smaller distance is realized between the adjacent grooves along the first direction, and further, the target pattern is beneficial to realizing a smaller line end distance at the head-to-head position, and the design freedom degree of the target pattern is improved.

In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below. Fig. 1 to 20 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.

Referring to fig. 1, fig. 1a is a top view, and fig. 1b is a cross-sectional view taken along line y1-y1 of fig. 1a, providing a substrate 200 including a target layer 100 for forming a target pattern. The target layer 100 is a film layer to be patterned to form a target pattern. The target pattern may be a gate structure, an interconnection trench in a back-end process, a fin in a fin field effect transistor (FinFET), a channel stack in a Gate All Around (GAA) transistor or a fork gate transistor (forkheet), a Hard Mask (HM) layer, or the like.

In this embodiment, the target layer 100 is a dielectric layer and the target pattern is an interconnect trench. And patterning the dielectric layer to form a plurality of interconnection grooves, and forming metal interconnection lines in the interconnection grooves, wherein the dielectric layer is used for realizing the electrical isolation among the metal interconnection lines. Thus, the dielectric layer is an inter-metal dielectric (IMD) layer.

The base 200 also includes a substrate 110 at the bottom of the target layer 100. In this embodiment, the substrate 200 further includes a hard mask material layer 115 on the target layer 100.

With continued reference to fig. 1, a core layer 120 is formed on a substrate 200, the core layer 120 including a first region 120a, and a second region 120b surrounding the first region 120 a. Subsequently, the core layer 120 in the second region 120b is doped with the first ions, which is suitable for improving the etching resistance of the core layer 120, and the core layer 120 doped with the ions in the second region 120b is used as an etching resistance layer.

The material of the core layer 120 includes one or more of amorphous silicon, polysilicon, silicon oxide, amorphous carbon, silicon nitride, amorphous germanium, silicon oxynitride, carbon nitride, silicon carbide, silicon carbonitride and silicon oxycarbonitride. In this embodiment, the material of the core layer 120 is amorphous silicon.

The present embodiment illustrates only one first region 120a for convenience of illustration and description. However, the shape, position, and number of the first regions 120a are not limited thereto. For example: in other embodiments, the number of the first areas may also be multiple and arranged along the second direction, and the multiple first areas are separated from each other.

Referring to fig. 2 to 4, the core layer 120 of the second region 120b is doped with first ions, which is suitable for improving the etching resistance of the core layer 120, and the ion-doped core layer 120 located in the second region 120b serves as an etching resistance layer 130. The etch resist layer 130 is used as a mask for subsequent patterning of the target layer 100.

After the subsequent formation of the first trench penetrating at least a portion of the core layer 120 of the first region 120a along the first direction, the core layer 120 of the first region 120a remains to serve as a sacrificial layer for occupying a spatial position for forming the second recess. The subsequent process further comprises: and forming a side wall on the side wall of the first groove, so that the side wall positioned on the side wall of the first groove is encircled to form a first groove.

The core layer 120 is doped with the first ions to form the anti-etching layer 130, so that patterning of the core layer 120 is achieved, the first ion doping is suitable for improving the etching resistance of the core layer 120, so that the etching resistance of the anti-etching layer 130 is greater than that of the core layer 120 not doped with the ions, a higher etching selection ratio exists between the core layer 120 not doped with the ions and the anti-etching layer 130, a first groove is formed subsequently, the core layer 120 of the remaining first region 120a serves as a sacrificial layer, accordingly, in the step of removing the sacrificial layer to form a second groove subsequently, the probability of causing false etching of the anti-etching layer 130 is low, reduction of probability of causing double etching (double etching) to the first groove is facilitated, the patterning precision of the first groove is guaranteed, and the anti-etching layer 130 can be reserved as a mask of the patterning target layer 100.

In this embodiment, the anti-etching layer 130 surrounds the core layer 120 of the first region 120 a. In this embodiment, the ions subjected to the first ion doping include one or more of boron ions, phosphorus ions, and argon ions.

In this embodiment, the etching selectivity between the undoped ion core layer 120 and the anti-etching layer 130 is at least 20: 1, the core layer 120 and the anti-etching layer 130, which are not doped with ions, have a high etching selectivity ratio, which is beneficial to significantly preventing the subsequent sacrificial layer removing process from causing the mis-etching of the anti-etching layer 130.

As an example, after the core layer 120 is formed, and before the first trench is formed, the core layer 120 of the second region 120b is first ion-doped. However, the step of first ion doping the core layer 120 of the second region 120b is not limited thereto. In other embodiments, the first ion doping may be performed on the core layer in the second region after the first trench is formed and before the side wall is formed. In other embodiments, the first ion doping may be performed on the core layer in the second region after the sidewall is formed and before the sacrificial layer is removed.

In this embodiment, the step of performing the first ion doping on the core layer 120 of the second region 120b includes:

as shown in fig. 2, fig. 2a is a top view, and fig. 2b is a cross-sectional view taken along line y1-y1 in fig. 2a, wherein a shielding layer 150 is formed on the core layer 120 in the first region 120a, and the shielding layer 150 exposes the second region 120 b. The blocking layer 150 is used as a mask for first ion doping of the core layer 120, and the blocking layer 150 correspondingly defines the shape and position of the anti-etching layer 130. In this embodiment, the blocking layer 150 includes a first planarizing layer 151 and a first patterning layer 152 on the first planarizing layer 151.

The first planarizing layer 151 serves to provide a flat surface for forming the first patterning layer 152, thereby improving the accuracy of pattern transfer. In this embodiment, the first planarizing layer 151 is made of Spin-On Carbon (SOC). The first patterning layer 152 is used as an etch mask for forming the first planarization layer 151, and the first patterning layer 152 defines the shapes and positions of the sacrificial layer 140 and the etch-resistant layer 130, respectively. In this embodiment, the material of the first patterned layer 152 is photoresist.

As shown in fig. 3, fig. 3a is a top view, and fig. 3b is a cross-sectional view taken along a cut line y1-y1 in fig. 3a, wherein the core layer 120 is first ion-doped using the shielding layer 150 as a mask. In this embodiment, an ion implantation process is used to perform the first ion doping. As shown in FIG. 4, FIG. 4a is a top view, and FIG. 4b is a cross-sectional view taken along line y1-y1 in FIG. 4a, with the masking layer 150 removed. The barrier layer 150 is removed by one or both of an ashing process and a wet stripping process.

Referring to fig. 5 to 8, a first trench 180 penetrating at least a portion of the core layer 120 of the first region 120a along a first direction (as shown in an X direction in fig. 7 a) is formed, and a direction perpendicular to the first direction is a second direction (as shown in a Y direction in fig. 7 b), in which a portion of the core layer 120 of the first region 120a remains on both sides of the first trench 180 to serve as the sacrificial layer 140.

In the second direction, the core layer 120 of a part of the first region 120a is left on two sides of the first trench 120 and is used as the sacrificial layer 140, that is, the first region 120a crosses the first trench 180 along the second direction, then a sidewall is formed on the sidewall of the first trench 180, so that the sidewall on the sidewall of the first trench 180 encloses a first groove, in the subsequent step of removing the sacrificial layer 140 to form a second groove, the second groove is correspondingly located on two sides of the first groove, and the first groove and the second groove are isolated by the sidewall.

Compared with the size of the second groove, the size of the first region 120a is larger, which is easy to meet the requirement of the photolithography process condition, and the part of the first region 120a except the overlapping region with the first groove 180, i.e. the sacrificial layer 140, is used to define the shape and size of the second groove, so that the superposition of the first region 120a pattern and the first groove 180 pattern is utilized to realize the smaller size of the second groove, and the interval between the second groove and the first groove is defined by the thickness of the sidewall, the minimum interval between the first groove and the second groove is easy to meet the design, thereby being capable of facilitating the target pattern to realize smaller critical dimension and further compressing the pitch between the target patterns without changing the limit condition of the photolithography process, so as to meet the requirement of high density and high integration degree of the integrated circuit, and having small change to the existing process and low process complexity, the photoetching process has high friendliness.

In this embodiment, the first groove 180 includes a first sidewall 181 along the second direction, and a second sidewall 182 opposite to the first sidewall 181 and parallel to the first sidewall 181.

In the present embodiment, the first groove 180 penetrates the core layer 120 of the first region 120a in the first direction; alternatively, in the first direction, the first trench 180 penetrates through the core layer 120 of the first region 120a, and either one or both of the first and second sidewalls 181 and 182 further extend to be located in the core layer 120 (i.e., the etch resist layer 130) of the adjacent second region 120 b. Therefore, in the embodiment, the core layers 120 of the first regions 120a located at two sides of the first trench 180 are spaced apart, that is, the sacrificial layers 140 located at two sides of the first trench 180 are spaced apart, and the second recesses formed by removing the sacrificial layers 140 are also spaced apart.

As an example, the first trench 180 penetrates the core layer 120 of the first region 120a along the first direction, and the first sidewall 181 and the second sidewall 182 both extend to be located in the core layer 120 (i.e., the etch resist layer 130) of the adjacent second region 120b, i.e., the end of the first trench 180 protrudes out of the first region 120a along the first direction. After the sacrificial layer 140 is subsequently removed to form a second groove, the end portion of the first groove protrudes out of the second groove along the first direction.

For convenience of illustration and explanation, the present embodiment illustrates only one first region 120a and one first groove 180 penetrating at least a portion of the core layer 120 of the first region 120a in the first direction. However, the shape, position, and number of the first regions 120a and the positional relationship with the first grooves 180 are not limited thereto.

As an example, the number of the first regions is plural and is arranged in the second direction, the plural first regions are separated from each other, the first grooves may be formed only in a part of the number of the core layers of the first regions, and the first grooves may not be formed in the remaining number of the core layers of the first regions. In other embodiments, the first grooves may be formed in all the core layers of the first region according to actual design requirements.

For convenience of illustration and description, the present embodiment only illustrates the first region 120a, the second region 120b and the first trench 180, and does not illustrate the pattern structure around the first region 120 a. It should be understood that in actual process, the first region 120a and the first trench 180 may not be independent patterns, and other pattern structures may be disposed around the first region 120a according to design requirements, for example: as shown in fig. 8, a second groove 185 may be further formed along one or both sides of the second direction first region 120 a. In the subsequent step of forming the sidewall on the sidewall of the first trench 180, the sidewall is further formed on the sidewall of the second trench 185, and the sidewall on the sidewall of the second trench 185 encloses a third groove, which is also used for defining the pattern of the target pattern.

In this embodiment, the step of forming the first trench 180 includes: as shown in fig. 5, fig. 5a is a top view, and fig. 5b is a cross-sectional view taken along line y1-y1 in fig. 5a, a mask layer 160 is formed on the core layer 120, the mask layer 160 having a mask opening 170 therein extending in a first direction (shown as X in fig. 5 a); on a projection plane parallel to the substrate 200, the first region 120a spans the mask opening 170 in a second direction (shown as Y-direction in fig. 5 b); as shown in fig. 6, fig. 6a is a top view, and fig. 6b is a cross-sectional view taken along line y1-y1 of fig. 6a, wherein the core layer 120 under the mask opening 170 is removed by using the mask layer 160 as a mask to form a first trench 180; as shown in fig. 7, fig. 7a is a top view, and fig. 7b is a cross-sectional view taken along line y1-y1 of fig. 7a, where masking layer 160 is removed.

The mask layer 160 is used as an etch mask for forming the first trench. The mask opening 170 is used to define the shape and location of the first trench. Before forming the mask layer 160, the method further includes: a second planarization layer 161 and an anti-reflection coating layer 162 are formed on the core layer 120, which are sequentially stacked. The second planarization layer 161 is used to provide a flat top surface for forming the mask layer 160 to improve the pattern accuracy of the mask opening 170. The anti-reflective coating 162 serves to reduce the effects of reflection upon exposure.

In this embodiment, the core layer 120 below the mask opening 170 is removed by using the mask layer 160 as a mask and using a dry etching process (e.g., an anisotropic dry etching process), which is beneficial to improving the precision of pattern transfer and the quality of the profile of the first trench 180.

The mask layer 160 is removed to facilitate subsequent process steps. In the step of removing the mask layer 160, the anti-reflection coating layer 162 and the second planarization layer 161 are also removed.

Referring to fig. 9 to 10, in the present embodiment, after the first trenches 180 are formed and before the sacrificial layer 140 is removed, the second division layer 145 (as shown in fig. 10) extending in the second direction is formed in the sacrificial layer 140, and the second division layer 145 divides the sacrificial layer 140 in the first direction.

By forming the second dividing layer 145, the second dividing layer 145 is formed in the second groove formed by subsequently removing the sacrificial layer 140, the second dividing layer 145 extends along the second direction, and the second groove is divided along the first direction, so that a smaller distance is realized between the second grooves along the first direction, a smaller line end distance is favorably realized at the head-to-head position of the target pattern, and the design freedom of the target pattern is improved.

In this embodiment, the step of forming the second division layer 145 includes:

as shown in fig. 9, fig. 9a is a top view, and fig. 9b is a cross-sectional view taken along line y1-y1 in fig. 9a, a division mask layer 146 is formed on the core layer 120 (i.e., the etch resist layer 130) in the second region 120b, a division groove 143 is formed in the division mask layer 146, the division groove 143 crosses the first region 120a along the second direction, and the sacrificial layer 140 with a partial width is exposed. The division mask layer 146 is used as a mask for forming a second division layer. Specifically, in the present embodiment, the division mask layer 146 is used as a mask for ion doping the sacrificial layer 140 to form the second division layer. The dividing groove 143 is used to define the pattern and position of the second division layer.

In this embodiment, the division mask layer 146 includes a third planarization layer 141 and a third patterning layer 142 on the third planarization layer 141.

As shown in fig. 10, the sacrificial layer 140 exposed by the dividing groove 143 is doped with second ions by using the dividing mask layer 146 as a mask, which is suitable for improving the etching resistance of the sacrificial layer 140, and the sacrificial layer 140 doped with ions is used as the second dividing layer 145. In this embodiment, the ions for doping the second ions into the sacrificial layer 140 are the same as the ions for doping the first ions, which is beneficial to improving the process compatibility. Specifically, the ions that second ion-dope the sacrificial layer 140 include one or more of boron ions, phosphorus ions, and argon ions. Therefore, in the present embodiment, the material of the second division layer 145 is the same as the material of the etch resist layer 130.

Fig. 10a is a top view, and fig. 10b is a cross-sectional view taken along a line y1-y1 of fig. 10a, where the division mask layer 146 is removed. The process of removing the division mask layer 146 includes one or both of ashing and wet stripping processes.

The subsequent steps further comprise: and forming a side wall on the side wall of the first trench, and correspondingly, in other embodiments, forming a second division layer in the step of forming the side wall. Specifically, in other embodiments, the forming method further comprises: after the core layer is formed and before the side wall is formed, forming a blocking groove penetrating through the core layer of the first region along the second direction, wherein the blocking groove divides the core layer at two sides along the first direction; the step of forming the second divided layer includes: in the step of forming the side wall, the side wall is further filled in the blocking groove, and the side wall in the blocking groove is used as a second division layer. The blocking groove is formed firstly, and then the side wall is filled in the blocking groove to form the second division layer, so that the process is simplified, and the process compatibility is improved.

Referring to fig. 11, fig. 11a is a top view, and fig. 11b is a cross-sectional view taken along line y2-y2 in fig. 11a, wherein a sidewall 190 is formed on the sidewall of the first trench 180, such that the sidewall 190 at the sidewall of the first trench 180 encloses the first recess 210. The first groove 210 is used to define a portion of the pattern of the target pattern. In this embodiment, the shape and position of the first groove 210 are defined by the first trench 180 and the sidewall 190, which is beneficial to making the first groove 210 have a smaller size.

The sidewall spacers 190 are made of a material having an etching selectivity with the sacrificial layer 140, the anti-etching layer 130 and the target layer 100, and the material of the sidewall spacers 190 includes one or more of titanium oxide, silicon nitride, silicon carbide, silicon oxycarbide, aluminum oxide and amorphous silicon.

In this embodiment, the sidewall 190 is formed by using an atomic layer deposition process, which is beneficial to improving the thickness uniformity of the sidewall 190 and is easy to accurately control the thickness of the sidewall 190. The ald process has a high step coverage capability, and therefore, in this embodiment, the sidewall spacers 190 are further formed on the top surfaces of the anti-etching layer 130 and the sacrificial layer 140, and the bottom surface of the first trench 180.

In this embodiment, the following steps further include: a first division layer is formed in the first groove 210, the first division layer extends along the second direction, and the first division layer contacts with a sidewall of the first groove 210. The first division layer divides the first groove 210 in the first direction.

In the embodiment, the step of forming the first dividing layer includes the steps of forming the dividing material layer and removing the dividing material layer higher than the top surface of the sacrificial layer 140, and the sidewall 190 on the top surfaces of the anti-etching layer 130 and the sacrificial layer 140 and the bottom surface of the first trench 180 is retained, so that in the process of subsequently etching back the dividing material layer to form the first dividing layer, the sidewall 190 on the top surfaces of the anti-etching layer 130 and the sacrificial layer 140 can temporarily define the position where etching stops, so as to reduce the probability that the anti-etching layer can cause false etching on the sacrificial layer 130 and the sacrificial layer 140, and the process of etching back the dividing material layer only needs to have an etching selection ratio between the dividing material layer and the sidewall 190, which is beneficial to reducing the process difficulty of etching back the dividing material layer to form the first dividing layer.

In other embodiments, after forming the sidewalls on the top surfaces of the etch-resistant layer and the sacrificial layer, and the sidewalls and the bottom surface of the first trench, the forming method may further include: and removing the side walls on the top surfaces of the anti-etching layer and the sacrificial layer and the bottom surface of the first groove, so that only the side walls on the side walls of the first groove are reserved.

Referring to fig. 12 to 14, a first division layer 215 extending in the second direction is formed in the first groove 210, the first division layer 215 is in contact with a sidewall of the first groove 210, and divides the first groove 210 in the first direction. In this embodiment, the first dividing layer 215 divides the first grooves 210 along the first direction, so that a smaller distance is realized between adjacent first grooves 210 along the first direction, which is further beneficial to realizing a smaller line end distance of the target pattern at the head-to-head position, and improving the design freedom of the target pattern.

In this embodiment, the first dividing layer 215 is selected to have an etching selectivity with the sacrificial layer 140, so that the first dividing layer 215 can be remained in the subsequent process of removing the sacrificial layer 140. Specifically, the material of the first division layer 215 includes one or more of silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, titanium oxide, titanium nitride, silicon carbide, silicon oxycarbide, and amorphous silicon. In this embodiment, after the first recess 210 is formed and before the sacrificial layer 140 is removed, the first division layer 215 is formed.

In this embodiment, the step of forming the first split layer 215 includes:

referring to fig. 12, in which fig. 12a is a top view and fig. 12b is a cross-sectional view taken along line y2-y2 in fig. 12a, a support layer 213 is formed on the core layer 120 (i.e., the etch resist layer 130) and the sacrificial layer 140 in the second region 120 b. The support layer 213 is used for forming the cutting opening later, and after the cutting opening is formed, the support layer 213 is used for providing a support function for forming the first division layer in the cutting opening.

After the first division layer is formed, the supporting layer 213 is also removed, and therefore, the supporting layer 213 is made of a material that is easily removed, so that the difficulty in removing the supporting layer 213 is reduced. Specifically, the material of the supporting layer 213 may further include one or more of SOC, Organic Dielectric Layer (ODL), bottom Anti-reflective Coating (boa), Silicon Anti-reflective Coating (Si-ARC), Deep ultraviolet absorbing Oxide (DUO), Dielectric Anti-reflective Coating (DARC), and Advanced Patterning Film (APF). In this embodiment, the support layer 213 includes a fourth planarizing layer 211 and a fourth patterning layer 212 on the fourth planarizing layer 211.

As shown in fig. 12, a cutting opening 216 is formed in the support layer 213, the cutting opening 216 crosses the first groove 210 in the second direction, and exposes a part of the width of the first groove 210. The cutting openings 216 are used to define the size, shape and location of the first segmentation layer. In this embodiment, the supporting layer 213 is etched by an anisotropic dry etching process to form the cutting opening 216. The anisotropic dry etching process has the characteristic of anisotropic etching, that is, the longitudinal etching rate is greater than the transverse etching rate, which is beneficial to improving the profile controllability of the cut opening 216, so that the opening size and the profile morphology of the cut opening 216 meet the process requirements, and further beneficial to improving the size precision and the profile morphology quality of the subsequent first segmentation layer.

As shown in fig. 13 to 14, the first divided layer 215 is formed in the cut opening 216.

Specifically, the step of forming the first divided layer 215 includes: as shown in fig. 13, the material layer 217 is fully filled in the cut opening 216, and the material layer 217 is further covered on the support layer 213; as shown in fig. 14, fig. 14a is a top view, and fig. 14b is a cross-sectional view taken along the line y2-y2 in fig. 14a, wherein the dividing material layer 217 above the top surface of the sacrificial layer 140 is removed, and the dividing material layer 217 in the first groove 210 is left to serve as the first dividing layer 215.

In this embodiment, the process of forming the dividing material layer 217 includes one or two of a chemical vapor deposition process, an atomic layer deposition process, and a spin coating process. The gap filling capability of the process for forming the dividing material layer 217 is strong, which is beneficial to improving the filling quality of the dividing material layer 217 in the cutting opening 216, and reducing the probability of generating defects such as voids in the dividing material layer 217, thereby improving the appearance quality of the first dividing layer 215 and ensuring the dividing effect of the first dividing layer 215 on the first groove 210.

In this embodiment, in the process of removing the dividing material layer 217 higher than the top surface of the sacrificial layer 140, the sidewall 190 on the top surfaces of the sacrificial layer 140 and the anti-etching layer 130 is used to define the position where the etching is stopped, and the process of etching back the dividing material layer 217 only needs to have an etching selection ratio for the dividing material layer 217 and the sidewall 190, which is beneficial to reducing the process difficulty of removing the dividing material layer 217 higher than the top surface of the sacrificial layer 140.

As shown in fig. 14, the support layer 213 is removed. The process of removing the support layer 213 includes one or both of a dry etching process and a wet etching process. In this embodiment, after the first partition layer 215 is formed, the sidewall spacers 190 on the top surfaces of the sacrificial layer 140 and the anti-etching layer 130 and the bottom surface of the first groove 210 are exposed.

Referring to fig. 15, fig. 15a is a top view, fig. 15b is a cross-sectional view taken along line y2-y2 in fig. 15a, in this embodiment, the forming method further includes: after the first division layer 215 is formed, the sidewall spacers 190 on the top surfaces of the sacrificial layer 140 and the anti-etching layer 130 and the bottom surface of the first recess 210 are removed, so as to expose the top surfaces of the sacrificial layer 140 and the anti-etching layer 130 and the bottom surface of the first recess 210, thereby facilitating the subsequent removal of the sacrificial layer 140 and the patterning target layer 100. Note that the sidewall spacers 190 at the bottom of the first split layer 215 are retained by the covering effect of the first split layer 215.

Specifically, in this embodiment, an anisotropic dry etching process is used to remove the sidewall spacers 190 on the top surfaces of the sacrificial layer 140 and the anti-etching layer 130 and the bottom surface of the first groove 210. The anisotropic dry etching process has an anisotropic etching characteristic, that is, the longitudinal etching rate is greater than the lateral etching rate, so that the lateral etching of the sidewall 190 of the sidewall of the first groove 210 is reduced while the top surfaces of the sacrificial layer 140 and the anti-etching layer 130 and the sidewall 190 of the bottom surface of the first groove 210 are removed, so that the sidewall 190 of the sidewall of the first groove 210 can be retained, thereby ensuring that the sidewall 190 serves as a mask for patterning the target layer 100 and realizing a spacing effect between the first groove 210 and the second groove.

Referring to fig. 16 to 17, fig. 16 is a top view, fig. 17a is a cross-sectional view taken along the line y2-y2 in fig. 16, and fig. 17b is a cross-sectional view taken along the line y3-y3 in fig. 16. after the first ion doping and the formation of the spacers 190, the sacrificial layer 140 is removed, and a second recess 220 is formed in the anti-etching layer 130.

The second grooves 220 are respectively located at both sides of the first groove 210. The second groove 220 and the first groove 210 together define a pattern of a target pattern. The second groove 220 and the first groove 210 are isolated by the sidewall 190, so that the minimum designed interval between the second groove 220 and the first groove 210 is easily met. In this embodiment, the end of the first groove 210 protrudes out of the second groove 220 along the first direction, the second groove 220 is located at two sides of the first groove 210, and the second grooves 220 are spaced apart from each other.

In this embodiment, the sacrificial layer 140 and the anti-etching layer 130 have a higher etching selectivity, and in the step of removing the sacrificial layer 140 to form the second groove 220, the first groove 210 is not easily subjected to double etching, so that the process risk is correspondingly reduced, and the pattern precision of the first groove 210 is ensured.

In one or both of the first groove 210 and the second groove 220, a dividing layer extending in the second direction is formed, and the dividing layer divides the corresponding groove in the first direction. The corresponding grooves are divided along the first direction by the dividing layer, so that a smaller distance can be realized between adjacent grooves along the first direction, the target graph is beneficial to realizing a smaller line end distance at the head-to-head position, and the design freedom of the target graph is improved.

As an example, the first groove 210 has the first division layer 215 formed therein, the first division layer 215 extends in the second direction, and the first division layer 215 is in contact with a sidewall of the first groove 210. As an example, the second groove 220 has the second division layer 145 formed therein, the second division layer 145 extends in the second direction, and divides the second groove 220 in the first direction. In other embodiments, a dividing layer is formed in any one of the first groove and the second groove.

The process of removing the sacrificial layer 140 includes one or both of wet etching and dry etching. As an example, the sacrificial layer 140 is removed using a wet etching process. In this embodiment, the etching solution for wet etching includes a TMAH solution (tetramethylammonium hydroxide solution), an SC1 solution, or an SC2 solution. SC1 solution refers to NH₄OH and H₂O₂The SC2 solution refers to HCl and H₂O₂The mixed solution of (1).

Referring to fig. 18 to 19, fig. 18 is a top view, fig. 19a is a cross-sectional view taken along a line y2-y2 in fig. 18, and fig. 19b is a cross-sectional view taken along a line y3-y3 in fig. 18. with the etch-resistant layer 130 and the sidewall spacers 190 and the split layer as masks, the target layer 100 under the first recess 210 and the second recess 220 is etched to form the target pattern 230.

Specifically, in the present embodiment, the target layer 100 under the first recess 210 and the second recess 220 is etched using the anti-etching layer 130 and the sidewall spacers 190, and the first dividing layer 215 and the second dividing layer 145 as masks.

In the embodiment, the superposition of the first region 120a pattern and the first trench 180 pattern is utilized to define the pattern of the second groove 220, so that the second groove 220 can realize a smaller size, and the minimum design interval between the second groove 220 and the first groove 210 is easily met, and further, under the limit condition of not changing the photolithography process, the target pattern 230 can realize a smaller critical size and further compress the pitch between the target patterns 230, so as to meet the requirements of high density and high integration of an integrated circuit.

In addition, the corresponding grooves are divided along the first direction by the dividing layer, so that a smaller distance can be realized between the adjacent grooves along the first direction, the target graph is beneficial to realizing a smaller line end distance at the head-to-head position, and the design freedom of the target graph is improved.

In this embodiment, the target layer 100 is a dielectric layer, and the anti-etching layer 130, the sidewall spacers 190 and the partition layer are used as masks, and the dielectric layer under the first recess 210 and the second recess 220 is etched to form the interconnect trench 30. The target pattern 230 corresponds to the interconnection groove 30 for providing a space for forming a metal interconnection line.

Specifically, the hard mask material layer 115 under the first groove 210 and the second groove 220 is etched by taking the anti-etching layer 130, the side wall 190 and the partition layer as masks, so as to form a hard mask layer 105; the dielectric layer is patterned to form the interconnect trench 30 using the hard mask layer 105 as a mask. In this embodiment, in the step of etching the target layer 100 under the first recess 210 and the second recess 220, the anti-etching layer 130, the sidewall spacers 190, and the partition layer are also consumed by a portion of the thickness.

Referring to fig. 20, a metal interconnection line 240 is formed in the interconnection groove 30. The metal interconnect lines 240 are used to electrically connect the semiconductor structure to external circuitry or other interconnect structures.

In this embodiment, the interconnection grooves 30 can realize a smaller critical dimension, and the pitch between the interconnection grooves 30 is further compressed, which is beneficial to further compressing the pitch of the metal interconnection lines 240, so as to meet the requirements of high density and high integration of the integrated circuit, and moreover, the interconnection grooves 30 easily meet the requirement of designing the minimum spacing, the pattern precision of the interconnection grooves 30 is higher, which is correspondingly beneficial to meeting the requirement of designing the minimum spacing between the metal interconnection lines 240 and improving the pattern precision of the metal interconnection lines 240, thereby improving the performance of the semiconductor structure. In addition, the interconnection groove 30 can achieve a smaller line end distance at the head-to-head position, so that the metal interconnection line 240 can achieve a smaller line end distance, which is beneficial to improving the design freedom of the metal interconnection line 240 and the connection capability of the metal interconnection line 240.

Fig. 21 to 22 are top views corresponding to steps in another embodiment of the method for forming a semiconductor structure of the present invention. The present embodiment has the same points as the previous embodiments, and is not described herein again, except that:

referring to fig. 21a, a first ion doping is performed on a core layer (not shown) in a second region (not shown) suitable for improving the etching resistance of the core layer 320, and the ion-doped core layer 320 in the second region serves as an etching resistance layer 330. As an example, the first ion doping is performed before the first trench is formed.

Referring to fig. 21b, a first trench 380 penetrating at least a portion of the core layer 320 of the first region in a first direction (as shown in X direction in fig. 21) is formed, and a direction perpendicular to the first direction is a second direction (as shown in Y direction in fig. 21), and in the second direction, a portion of the core layer 320 of the first region is left on both sides of the first trench 380 to serve as the sacrificial layer 340.

The first groove 380 includes a first sidewall 381 along the second direction, and a second sidewall 382 opposite to the first sidewall 381 and parallel to the first sidewall 381. In this embodiment, the first sidewall 381 of the first trench 380 is located in the first region, and there is a gap between the first sidewall 381 and the boundary of the same side of the first region; the second sidewall 382 of the first trench 380 is flush with the boundary of the same side of the first region, or the second sidewall 382 of the first trench 380 is located in an adjacent second region.

Specifically, in the present embodiment, the first sidewall 381 of the first trench 380 is located in the sacrificial layer 340, and there is a space between the first sidewall 381 and the sidewall of the same side of the sacrificial layer 340; the second sidewall 382 of the first trench 380 is flush with the sidewall of the same side of the sacrificial layer 340, or the second sidewall 382 of the first trench 380 is located in the adjacent etch-resistant layer 330. As an example, the first sidewall 381 of the first trench 380 is located in the sacrificial layer 340 with a space between the first sidewall 381 and the sidewall of the same side of the sacrificial layer 340, and the second sidewall 382 of the first trench 380 is located in the adjacent anti-etching layer 330.

Referring to fig. 22a, a sidewall 390 is formed on the sidewall of the first trench 380, such that the sidewall 390 located on the sidewall of the first trench 380 encloses the first recess 310.

Referring to fig. 22b, after the first ion doping and the formation of the sidewall spacers 390, the sacrificial layer 340 is removed, and a second recess 320 is formed in the etch-resistant layer 330. In any one or both of the first groove 310 and the second groove 320, a dividing layer extending in the second direction is formed, and the dividing layer divides the corresponding groove in the first direction. In the step of removing the sacrificial layer 340, the second recesses 320 communicate at the location of the first sidewalls 381. The second recess 320 correspondingly exposes sidewalls of the first sidewalls 381.

Therefore, the second groove 320 not only extends along the first direction, but also the second groove 320 located outside the first sidewall 381 extends along the second direction, so that the first area pattern and the first trench 380 pattern are superimposed to make the pattern of the second groove 320 a two-dimensional pattern, which is beneficial to improving the design freedom of the target pattern, and compared with the two-dimensional pattern realized by using a mask, the two-dimensional pattern is beneficial to reducing the process difficulty and increasing the photolithography process window in this embodiment.

In this embodiment, the target layer is a dielectric layer, and the anti-etching layer 330 and the sidewall 390 are used as masks to etch the dielectric layer under the first recess 310 and the second recess 320 to form an interconnection trench, where the interconnection trench is used to provide a spatial location for forming a metal interconnection line. Correspondingly, the metal interconnection line corresponding to the second groove 320 extends in the first direction and also extends in the second direction, so that two-dimensional winding can be realized, the graphic design and layout freedom of the metal interconnection line can be improved, and the connection capacity of the metal interconnection line can be improved.

As an example, the first groove 310 has a first division layer 315 formed therein, the first division layer 315 extends in the second direction, and the first division layer 315 is in contact with a sidewall of the first groove 310. As an example, the second groove 320 has a second division layer 325 formed therein, the second division layer 325 extends in the second direction, and divides the second groove 320 in the first direction.

For specific description of the first split layer 315 and the second split layer 325, reference may be made to the corresponding description of the foregoing embodiments, and further description is omitted here. For a detailed description of the method for forming the semiconductor structure of this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and further description of this embodiment is omitted here.

Fig. 23 to 24 are top views corresponding to steps in yet another embodiment of the method for forming a semiconductor structure of the present invention. The present embodiment has the same points as the previous embodiments, and is not described herein again, except that:

referring to fig. 23a, the core layer 420 of the second region is first ion-doped, which is suitable for improving the etching resistance of the core layer 420, and the ion-doped core layer 420 located in the second region serves as an etching resistance layer 430.

As an example, the first ion doping is performed before the first trench is formed.

Referring to fig. 23b, a first groove 480 penetrating at least a portion of the core layer 420 of the first region in a first direction (as shown in the X direction in fig. 23) is formed, and a direction perpendicular to the first direction is a second direction (as shown in the Y direction in fig. 23) in which a portion of the core layer 420 of the first region remains on both sides of the first groove 480 to serve as the sacrificial layer 440. The first groove 480 is located in the core layer 420 of the first region, and in the first direction, a space is provided between a sidewall of the first groove 480 and a boundary of the same side of the first region.

Specifically, in the first direction, a sidewall of the first trench 480 has a space from a sidewall of the same side as the sacrificial layer 440. Also, in the second direction, both sides of the first trench 480 remain with a portion of the core layer 420 of the first region, that is, in the second direction, a sidewall of the first trench 480 also has a space with a sidewall of the same side as the sacrificial layer 440. Thus, the sacrificial layer 440 surrounds the first trench 480.

Referring to fig. 24a, a sidewall 490 is formed on a sidewall of the first trench 480, such that the sidewall 490 positioned on the sidewall of the first trench 480 encloses the first recess 410.

Referring to fig. 24b, after the first ion doping and the formation of the sidewalls 490, the sacrificial layer 440 is removed, and a second recess 420 is formed in the etch-resistant layer 430. In any one or both of the first groove 410 and the second groove 420, a dividing layer extending in the second direction is formed, and the dividing layer divides the corresponding groove in the first direction. In this embodiment, the sacrificial layer 440 surrounds the first recess 410, and thus, after the sacrificial layer 440 is removed, the second recess 420 is formed to surround the first recess 410. Specifically, the second groove 420 surrounds the outer sidewall of the sidewall 490, and the second groove 420 is an annular groove.

Correspondingly, the second groove 420 extends along the first direction and also extends along the second direction, so that the superposition of the first region graph and the first groove 480 graph is utilized to enable the graph of the second groove 420 to be a two-dimensional graph, the design freedom degree of a target graph is favorably improved, and compared with the two-dimensional graph realized by utilizing the graph of a photomask, the two-dimensional graph is favorably reduced in process difficulty and increased in photoetching process window.

In this embodiment, the target layer is a dielectric layer, and the anti-etching layer 430 and the sidewall spacers 490 are used as masks to etch the dielectric layer under the first recess 410 and the second recess 420 to form an interconnection trench, where the interconnection trench is used to provide a spatial location for forming a metal interconnection line. Correspondingly, the metal interconnection line corresponding to the second groove 420 extends in the first direction and also extends in the second direction, so that two-dimensional winding can be realized, the graphic design and layout freedom of the metal interconnection line can be improved, and the connection capacity of the metal interconnection line can be improved.

In this embodiment, a first dividing layer 415 is formed in the first groove 410, and divides the first groove 410 along a first direction; the second groove 420 has a second division layer 425 formed therein, and divides the second groove 420 in the first direction. For a detailed description of the method for forming the semiconductor structure of this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and further description of this embodiment is omitted here.

Fig. 25 to 27 are top views corresponding to steps in yet another embodiment of a method for forming a semiconductor structure according to the present invention. The present embodiment has the same points as the previous embodiments, and is not described herein again, except that:

as shown in fig. 25a, a core layer 12 is formed on a substrate, including a first region 12a and a second region 12b surrounding the first region 12 a; the number of the first regions 12a is plural and is arranged along the second direction, and the plural first regions 12a are separated from each other. The shape, position, arrangement and number of the first regions 12a are merely examples, and the shape, position, number and arrangement of the first regions 12a are not limited thereto.

As shown in fig. 25b, the core layer 12 of the second region 12b is doped with the first ions, which is suitable for improving the etching resistance of the core layer 12, and the core layer 12 doped with the ions in the second region 12b is used as the anti-etching layer 13.

As shown in fig. 26a, a first trench 15 penetrating at least a part of the core layer 12 of the first region 12a in a first direction (as shown in an X direction in fig. 26) is formed, and a direction perpendicular to the first direction is a second direction (as shown in a Y direction in fig. 26), and in the second direction, a part of the core layer 12 of the first region 12a remains on both sides of the first trench 15 for use as the sacrificial layer 14.

As an example, the first grooves 15 may be formed only in a partial number of the core layers 12 of the first region 12a, and the first grooves 15 may not be formed in the remaining number of the core layers 12 of the first region 12 a. In other embodiments, the first trenches may also be formed in the entire number of the first regions according to design requirements.

As shown in fig. 26a, the forming method further includes: after the core layer 12 is formed, a second groove 16 is formed to penetrate the core layer 12 between the first regions 12a in the second direction.

As an example, after the first ion doping is performed, the second trenches 16 are formed, and the second trenches 16 respectively penetrate the etch resist layer 13 between the sacrificial layers 14 along the second direction. It should be noted that the second trench 16 and the first trench 15 may be formed in the same step, or may be formed in different steps, and the specific steps for forming the first trench 15 and the second trench 16 are not limited in this embodiment.

As shown in fig. 26b, a sidewall 17 is formed on the sidewall of the first trench 15, so that the sidewall 17 on the sidewall of the first trench 15 encloses a first groove 21. In this embodiment, the side wall 17 is further formed on the side wall of the second trench 16, and the side wall 17 on the side wall of the second trench 16 encloses a third groove 23. The third recess 23 is correspondingly also used for defining the pattern of the target pattern. Correspondingly, the sacrificial layer 14 is subsequently removed to form a second groove, the second groove is arranged with the first groove 21 and the third groove 23 along the second direction, and adjacent grooves are isolated by the side wall 17.

As shown in fig. 27, the sacrificial layer 14 is removed, and a second groove 22 is formed in the etch resist layer 13. In any one or both of the first groove 21 and the second groove 22, a dividing layer extending in the second direction is formed, and the dividing layer divides the corresponding groove in the first direction. The first groove 21, the second groove 22 and the third groove 23 are used together to define a pattern of a target pattern. Correspondingly, the target layer below the first groove 21, the second groove 22 and the third groove 23 is etched by using the anti-etching layer 13, the side wall 17 and the partition layer as masks, so as to form a target pattern.

As an example, the first groove 21 has the first dividing layer 2105 formed therein, and a part of the second groove 22 has the second dividing layer 2205 formed therein. In other embodiments, a third dividing layer may be formed in the third groove, and the third dividing layer divides the third groove along the first direction.

For a detailed description of the method for forming the semiconductor structure of this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and further description of this embodiment is omitted here.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (20)

1. A method of forming a semiconductor structure, comprising:

providing a substrate comprising a target layer for forming a target pattern;

forming a core layer on the substrate, including a first region and a second region surrounding the first region;

carrying out first ion doping on the core layer of the second region, wherein the first ion doping is suitable for improving the etching resistance of the core layer, and the core layer which is positioned in the second region and doped with ions is used as an etching resistance layer;

forming a first groove penetrating through at least part of the core layer of the first area along a first direction, wherein the direction perpendicular to the first direction is a second direction, and in the second direction, part of the core layer of the first area is reserved on two sides of the first groove and is used as a sacrificial layer;

forming a side wall on the side wall of the first groove, so that the side wall positioned on the side wall of the first groove is surrounded into a first groove;

after first ion doping is carried out and the side wall is formed, the sacrificial layer is removed, and a second groove is formed in the anti-etching layer;

a dividing layer extending along the second direction is formed in any one or two of the first groove and the second groove, and the dividing layer divides the corresponding groove along the first direction;

and etching the target layer below the first groove and the second groove by taking the anti-etching layer, the side wall and the partition layer as masks to form a target pattern.

2. The method of forming a semiconductor structure according to claim 1, wherein a first divided layer is formed in the first groove, the first divided layer extends in the second direction, and the first divided layer is in contact with a sidewall of the first groove.

3. The method of forming a semiconductor structure according to claim 2, wherein the first dividing layer is formed in the first groove after the first groove is formed and before the sacrificial layer is removed, the first dividing layer dividing the first groove in a first direction.

4. The method of forming a semiconductor structure of claim 3, wherein the step of forming the first dividing layer comprises: forming a support layer on the core layer and the sacrificial layer of the second region; forming a cutting opening in the support layer, the cutting opening traversing the first groove in a second direction and exposing a portion of the width of the first groove; forming the first division layer in the cutting opening; and removing the supporting layer.

5. The method of forming a semiconductor structure according to claim 1, wherein a second dividing layer is formed in the second groove, the second dividing layer extending in the second direction, and dividing the second groove in the first direction.

6. The method of forming a semiconductor structure of claim 5, wherein the second split layer is formed after forming the first trench and before removing the sacrificial layer.

7. The method of forming a semiconductor structure of claim 6, wherein the step of forming the second split layer comprises: forming a division mask layer on the core layer of the second region, wherein division grooves are formed in the division mask layer, the division grooves cross the first region along the second direction, and the sacrificial layer with partial width is exposed; and performing second ion doping on the sacrificial layer exposed by the dividing groove by taking the dividing mask layer as a mask, wherein the sacrificial layer is suitable for improving the etching resistance of the sacrificial layer, and the sacrificial layer doped with ions is used as the second dividing layer.

8. The method for forming the semiconductor structure according to claim 5, wherein in the step of forming the side wall, the second division layer is formed; the method for forming the semiconductor structure further comprises the following steps: after the core layer is formed and before the side wall is formed, forming a blocking groove penetrating through the core layer in the first region along the second direction, wherein the blocking groove divides the core layer in the first region along the first direction;

the step of forming the second divided layer includes: in the step of forming the side wall, the side wall is further filled in the blocking groove, and the side wall in the blocking groove is used as the second division layer.

9. The method of forming a semiconductor structure of claim 1, wherein in the step of forming the first trench, the first trench includes a first sidewall along a second direction and a second sidewall opposite to and parallel to the first sidewall;

the first groove penetrates through the core layer of the first region along the first direction; or, along the first direction, the first groove penetrates through the core layer of the first region, and any one or two of the first side wall and the second side wall further extend to be located in the core layer of the adjacent second region; in the step of removing the sacrificial layer, the second grooves are spaced.

10. The method of forming a semiconductor structure of claim 1, wherein in the step of forming the first trench, the first trench includes a first sidewall along the second direction and a second sidewall opposite to and parallel to the first sidewall; a first sidewall of the first trench is located in the first region with a space between the first sidewall and a boundary of the same side of the first region; the second side wall of the first groove is flush with the boundary of the same side of the first area, or the second side wall of the first groove is positioned in the adjacent second area;

in the step of removing the sacrificial layer, the second grooves communicate at the position of the first side wall.

11. The method of forming a semiconductor structure according to claim 1, wherein in the step of forming the first trench, the first trench is located in a core layer of the first region with a space between a sidewall of the first trench and a boundary of the same side as the first region in the first direction;

in the step of removing the sacrificial layer, the second groove surrounds the first groove.

12. The method of claim 1, wherein the core layer of the second region is first ion doped after the core layer is formed and before the first trench is formed; or after the first trench is formed and before the side wall is formed, performing first ion doping on the core layer in the second region; or after the side walls are formed and before the sacrificial layer is removed, performing first ion doping on the core layer in the second region.

13. The method of claim 1, wherein the core layer comprises one or more of amorphous silicon, polysilicon, silicon oxide, amorphous carbon, silicon nitride, amorphous germanium, silicon oxynitride, carbon nitride, silicon carbide, silicon carbonitride, and silicon oxycarbonitride.

14. The method of forming a semiconductor structure according to claim 1, wherein the ions for performing the first ion doping comprise one or more of boron ions, phosphorus ions, and argon ions.

15. The method of claim 1, wherein the core layer of the second region is first ion doped using an ion implantation process.

16. The method of forming a semiconductor structure of claim 1, wherein forming the first trench comprises: forming a mask layer on the core layer, wherein the mask layer is provided with a mask opening extending along a first direction; on a projection plane parallel to the substrate, the first region crosses the mask opening along the second direction; taking the mask layer as a mask, removing the core layer below the mask opening to form the first groove; and removing the mask layer.

17. The method of forming a semiconductor structure of claim 1, wherein an etch selectivity between the sacrificial layer and the etch-resistant layer is at least 20: 1.

18. the method of forming a semiconductor structure according to claim 1, wherein the number of the first regions is plural and is arranged in the second direction, and the plural first regions are separated from each other;

the method for forming the semiconductor structure further comprises the following steps: after the core layer is formed and before the side wall is formed, forming a second groove which penetrates through the core layer located between the first regions along a second direction;

in the step of forming the side wall, the side wall is further formed on the side wall of the second groove, and a third groove is formed by the side wall located on the side wall of the second groove in a surrounding mode;

and etching the first groove, the second groove and the target layer below the third groove by taking the anti-etching layer and the side wall as masks to form a target pattern.

19. The method of forming a semiconductor structure of claim 1, wherein the process of removing the sacrificial layer comprises a wet etch process.

20. The method of forming a semiconductor structure of claim 1, wherein the target layer is a dielectric layer; the target graph is an interconnection groove;

the method for forming the semiconductor structure further comprises the following steps: after the forming of the interconnection groove, a metal interconnection line is formed in the interconnection groove.

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