JPH07297414A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To secure a current passage which does not pass through crystal defects in an element by dividing the crystal defects so that a difference can be obtained in vertical distance. CONSTITUTION:Crystal defects 31 are formed at an He<2+> dosing amount of 1X10<12>atoms.cm<-2> and acceleration energy of 24MeV by using an aluminum plate having a thickness of 285mum at its thicker part and 243mum at its thinner part. As a results, crystal defects 31 having widths of 3mum are formed in an element at distances 34mum and 70mum, respectively, from the interface of a P-N junction and a layer 32 having a shorter life time is formed from the interface of the P-N junction. Since the layer 32 can exercise its effect at this position, the leak currents can be reduced and a current passage which does not pass through the crystal defects can be secured in the element.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing method, and more particularly to a high speed switching semiconductor device having a low lifetime layer and its manufacturing method.

[0002]

2. Description of the Related Art In a semiconductor device for switching such as a diode, when the voltage is switched from a forward direction to a reverse direction, it takes a certain time for the excess minority carriers accumulated when the voltage is in the forward direction to disappear. This excess minority carrier is an obstacle to speeding up the switching element, and because minority carriers disappear in a short time, gold or platinum is thermally diffused in the device to shorten the life time, electron beam or neutrons. The lifetime of excess minority carriers is shortened by irradiating a ray to form a crystal defect and act as a recombination center.

This technique is disclosed in Japanese Patent Laid-Open No. 4-
It is reported in Japanese Patent No. 252078. This technology uses a lattice defect with a high level density near the stop position when protons stop in the semiconductor substrate, so it is used as a low lifetime layer. Further, the crystal defects for forming the low lifetime layer are localized and formed.

In addition, it is possible to localize crystal defects having a narrower width, and to perform conventional proton irradiation, electron beam irradiation, etc. by a process that does not require heat treatment at high temperature after irradiation of charged particles. A technique for improving both the on-resistance and the switching speed is disclosed by the present inventors in Japanese Unexamined Patent Publication No.
No. 102161 is reported. This technique is to irradiate helium ion ³ He ²⁺ instead of the conventionally used proton irradiation, and can form crystal defects with a higher level density than the irradiation of proton.

However, in forming any of the low lifetime layers, crystal defects are centrally formed in the direction parallel to the substrate surface of the device. Therefore, interrupt the current path of the current flowing from one electrode in the element to the other electrode,
Crystal defects and low lifetime layers will be present.
Therefore, the current flowing between the substrate of the element always passes through the portion where the crystal defect is formed. When the crystal defect is considered as a current path, its resistance is high, so that the on-resistance of the device increases. For example, even if the formation position of the crystal defect for forming the low lifetime layer is changed, it is possible that the current flowing between the substrates always flows in the crystal defect if the crystal defect is formed centrally inside the element. Therefore, the on-resistance increases.

Further, when a crystal defect is formed near the PN junction and a reverse bias is applied to the device, the depletion layer extending from the PN junction also extends into the region of the crystal defect, and a large electric field is applied to the crystal defect. Become. When an electric field is applied to this crystal defect, this crystal defect becomes the center of carrier generation, which causes an increase in leak current during reverse bias. In order to prevent this, if the crystal defects are formed farther from the PN junction, they cannot be captured within the distance in which the minority carriers are diffused, the switching speed is reduced, and the effect of forming the low lifetime layer is lost. As described above, there is no clear index for determining the formation position of crystal defects, and it has been determined by empirical numerical values.

[0007]

As described above, in the conventional formation of the low lifetime layer, the crystal defects for forming the low lifetime layer are formed by blocking the current path of the device, The problem that the on-resistance increases,
Since the formation position of the low lifetime layer was determined only by an empirical numerical value without a clear index, it was difficult to form the crystal defect at the optimum position.

In the present invention, in order to solve the above problems, the crystal defects for forming the low lifetime layer are formed so as not to interrupt the current path of the current flowing between the substrates of the element, The purpose is to reduce the on-resistance more than that produced by the conventional production method. Also,
The formation of crystal defects does not depend on the empirical numerical value of the formation position, but from the viewpoint of its principle, it aims to form a crystal defect for forming a low lifetime layer by showing a certain index. To do.

[0009]

In order to achieve the above object, in the present invention, the crystal defects are divided into some, and the respective formation positions are formed with a difference in the vertical direction of the element. This ensures that the current path does not pass through the crystal defects and prevents the on-resistance of the device from rising. The formation position of this crystal defect is the distance until the minority carriers diffuse and disappear in order to suppress the recombination current generated by the minority carriers being injected into the low lifetime layer. Introducing the concept of diffusion length, crystal defects are formed within the diffusion length of minority carriers from the interface of the PN junction, minority carriers are captured within their lifetimes, the switching speed is improved and leakage current is reduced.

[0010]

According to the present invention, since the crystal defects are divided and formed with different vertical distances, a current path that does not pass through the crystal defects is ensured in the device. The on resistance of is reduced. Further, by forming the crystal defect away from the PN junction interface by the diffusion length of minority carriers, it is possible to improve the switching speed and reduce the leak current.

[0011]

Embodiments of the present invention will be described with reference to the drawings. First, as shown in FIG. 1A, an N-type silicon semiconductor substrate 11 is prepared. This semiconductor substrate 11 has a specific resistance of 5
According to the measurement result of 0 Ωm, the thickness of 400 μm, and the photoluminescence method, the diffusion length of the minority carrier is about 70 μm.
m. A film thickness of 1000 is formed on the surface of the semiconductor substrate 11.
An angstrom silicon oxide film 12 is formed by a CVD method. Next, a photoresist is formed on the silicon oxide film 12 and patterned to form a resist mask 13 for implanting impurities.

Subsequently, in order to form a P-type impurity region in the semiconductor substrate 11 as shown in FIG. 1B, B is accelerated at an energy of 70 keV and a dose amount of 1 × 10 ¹⁵ atoms ·
Inject at cm ^-2 . Next, annealing is performed at 1150 ° C. for 4 hours to activate the implanted impurities. As a result,
The P-type impurity region 21 formed of B is the semiconductor substrate 1
A region having a depth of 10 μm is formed from the surface of 1. Next, the photoresist is peeled off, an Al film having a film thickness of 1 μm is formed on the surface of the oxide film 12, and this is etched to form the surface electrode 22. Next, an Al film having a film thickness of 9000 angstrom is formed on the back surface of the semiconductor substrate 11 to form the back electrode 23.

Subsequently, crystal defects are formed in order to form a low lifetime layer in the device. The crystal defect, which was conventionally formed centrally in parallel with the electrode so that the current path in the device is not blocked by the crystal defect, is divided into three to give a difference in distance from the electrode. As a result, a current path that is not interrupted by crystal defects is formed. Further, the formation position of this crystal defect is the distance until the minority carriers diffusing from the PN junction interface disappear in order to suppress the recombination current generated by the minority carriers being injected into the low lifetime layer. A crystal defect is formed within a certain minority carrier diffusion length.

Therefore, as shown in FIG. 1C, the formation of the crystal defect 31 for forming the low lifetime layer 32 is as follows.
Irradiation of ³ He ²⁺ is performed through the metal plate 33 having a different film thickness, and the irradiation energy is changed by this metal plate to change the formation position of crystal defects. Low lifetime 32
Is 70 μm vertically from the center of the crystal defect 31.
It is formed with a width of m. Therefore, low lifetime layer 3
In order to form 2 without gaps in the device, crystal defects 31
Can be obtained in a vertical direction at a maximum distance of 140 μm to obtain a certain effect. However, for the above reason, the crystal defect 31 needs to be formed within the range of 70 μm, which is the diffusion length of minority carriers, from the PN junction interface. Also, to prevent the current path from being blocked by crystal defects,
The crystal defects 31 are divided and formed so that the respective crystal defects 31 have a difference in distance from the surface of the semiconductor substrate 11.

Therefore, in this embodiment, the crystal defect 31
Is formed at a distance of 70 μm when its center is farthest from the PN junction interface, and at a distance of 34 μm from the PN junction interface where it is closest to the PN junction. The above positions are positions where the effects of the low lifetime layer can be most expected, and are optimum positions for realizing reduction of leak current and improvement of switching speed.

The crystal defect 31 and the low lifetime layer 32
FIG. 2A is a cross-sectional view for explaining the formation position of the. As shown in the figure, the crystal defect 31 has a width of 3 μm in the device, and the central position thereof is 34 μm from the PN junction interface.
Low lifetime layer 3 formed at a position 0 μm away
2 is formed from the PN junction interface.

In order to form the crystal defect 31 at a desired position, it is necessary to determine the film thickness and size of the metal plate 33, the dose amount of ³ He ²⁺ and the acceleration energy. In this embodiment, the dose is 1 × 10 ¹² atoms · cm ⁻² and the acceleration energy is 24 MeV. Further, as shown in FIG. 2B, the film thickness of the metal plate 33 is 285 μm in the thick part.
m and a thin film portion is performed using an Al plate of 243 μm.

The formation of crystal defects can also be carried out by using, for example, protons. In this case, the dose amount is 7 × 10 ¹² atoms · cm ⁻² and the acceleration energy is 4.5.
Perform with MeV. As shown in FIG. 2C, the thickness of the metal plate is 125 μm in the thick part and 96 μm in the thin part. The width of crystal defects formed by irradiation with protons is 15 μm, which is more difficult to form by localization than the width of ³ He ²⁺ , but some effects can be expected.

In the above embodiment, an example of ³ He ²⁺ is shown, but in addition to this, H ⁺ , ² D ⁺ , ⁴ He ²⁺ , e ⁻ , Pt.
^It can also be implemented by using ^{+ +} and Au ⁺ ions. With these ions, the width of crystal defects can be shortened to a certain extent, and the concentration thereof can be set to a high level, so that an efficient low lifetime layer can be formed.

In addition to a metal plate made of an Al plate, Si or Si
The acceleration energy of the irradiated particles can be changed by each substance of O ₂ and it can be carried out. Further, it is possible to form a crystal defect by partially irradiating ions without using these substances and changing the irradiation position, the acceleration energy and the dose amount.

Next, FIG. 3 shows a characteristic diagram of the switching speed and the on-voltage, which shows the effect of the embodiment of the present invention. Here, the on-voltage is assumed to be proportional to the on-resistance. The characteristic of the conventional structure in the figure is the diffusion length of minority carriers at the center position of the crystal defect from the PN junction interface.
The crystal defects are formed in parallel with the electrodes of the device and are characteristically formed in parallel with the electrodes of the device.
As shown in the figure, the characteristics of this embodiment are higher than the conventional one in both the switching speed and the on-voltage (on-resistance), and it can be seen that the characteristics are significantly improved.

An object of the present invention is to secure a current path that is not interrupted by crystal defects formed in the element and to form crystal defects within a range within the diffusion length of minority carriers to form a low lifetime layer. In addition to the above-mentioned embodiment, the formation position of the crystal defect is further divided into finer crystal defects, and the formation positions thereof are alternately formed. Alternatively, the crystal defect at the center is formed by PN junction. There is a form such that it is formed farthest from the interface. A cross-sectional view for explaining these is shown in FIG.
Shown in (a) to (c). 41 in the figure is a crystal defect, 42
Is a low lifetime layer. The same effect can be obtained by any of these forms.

[0023]

According to the present invention, a current path that does not pass through crystal defects is ensured in the device, so that the on-resistance of the device is reduced. In addition, by forming the crystal defect away from the PN junction interface by the diffusion length of minority carriers, it is possible to improve the switching speed and reduce the leak current.
Further improvement in device characteristics can be realized.

[Brief description of drawings]

FIG. 1 is a sectional view illustrating a manufacturing process according to an embodiment of the present invention.

FIG. 2 is a sectional view illustrating an embodiment of the present invention.

FIG. 3 is a characteristic diagram of the switching speed and the on-voltage of the present embodiment.

FIG. 4 is a sectional view illustrating another embodiment of the present invention.

[Explanation of symbols]

 11 N-type Silicon Semiconductor Substrate 12 Silicon Oxide Film 13 Resist Mask 21 P-type Impurity Region 22 Front Surface Electrode 23 Back Surface Electrode 31, 41 Crystal Defect 32, 42 Low Lifetime Layer 33 Metal Plate

Claims (13)

[Claims] 1. A region of the first conductivity type and a second conductivity type formed in a semiconductor substrate, a first electrode connected to the region of the first conductivity type, and a region of the second conductivity type. In the semiconductor device having the formed second electrode and a crystal defect in the semiconductor substrate, the crystal defect is divided into a plurality of parts. 2. The semiconductor device according to claim 1, wherein the plurality of divided crystal defects are minority carriers of the semiconductor substrate from an interface between the first conductivity type region and the second conductivity type region. A semiconductor device having a center within a range up to a diffusion distance. 3. The semiconductor device according to claim 1, wherein the crystal defects divided into a plurality are substantially at an interface between the first conductivity type region and the second conductivity type region in the semiconductor substrate. A semiconductor device, characterized in that it is formed with a step in a direction parallel to, without a gap. 4. The semiconductor device according to claim 1, wherein a main current path between the first and second electrodes is provided in a region between the divided crystal defects. 5. The semiconductor device according to claim 1, wherein the distance between the centers of the crystal defects divided into the plurality is within twice the diffusion length of minority carriers in the semiconductor substrate. Semiconductor device. 6. The semiconductor device according to claim 1, wherein the crystal defects are H ⁺ , ² D ⁺ , ³ He ²⁺ , ⁴ He ²⁺ , e.
^-, Pt ^+, and wherein a being formed by irradiating the Izure of ions of Au ^+. 7. A step of forming a second conductivity type region in a predetermined region of a first conductivity type semiconductor substrate; and a step of forming the first conductivity type semiconductor substrate in the first conductivity type semiconductor substrate. A step of forming a plurality of crystal defects so that a center thereof exists within a range from an interface of the second conductivity type region to a position away from a diffusion length of minority carriers of the semiconductor substrate. Device manufacturing method. 8. The method of manufacturing a semiconductor device according to claim 7, wherein the distance between the centers of the plurality of crystal defects is formed within a distance of twice the diffusion length of minority carriers of the semiconductor substrate. And a method for manufacturing a semiconductor device. 9. The method for manufacturing a semiconductor device according to claim 7, wherein the plurality of crystal defects are parallel to an interface between the semiconductor substrate of the first conductivity type and the region of the second conductivity type in the semiconductor substrate. A semiconductor device characterized by being formed with a step in any direction without gaps. 10. The method of manufacturing a semiconductor device according to claim 7, wherein the step of forming the plurality of crystal defects is performed by changing irradiation energy of predetermined ions. . 11. The method of manufacturing a semiconductor device according to claim 10, wherein the means for changing the irradiation energy is performed by interposing a predetermined substance between an irradiation source of the predetermined ions and the semiconductor substrate. A method for manufacturing a semiconductor device, comprising: 12. The method of manufacturing a semiconductor device according to claim 10, wherein the means for changing the irradiation energy is performed by changing a film thickness of the predetermined substance. 13. The method of manufacturing a semiconductor device according to claim 12, wherein the predetermined substances having different film thicknesses are Al, Si, and SiO _2.
A method of manufacturing a semiconductor device, characterized by performing using any one of the substances.