JPH05102161A - Manufacture of semiconductor device, and the semiconductor device - Google Patents

Manufacture of semiconductor device, and the semiconductor device

Info

Publication number
JPH05102161A
JPH05102161A JP19998991A JP19998991A JPH05102161A JP H05102161 A JPH05102161 A JP H05102161A JP 19998991 A JP19998991 A JP 19998991A JP 19998991 A JP19998991 A JP 19998991A JP H05102161 A JPH05102161 A JP H05102161A
Authority
JP
Japan
Prior art keywords
irradiation
semiconductor device
irradiated
voltage
helium ions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19998991A
Other languages
Japanese (ja)
Inventor
Akihiko Osawa
明彦 大澤
Yoshiaki Baba
嘉朗 馬場
Shunichi Kai
俊一 開
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP19998991A priority Critical patent/JPH05102161A/en
Publication of JPH05102161A publication Critical patent/JPH05102161A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/30Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface
    • H01L29/32Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface the imperfections being within the semiconductor body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861Diodes
    • H01L29/8611Planar PN junction diodes

Abstract

PURPOSE:To localize a low lifetime layer whose half-width is narrower, to eliminate a need for a heat treatment at a high temperature and to enhance an ON voltage and a switching speed as compared with those by a proton irradiation operation or an electron-beam irradiation operation in conventional cases by a method wherein a prescribed region inside a semiconductor substrate is irradiated with helium ions. CONSTITUTION:This device is provided with a process wherein a prescribed region inside a semiconductor substrate 1 is irradiated with helium ions <3>He<2+>. The accelerating energy of the helium ions is set at 1 to 40MeV, and their dose is set at 1X10<9> to 5X10<13>/cm<2>. In addition, it is preferable that the semiconductor substrate 1 is heated to 300 to 400 deg.C after the helium ions have been irradiated. For example, a P<+> diffusion layer at a depth of d3=10mum is formed on the main face of an N-type silicon substrate 1 (its thickness d1 = about 400mum). Then, the surface side of the substrate 1 is irradiated with helium ions; a low lifetime layer 7 having a half-width of (w) is formed in the position of a depth of d2, and a P<+> N-type switching diode is formed.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体装置の製造方法
及びその製造方法により製造される半導体装置に関する
もので、特に該装置が形成される半導体基板の局在領域
に低ライフタイム層を設ける高速スイッチング素子に使
用されるものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device manufactured by the manufacturing method, and in particular, a low lifetime layer is provided in a localized region of a semiconductor substrate on which the device is formed. It is used for high speed switching devices.

【0002】[0002]

【従来の技術】周知のように、スイッチング用半導体素
子では、順方向から逆方向に切替えたとき、順方向時に
蓄積された過剰少数キャリアの消滅に一定の時間がかか
り、高速化の障害となっている。このため従来技術で
は、デバイス中に金や白金を熱拡散してライフタイムを
小さくしたり、あるいは電子線、中性子線等を照射して
格子欠陥をつくり、再結合中心として作用させ、ライフ
タイムの短縮化を計っている。 従来技術のうち、低ラ
イフタイム層の局在化技術として、プロトン照射技術が
ある。これは半導体基板中にプロトンが停止するとき、
停止位置付近に高準位密度の欠陥が生じる。この現象を
利用し、低ライフタイム層を局在化することができる。
As is well known, when switching from a forward direction to a reverse direction in a switching semiconductor element, it takes a certain amount of time for the excess minority carriers accumulated during the forward direction to disappear, which is an obstacle to speeding up. ing. Therefore, in the conventional technology, gold or platinum is thermally diffused in the device to reduce the lifetime, or electron beams or neutron beams are irradiated to form lattice defects, which act as recombination centers to reduce the lifetime. We are trying to shorten it. Among conventional techniques, there is a proton irradiation technique as a localization technique for the low lifetime layer. This is because when protons stop in the semiconductor substrate,
High level density defects occur near the stop position. By utilizing this phenomenon, the low lifetime layer can be localized.

【0003】この従来例について図面を参照して説明す
る。図6はスイッチング用P+ N型ダイオードの模式的
な断面図である。N型シリコン基板1の主面に、選択的
にP+ 拡散層2が形成されている。P+拡散層2に接し
てアノード電極4(表面電極)が、またN型基板1に接
して、カソード電極5(裏面電極)が設けられる。符号
3は絶縁膜である。
This conventional example will be described with reference to the drawings. FIG. 6 is a schematic cross-sectional view of a switching P + N type diode. A P + diffusion layer 2 is selectively formed on the main surface of the N-type silicon substrate 1. An anode electrode 4 (front surface electrode) is provided in contact with the P + diffusion layer 2, and a cathode electrode 5 (back surface electrode) is provided in contact with the N-type substrate 1. Reference numeral 3 is an insulating film.

【0004】スイッチング用ダイオードでは、オン電圧
特性及びスイッチング速度は重要な電気的特性である。
オン電圧特性は、指定の順電流IF を流したときの、素
子のアノード・カソード間の順電圧降下VF (サイリス
タ等ではVon)であらわす。図6のP+ N型ダイオード
では、VF は主として接合及びNカソード領域1の抵抗
により決められ、素子としては小さいほど良い。またス
イッチング速度は逆回復時間trrで表わされる。逆回復
時間は、図7に示すように、ダイオードに指定の順電流
F を流し、t1 において指定の逆電圧VRを印加し、
指定の順電流減少率(di/dt)で減少させたとき、
逆電流の流れるt2 からt3 までの時間で、trrと記
す。逆電流は主としてN型領域1に蓄積された正孔によ
るもので、高速スイッチングダイオードにおいては、t
rrはできるだけ短いことが望ましいので、N型領域1に
おける少数キャリアのライフタイムを短縮する必要があ
る。
In the switching diode, the on-voltage characteristic and the switching speed are important electrical characteristics.
The on-voltage characteristic is represented by a forward voltage drop V F between the anode and the cathode of the device (V on in a thyristor or the like) when a specified forward current I F is passed. In the P + N type diode of FIG. 6, V F is mainly determined by the junction and the resistance of the N cathode region 1, and the smaller the element, the better. The switching speed is represented by the reverse recovery time trr . As for the reverse recovery time, as shown in FIG. 7, a specified forward current I F is applied to the diode, and a specified reverse voltage V R is applied at t 1 ,
When it is reduced at the specified forward current reduction rate (di / dt),
The time from t 2 to t 3 at which the reverse current flows is referred to as t rr . The reverse current is mainly due to the holes accumulated in the N-type region 1.
Since it is desirable that rr is as short as possible, it is necessary to shorten the lifetime of minority carriers in the N-type region 1.

【0005】図6の符号6は、半導体基板1の表面また
は裏面からプロトンを照射した後、熱処理をして安定化
した低ライフタイム層で、幅wは半値幅である。なお半
値幅は、基板の厚さ方向に対する欠陥濃度分布(通常山
形)が最大値の半分となる基板位置間の距離で、プロト
ン照射の場合、例えば15μmである。
Reference numeral 6 in FIG. 6 is a low lifetime layer which is stabilized by irradiating protons from the front surface or the back surface of the semiconductor substrate 1 and then performing heat treatment, and the width w is a half width. The full width at half maximum is the distance between substrate positions where the defect concentration distribution (normally chevron) in the thickness direction of the substrate is half of the maximum value, and is 15 μm in the case of proton irradiation.

【0006】プロトン照射によるライフタイム制御で
は、照射量を5×1012 atoms/cm2 程度にしないと、
白金拡散や電子線照射の場合と比較して、オン電圧(V
F )やスイッチング速度(trr)がより高性能にならな
い。他方、プロトンの照射量が5×1012 atoms/cm2
なると素子耐圧が劣化する。図5は、P+ N型ダイオー
ドの耐圧の照射量依存性を示すもので、曲線aはプロト
ン照射(1.5MeV)のとき、また曲線bは 3He 2+
照射(6MeV)のとき、照射量を増加したときの耐圧
低下を示すものである。このためプロトン照射後、40
0℃、10分以上の熱処理が必要になる。この熱処理に
よりライフタイムキラーとして形成した欠陥準位も回復
してしまうため、プロトン照射では、白金拡散や電子線
照射技術と比べると、表1に示すように、オン電圧(V
F )が多少回復するだけで、スイッチング速度(trr
の改善は殆ど見られない。
In the lifetime control by proton irradiation, unless the irradiation dose is set to about 5 × 10 12 atoms / cm 2 ,
Compared with the case of platinum diffusion or electron beam irradiation, the on-voltage (V
F ) and switching speed (t rr ) do not become higher performance. On the other hand, the proton dose is 5 × 10 12 atoms / cm 2
If this happens, the breakdown voltage of the element will deteriorate. FIG. 5 shows the dose dependence of the breakdown voltage of the P + N-type diode. Curve a is for proton irradiation (1.5 MeV), and curve b is 3 He 2+.
In the case of irradiation (6 MeV), it shows a decrease in withstand voltage when the irradiation amount is increased. Therefore, after proton irradiation, 40
Heat treatment at 0 ° C. for 10 minutes or more is required. Since the defect level formed as a lifetime killer is also recovered by this heat treatment, in the proton irradiation, as compared with platinum diffusion and electron beam irradiation techniques, as shown in Table 1, the on-voltage (V
Switching speed (t rr ) with only a slight recovery of F )
Is hardly seen.

【0007】またプロトン照射による低ライフタイム層
の半値幅は約15μmのため、幅10μm以下の低ライ
フタイム層の局在化領域を必要とする場合、この技術は
使えないことになる。
Further, since the full width at half maximum of the low lifetime layer due to proton irradiation is about 15 μm, this technique cannot be used when a localized region of the low lifetime layer having a width of 10 μm or less is required.

【0008】[0008]

【発明が解決しようとする課題】これまで述べたよう
に、従来低ライフタイム層の局在化技術としてプロトン
照射技術があるが、照射量を5×1012atoms/cm2
度とすると、耐圧劣化を回復するため400℃10分以
上の熱処理を必要とするので、結果的には従来の白金拡
散や電子線照射技術に比べ、オン電圧(VF )が多少改
善される程度で、スイッチング速度(trr)が殆ど良く
ならない。またプロトン照射の低ライフタイム層の局在
化技術では、低ライフタイム層の半値幅が10数μmと
広く、より狭い半値幅の低ライフタイム層の形成はでき
ない。
As described above, there has been a proton irradiation technique as a conventional localization technique for the low lifetime layer. However, when the dose is set to about 5 × 10 12 atoms / cm 2 , the breakdown voltage is reduced. Since heat treatment at 400 ° C. for 10 minutes or more is required to recover the deterioration, as a result, the on-voltage (V F ) is slightly improved as compared with the conventional platinum diffusion and electron beam irradiation techniques, and the switching speed is increased. (T rr ) hardly improves. Further, with the localization technique of the low lifetime layer of proton irradiation, the half width of the low lifetime layer is as wide as 10 μm, and it is not possible to form a low lifetime layer with a narrower half width.

【0009】本発明は、上記の問題にかんがみなされた
もので、その目的は、より狭い半値幅の低ライフタイム
層の局在化を可能とすると共に、荷電粒子照射後、高温
の熱処理を必要としないプロセスにより、従来のプロト
ン照射、電子線照射等に比べて、オン電圧(VF )及び
スイッチング速度(trr)が共に向上する半導体装置の
製造方法とその製造方法により製造された半導体装置を
提供することである。
The present invention has been made in view of the above problems, and an object thereof is to enable localization of a narrow lifetime half-width low lifetime layer and to require heat treatment at high temperature after irradiation of charged particles. the non processes and conventional proton irradiation, as compared with electron beam irradiation or the like, the oN voltage (V F) and the switching speed (t rr) manufacturing method of a semiconductor device to be improved along with the semiconductor device manufactured by the manufacturing method Is to provide.

【0010】[0010]

【課題を解決するための手段と作用】本発明の請求項1
ないし請求項3の半導体装置の製造方法は、半導体基板
内の所定領域(例えばP+ N型スイッチング用ダイオー
ドではN型カソード領域中で、あらかじめ試行により求
めた最適領域(図1参照))にヘリウムイオン 3He 2+
を照射する工程を具備することを特徴とするものであ
る。
Means and Actions for Solving the Problems Claim 1 of the present invention
The method of manufacturing a semiconductor device according to claim 3 is characterized in that helium is applied to a predetermined region (for example, in an N type cathode region of a P + N type switching diode, an optimum region obtained by trial in advance (see FIG. 1)) in a semiconductor substrate. Ion 3 He 2+
Is provided.

【0011】半導体装置にヘリウムイオン 3He 2+を照
射したときと、プロトン 1+ を照射したときの素子の
耐圧特性(図5参照)はほぼ同一である。しかし照射損
傷による高準位密度の欠陥準位は、プロトン照射の場合
には(Ec −0.39)、ヘリウムイオン 3He 2+照射
の場合には(Ec −0.43)となり、ヘリウムイオン
3He 2+照射の方が深い準位となり、高速スイッチング
素子に対してはヘリウムイオン 3He 2+は有効なプロセ
スと考えられた。このような考えをもとに、本発明にお
いては低ライフタイム層の局在化技術として 3He 2+
照射を行ない、プロトン照射に比し狭い半値幅wの低ラ
イフタイム層(図3参照)が得られた。また上記ヘリウ
ムイオン照射により、従来技術に比し低オン電圧
(VF )で高スイッチング速度(trr)の素子が得られ
た。
The breakdown voltage characteristics (see FIG. 5) of the element when the semiconductor device is irradiated with helium ion 3 He 2+ and when irradiated with proton 1 H + are almost the same. However defect level of the high level position density by irradiation damage in the case of proton irradiation (E c -0.39), in the case of helium ions 3 the He 2+ irradiation (E c -0.43), and the Helium ion
Towards 3 the He 2+ irradiation becomes deep level, helium ions 3 the He 2+ was considered valid process for high-speed switching element. Based on such a concept, in the present invention, 3 He 2+ irradiation is performed as a localization technique of the low lifetime layer, and the low lifetime layer having a half width w narrower than that of proton irradiation (see FIG. 3). )was gotten. Further, by the above helium ion irradiation, a device having a low on-voltage (V F ) and a high switching speed (t rr ) as compared with the prior art was obtained.

【0012】請求項2記載の半導体装置の製造方法は、
請求項1記載の製造方法でヘリウムイオン 3He 2+の加
速エネルギーを1MeVないし40MeVとし、かつ照
射量を1×109 atoms/cm2 ないし5×1013 atoms
/cm2 とするものである。ヘリウムイオンの加速エネル
ギーを1MeVないし40MeVとするのは、ヘリウム
イオンを半導体装置を形成する半導体基板内の所望の領
域に照射し、前記所定領域を設定するために必要な加速
エネルギー範囲を示す。また照射量1×109 atoms/c
m2 は、実質的に有用な本発明の効果が得られる下限値
であり、また照射量5×1013 atoms/cm2 は、損傷を
受けても熱処理により回復し、単結晶基板として機能で
きる上限値である。
A method of manufacturing a semiconductor device according to claim 2 is
2. The method according to claim 1, wherein the helium ion 3 He 2+ has an acceleration energy of 1 MeV to 40 MeV and a dose of 1 × 10 9 atoms / cm 2 to 5 × 10 13 atoms.
/ Cm 2 . The acceleration energy of helium ions is set to 1 MeV to 40 MeV to indicate an acceleration energy range required for setting a predetermined region by irradiating a desired region in a semiconductor substrate forming a semiconductor device with helium ions. In addition, the dose of 1 × 10 9 atoms / c
m 2 is the lower limit value at which the practically useful effect of the present invention is obtained, and the dose of 5 × 10 13 atoms / cm 2 can be recovered by heat treatment even if damaged and can function as a single crystal substrate. It is the upper limit.

【0013】請求項3記載の半導体装置の製造方法は、
請求項1または請求項2いずれか記載の製造方法におい
て、ヘリウムイオン 3He 2+を照射した後、該半導体基
板を300℃ないし400℃に加熱することを特徴とす
るものである。熱処理は、ヘリウムイオン照射による基
板の損傷を回復すると共に欠陥を安定化するために行な
う。ヘリウムイオン照射は、ウェーハプロセスを終え
て、ダイシング前の状態のウェーハに対し施されること
が多いので、熱処理温度の上限(400℃)は、基板に
形成されている素子が熱破壊のおそれのない温度とし、
下限(300℃)は、実用的な熱処理時間(例えば30
分以下)で欠陥の安定化ができる温度とする(図4参
照)。なお加熱手段として、抵抗加熱、高周波誘導(R
F)加熱、輻射加熱を用いることが望ましい。
A method of manufacturing a semiconductor device according to claim 3 is
The manufacturing method according to claim 1 or 2, wherein the semiconductor substrate is heated to 300 ° C to 400 ° C after irradiation with helium ions 3 He 2+ . The heat treatment is performed in order to recover the damage to the substrate due to the helium ion irradiation and stabilize the defects. Since the helium ion irradiation is often performed on the wafer before the dicing after the wafer process is completed, the upper limit of the heat treatment temperature (400 ° C.) may cause thermal destruction of the elements formed on the substrate. No temperature and
The lower limit (300 ° C) is the practical heat treatment time (for example, 30
The temperature is set to a temperature at which defects can be stabilized in (min. As heating means, resistance heating, high frequency induction (R
F) It is desirable to use heating or radiant heating.

【0014】請求項4記載の半導体装置は、請求項1な
いし請求項3いずれか記載の製造方法により製造された
半導体装置である。
A semiconductor device according to a fourth aspect is a semiconductor device manufactured by the manufacturing method according to any one of the first to third aspects.

【0015】[0015]

【実施例】図面を参照し、本発明の実施例について以下
説明する。図1は、本発明を行なうにあたり、使用した
+ N型スイッチング用ダイオードの模式的な断面図で
ある。N型シリコン基板1(厚さd1 =約400μm)
の主表面に深さd3 =10μmのP+ 拡散層2が形成さ
れる。基板の表面側からヘリウムイオンを照射し、深さ
2 の位置に半値幅wの低ライフタイム層7を形成す
る。例えばヘリウムイオン 3He 2+を加速エネルギー6
MeV,照射量1×1012 atoms/cm2 で照射すると
き、d2 =40μm,w=3μmとなる。
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic sectional view of a P + N type switching diode used in carrying out the present invention. N-type silicon substrate 1 (thickness d 1 = about 400 μm)
A P + diffusion layer 2 having a depth d 3 = 10 μm is formed on the main surface of. Helium ions are irradiated from the front surface side of the substrate to form a low lifetime layer 7 having a half width w at the position of depth d 2 . For example, helium ion 3 He 2+ is accelerated energy 6
When irradiation is performed with MeV at a dose of 1 × 10 12 atoms / cm 2 , d 2 = 40 μm and w = 3 μm.

【0016】次に図1に示すP+ N型ダイオードを使用
して行なった代表的な試行例について、図2を参照して
説明する。加速エネルギー6MeVで、照射量1×10
10 atoms/cm2 (A1 )、5×1011 atoms/cm2 (A
2 )、1×1012 atoms/cm2 (A3 )、1×1013 a
toms/cm2 (A4 )の 3He 2+を照射し、300℃10
分の熱処理を行ない、それぞれの素子について、オン電
圧VF (順方向電流IF 15Aのときのアノード・カソ
ード間の電圧)及びスイッチング速度trr(図7におい
てIF =2A、di/dt=50μA/sec 、VR =3
0V)を求める。図2は、横軸がオン電圧VF (V)、
縦軸がスイッチング速度trr(nsec)で、前記照射
量の異なるA1 ないしA4 のそれぞれの場合の測定結果
を○印で打点する。また比較サンプルとして加速エネル
ギー1.5MeV、照射量1×1012 atoms/cm2 (B
1 )、5×1012 atoms/cm2 (B2 )、1×1013 a
toms/cm2 (B3 )のプロトンを照射し、400℃10
分の熱処理を行なった素子及び加速エネルギー10Me
V、照射量5×1013 atoms/cm2 の電子を白金拡散を
してあるサンプルに照射した素子(C1 )、について、
それぞれオン電圧VF とスイッチング速度trrとを測定
し、結果を△印及び□印で図2に打点し、オン電圧とス
イッチング速度の関係を比較した。なお●印は未照射の
サンプルの測定値を示す。
Next, a typical trial example performed using the P + N type diode shown in FIG. 1 will be described with reference to FIG. Irradiation dose 1 × 10 with acceleration energy 6 MeV
10 atoms / cm 2 (A 1 ), 5 × 10 11 atoms / cm 2 (A 1
2 ) 1 × 10 12 atoms / cm 2 (A 3 ), 1 × 10 13 a
Irradiate with 3 He 2+ of toms / cm 2 (A 4 ), 300 ° C. 10
Performs minute thermal treatment, for each element, I F = 2A in (anode voltage between the cathode when the forward current I F 15A) and switching speed t rr (7 ON voltage V F, di / dt = 50 μA / sec, V R = 3
0V) is calculated. In FIG. 2, the horizontal axis represents the ON voltage V F (V),
The vertical axis represents the switching speed trr (nsec), and the measurement results in the cases of A 1 to A 4 with different irradiation doses are marked with a circle. As a comparative sample, the acceleration energy was 1.5 MeV and the dose was 1 × 10 12 atoms / cm 2 (B
1 ), 5 × 10 12 atoms / cm 2 (B 2 ), 1 × 10 13 a
Irradiated with protons of toms / cm 2 (B 3 ), 400 ° C. 10
And the acceleration energy of 10Me
V, an element (C 1 ) in which a sample in which platinum was diffused was irradiated with electrons with a dose of 5 × 10 13 atoms / cm 2
The on-voltage V F and the switching speed trr were measured respectively, and the results are plotted in FIG. 2 with Δ marks and □ marks to compare the relationship between the on-voltage and the switching speed. The mark ● indicates the measured value of an unirradiated sample.

【0017】図2に示すように、 3He 2+照射を行なう
ことにより、従来のプロトン照射や電子線照射+白金拡
散)に比べてオン電圧及びスイッチング速度ともに向上
することがわかる。また点A1 ないし点A4 を通る曲線
aは、 3He 2+の照射量を変化させたときのスイッチン
グ速度trrとオン電圧VFとの関係を示すもので、 3He
2+の照射量は1×109 atoms/cm2 ないし5×10
13 atoms/cm2 とすることが望ましい。
As shown in FIG. 2, it is understood that the irradiation with 3 He 2+ improves both the on-voltage and the switching speed as compared with the conventional proton irradiation or electron beam irradiation + platinum diffusion. The curve a passing through the point A 1 to the point A 4 shows a relation between the switching speed t rr and the ON voltage V F when changing the irradiation amount of 3 He 2+, 3 He
The dose of 2+ is 1 × 10 9 atoms / cm 2 to 5 × 10
13 atoms / cm 2 is desirable.

【0018】なお上記実施例では、抵抗加熱により熱処
理を行なったが、RF加熱や輻射加熱を利用してもよ
い。また電子ビーム加熱、レーザ加熱により処理しても
同様の結果が得られる。
Although the heat treatment is performed by resistance heating in the above embodiment, RF heating or radiant heating may be used. Also, similar results can be obtained by treating with electron beam heating or laser heating.

【0019】図3にヘリウムイオン 3He 2+を加速エネ
ルギー6MeV、照射量1×1012atoms/cm2 でP+
N型ダイオードに照射したときの、基板表面からの深さ
と、各深さにおける結晶欠陥密度(相対値)を示す。測
定は、DLTS(deep leveltransient spectroscopy
)法により行なった。低ライフタイム層は、深さ約4
0μmの位置に半値幅w=3μmで形成される。従来の
プロトン照射の場合における低ライフタイム層の半値幅
は約15μmであり、ヘリウムイオンの場合はその1/
5で、極めて狭い。そのため幅が10μm以下の領域内
に低ライフタイム層を局在化することもできる。
In FIG. 3, helium ion 3 He 2+ is added to P + with an acceleration energy of 6 MeV and a dose of 1 × 10 12 atoms / cm 2.
The depth from the substrate surface and the crystal defect density (relative value) at each depth when the N-type diode is irradiated are shown. DLTS (deep level transient spectroscopy)
) Method. The low lifetime layer has a depth of about 4
A half width w = 3 μm is formed at a position of 0 μm. In the case of conventional proton irradiation, the half-width of the low lifetime layer is about 15 μm, and in the case of helium ion,
5 is extremely narrow. Therefore, the low lifetime layer can be localized in a region having a width of 10 μm or less.

【0020】次に熱処理条件の適値を求めるために行な
った試行例について述べる。P+ N型ダイオード(図1
参照)にヘリウムイオン 3He 2+を加速エネルギー6M
eV、照射量1×1012 atoms/cm2 で照射した複数個
のサンプルを用意する。熱処理はイオン照射により生成
した結晶欠陥の安定化のため実施するもので、本試行例
では、素子に逆バイアスを印加したときのリーク電流が
熱処理により安定化するのを熱処理効果の評価基準とす
る。熱処理温度条件を、400℃(○印)、385℃
(△印)、350℃(□印)及び300℃(×印)の4
条件とし、各条件ごとに素子のリーク電流(逆バイアス
電圧100V)が、熱処理時間(分)の経過に伴い減少
(安定化)する様子を調べた。その結果を図4に示す。
同図より熱処理温度条件を300℃以下とすると、リー
ク電流が安定するのに時間がかかりすぎ、400℃以上
とすると短時間で安定するが、素子を熱破壊するおそれ
のあることがわかる。
Next, an example of trials carried out for obtaining an appropriate value of heat treatment conditions will be described. P + N type diode (Fig. 1
Helium ion 3 He 2+ as acceleration energy 6M
A plurality of samples irradiated with eV and a dose of 1 × 10 12 atoms / cm 2 are prepared. The heat treatment is performed to stabilize the crystal defects generated by the ion irradiation. In this trial example, the leakage current when a reverse bias is applied to the device is stabilized by the heat treatment as the evaluation criterion for the heat treatment effect. .. Heat treatment temperature conditions are 400 ° C (○ mark), 385 ° C
(△ mark), 350 ℃ (□ mark) and 300 ℃ (× mark) 4
As a condition, it was examined how the leak current (reverse bias voltage 100 V) of the device decreases (stabilizes) with the elapse of the heat treatment time (min) for each condition. The result is shown in FIG.
It can be seen from the figure that when the heat treatment temperature condition is 300 ° C. or less, it takes too long for the leak current to stabilize, and when it is 400 ° C. or more, it stabilizes in a short time, but there is a risk of thermal destruction of the element.

【0021】図5は、前記P+ N型ダイオード(図1参
照)に、加速エネルギー1.5MeVのプロトンを照射
したとき(曲線a)及び加速エネルギー6MeVのヘリ
ウムイオン 3He 2+を照射したとき(曲線b)、それぞ
れの耐圧(縦軸)と照射量(横軸)との関係を示す曲線
である。照射量の増加に伴い、耐圧が低下する傾向は、
プロトンとヘリウムイオンとで殆ど同じである。他方ヘ
リウムイオン照射では、プロトンと同じ照射量でも、プ
ロトン照射以上の欠陥をつくる。同じ欠陥密度を生成す
るためには、ヘリウムイオン照射ではプロトン照射より
照射量を低減でき、図5よりみられるように、耐圧劣化
も少なくプロトン照射ほどの高温の熱処理を必要としな
い。
FIG. 5 shows the P + N type diode (see FIG. 1) irradiated with protons having an acceleration energy of 1.5 MeV (curve a) and with helium ions 3 He 2+ having an acceleration energy of 6 MeV. (Curve b) is a curve showing the relationship between each breakdown voltage (vertical axis) and the irradiation amount (horizontal axis). The tendency for the breakdown voltage to decrease with increasing irradiation dose is
Almost the same for proton and helium ion. On the other hand, with helium ion irradiation, even if the irradiation amount is the same as that of protons, defects larger than those of proton irradiation are created. In order to generate the same defect density, helium ion irradiation can reduce the irradiation amount as compared with proton irradiation, and as shown in FIG.

【0022】[0022]

【表1】 [Table 1]

【0023】表1は、低ライフタイム層形成の代表的な
データを比べるための比較表である。すなわち処理方法
としては、(a)未照射の場合、(b)電子線を、白金
拡散した基板に、加速エネルギー5MeV、照射量5×
1013atoms/cm2 で照射した場合、(c)プロトン 1
+ を、加速エネルギー1.5MeV、照射量5×10
12 atoms/cm2 で照射した後、400℃10分間の熱処
理を施した場合、(d)ヘリウムイオン 3He 2+を加速
エネルギー6MeV、照射量1×1012 atoms/cm2
照射した後、300℃10分間の熱処理を施した場合の
4つに区分する。各処理方法ごとに複数個のサンプルを
作成し、スイッチング速度trrとオン電圧VF を測定
し、平均値を求める。測定条件は図2に示す試行例と同
じである。また比較を容易にするため、未照射の素子の
rrまたはVF の値を1とし、他の処理方法による素子
のtrrまたはVF の相対値を計算する。表1はこれらの
データをまとめたものである。表1のようにヘリウムイ
オン 3He 2+照射の場合には、スイッチング速度trr
未照射素子の12%、オン電圧VF は1.2倍と従来の
技術と比べて高速化及び低オン電圧化が達成される。
Table 1 is a comparison table for comparing representative data of low lifetime layer formation. That is, as the treatment method, (a) in the case of non-irradiation, (b) the substrate on which the electron beam was platinum-diffused, the acceleration energy was 5 MeV, and the dose was 5 ×
When irradiated with 10 13 atoms / cm 2 , (c) 1 proton
H + , acceleration energy 1.5 MeV, irradiation dose 5 × 10
When heat treatment is performed at 400 ° C. for 10 minutes after irradiation with 12 atoms / cm 2 , (d) helium ion 3 He 2+ is irradiated with an acceleration energy of 6 MeV and a dose of 1 × 10 12 atoms / cm 2 , It is classified into four cases when heat treatment is performed at 300 ° C. for 10 minutes. Create a plurality of samples for each treatment method, to measure the switching speed t rr and the ON voltage V F, the average value. The measurement conditions are the same as in the trial example shown in FIG. Further, in order to facilitate the comparison, the value of trr or V F of the unirradiated element is set to 1, and the relative value of trr or V F of the element by another processing method is calculated. Table 1 summarizes these data. As shown in Table 1, in the case of helium ion 3 He 2+ irradiation, the switching speed trr is 12% that of the unirradiated element, and the on-voltage V F is 1.2 times, which is faster and lower on-state than the conventional technology. Voltage conversion is achieved.

【0024】なお前記実施例は、P+ N型スイッチング
用ダイオードについて述べてあるが、本発明はパワート
ランジスタ、サイリスタ(GTO等を含む)及びその他
の電力制御用半導体デバイスに用いることがでる。
Although the above embodiment describes the P + N type switching diode, the present invention can be applied to power transistors, thyristors (including GTO etc.) and other power control semiconductor devices.

【0025】[0025]

【発明の効果】これまで述べたように、本発明において
は、ヘリウムイオン 3He 2+を照射することにより低ラ
イフタイム層を形成するので、従来技術に比しより狭い
半値幅の低ライフタイム層の局在化を可能とすると共
に、高温の熱処理を必要としないプロセスにより、従来
のプロトン照射、電子線照射等に比べてオン電圧V
F (またはVon)及びスイッチング速度trr(またはt
off )が共に向上する半導体装置の製造方法と、その製
造方法により製造された半導体装置を提供することがで
きた。
As described above, in the present invention, since the low lifetime layer is formed by irradiating the helium ion 3 He 2+ , the half lifetime is narrower than that of the prior art. The on-state voltage V is higher than that of conventional proton irradiation, electron beam irradiation, etc. by the process that enables localization of the layer and does not require high temperature heat treatment.
F (or V on ) and switching speed t rr (or t
It was possible to provide a method for manufacturing a semiconductor device in which both off ) are improved and a semiconductor device manufactured by the manufacturing method.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明を適用した半導体装置(一例)の断面図
である。
FIG. 1 is a cross-sectional view of a semiconductor device (an example) to which the present invention is applied.

【図2】本発明及び従来技術それぞれの方法による半導
体装置のスイッチング速度とオン電圧との関係を示す特
性図である。
FIG. 2 is a characteristic diagram showing a relationship between a switching speed and an ON voltage of a semiconductor device according to the methods of the present invention and the related art.

【図3】本発明の方法による半導体装置の基板表面から
の深さと相対欠陥密度とを示す特性図である。
FIG. 3 is a characteristic diagram showing the depth from the substrate surface and the relative defect density of the semiconductor device according to the method of the present invention.

【図4】本発明の方法による半導体装置の熱処理温度を
パラメータとしたときのリーク電流と熱処理時間との関
係を示す特性図である。
FIG. 4 is a characteristic diagram showing the relationship between the leak current and the heat treatment time when the heat treatment temperature of the semiconductor device according to the method of the present invention is used as a parameter.

【図5】本発明及び従来技術それぞれの半導体装置の耐
圧と照射量との関係を示す特性図である。
FIG. 5 is a characteristic diagram showing the relationship between the withstand voltage and the dose of semiconductor devices of the present invention and the prior art.

【図6】従来技術を適用した半導体装置の断面図であ
る。
FIG. 6 is a cross-sectional view of a semiconductor device to which a conventional technique is applied.

【図7】図1または図6に示す半導体装置のターンオフ
時の電流波形を示す図である。
7 is a diagram showing a current waveform when the semiconductor device shown in FIG. 1 or 6 is turned off.

【符号の説明】[Explanation of symbols]

1 N型半導体基板 2 P+ 拡散層 6 低ライフタイム層(従来) 7 低ライフタイム層(本発明) trr スイッチング速度 VF オン電圧 w 低ライフタイム層の半値幅1 N-type semiconductor substrate 2 P + diffusion layer 6 Low lifetime layer (conventional) 7 Low lifetime layer (present invention) t rr Switching speed V F ON voltage w Half-width of low lifetime layer

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】半導体基板内の所定領域に、ヘリウムイオ
3He2+を照射する工程を、具備することを特徴とす
る半導体装置の製造方法。
1. A method of manufacturing a semiconductor device, comprising the step of irradiating a predetermined region in a semiconductor substrate with helium ions 3 He 2+ .
【請求項2】ヘリウムイオン 3He 2+の加速エネルギー
を1MeVないし40MeVとし、かつ照射量を1×1
9 atoms/cm2 ないし5×1013 atoms/cm2 とする
請求項1記載の半導体装置の製造方法。
2. The helium ion 3 He 2+ acceleration energy is 1 MeV to 40 MeV, and the irradiation dose is 1 × 1.
The method for manufacturing a semiconductor device according to claim 1, wherein the amount is set to 0 9 atoms / cm 2 to 5 × 10 13 atoms / cm 2 .
【請求項3】ヘリウムイオン 3He 2+を照射した後、該
半導体基板を300℃ないし400℃に加熱することを
特徴とする請求項1または請求項2いずれか記載の半導
体装置の製造方法。
3. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor substrate is heated to 300 ° C. to 400 ° C. after irradiation with helium ions 3 He 2+ .
【請求項4】請求項1、請求項2及び請求項3いずれか
記載の製造方法により製造された半導体装置。
4. A semiconductor device manufactured by the manufacturing method according to claim 1, claim 2, or claim 3.
JP19998991A 1991-07-15 1991-07-15 Manufacture of semiconductor device, and the semiconductor device Pending JPH05102161A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Application Number Priority Date Filing Date Title
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Publications (1)

Publication Number Publication Date
JPH05102161A true JPH05102161A (en) 1993-04-23

Family

ID=16416945

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Link
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* Cited by examiner, † Cited by third party
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EP0497290A2 (en) * 1991-01-28 1992-08-05 Kabushiki Kaisha Toshiba Switching semiconductor device and method of manufacturing the same
EP0689251A1 (en) * 1994-06-20 1995-12-27 Semikron Elektronik Gmbh Quick power diode
EP0694960A1 (en) * 1994-07-25 1996-01-31 Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno - CoRiMMe Process for the localized reduction of the lifetime of charge carriers
US5707879A (en) * 1997-01-08 1998-01-13 Reinitz; Karl Neutron detector based on semiconductor materials
WO1998020525A1 (en) * 1996-11-06 1998-05-14 Southwest Research Institute Suppression of transient enhanced diffusion in ion implanted silicon
WO1999009600A1 (en) * 1997-08-14 1999-02-25 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and method for manufacturing the same
EP0982768A1 (en) * 1998-08-21 2000-03-01 Asea Brown Boveri AG Process for adjusting the carrier lifetime in a semiconductor device
WO2007055352A1 (en) * 2005-11-14 2007-05-18 Fuji Electric Device Technology Co., Ltd. Semiconductor device and method for manufacturing same
JP2009239269A (en) * 1998-08-05 2009-10-15 Memc Electron Materials Inc Non-uniform minority carrier lifetime distribution in high performance silicon power device
US7781294B2 (en) 2006-07-31 2010-08-24 Infineon Technologies Austria Ag Method for producing an integrated circuit including a semiconductor
US7919790B2 (en) 2008-02-08 2011-04-05 Fuji Electric Systems Co., Ltd. Semiconductor device and method of producing the same
JP2012165013A (en) * 2012-04-26 2012-08-30 Fuji Electric Co Ltd Semiconductor device and manufacturing method of the same
JP2014060426A (en) * 2013-11-08 2014-04-03 Fuji Electric Co Ltd Semiconductor device and method for manufacturing the same
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Cited By (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0497290A3 (en) * 1991-01-28 1995-11-29 Toshiba Kk Switching semiconductor device and method of manufacturing the same
EP0497290A2 (en) * 1991-01-28 1992-08-05 Kabushiki Kaisha Toshiba Switching semiconductor device and method of manufacturing the same
EP0689251A1 (en) * 1994-06-20 1995-12-27 Semikron Elektronik Gmbh Quick power diode
US6168981B1 (en) 1994-07-25 2001-01-02 Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno Method and apparatus for the localized reduction of the lifetime of charge carriers, particularly in integrated electronic devices
EP0694960A1 (en) * 1994-07-25 1996-01-31 Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno - CoRiMMe Process for the localized reduction of the lifetime of charge carriers
US5900652A (en) * 1994-07-25 1999-05-04 Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno Apparatus for the localized reduction of the lifetime of charge carriers, particularly in integrated electronic devices
WO1998020525A1 (en) * 1996-11-06 1998-05-14 Southwest Research Institute Suppression of transient enhanced diffusion in ion implanted silicon
US5759904A (en) * 1996-11-06 1998-06-02 Southwest Research Institute Suppression of transient enhanced diffusion in ion implanted silicon
US5707879A (en) * 1997-01-08 1998-01-13 Reinitz; Karl Neutron detector based on semiconductor materials
US6603189B2 (en) 1997-08-14 2003-08-05 Mitsubishi Denki Kabushiki Kaisha Semiconductor device with deliberately damaged layer having a shorter carrier lifetime therein
WO1999009600A1 (en) * 1997-08-14 1999-02-25 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and method for manufacturing the same
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JP2009239269A (en) * 1998-08-05 2009-10-15 Memc Electron Materials Inc Non-uniform minority carrier lifetime distribution in high performance silicon power device
US6475876B2 (en) 1998-08-21 2002-11-05 Abb Schweiz Holding Ag Process for fabricating a semiconductor component
EP0982768A1 (en) * 1998-08-21 2000-03-01 Asea Brown Boveri AG Process for adjusting the carrier lifetime in a semiconductor device
US7799662B2 (en) 2005-11-14 2010-09-21 Fuji Electric Systems Co., Ltd. Power semiconductor device with soft switching characteristic and manufacturing method for same
WO2007055352A1 (en) * 2005-11-14 2007-05-18 Fuji Electric Device Technology Co., Ltd. Semiconductor device and method for manufacturing same
US7781294B2 (en) 2006-07-31 2010-08-24 Infineon Technologies Austria Ag Method for producing an integrated circuit including a semiconductor
DE102006035630B4 (en) * 2006-07-31 2012-12-06 Infineon Technologies Austria Ag Method for producing a semiconductor component
US7919790B2 (en) 2008-02-08 2011-04-05 Fuji Electric Systems Co., Ltd. Semiconductor device and method of producing the same
US8076173B2 (en) 2008-02-08 2011-12-13 Fuji Electric Co., Ltd. Semiconductor device and method of producing the same
JP2012165013A (en) * 2012-04-26 2012-08-30 Fuji Electric Co Ltd Semiconductor device and manufacturing method of the same
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