JPH01272158A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPH01272158A
JPH01272158A JP10060488A JP10060488A JPH01272158A JP H01272158 A JPH01272158 A JP H01272158A JP 10060488 A JP10060488 A JP 10060488A JP 10060488 A JP10060488 A JP 10060488A JP H01272158 A JPH01272158 A JP H01272158A
Authority
JP
Japan
Prior art keywords
region
anode
cathode
buried
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10060488A
Other languages
Japanese (ja)
Inventor
Takuji Keno
毛野 拓治
Kazuyuki Tomii
富井 和志
Yasunori Miyamoto
宮本 靖典
Takuya Komoda
卓哉 菰田
Mitsuhide Maeda
前田 光英
Yuji Suzuki
裕二 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP10060488A priority Critical patent/JPH01272158A/en
Publication of JPH01272158A publication Critical patent/JPH01272158A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To obtain a semiconductor device having a small leakage current and a short turn-off period with low degree of irregularity by a method wherein a buried region having the conductivity reverse to an anode region is provided at the position opposing to the cathode region in an anode region. CONSTITUTION:A thyristor 1 is equipped with an anode region 2 provided on the rear surface of a semiconductor substrate 1a, a cathode region 4 provided on the surface, and a gate region 5, and a high specific resistance region 3 to be used as a current path, is provided between the anode region 2 and the cathode region 4. On the thyristor 1, a buried region 6 with which the life of a charged carrier (a hole in this case) is provided on the position opposite to the cathode region 4 in the anode region 2. The buried region 6 in the impurity region of the conductivity reverse to that of the anode region 2. As a result, a hole is instantaneously vanished by the above-mentioned buried region 6 without increasing a leakage current, and the region 6 works to shorten the turn-off period. Moreover, as the density of impurities is in an excellently uniform state, the degree of irregularity in the turn-off period is small.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は半導体装置およびその製法に関する〔従来の
技術〕 半導体装置として、静電誘導サイリスクや絶縁ゲート型
バイポーラトランジスタ(IGBT)のように、アノー
ド領域とカソード領域の間に、アノード領域と逆導電型
の高比抵抗領域を備え、同高比抵抗領域を流れる電流が
ゲート電極に印加される電圧に応じて制御され、電子と
正札の両方の荷電担体がキャリアとなっている装置があ
る。例えば、静電誘導サイリスクは、第3図にみるよう
な構成である。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device and its manufacturing method [Prior Art] As a semiconductor device, an anode, such as a static induction silice or an insulated gate bipolar transistor (IGBT), A high resistivity region of the opposite conductivity type to the anode region is provided between the region and the cathode region, and the current flowing through the high resistivity region is controlled according to the voltage applied to the gate electrode, so that both electrons and the genuine tag There are devices in which charge carriers serve as carriers. For example, an electrostatic induction cyrisk has a configuration as shown in FIG.

静電誘導サイリスタ20は、アノード領域21とカソー
ド領域23の間に高比抵抗領域(ベース領域)22を備
え、カソード領域23の近傍にゲート領域24を備えて
いる。もちろん各領域21.23.24には電極21′
、23′、24′が、それぞれ設けられている。この静
電誘導サイリスタ20は、電流密度が大きく、かつ、順
方向電圧降下(オン抵抗)が小さく、しかも、ターンオ
ン時間が短いという特徴を有する。しかしながら、遮断
時は、アノード側から注入される正孔を瞬時にして断て
ないため、ターンオフ時間が、例えば、MOS F E
T等に比べて長い(通常、数μs〜数十μs程度)とい
う問題がある。
The electrostatic induction thyristor 20 includes a high resistivity region (base region) 22 between an anode region 21 and a cathode region 23, and a gate region 24 near the cathode region 23. Of course, each region 21, 23, 24 has an electrode 21'
, 23', and 24' are provided, respectively. This electrostatic induction thyristor 20 has the characteristics of high current density, low forward voltage drop (on resistance), and short turn-on time. However, when shutting off, the holes injected from the anode side are not instantaneously cut off, so the turn-off time is shortened, for example, when the MOS F E
There is a problem that it is longer than T, etc. (usually about several μs to several tens of μs).

従来、ターンオフ時間を短くするために、高比抵抗領域
内に電子線やプロトンを照射して格子欠陥領域を形成し
たり、金や白金等の重金属を拡散してライフタイムキラ
ー領域を形成したりすることが行われている。格子欠陥
領域やライフタイムキラー領域はターンオフ時にアノー
ド側から注入されてくる正孔を直ちに消滅させるため、
ターンオフ時間が短くなる。
Conventionally, in order to shorten the turn-off time, electron beams or protons are irradiated into the high resistivity region to form a lattice defect region, or heavy metals such as gold or platinum are diffused to form a lifetime killer region. things are being done. The lattice defect region and lifetime killer region immediately annihilate holes injected from the anode side at turn-off.
Turn-off time becomes shorter.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかしながら、前記の格子欠陥領域の形成やう・イフタ
イムキラー領域の形成は、逆方向リーク電流の増加とい
う半導体装置の性能低下を伴う。
However, the formation of the lattice defect region and the if-time killer region are accompanied by a decrease in the performance of the semiconductor device, such as an increase in reverse leakage current.

しかも、電子線やプロトンの照射による格子欠陥領域の
形成や重金属の拡散によるライフタイムキラー領域の形
成は、その欠陥濃度や重金属濃度を一定に揃えることが
難しいために、ターンオフ時間のバラツキが大きい。
Moreover, in the formation of lattice defect regions by electron beam or proton irradiation and the formation of lifetime killer regions by heavy metal diffusion, it is difficult to keep the defect concentration and heavy metal concentration constant, so the turn-off time varies widely.

この発明は、上記事情に鑑み、リーク電流が少なく、し
かも、短くてバラツキの少ないターンオフ時間を有する
半導体装置とその製法を提供することを課題とする。
SUMMARY OF THE INVENTION In view of the above circumstances, it is an object of the present invention to provide a semiconductor device having a low leakage current and a short turn-off time with little variation, and a method for manufacturing the same.

〔課題を解決するための手段〕[Means to solve the problem]

前記課題を解決するため、請求項1記載の半導体装置は
、半導体基板の一例にアノード領域を、他側にカソード
領域を備え、円領域の間に電流通路となる高比抵抗領域
を備えている構成において、前記アノード領域における
カソード領域と相対する位置に、同アノード領域と逆導
電型の埋め込み領域を設けるようにしている。
In order to solve the above problem, a semiconductor device according to a first aspect of the present invention includes an anode region on one side of the semiconductor substrate, a cathode region on the other side, and a high resistivity region between the circular regions that serves as a current path. In the structure, a buried region of a conductivity type opposite to that of the anode region is provided at a position facing the cathode region in the anode region.

請求項2に記載の半導体装置の製法では、アノード領域
の全厚みのうち一部の厚みを有する半導体基板を用い、
カソード領域と相対する個所に逆導電型の不純物領域を
形成した後、前記アノード領域の残りの厚み分を積層す
る工程を含むようにしている。
In the method for manufacturing a semiconductor device according to claim 2, a semiconductor substrate having a thickness of a part of the total thickness of the anode region is used,
The method includes a step of forming an impurity region of the opposite conductivity type in a portion facing the cathode region, and then laminating the remaining thickness of the anode region.

〔作   用〕[For production]

請求項1記載の半導体装置は、アノード領域において、
ターンオフ時に荷電担体(例えば、正孔)が多く残るカ
ソード領域に相対する位置に、逆導電型の埋め込み領域
があり、ターンオフ時、同埋め込み領域がアノード領域
内での正孔の再結合が効果的に促進されるなどして、正
孔は極めて短い間に消滅してしまう。しかも、基板内に
は、リーク電流の増加を伴う格子欠陥領域や重金属の拡
散領域がなく、あるのは、精度良く不純物濃度制御がで
きる逆導電型の埋め込み不純物領域だけである。
In the semiconductor device according to claim 1, in the anode region,
There is a buried region of the opposite conductivity type in a position opposite to the cathode region where many charge carriers (for example, holes) remain during turn-off, and during turn-off, the buried region effectively recombines the holes in the anode region. As a result, the holes disappear in an extremely short period of time. Furthermore, there is no lattice defect region or heavy metal diffusion region in the substrate that would cause an increase in leakage current, and there is only a buried impurity region of the opposite conductivity type that allows for precise control of impurity concentration.

請求項2記載の発明では、アノード領域の全厚みのうち
一部の厚み分を有する基板の、カソード領域に相対する
個所に逆導電型の不純物領域を形成し、ついで、アノー
ド領域の残りの厚み分を積層している。残りの厚み分の
積層により、不純物領域が埋め込まれるので、埋め込み
領域がアノード領域内に形成される。
In the invention according to claim 2, an impurity region of an opposite conductivity type is formed in a portion of the substrate having a part of the total thickness of the anode region facing the cathode region, and then a part of the remaining thickness of the anode region is formed. The parts are laminated. The impurity region is buried by the remaining thickness of the stack, so that a buried region is formed in the anode region.

埋め込み領域の形成は、不純物拡散と半導体層の積層(
例えば、エピタキシャル成長)等、半導体装置の製法で
極く普通に用いられている工程であり、しかも、不純物
拡散領域での不純物濃度の制御は、格子欠陥密度や重金
属濃度の制御に比べて容易である。
The buried region is formed by impurity diffusion and semiconductor layer stacking (
This is a process that is extremely commonly used in the manufacturing of semiconductor devices, such as epitaxial growth (e.g., epitaxial growth), and it is easier to control the impurity concentration in the impurity diffusion region than to control the lattice defect density or heavy metal concentration. .

さらに、この請求項2記載の発明では、埋め込み領域形
成用の不純物拡散は浅く拡散時間が短くてすむ、不純物
領域の埋め込みをアノード領域の残りの厚分の81層に
より行うからである。拡散時間が短い場合は、拡散時間
が長い場合に比べて、完成した不純物領域自体のバラツ
キが少ない。領域のデイメンジョンや不純物濃度が良く
揃うのである。
Furthermore, in the invention as claimed in claim 2, the impurity diffusion for forming the buried region is shallow and the diffusion time is short, because the impurity region is buried in 81 layers of the remaining thickness of the anode region. When the diffusion time is short, there are fewer variations in the completed impurity region itself than when the diffusion time is long. The dimensions and impurity concentrations of the regions are well matched.

〔実 施 例〕〔Example〕

以下、この発明にかかる半導体装置およびその製法を、
その一実施例をあられす図面を参照しながら、装置、続
いて製法という順で説明する。
Hereinafter, the semiconductor device and its manufacturing method according to the present invention will be described.
One embodiment of the invention will be described in the order of the apparatus and the manufacturing method, with reference to the accompanying drawings.

第1図は、請求項1記載の半導体装置の一例である静電
誘導サイリスタ(以下、「サイリスク」という)をあら
れす。
FIG. 1 shows an electrostatic induction thyristor (hereinafter referred to as "thyristor") which is an example of a semiconductor device according to a first aspect of the present invention.

サイリスタ1は、半導体基板1aの裏面(−例)に設け
られたアノード領域2と、この基板1aの表面(他側)
に設けられたカソード領域4およびゲート領域5とを備
えている。電流通路となる高比抵抗領域3はアノード領
域2とカソード領域4の間に設けられている。この高比
抵抗領域(ベース領域とも称される)3は真性半導体層
であってもよいことはいうまでもない。アノード領域2
にはアノード電極2′が、カソード領域4にはカソード
電極4′が、ゲート領域5にはゲート電極5′が、それ
ぞれ設けられている。このサイリスタ1では、ゲート電
極5′に印加される電圧を調節することにより、高比抵
抗領域3を制御(いわゆる電導変調)して、導通・遮断
動作がなされるサイリスタ1では、荷電担体(この場合
は正孔)寿命を縮める埋め込み領域6が、アノード領域
2におけるカソード領域4と相対する位置に設けられて
いる。同埋め込み領域6は、アノード領域2と逆導電型
の不純物領域である。そのため、この埋め込み領域6が
リーク電流の増加を伴わずに、正孔を瞬時にして消滅さ
せ、ターンオフ時間を縮める作用をすることは、上で説
明した通りである。しかも、不純物濃度は良く一定に揃
っているため、ターンオフ時間のバラツキも少ない。
The thyristor 1 includes an anode region 2 provided on the back surface (-example) of a semiconductor substrate 1a, and a surface (other side) of the substrate 1a.
A cathode region 4 and a gate region 5 are provided. A high resistivity region 3 serving as a current path is provided between the anode region 2 and the cathode region 4. It goes without saying that this high resistivity region (also referred to as a base region) 3 may be an intrinsic semiconductor layer. Anode area 2
, an anode electrode 2' is provided in the cathode region 4, a cathode electrode 4' is provided in the cathode region 4, and a gate electrode 5' is provided in the gate region 5, respectively. In this thyristor 1, the high resistivity region 3 is controlled (so-called conduction modulation) by adjusting the voltage applied to the gate electrode 5' to conduct conduction/cutoff operations. A buried region 6 that shortens the lifetime (in case of holes) is provided at a position opposite to the cathode region 4 in the anode region 2 . The buried region 6 is an impurity region of a conductivity type opposite to that of the anode region 2. Therefore, as described above, the buried region 6 acts to instantly eliminate holes and shorten the turn-off time without increasing leakage current. Moreover, since the impurity concentration is well kept constant, there is little variation in the turn-off time.

続いて、請求項2記載の半導体装置の製法の一例による
サイリスク製造について説明する。
Next, a description will be given of the production of SIRISK according to an example of the method for producing a semiconductor device according to the second aspect.

まず、第2図(a)にみるように、P層の上にN−層が
ある半導体基板10を準備する。Pffiはアノード領
域の一部の厚み分である。一方、N−層は高比抵抗領域
となるが、もちろん、ゲート領域およびカソード領域が
形成される。請求項2記載の発明では、半導体基板とし
て、このように、アノード領域の全厚みのうち一部の厚
みを有するものを用いて製造を行うようにする。
First, as shown in FIG. 2(a), a semiconductor substrate 10 having an N- layer on a P layer is prepared. Pffi is the thickness of a portion of the anode region. On the other hand, the N- layer becomes a high resistivity region, and of course, a gate region and a cathode region are formed therein. According to the second aspect of the invention, the semiconductor substrate is manufactured using a semiconductor substrate having a thickness that is a part of the total thickness of the anode region.

ついで、N−層表面にマスク(図示省略)を設け、不純
物を選択拡散することにより、第2図(b)に示すよう
に、ゲート領域5を形成する。ゲート領域5形成後、第
2図(b)にみるように、N−層表面のSi0g膜にカ
ソード領域形成用の不純物を拡散するための窓12を明
け、一方、P層表面の5t(h膜には埋め込み領域形成
用の不純物を拡散するための窓14を明ける。窓14は
窓12の直下にあるように明けられる。つまり、窓12
を備えたマスク11と窓14を備えたマスク13を形成
するのである。
Next, a mask (not shown) is provided on the surface of the N- layer and impurities are selectively diffused to form a gate region 5 as shown in FIG. 2(b). After the formation of the gate region 5, as shown in FIG. A window 14 is formed in the film for diffusing impurities for forming a buried region.The window 14 is formed directly below the window 12.
A mask 11 with a window 14 and a mask 13 with a window 14 are formed.

マスク11.13を形成した後、N型用の不純物を注入
拡散する。そうすると、第2図(C1にみるように、N
゛型不純物領域ができる。窓工2に形成されたN゛領域
カソード領域4であり、窓14に形成されたN“領域6
′は埋め込み領域になる。Nゝ領域6′は、丁度、カソ
ード領域4に相対する位置にある。窓14が窓12の直
下にあったからである。
After forming masks 11 and 13, N-type impurities are implanted and diffused. Then, as shown in Figure 2 (C1), N
A type impurity region is formed. N' region cathode region 4 formed in the window 2, and N" region 6 formed in the window 14.
' becomes the embedding area. The N area 6' is located exactly opposite the cathode area 4. This is because the window 14 was directly below the window 12.

裏面のマスク13をエツチング除去した後、P層の上に
C5tlB = 10 ”儂゛3以上の濃度でP”Nを
積石する。そうすると、第2図(d)にみるように、ア
ノード領域2と埋め込み領域6が完成することとなる。
After removing the mask 13 on the back surface by etching, P''N is deposited on the P layer at a concentration of C5tlB = 10'' or more. Then, as shown in FIG. 2(d), the anode region 2 and the buried region 6 are completed.

最終的には、第1図のサイリスタ1と同様、各電極を形
成してサイリスタを完成させるようにする。
Finally, each electrode is formed to complete the thyristor, similar to the thyristor 1 shown in FIG. 1.

このようにして、前記の利点を有するサイリスクを作成
することができるのである。
In this way, it is possible to create a cyrisk with the advantages mentioned above.

上に説明した製法の一例では、マスク11.13を形成
する際の窓12.14が明く個所以外のところを覆うレ
ジストを両5ins膜上に形成するまでは、個別の作業
で行うが、それ以後、5iOi膜をエツチングして窓1
2.14を明けたり、窓12.14に不純物領域を形成
したりするのは同時に行える。したがって、作業として
は、P層表面のマスク13形成用のパターン化レジスト
を設ける作業と、P+層をエピタキシャル成長させる作
業が増える程度である。
In the example of the manufacturing method described above, the steps up to forming a resist on both 5ins films to cover areas other than the areas where the windows 12.14 are bright when forming the mask 11.13 are performed in separate operations. After that, the 5iOi film was etched to form the window 1.
Opening the window 2.14 and forming an impurity region in the window 12.14 can be performed at the same time. Therefore, the only additional work required is the work of providing a patterned resist for forming the mask 13 on the surface of the P layer and the work of epitaxially growing the P+ layer.

なお、第1図および第2図(d)では、便宜上、図面で
はアノード領域2全体をP“眉として表しているが、高
比抵抗領域3寄りでは厳密にはPJiである。先に形成
したアノード領域の一部厚み分が2層であるからである
。アノード領域2の先に形成した一部厚みを、後で積む
P゛層よりも少し不純物濃度が低い2層にするのは、先
のPMで、もし不純物濃度が余り高いと、N型用不純物
を拡散しても、P型不純物で帳消しされる量が多くなり
、N+領領域変えるのが難しい場合があるためである。
In addition, in FIG. 1 and FIG. 2(d), for convenience, the entire anode region 2 is represented as P'' in the drawings, but strictly speaking, it is PJi near the high resistivity region 3. This is because a part of the thickness of the anode region 2 is made up of two layers.The reason why the part of the thickness formed before the anode region 2 is made into two layers with a slightly lower impurity concentration than the P' layer to be stacked later is to This is because if the impurity concentration is too high in PM, even if N-type impurities are diffused, a large amount will be canceled out by P-type impurities, making it difficult to change the N+ region.

もちろん、先に形成するアノード領域の一部厚み分がP
“層であってもよい。また、逆に、後に積まれるアノー
ド領域の残り分がPMであってもよい。
Of course, a portion of the thickness of the anode region formed first is P
Conversely, the remaining portion of the anode region to be deposited later may be PM.

この発明は上記実施例に限らない。例えば、サイリスタ
が、第1図に示すような表面ゲート型でなく、いわゆる
埋め込みゲート型等の他の構造のものであってもよい。
This invention is not limited to the above embodiments. For example, the thyristor may not be of the surface gate type as shown in FIG. 1, but may have another structure such as a so-called buried gate type.

半導体装置も、絶縁ゲート型バイポーラトランジスタ等
の他の種類の半導体装置であってもよい。なお、トラン
ジスタの場合は、通常、カソード領域はソース領域と、
アノード領域はドレイン領域と称される。
The semiconductor device may also be another type of semiconductor device such as an insulated gate bipolar transistor. Note that in the case of a transistor, the cathode region is usually the source region,
The anode region is called the drain region.

〔発明の効果〕〔Effect of the invention〕

上記で説明した請求項1記載の半導体装置は、以下の効
果を奏する。
The semiconductor device according to the first aspect described above has the following effects.

ターンオフ動作の際、荷電担体が多く残るカソード領域
に相対する位置に、逆導電型の埋め込み層があり、同埋
め込み層が荷電担体の再結合を促進するなどして瞬時に
消滅させるため、ターンオフ時間が短い。
During the turn-off operation, there is a buried layer of the opposite conductivity type in a position opposite to the cathode region where many charge carriers remain, and this buried layer promotes the recombination of charge carriers and instantly eliminates them, so the turn-off time is shortened. is short.

格子欠陥領域やライフタイムキラー領域がないため、リ
ーク電流が少ない。
There are no lattice defect regions or lifetime killer regions, so leakage current is low.

埋め込み領域の不純物濃度は比較的良く揃うため、ター
ンオフ時間のバラツキが少ない。
Since the impurity concentration in the buried region is relatively well aligned, there is little variation in turn-off time.

請求項2記載の発明は、上記の効果を有する半導体装置
を得ることができる他に、下記のような効果がある。
The invention according to claim 2 provides the following effects in addition to being able to obtain a semiconductor device having the above effects.

埋め込み領域形成に必要な工程が、不純物の拡散や半導
体層の積層等、半導体製造で極く普通に用いられる工程
ばかりであるから、半導体装置の製造は容易である。
The manufacturing of the semiconductor device is easy because the steps required to form the buried region are those commonly used in semiconductor manufacturing, such as diffusion of impurities and lamination of semiconductor layers.

埋め込み領域形成の際の不純物拡散は浅く行うだけであ
るから、埋め込み領域自体のバラツキが少なく、−層、
ターンオフ時間のバラツキが少なくなる。
Since the impurity diffusion when forming the buried region is only performed shallowly, there is little variation in the buried region itself, and the
Variations in turn-off time are reduced.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、請求項1記載の発明の半導体装置の一例のサ
イリスタをあられす縦断面図、第2図(a)〜Td)は
、このサイリスクを請求項2記載の発明の半導体装置の
製法の一例により製造するときの様子を工程順にあられ
す縦断面図、第3図は、サイリスタの基本構成をあられ
す縦断面図である。 ■・・・サイリスク(半導体装置)   la・・・半
導体基板 2・・・アノード領域  3・・・高比抵抗
領域4・・・カソード領域  6・・・埋め込み領域 
 lO・・・アノード領域の全厚みのうち一部の厚みを
有する半導体基板 代理人 弁理士  松 本 武 彦 第2図 (b) 第2図 (C) (d)
FIG. 1 is a vertical cross-sectional view of a thyristor as an example of a semiconductor device according to the invention as claimed in claim 1, and FIGS. FIG. 3 is a vertical cross-sectional view showing the basic structure of a thyristor in the order of steps during manufacturing according to an example. ■...Sirisk (semiconductor device) la...Semiconductor substrate 2...Anode region 3...High resistivity region 4...Cathode region 6...Buried region
lO... Semiconductor substrate having a part of the total thickness of the anode region Patent attorney Takehiko Matsumoto Figure 2 (b) Figure 2 (C) (d)

Claims (1)

【特許請求の範囲】 1 半導体基板の一側にアノード領域を、他側にカソー
ド領域を備え、両領域の間に電流通路となる高比抵抗領
域を備えている半導体装置において、前記アノード領域
におけるカソード領域と相対する位置に、同アノード領
域と逆導電型の埋め込み領域が設けられていることを特
徴とする半導体装置。 2 半導体基板の一側にアノード領域を、他側にカソー
ド領域を備え、両領域の間に電流通路となる高比抵抗領
域を備えている半導体装置を製造する方法において、前
記アノード領域の全厚みのうち一部の厚みを有する半導
体基板を用い、前記カソード領域と相対する個所に逆導
電型の不純物領域を形成した後、前記アノード領域の残
りの厚み分を積層する工程を含むことを特徴とする半導
体装置の製法。
[Scope of Claims] 1. A semiconductor device comprising an anode region on one side of a semiconductor substrate, a cathode region on the other side, and a high resistivity region serving as a current path between the two regions. A semiconductor device characterized in that a buried region of a conductivity type opposite to that of the anode region is provided at a position facing the cathode region. 2. In a method for manufacturing a semiconductor device comprising an anode region on one side of a semiconductor substrate, a cathode region on the other side, and a high resistivity region serving as a current path between the two regions, the total thickness of the anode region using a semiconductor substrate having a thickness of a part of the thickness, forming an impurity region of an opposite conductivity type in a portion facing the cathode region, and then laminating the remaining thickness of the anode region. A manufacturing method for semiconductor devices.
JP10060488A 1988-04-23 1988-04-23 Semiconductor device and manufacture thereof Pending JPH01272158A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10060488A JPH01272158A (en) 1988-04-23 1988-04-23 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10060488A JPH01272158A (en) 1988-04-23 1988-04-23 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH01272158A true JPH01272158A (en) 1989-10-31

Family

ID=14278467

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10060488A Pending JPH01272158A (en) 1988-04-23 1988-04-23 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH01272158A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6787420B2 (en) 1998-11-12 2004-09-07 Fuji Electric Co., Ltd. Semiconductor device with alternating conductivity type layer and method of manufacturing the same
US6815766B2 (en) 1999-01-11 2004-11-09 Fuji Electric Co., Ltd. Semiconductor device with alternating conductivity type layer and method of manufacturing the same
US6900109B2 (en) 1999-10-20 2005-05-31 Fuji Electric Co., Ltd. Method of manufacturing a semiconductor device with a vertical drain drift layer of the alternating-conductivity-type
US7002205B2 (en) 2000-02-09 2006-02-21 Fuji Electric Device Technology Co., Ltd. Super-junction semiconductor device and method of manufacturing the same

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6787420B2 (en) 1998-11-12 2004-09-07 Fuji Electric Co., Ltd. Semiconductor device with alternating conductivity type layer and method of manufacturing the same
US6815766B2 (en) 1999-01-11 2004-11-09 Fuji Electric Co., Ltd. Semiconductor device with alternating conductivity type layer and method of manufacturing the same
US6900109B2 (en) 1999-10-20 2005-05-31 Fuji Electric Co., Ltd. Method of manufacturing a semiconductor device with a vertical drain drift layer of the alternating-conductivity-type
US7002205B2 (en) 2000-02-09 2006-02-21 Fuji Electric Device Technology Co., Ltd. Super-junction semiconductor device and method of manufacturing the same
US7042046B2 (en) 2000-02-09 2006-05-09 Fuji Electric Device Technology Co., Ltd. Super-junction semiconductor device and method of manufacturing the same

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