JP4710822B2 - Super junction semiconductor device - Google Patents

Description

  The present invention relates to a MOSFET (insulated gate field effect transistor), IGBT (insulated gate bipolar transistor), bipolar transistor having a special vertical structure composed of a parallel pn layer that flows current in the on state and depletes in the off state. The present invention relates to a semiconductor element such as a diode.

  In a vertical semiconductor element in which current flows between electrodes provided on two opposing main surfaces, in order to achieve high breakdown voltage, the thickness of the high resistance layer between both electrodes must be increased, On the other hand, an element having such a thick high-resistance layer inevitably increases the forward voltage, the on-resistance, etc. during conduction between both electrodes, and increases the loss. That is, there is a trade-off relationship between the forward voltage, on-resistance (current capacity), and breakdown voltage. It is known that this trade-off relationship is similarly established in semiconductor elements such as IGBTs, bipolar transistors, and diodes.

  As a solution to this problem, the drift layer is composed of parallel pn layers in which n-type regions and p-type regions with an increased impurity concentration are alternately stacked, and in the off state, the drift layer is depleted and bears a withstand voltage. A semiconductor device having such a structure is disclosed in EP0053854, USP5216275, USP5438215, and Japanese Patent Laid-Open No. 9-266611 by the inventors of the present invention.

FIG. 18 is a partial cross-sectional view of a vertical MOSFET which is an embodiment of a semiconductor device disclosed in US Pat. No. 5,216,275. A typical vertical semiconductor element is characterized in that the drift layer 12 formed as a single layer is a parallel pn layer composed of an n drift region 12a and a p partition region 12b. Reference numeral 13 denotes a p-well region, 14 denotes an n ⁺ source region, 15 denotes a gate insulating film, 16 denotes a gate electrode, 17 denotes a source electrode, and 18 denotes a drain electrode. Of the n drift region 12a and the p partition region 12b, the drift current flows through the n drift region 12a. Hereinafter, the n drift region 12a and the p partition region 12b will be referred to as the drift layer 12.

For example, the drift layer 12 is formed by growing an n-type layer having high resistance by an epitaxial method using the n ⁺ drain layer 11 as a substrate, and selectively etching the trench reaching the n ⁺ drain layer 11 to form the n drift region 12a. Thereafter, a p-type layer is further grown in the trench by an epitaxial method to form a p partition region 12b.
The inventors of the present invention have decided to call a semiconductor element including a drift layer composed of a parallel pn layer that flows a current in the on state and is depleted in the off state as a super junction semiconductor element.

As a specific description of the dimensions in USP 5216275, when the breakdown voltage is V _B , the thickness of the drift layer 12 is 0.024 V _B ^1.2 [μm], and the n drift region 12a and the p drift region 12b have the same width b. If the impurity concentration is the same, the impurity concentration is 7.2 × 10 ¹⁶ V _B ^−0.2 / b [cm ⁻³ ]. Assuming that V _B = 300 V and b = 5 μm, the drift layer 12 has a thickness of 23 μm and an impurity concentration of 4.6 × 10 ¹⁵ cm ⁻³ . Since the impurity concentration in the case of a single layer is about 5 × 10 ¹⁴ , the on-resistance is certainly reduced, but such a narrow width and a deep depth (that is, a large aspect ratio) trench has a good quality. At present, the epitaxial method for embedding a semiconductor layer is a very difficult technique. The problem of the trade-off between on-resistance and breakdown voltage is common to lateral semiconductor elements. In the other inventions listed above, EP0053854, USP5438215 and Japanese Patent Laid-Open No. 9-266611, horizontal superjunction semiconductor elements are also described. As a common manufacturing method for horizontal and vertical, selective etching and epitaxial processes are described. A method of legal embedding is disclosed.

However, with respect to a vertical superjunction semiconductor device, selective etching and epitaxial filling have the same difficulties as USP 5216275. Japanese Patent Application Laid-Open No. 9-266611 also describes a transmutation method using neutron beams or the like, but the apparatus becomes large and cannot be applied easily.
In view of the circumstances as described above, the object of the present invention is to greatly relax the trade-off relationship between forward voltage and on-resistance and withstand voltage, and to increase current capacity by reducing forward voltage and on-resistance while maintaining high withstand voltage. An object of the present invention is to provide a manufacturing method capable of manufacturing a possible superjunction semiconductor element easily and with high mass productivity, and a superjunction semiconductor element by the manufacturing method.

In order to solve the above problems, the present invention provides a first main surface on the second main surface side between the first and second main surfaces, an electrode provided on each main surface, and the first and second main surfaces. A conductive type low resistance layer, a first conductive type drift region and a second conductive type partition that flow current in the on state and deplete in the off state to the first main surface side between the first and second main surfaces. Parallel pn layers in which regions are alternately arranged, and the depths y of both the first conductivity type drift region and the second conductivity type partition region are the same as that of the first conductivity type drift region and the second conductivity type partition region, respectively. in W x larger super-junction semiconductor device, have a first conductivity type low impurity concentration layer of low impurity concentration between the first conductive type drift region and a second conductivity-type partition regions low resistance layer, the second conductive The depth of the mold partition region is deeper than the depth of the first conductivity type drift region And bonding the semiconductor device.

The depth of the second conductivity type partition region is 1.2 times or less than the depth of the first conductivity type drift region.
In addition, the thickness t _{n of} the first conductivity type low impurity concentration layer is smaller than the depth of the second conductivity type partition region.
The main surface is a (110) surface.

If the depth y is larger than the width x, the depletion layer easily spreads to the full width of the first conductivity type drift region and the second conductivity type partition region, and then spreads downward.
The depth of the second conductivity type partition region is assumed to be deeper than the depth of the first conductivity type drift region. If the depth of the second conductivity type partition region is shallower than the depth of the first conductivity type drift region, the first conductivity type region will remain below the second conductivity type partition region, and the remaining first The conductivity type region is not completely depleted, and the withstand voltage may be reduced.

The depth of the second conductivity type partition region is 1.2 times or less than the depth of the first conductivity type drift region.
It is useless to make the depth of the second conductivity type partition region extremely larger than the depth of the first conductivity type drift region.
The first conductivity type low impurity concentration layer having a low impurity concentration below the second conductivity type partition region, the thickness t _{n of} the first conductivity type low impurity concentration layer being the junction depth y of the second conductivity type partition region _Let it be smaller than _p .

The first conductivity type low impurity concentration layer is a high resistance layer, which leads to an increase in forward voltage, on-resistance, or on-voltage. In particular, when the layer is thick, the depletion layer is likely to spread, and a JFET effect is generated in which the current path is narrowed by the spread depletion layer, thereby further increasing the forward voltage, the on-resistance, and the like.
If the main surface is the (110) plane, ion implantation can be performed to the depth of more than twice the normal depth with the same acceleration voltage by utilizing the channeling phenomenon during ion implantation.

As described above, the present invention includes the first and second main surfaces, the electrodes provided on the respective main surfaces, and the first conductive surface on the second main surface side between the first and second main surfaces. type and the low resistance layer, the first and second of the first first-conductivity-type drift region and a second conductivity-type partition regions depleted in the off state with a current flows in the principal surface side in the on-state between the main surface Are arranged in parallel, and the depth y of both the first conductivity type drift region and the second conductivity type partition region is the width of each of the first conductivity type drift region and the second conductivity type partition region. in x larger super-junction semiconductor device, the first conductivity type low impurity concentration layer of low impurity concentration between the first conductive type drift region and a second conductivity-type partition regions low resistance layer possess, the second conductivity type The partition region has a depth greater than that of the first conductivity type drift region. And if semiconductor element.

The depth of the second conductivity type partition region is 1.2 times or less than the depth of the first conductivity type drift region.
The layer serving as the other region can be epitaxially grown or a diffusion layer from the surface, and both regions can be formed by ion implantation. Therefore, the following effects are produced.

By making it possible to increase the impurity concentration of the parallel pn layer and thereby reducing the thickness of the parallel pn layer, the forward voltage, the on-resistance or the on-voltage can be greatly reduced, and the forward voltage and the on-resistance can be reduced. The trade-off characteristics with the withstand voltage can be improved.
The present invention realizes an innovative device that enables dramatic reduction of power loss, particularly in a power semiconductor device.

Embodiments of the present invention will be described below with reference to the accompanying drawings. In the following, layers and regions with n or p are used to mean layers and regions having electrons and holes as majority carriers, respectively. Also of ⁺ a relatively high impurity concentration, ^- are relatively low impurity concentration in the region of means, respectively.
[Example 1]
FIG. 1A is a partial cross-sectional view of the main part of the superjunction diode of Example 1 of the present invention. In addition to the portion shown in the figure, there is a portion that bears a withstand voltage at the peripheral portion, but this portion may be a guard ring structure or a field plate structure similar to a general semiconductor element, and is omitted here.

In FIG. 1A, reference numeral 21 denotes a low resistance n ⁺ cathode layer, and reference numeral 22 denotes an n drift region 22a and a p partition region 22b. For convenience, the parallel pn layer including the n drift region 22 a and the p partition region 22 b is referred to as a drift layer 22. A p ⁺ anode region 23 is formed in the surface layer. An anode electrode 28 is provided in contact with the p ⁺ anode region 23, and a cathode electrode 27 is provided in contact with the n ⁺ cathode layer. The n drift region 22a and the p partition region 22b are striped in plan view.

At the time of forward bias, holes are injected from the p ⁺ anode region 23 into the n drift region 22a, and electrons are injected from the n ⁺ cathode layer 21 into the p partition region 22b, and both conduct conductivity modulation and current flows.
At the time of reverse bias, the depletion layer spreads in the parallel pn layer of the n drift region 22a and the p partition region 22b, and the breakdown voltage can be maintained by depletion. In particular, by alternately forming the n drift region 22a and the p partition region 22b, the depletion layer from the pn junction between the n drift region 22a and the p partition region 22b extends in the width direction of the n drift region 22a and the p partition region 22b. Further, since the depletion layer spreads from the p partition region 22b and the n drift region 22a on both sides, the depletion is extremely accelerated. Therefore, the impurity concentration of the n drift region 22a can be increased.

The widths (x _n , x _p ) of the n drift region 22a and the p partition region 22b are smaller than the respective depths (y _n , y _p ). In this way, the depletion layer easily expands to the full width of the n drift region 22a and the p partition region 22b and then expands downward, so that a high breakdown voltage can be maintained in a small area. In order to promote depletion, x _n = x _p is desirable.

2A is an impurity concentration distribution diagram along the line AA in FIG. 1, FIG. 2B is an impurity concentration distribution diagram along the line BB, and FIG. It is an impurity concentration distribution map along the -C line. In either case, the vertical axis represents the impurity concentration expressed logarithmically. In FIG. 2A, n drift regions 22a and p partition regions 22b are alternately arranged. Since the n drift region 22a is an epitaxial layer, it has a substantially uniform impurity concentration, while the p partition region 22b is formed by ion implantation and heat treatment, so that a concentration gradient is observed at the end portion. In FIG. 2B, a substantially uniform concentration distribution of the p partition region 22b is observed following the p ⁺ anode region 23 due to diffusion from the surface, and a low resistance n ⁺ cathode layer 21 appears. Also in FIG. 2C, a uniform concentration distribution of the n drift region 22a and a low resistance n ⁺ cathode layer 21 continue from the p ⁺ anode region 23 due to diffusion from the surface.

For example, as a 300 V class diode, the dimensions and impurity concentrations of each part have the following values. The specific resistance of the n ⁺ cathode layer 21 is 0.01 Ω · cm, the thickness is 350 μm, the width (x _n ) of the n drift region 22 a is 3 μm, the specific resistance is 0.3 Ω · cm (impurity concentration 2 × 10 ¹⁶ cm ⁻³ ), The thickness of the drift layer 22 is 10 μm, the width (x _p ) of the p partition region 22 b is 3 μm (that is, the center distance between the buried regions of the same type is 6 μm), the average impurity concentration is 2 × 10 ¹⁶ cm ⁻³ , and the p ⁺ anode region 23 The diffusion depth is 1 μm and the surface impurity concentration is 5 × 10 ¹⁹ cm ⁻³ . In order to deplete the parallel pn layers in which the n drift regions 22a and the p partition regions 22b are alternately arranged in the off state, it is necessary that the amounts of impurities in both regions are substantially equal. If one impurity concentration is half of the other impurity concentration, the width must be doubled. Therefore, if both regions have the same impurity concentration, they need only have the same width, which is the best from the viewpoint of utilization efficiency of the semiconductor surface.

3A to 3D are cross-sectional views in order of steps for explaining the method of manufacturing the superjunction diode of Example 1. FIG. This will be described below with reference to the drawings.
An n drift region 22a is grown on the low resistance n-type substrate to be the n ⁺ cathode layer 21 by an epitaxial method [FIG. 3 (a)].
A tungsten film is deposited to a thickness of about 3 μm by CVD, and the first mask 1 is formed by photolithography [FIG. In ion implantation, since the atomic distribution is wider than the width of the mask, it is necessary to consider in advance.

Boron (hereinafter referred to as B) ions 2a are ion-implanted [FIG. The accelerating voltage is continuously changed between 100 keV and 10 MeV so as to be approximately 2 × 10 ¹⁶ cm ⁻³ evenly. 2b is an implanted B atom.
After removing the first mask 1, B ions 2 a for forming the p ⁺ anode region 23 are implanted [FIG. The acceleration voltage was 100 keV and the dose was 3 × 10 ¹⁵ cm ⁻² .

The impurities implanted by heat treatment at 1000 ° C. for 1 hour are activated, and the defects are annealed to form the n drift region 22a, the p partition region 22b, and the p ⁺ anode region 23 [FIG. Thereafter, the cathode electrode 27 and the anode electrode 28 are formed to complete the process.
Since the maximum acceleration voltage at the time of ion implantation for forming the p partition region 22b is increased and the acceleration voltage is continuously changed, the pn junction between the p partition region 22b and the n drift region 22a is deep. Smooth joint surface.

In particular, by selecting a specific crystal orientation such as the (110) plane, ion channeling can be used to form a deep ion implantation region that is twice or more that of normal ion implantation.
In the superjunction diode of the first embodiment, the n drift region 22a and the p partition region 22b have substantially the same dimensions and impurity concentration, and the drift layer 22 is depleted and bears a breakdown voltage when a reverse bias voltage is applied. It is.

In a conventional diode having a single high-resistance drift layer, the impurity concentration of the drift layer is required to be about 2 × 10 ¹⁴ cm ⁻³ and about 40 μm thick in order to obtain a breakdown voltage of 300 V class. In the superjunction diode of the example, since the impurity concentration of the n drift region 22a was increased and the thickness of the drift layer 22 was thereby reduced, the on-resistance could be reduced to about 1/5.

With such a manufacturing method, a technique that has been extremely difficult in the past, such as forming a trench with a large aspect ratio and embedding a high-quality epitaxial layer in the trench, is avoided. By ion implantation and diffusion, a super-junction diode having a high breakdown voltage and a low forward voltage can be easily manufactured.
Further, by reducing the width of the n drift region 22a and increasing the impurity concentration, it is possible to further reduce the operating resistance and improve the trade-off relationship between the operating resistance and the withstand voltage.

FIG. 1B is a partial cross-sectional view of a superjunction diode according to a modification of the first embodiment.
That is different from the super junction diode of Example 1 is that the depth y _p of the p partition regions 22b is deeper than the depth y _n of the n drift region 22a.
If If the depth y _p of the p partition regions 22b are, when shallower than the depth y _n of the n drift region 22a is made to be n drift region 22a under the p partition regions 22b remain, the remaining n drift region 22a is not completely depleted, and the withstand voltage may be reduced. Thus, as the depth y _p of the p partition regions 22b as shown in FIG becomes deeper than the depth y _n of the n drift region 22a, it is good to reach the n ⁺ cathode layer 21.

However, since it is useless to y _p is extremely larger than y _n, and a guide about 20%, to the extent that y _n <y _p ≦ 1.2y _n holds. Thereby, the withstand voltage retention in the parallel pn layer and the reduction of the forward voltage are compatible.
To increase the depth y _p of the p partition regions 22b may be higher acceleration voltage during the ion implantation. It is possible to increase the acceleration voltage of ion implantation and to make a diode having a higher breakdown voltage.

In the superjunction diode of Example 1, the planar arrangement of the n drift region 22b and the p partition region 22b is both striped. However, the present invention is not limited to this, and one of them may have various shapes such as a lattice shape, a net shape, and a honeycomb shape. It can be arranged. The same applies to the following examples.
It is also possible to form the n-type drift region 22b by forming the p-partition region 22a by the epitaxial method and ion-implanting donor impurities therein.
[Example 2]
FIG. 4 is a partial cross-sectional view of the superjunction diode of Example 2 of the present invention.

The difference from the superjunction diode of Example 1 is that the shape of the p partition region 32b is different.
In FIG. 4, the boundary between the p partition region 32b and the n drift region 32a is a curved line (a curved surface in three dimensions).
FIG. 5 is an impurity concentration distribution diagram along the line DD in FIG. The vertical axis represents the logarithmically expressed impurity concentration. In FIG. 5, the concentration distribution of the p partition region 32b due to diffusion from the discrete impurity source ion-implanted after the p ⁺ anode region 33 is seen, and a low resistance n ⁺ cathode layer 31 appears. Since the n drift region 32a is an epitaxial layer, the n drift region 32a has a substantially uniform impurity concentration and has the same impurity distribution as that of FIG.

As a manufacturing method of the superjunction diode of Example 2, the acceleration voltage is not continuously changed at the time of ion implantation of B ions 2 after FIG. 3B, for example, 100 keV, 200 keV, 500 keV, 1 MeV, 2 MeV, What is necessary is just to carry out multiple injection | pouring by changing it like 5MeV and 10MeV.
Also in this case, a superjunction diode having a high breakdown voltage and a low forward voltage can be easily manufactured by epitaxial growth, ion implantation, and diffusion, which are very general techniques. When the drift layer is shallow in a low breakdown voltage semiconductor device, the drift layer may be formed by one ion implantation without performing multiple ion implantation.

[Example 3]
The superjunction diode as shown in FIG. 1B can be manufactured by another manufacturing method.
6A to 6E are cross-sectional views in order of steps for explaining the method of manufacturing the superjunction diode of Example 3. FIG. This will be described below with reference to the drawings.
An n ⁺ cathode layer 41 is formed by deep diffusion from one surface of a high resistance n-type wafer. Reference numeral 42c denotes a high resistance n ⁻ high resistance layer. [FIG. 6 (a)]. After diffusing from both sides, one may be removed.

For example, a W film is deposited to a thickness of about 3 μm by the CVD method, the first mask 1 is formed by photolithography, and phosphorus (hereinafter referred to as P) ions 3a are ion-implanted [FIG. The acceleration voltage is continuously changed between 100 keV and 15 MeV so as to be approximately 2 × 10 ¹⁶ cm ⁻³ evenly. 3b is an implanted P ion.
After the first mask 1 is removed, a second mask 4 is formed in the same manner, and B ions 2a are ion-implanted [FIG. The accelerating voltage is continuously changed between 100 keV and 10 MeV so as to be approximately 2 × 10 ¹⁶ cm ⁻³ evenly.

After removing the second mask 4, B ions 2 a for forming the p ⁺ anode region 43 are implanted [(d)]. The acceleration voltage was 100 keV and the dose was 3 × 10 ¹⁵ cm ⁻² .
The impurities implanted by heat treatment at 1000 ° C. for 1 hour are activated, the defects are annealed, and the n drift region 42a, the p partition region 42b, and the p ⁺ anode region 43 are formed [FIG. The n ⁻ high resistance layer 42c does not remain in the central portion of the diode, but only in the peripheral voltage holding portion. Thereafter, the cathode electrode and the anode electrode are formed to complete the process.

Also in this example, since the maximum acceleration voltage during ion implantation is increased and continuously changed, the pn junction between the p partition region 42b and the n drift region 42a becomes a deep and smooth junction surface. Then, a super-junction diode having a high breakdown voltage and a low forward voltage can be easily manufactured by ion implantation and diffusion, which are very general techniques.
Also in the superjunction diode of the third embodiment, the n drift region 42a and the p partition region 42b have substantially the same dimensions and impurity concentration, and the drift layer 42 is depleted when the reverse bias voltage is applied, and bears a withstand voltage.

In this way, a superjunction semiconductor element can be manufactured by a process mainly including ion implantation and heat treatment.
As shown in FIG. 1A, the n drift region 42a and the p partition region 42b may be ion-implanted to substantially the same depth, and ion implantation is performed at a discrete acceleration voltage as in the second embodiment. You can also.

In this embodiment, the n ⁺ cathode layer 41 is formed by diffusion to the high resistance substrate to be the n ⁻ high resistance region 42c, but is formed by epitaxial growth on the low resistance substrate to be the n ⁺ cathode layer 41. An epitaxial wafer may be used. [Example 4]
FIG. 7 is a partial cross-sectional view of the superjunction diode of Example 4 of the present invention.
In FIG. 7, 51 is a low resistance n ⁺ cathode layer, and 52 is a drift layer comprising an n drift region 52a and a p partition region 52b. A p ⁺ anode region 53 is formed in the surface layer. An anode electrode 58 is provided in contact with the p ⁺ anode region 53, and a cathode electrode 57 is provided in contact with the n ⁺ cathode layer 51.

  Although it looks the same as the cross-sectional view of FIG. 1B, the structure inside the semiconductor is different because the manufacturing method is different. That is, in the example of FIG. 1B, the n drift region 12a is formed by the epitaxial method and has a substantially uniform impurity concentration distribution, whereas in the superjunction diode of the third embodiment, n drift The region 32a has a distribution due to impurity diffusion from the surface.

FIG. 8 is an impurity concentration distribution diagram along the line EE in FIG. The vertical axis represents the logarithmically expressed impurity concentration. In FIG. 8, a concentration distribution due to diffusion from the surface of the n drift region 52a is observed following the p ⁺ anode region 53 of the surface layer, and a low resistance n ⁺ cathode layer 51 appears.
FIGS. 9A to 9E are cross-sectional views in order of steps for explaining the method of manufacturing the superjunction diode according to the fourth embodiment. This will be described below with reference to the drawings.

Deep diffusion is performed from one surface of the high resistance n-type wafer to form an n ⁺ cathode layer 51, and P ions 3a are implanted into the surface of the n ⁻ high resistance layer 52c [FIG. 9A]. The acceleration voltage is 100 keV, and the dose is about 2 × 10 ¹³ cm ⁻² .
Diffusion is performed at 1250 ° C. for about 10 hours, and an n drift region 52a is formed so as to reach the n ⁺ cathode layer 51 [FIG. Therefore, the n ⁻ high resistance layer 52c does not remain in the central portion of the diode, but only in the peripheral voltage holding portion.

A W film is deposited to a thickness of about 3 μm by a CVD method, a first mask 1 is formed by photolithography, and B ions 2a are ion-implanted [FIG. The accelerating voltage is continuously changed between 100 keV and 10 MeV so as to be approximately 2 × 10 ¹⁶ cm ⁻³ evenly.
The first mask 1 is removed, and B ions 2a for forming the p anode region 53 are selectively implanted [(d)].

Heat treatment is performed at 1000 ° C. for 1 hour to activate the ion-implanted impurities, anneal the defects, and form the p partition region 52b and the p ⁺ anode region 53 [FIG. Thereafter, the cathode electrode and the anode electrode are formed to complete the process.
For example, for a 300 V class diode, the dimensions and impurity concentrations of each part have the following values. The surface impurity concentration of the n ⁺ cathode layer 11 is 3 × 10 ²⁰ cm ⁻³ , the diffusion depth is 200 μm, the width of the n drift region 12a is 3 μm, the surface impurity concentration is 1 × 10 ¹⁷ cm ⁻³ , the diffusion depth is 10 μm, and the p partition region 12b. The width is 3 μm, the average impurity concentration is 2 × 10 ¹⁶ cm ⁻³ , the diffusion depth of the p ⁺ anode region 13 is 1 μm, and the surface impurity concentration is 5 × 10 ¹⁹ cm ⁻³ .

Also in this case, a superjunction diode having a high withstand voltage and a low forward voltage can be easily manufactured by ion implantation and diffusion, which are very general techniques.
In exactly the same manner, the n-type drift region 52a can also be formed by forming the p partition region 52b by diffusion and ion-implanting donor impurities therein.
The n ⁻ high resistance region 52 c may be an epitaxial wafer formed by epitaxial growth on a low resistance substrate to be the n ⁺ cathode layer 51.

As shown in FIG. 1A, the n drift region 52a and the p partition region 52b may be ion-implanted to substantially the same depth, and ion implantation is performed at a discrete acceleration voltage as in the second embodiment. You can also.
[Example 5]
FIG. 10 is a partial cross-sectional view of the superjunction diode of Example 5 of the present invention.

In FIG. 10, reference numeral 61 denotes a low resistance n ⁺ cathode layer. A p ⁺ anode region 63 is formed in the surface layer of the drift layer 62 composed of the n drift region 62a and the p partition region 62b. An anode electrode 68 is provided in contact with the p ⁺ anode region 63, and a cathode electrode 67 is provided in contact with the n ⁺ cathode layer 61.
Although it looks the same as the cross-sectional view of FIG. 1B, the structure inside the semiconductor is different because the manufacturing method is different. That is, in the superjunction diode of Example 5, both the n drift region 62a and the p partition region 62b have a distribution due to impurity diffusion from the surface.

FIG. 11 is an impurity concentration distribution diagram along line EE in FIG. The vertical axis represents the logarithmically expressed impurity concentration. In FIG. 11, the concentration distribution of the p partition region 62b formed by impurity diffusion from the surface is observed following the p ⁺ anode region 63 by diffusion from the surface, and the n ⁺ cathode layer 61 having a low resistance appears. . Although the impurity concentration distribution in the n drift region 62a is not shown, it is almost the same as the concentration distribution in the p partition region 62b.

12A to 12E are cross-sectional views in order of steps for explaining the method of manufacturing the superjunction diode of Example 5. This will be described below with reference to the drawings.
An n ⁺ cathode layer 61 is formed by deep diffusion from one surface of a high resistance n-type wafer. 62 c is a high resistance n ⁻ high resistance layer. [FIG. 12 (a)].
A first mask 5 of an oxide film is formed on the surface of the n ⁻ high resistance layer 62c, and B ions 2a are implanted [FIG. 2b is an implanted B atom. The acceleration voltage is 100 keV, and the dose is 7 × 10 ¹² cm ⁻² .

After heat treatment at 1200 ° C. for 30 hours, a second mask 6 of oxide film is formed, and P ions 3a are implanted [FIG. 3b is an implanted P atom. The acceleration voltage is 100 keV, and the dose is 7 × 10 ¹² cm ⁻² . The impurity doping method is not necessarily limited to ion implantation, and may be gas doping. However, an impurity having a low diffusion coefficient is first subjected to heat treatment.
The n drift region 62 a and the p partition region 62 b are formed so as to reach the n ⁺ cathode layer 61 by heat treatment at 1200 ° C. for about 50 hours. Therefore, the n ⁻ high resistance layer 62c does not remain in the central portion of the diode but only in the peripheral voltage holding portion. Thereafter, B ions 2a for forming the p anode region 63 are implanted [(d)].

Heat treatment is performed at 1000 ° C. for 1 hour to activate the ion-implanted impurities and anneal the defects to form the n drift region 62a, the p partition region 62b, and the p ⁺ anode region 63 [FIG. Thereafter, the cathode electrode and the anode electrode are formed to complete the process.
Such a very common technique, such as epitaxial growth, ion implantation, and diffusion, can easily produce a superjunction diode having a high breakdown voltage and a low forward voltage.

Since B has a diffusion coefficient slower than that of P, the above-described process is performed. However, a combination of another donor impurity and an acceptor impurity may be used, and in this case, it is necessary to change the diffusion time. [Example 6]
Although the embodiments so far are diodes having the simplest structure, FIG. 13 is a partial sectional view of a superjunction Schottky barrier diode (SBD) according to Embodiment 6 of the present invention.

In FIG. 13, 71 is a low resistance n ⁺ cathode layer, and 72 is a drift layer comprising an n drift region 72a and a p partition region 72b. On the surface, an n drift region 72a and a p partition region 72b are exposed, and a Schottky electrode 78 that forms a Schottky barrier with the n drift region 72a is provided. A cathode electrode 77 in ohmic contact is provided on the back surface side of the n ⁺ cathode layer 71.

  Also in the superjunction Schottky diode of Example 6, the n drift region 72a and the p partition region 72b have substantially the same dimensions and impurity concentration, and the drift layer 72 is depleted and bears a withstand voltage when a reverse bias voltage is applied. To do. For example, the Schottky electrode 78 and the cathode electrode 77 are formed after the parallel pn layer is formed by the same process as in the first embodiment described above. Of course, any one of the methods of Embodiments 2 to 5 may be used.

At the time of reverse bias, the depletion layer spreads in the parallel pn layer and is depleted like the diode of Example 1 in FIG. During forward bias, a drift current flows through n drift region 72a.
The width and depth of the n drift region 72a and the p partition region 72b are the same as in the first embodiment.

FIG. 14 is a forward voltage-current characteristic diagram of a 300 V class superjunction Schottky diode in which the drift layer 72 is formed by the same process as in the first embodiment. The horizontal axis represents the forward voltage (V _F ), and the vertical axis represents the forward current (I _F ) per unit area. As the Schottky electrode 78, molybdenum was used. For comparison, the characteristics of a conventional Schottky barrier diode having a uniform drift layer are also shown in the figure.

From the figure, it can be seen that the forward voltage (V _F ) of the same withstand voltage class can be significantly reduced as compared with the conventional Schottky barrier diode.
Since the n buried region 72b and the p buried region 72c are easily depleted, the impurity concentration can be increased and the thickness of the drift layer 72 can be reduced, thereby greatly reducing the forward voltage, the forward voltage and the breakdown voltage. It is possible to improve the trade-off characteristics.

As described above, a superjunction Schottky barrier diode having a high withstand voltage and a low forward voltage can be easily manufactured by ion implantation and impurity diffusion, which are very general techniques in a Schottky barrier diode. [Example 7]
FIG. 15 is a partial cross-sectional view of a superjunction MOSFET according to Example 7 of the invention.
In FIG. 15, 81 is a low resistance n ⁺ drain layer, and 82 is a drift layer of a parallel pn layer composed of an n drift region 82a and a p partition region 82b. In the surface layer, an n channel region 82d is formed connected to the n drift region 82a, and a p well region 83a is formed connected to the p partition region 82b. An n ⁺ source region 84 is formed inside the p well region 83a. On the surface of the p well region 83a sandwiched between the n ⁺ source region 84 and the n channel region 82d, the gate electrode layer 86 is interposed via the gate insulating film 85, and the n ⁺ source region 84 and the p well region 73a. A source electrode 87 is provided in common contact with the surface. A drain electrode 88 is provided on the back surface of the n ⁺ drain layer 81. Reference numeral 89 denotes an insulating film for surface protection and stabilization, and is made of, for example, a thermal oxide film and phosphor silica glass (PSG). The source electrode 87 is often extended on the gate electrode layer 86 through the insulating film 89 as shown in the figure. In the drift layer 82, the drift current flows in the n drift region 82a.

Note that the planar arrangement of the n drift region 82a and the p partition region 82b is both striped, but the present invention is not limited to this, and one of them can be arranged in various forms such as a lattice, a net, or a honeycomb.
Further, the p-type well region 83a and the p-partition region 82b in the surface layer do not have to have the same planar shape, and may have completely different patterns as long as the connection is maintained. For example, when both are made into a stripe shape, they can also be made into a stripe shape in which they are orthogonal to each other.

Also in the superjunction MOSFET of the seventh embodiment, the n drift region 82a and the p partition region 82b have substantially the same dimensions and impurity concentration, and are depleted when a reverse bias voltage is applied to bear a withstand voltage.
As the manufacturing method, the following steps are taken. In the same manner as in any of the first to fifth embodiments, the n ⁺ drain layer 81, the n drift region 82a, and the p partition region 82b are formed.

An n-channel region 82d is grown by an epitaxial method.
Similar to a normal vertical MOSFET, a p well region 83a and an n ⁺ source region 84 are formed in the surface layer by selective implantation of impurity ions and heat treatment.
Thereafter, a gate insulating film 85 is formed by thermal oxidation, a polycrystalline silicon film is deposited by a low pressure CVD method, and a gate electrode layer 86 is formed by photolithography. Further, an insulating film 89 is deposited, a window is opened by photolithography, an aluminum alloy is deposited, and a source electrode 87, a drain electrode 88 and a gate electrode (not shown) are formed by pattern formation, thereby completing a super junction MOSFET as shown in FIG. To do.

The operation of the superjunction MOSFET of FIG. 15 is performed as follows. When a predetermined positive voltage is applied to the gate electrode layer 86, an inversion layer is induced in the surface layer of the p well region 83a immediately below the gate electrode layer 86, and the n ⁺ source region 84 passes through the inversion layer to the n channel region 82d. The injected electrons reach the n ⁺ drain layer 81 through the n drift region 82a, and the drain electrode 88 and the source electrode 87 are conducted.

  When the positive voltage to the gate electrode layer 86 is removed, the inversion layer induced in the surface layer of the p-well region 83a disappears, and the drain and source are blocked. Further, when the reverse bias voltage is increased, each p partition region 82b is connected to the source electrode 87 via the p well region 83a, so that the pn junctions Ja, p between the p well region 83a and the n channel region 82d are connected. From the pn junction Jb between the partition region 82b and the n drift region 82a and the pn junction between the p partition region 82b and the n channel region 82d (not shown), the depletion layers are the n channel region 82d, the n drift region 82a, and the p partition region 82b, respectively. They spread in and are depleted.

For example, in a 300V class MOSFET, the dimensions of the n drift region 82a and the p partition region 82b are the same as those in FIG. The dimensions and impurity concentrations of other parts take the following values. The specific resistance of the n ⁺ drain layer 81 is 0.01 Ω · cm, the thickness is 350 μm, the specific resistance of the n ⁻ high resistance layer 82 c is 10 Ω · cm, the diffusion depth of the p-well region 83 a is 1 μm, and the surface impurity concentration is 3 × 10 ¹⁸ cm. ⁻³ , the diffusion depth of the n ⁺ source region 84 is 0.3 μm, and the surface impurity concentration is 1 × 10 ²⁰ cm ⁻³ .

In a conventional vertical MOSFET having a single high-resistance drift layer, the impurity concentration of the drift layer 12 needs to be about 2 × 10 ¹⁴ cm ⁻³ and a thickness of about 40 μm in order to obtain a breakdown voltage of 300 V class. However, in the superjunction MOSFET of this embodiment, the impurity concentration of the n drift region 82a is increased, and the thickness of the drift layer 82 can be reduced thereby, so that the on-resistance can be reduced to about 1/5. It was.

The formation of a buried region by epitaxial growth with a thickness of several μm and diffusion of impurities introduced by ion implantation is a very general technique, and a super-junction MOSFET with easily improved trade-off characteristics between on-resistance and breakdown voltage Can be manufactured.
Further, by reducing the width of the n drift region 82a and increasing the impurity concentration, it is possible to further reduce the on-resistance and improve the trade-off relationship between the on-resistance and the breakdown voltage.

A sectional view of a modification of the super junction MOSFET is shown in FIG.
In this example, there is an n ⁻ high resistance layer 82c below the n drift region 82a and the p partition region 82b.
If the depth of the p partition region 82b is sufficient, the n ⁻ high resistance layer 82c may be provided therebelow. However, if the n ⁻ high resistance layer 82 c remains between the n drift region 82 a and the n ⁺ drain layer 81, the on-resistance increases. In addition, since the depletion layer extending from the p partition region 82b causes a JFET effect to narrow the current path, it is preferable that the thickness of the n ⁻ high resistance layer 82c is not excessively increased. It is better to be thinner than the thickness y _p of at least p partition regions 82b.

FIG. 17 shows a cross-sectional view of another modification of the superjunction MOSFET. A high concentration p ⁺ contact region 83b is formed on the surface layer in the p well region 83a. By arranging p ⁺ contact region 83b between n ⁺ source regions 84, the contact resistance between p well region 83a and source electrode 87 is reduced. Further, by making the diffusion depth of the p ⁺ contact region 83b shallower than the depth of the n ⁺ source region 84, depletion of the pn divided layer can be prevented.

  The superjunction structure according to the present invention as described above is not limited to the diodes, Schottky barrier diodes, and MOSFETs shown in the embodiments. Almost all semiconductor devices such as bipolar transistors, IGBTs, JFETs, thyristors, MESFETs, HEMTs, etc. It is applicable to. Further, the conductivity type can be appropriately changed to a reverse conductivity type.

(A) is the fragmentary sectional view of the super junction diode of Example 1 of this invention, (b) is the fragmentary sectional view of the super junction diode of a modification. 1A is an impurity concentration distribution diagram along line AA of the superjunction diode of Example 1 in FIG. 1, FIG. 1B is an impurity concentration distribution diagram along line BB, and FIG. Impurity concentration distribution diagram along the line (A) thru | or (d) is the fragmentary sectional view for every main processes shown in order of the manufacturing process of the super junction diode of Example 1. FIG. Partial sectional view of the superjunction diode of Example 2 of the present invention Impurity concentration distribution diagram along line DD of the superjunction diode of Example 2 in FIG. (A) thru | or (e) are the fragmentary sectional views for every main processes shown in order of the manufacturing process of the super junction diode of Example 3. Partial sectional view of the superjunction diode of Example 4 of the present invention, Impurity concentration distribution diagram along line EE of the superjunction diode of Example 4 in FIG. (A) thru | or (e) are the fragmentary sectional views for every main processes shown in order of the manufacturing process of the super junction diode of Example 4. Partial cross-sectional view of the superjunction diode of Example 5 of the present invention, Impurity concentration distribution diagram along line FF of the superjunction diode of Example 5 (A) thru | or (e) is the fragmentary sectional view for every main processes shown in order of the manufacturing process of the super junction diode of Example 5. FIG. Partial sectional view of a superjunction Schottky barrier diode of Example 6 of the present invention Forward voltage-forward current characteristic diagram of superjunction Schottky barrier diode of Example 6 of the present invention Partial sectional view of the superjunction MOSFET of Example 7 of the present invention Partial sectional view of a modified example of a super junction MOSFET Partial sectional view of another variation of superjunction MOSFET Partial sectional view of a conventional superjunction MOSFET

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 1st mask 2a Boron ion 2b Boron atom 3a Phosphorus ion 3b Phosphorus atom 4 2nd mask 5 1st mask 6 2nd mask 11, 81 n ⁺ drain layer 12, 22, 32, 42, 52, 62, 72 , 82 Drift layer 12a, 22a, 32a, 42a, 52a, 62a, 72a, 82an Drift region 12b, 22b, 32b, 42b, 52b, 62b, 72b, 82b p partition region 13a, 83a p well region 14, 84 n ⁺ Source region 15, 85 Gate insulating film 16, 86 Gate electrode layer 17, 87 Source electrode 18, 88 Drain electrode 19, 89 Insulating film 21, 31, 41, 51, 61, 71 n ⁺ Cathode layer 23, 33, 43 53, 63 p ⁺ anode region 27, 37, 47, 57, 67, 77 Cathode electrode 28, 38, 48, 5 8, 68 Anode electrode 52c, 62c, 82c n ⁻ High resistance layer 78 Schottky electrode 82d n channel region 83b p ⁺ contact region

Claims (4)

A first and second major surface, an electrode provided on each major surface, and first and second second first-conductivity-type on the principal surface side of between the main surface of the low-resistance layer, a first A parallel pn layer in which a first conductivity type drift region and a second conductivity type partition region, which flow current in the on state and are depleted in the off state, are alternately arranged on the first main surface side between the first main surface and the second main surface In a superjunction semiconductor element in which the depth y of both the first conductivity type drift region and the second conductivity type partition region is larger than the width x of each of the first conductivity type drift region and the second conductivity type partition region, have a first conductivity type low impurity concentration layer of low impurity concentration between the first conductive type drift region and a second conductivity-type partition region and the low-resistance layer, the depth of the second conductivity type partition regions first conductive A superjunction semiconductor device characterized by being deeper than the depth of the type drift region. 2. The superjunction semiconductor device according to claim 1, wherein a depth of the second conductivity type partition region is 1.2 times or less of a depth of the first conductivity type drift region. The super junction semiconductor device according to claim 1, wherein the thickness t _{n of} the first conductivity type low impurity concentration layer is smaller than the depth of the second conductivity type partition region. The superjunction semiconductor element according to claim 1, wherein the main surface is a (110) plane.

Images