JP2013069871A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device, in which an insulated-gate bipolar transistor and a diode are integrated, that allows improving the switching speed.SOLUTION: A semiconductor device 10 includes a drift layer 11, a base layer 17, a plurality of first trenches 12, a plurality of gate electrodes 14, a plurality of emitter layers 19, a plurality of second trenches 13, an emitter electrode 15, a buffer layer 21, a plurality of collector layers 22, and a collector electrode 23. The plurality of first trenches 12 are disposed so as to be in parallel to each other and to be spaced apart from each other on an upper surface of the base layer 17, and are formed so as to penetrate through the base layer 17. Each of the plurality of second trenches 13 is disposed between the first trenches 12 and is formed so as not to penetrate through the base layer 17. The emitter electrode 15 is formed on a surface of the base layer 17 including the insides of the plurality of second trenches 13.

Description

  Embodiments described herein relate generally to a semiconductor device in which an insulated gate bipolar transistor and a diode are integrated.

  In general, in an IH cooker, an inverter system, or the like, a semiconductor device including an insulated gate bipolar transistor (hereinafter referred to as an IGBT (Insulated Gate Bipolar Transistor)) and a diode connected in parallel thereto is used.

  In recent years, in order to reduce the chip cost of this type of device, attention has been focused on a reverse conducting IGBT (hereinafter referred to as RC-IGBT) in which a diode is incorporated in the IGBT. In the RC-IGBT, a P + type impurity layer on the lower surface side is partially formed, and the P base layer / N drift layer / N buffer layer is actively used as a diode. As a result, the diode connected in parallel to the IGBT can be omitted, and the cost can be reduced.

However, in general, in the IGBT, in order to keep the gate threshold voltage at a desired value, the impurity concentration of the P base layer needs to be high (for example, on the order of 10 ¹⁷ cm ⁻³ ). When the P base layer has a high concentration as described above, the amount of holes to be supplied from the emitter electrode provided on the P base to the P base layer is large, and therefore the switching speed of the diode built in the RC-IGBT is high. There is a problem that slows down. As a result, it becomes difficult to use the RC-IGBT as a hard switching element such as an HEV inverter.

JP 2010-171385 A

  An object of the embodiment is to provide a semiconductor device capable of improving a switching speed in a semiconductor device in which an insulated gate bipolar transistor and a diode are integrated.

  The semiconductor device according to the embodiment includes a first semiconductor layer, a second semiconductor layer, a plurality of first trenches, a first electrode, a plurality of third semiconductor layers, a second trench, a second electrode, A fourth impurity layer; a plurality of fifth impurity layers; and a third electrode. The first semiconductor layer is made of a first conductivity type semiconductor substrate. The second semiconductor layer is of a second conductivity type and is formed on the upper surface of the first semiconductor layer. The plurality of first trenches are arranged so as to be parallel and spaced apart from each other, and are formed so as to penetrate the second semiconductor layer. The first electrode is formed in each of the plurality of first trenches via a first insulating film. The plurality of third semiconductor layers are each of a first conductivity type, are disposed so as to be in contact with each of the plurality of first electrodes via the first insulating film, and the second semiconductor layer Formed on the top surface of the layer. A plurality of the second trenches are provided so as to be respectively disposed between the plurality of first trenches, and each of the second trenches is formed so as not to penetrate the second semiconductor layer. The second electrode is formed on the upper surface of the second semiconductor layer including the plurality of second trenches so as to be insulated from the first electrode. The fourth impurity layer is of a first conductivity type and is formed on the lower surface of the first semiconductor layer. The plurality of fifth impurity layers are of a second conductivity type and are selectively formed on the lower surface of the fourth impurity layer. The third electrode is formed on a lower surface of the fourth impurity layer including the plurality of fifth impurity layers.

1 is a schematic top view showing a semiconductor device according to a first embodiment. It is sectional drawing of the apparatus center part along the dashed-dotted line XX 'of FIG. It is sectional drawing of the apparatus termination | terminus part along the dashed-dotted line YY 'of FIG. It is sectional drawing of the center part of the semiconductor device which concerns on 1st Embodiment, Comprising: It is explanatory drawing for demonstrating the movement of a hole and an electron at the time of IGBT ON. It is sectional drawing of the termination | terminus part of the semiconductor device which concerns on 1st Embodiment, Comprising: It is explanatory drawing for demonstrating the motion of a hole and an electron at the time of IGBT ON. It is sectional drawing of the center part of the semiconductor device which concerns on 1st Embodiment, Comprising: It is explanatory drawing for demonstrating the movement of a hole and an electron at the time of IGBT OFF. It is sectional drawing of the termination | terminus part of the semiconductor device which concerns on 1st Embodiment, Comprising: It is explanatory drawing for demonstrating the movement of a hole and an electron at the time of IGBT OFF. A semiconductor device according to the first embodiment in which the total amount of impurities in the base layer between the bottom of the second trench and the joint surface of the base layer and the drift layer is reduced, and the semiconductor device when the IGBT is off FIG. 3 is a cross-sectional view corresponding to FIG. FIG. 2 shows the semiconductor device 10 in which the total amount of impurities in the base layer between the bottom of the second trench and the joint surface of the base layer and the drift layer is increased, and the semiconductor device 10 is shown when the IGBT is off. FIG. FIG. 4 is a diagram illustrating a terminal portion of a semiconductor device according to a second embodiment, which is a cross-sectional view corresponding to FIG. 3. FIG. 5 is a view showing a central portion of a semiconductor device according to a third embodiment, and is a cross-sectional view corresponding to FIG. 2. It is a figure which shows the termination | terminus part of the semiconductor device which concerns on 4th Embodiment, Comprising: It is sectional drawing equivalent to FIG.

  Hereinafter, a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings. Note that a semiconductor device described below includes a reverse-conducting IGBT (hereinafter referred to as RC-IGBT) in which an insulated gate bipolar transistor (hereinafter referred to as IGBT (Insulated Gate Bipolar Transistor)) and a diode are integrally formed. It is.

(First embodiment)
FIG. 1 is a schematic top view showing the semiconductor device according to the first embodiment. In FIG. 1, an emitter electrode and a gate insulating film covering the gate electrode are omitted in order to avoid complication of the drawing.

  In the semiconductor device 10 shown in FIG. 1, a plurality of first trenches 12 are formed in an n− type semiconductor substrate 11 made of, for example, silicon, which is a first semiconductor layer. The plurality of first trenches 12 are band-shaped patterns on the upper surface of the semiconductor substrate 11 and are formed in parallel with each other and spaced apart from each other.

  A plurality of second trenches 13 are formed in the semiconductor substrate 11. The plurality of second trenches 13 are band-shaped patterns on the upper surface of the semiconductor substrate 11 and are formed in parallel with each other and spaced apart from each other. The second trench 13 is formed so that the pattern of the second trench 13 on the upper surface of the semiconductor substrate 11 is not in contact with the pattern between the pattern of the first trench 12 on the upper surface of the semiconductor substrate 11. Yes.

  The second trenches 13 are preferably formed between the first trenches 12 as shown in the drawing, but may be selectively formed between the arbitrary first trenches 12.

  2 is a cross-sectional view of the central portion of the apparatus along the one-dot chain line XX ′ in FIG. FIG. 3 is a cross-sectional view of the terminal portion of the apparatus along the one-dot chain line YY ′ of FIG. The n − type semiconductor substrate 11 shown in FIGS. 2 and 3 is a so-called drift layer 11. In a predetermined region on the upper surface of the drift layer 11, a base layer 17 that is a p-type impurity layer is formed as a second semiconductor layer. As shown in FIG. 3, the base layer 17 is formed shallower than the guard ring layer 16 inside a guard ring layer 16 described later.

  Here, the first trench 12 is formed so as to penetrate the base layer 17 in the depth direction and reach the drift layer 11. The second trench 13 is formed so as not to penetrate the base layer 17 in the depth direction.

The total impurity amount Qb of the base layer 17 between the bottom of the second trench 13 and the junction surface S of the base layer 17 and the drift layer 11 is Qb> εsEc / q = 1.31E ¹² cm ^−2. Is preferred. εs is the dielectric constant of Si, Ec is the critical electric field, and q is the elementary charge. By making the total impurity amount Qb greater than 1.31E ¹² cm ⁻² , it is possible to suppress the base layer 17 from being fully depleted when the IGBT is turned off. Accordingly, it is possible to suppress a decrease in the breakdown voltage of the semiconductor device 10. The reason for this will be described later.

  In each first trench 12, a gate electrode 14 that is a first electrode is formed via a gate insulating film 18 that is a first insulating film. The gate electrode 14 is made of, for example, polysilicon. Note that the gate insulating film 18 also covers the upper surface of the gate electrode 14, and the first trench 12 is filled with the gate electrode 14 including the gate insulating film 18.

  On the upper surface of the base layer 17, a plurality of n + -type emitter layers 19 are formed as a plurality of third semiconductor layers. The plurality of emitter layers 19 are arranged so as to sandwich the gate electrode 14 with the gate insulating film 18 interposed therebetween.

  As shown in FIG. 1, the emitter layer 19 is formed so as to be in contact with the side surface of the gate electrode 14 via the gate insulating film 18 along the gate electrode 14. Each emitter layer 19 is formed such that the upper surface of each emitter layer 19 forms a strip pattern in contact with the strip pattern of the gate electrode 14 via the gate insulating film 18 on the top surface of the base layer 17.

  Although not shown, the emitter layer 19 may be selectively formed along the gate electrode 14. That is, the emitter layer 19 may be divided into a plurality of parts along the gate electrode 14.

  In addition, a buffer layer 21 that is an n + type high concentration impurity layer is uniformly formed as a fourth semiconductor layer on the lower surface of the drift layer 11. Further, a collector layer 22 which is a p-type high concentration impurity layer is selectively formed on the lower surface of the buffer layer 21 as a fifth semiconductor layer. The collector layer 22 is formed below the buffer layer 21 below the first trench 12 and below the guard ring layer 16 including between the first trench 12 and a guard ring layer 16 described later. . Therefore, the collector layer 22 exposed on the lower surface of the buffer layer 21 has a strip-like pattern formed so as to be parallel to the first and second trenches 11 and 12, the gate electrode 14, or the emitter layer 19.

  The collector layer 22 only needs to be selectively formed on the lower surface of the buffer layer 21, and does not necessarily have to be formed in the above-described position so as to form a belt-like pattern as described above.

  As shown in FIG. 3, a guard ring layer 16 that is a p + type impurity layer is formed on the upper surface of the drift layer 11 as a sixth semiconductor layer. As shown in FIG. 1, the guard ring layer 16 is formed in an annular shape so as to surround the plurality of first trenches 12 and the plurality of second trenches 13.

  As shown in FIG. 2, on the upper surface of the drift layer 11 on which the base layer 17 and the guard ring layer 16 (FIG. 3) are formed, a second electrode is formed so as to fill the plurality of second trenches 13. An emitter electrode 15 is formed. The emitter electrode 15 is made of, for example, metal, and is formed to be insulated from the gate electrode 14 by a gate insulating film 18 formed on the upper surface of the gate electrode 14. As shown in FIG. 3, the end portion of the emitter electrode 15 is formed on the upper surface of the drift layer 11 so as to protrude outside the guard ring layer 16.

  An insulating film 20 is formed outside the guard ring layer 16 on the upper surface of the base layer 17, and an end portion of the emitter electrode 15 is formed on the upper surface of the drift layer 11 via the insulating film 20. ing.

  A plate-like collector electrode 23 having a uniform thickness is formed as a third electrode on the lower surface of the buffer layer 21 including the collector layer 22. The collector electrode 23 is made of metal, for example.

  Hereinafter, the operation of the semiconductor device 10 will be described separately for a case where the device operates as an IGBT and a case where the device operates as a diode.

  4 and 5 are explanatory diagrams for explaining the movement of holes and electrons when the IGBT is turned on. 4 shows the movement of holes and electrons in the central part of the device, and FIG. 5 shows the movement of holes and electrons in the terminal part of the device.

  As shown in FIG. 4, when a voltage is applied to the gate electrode 14 with a bias V applied between the collector electrode 23 and the emitter electrode 15 in the central portion of the semiconductor device 10, the base layer around the side surface of the gate electrode 14. A channel is formed at 17, and electrons e flow from the emitter layer 19 into the drift layer 11. At the same time, holes h flow from the collector layer 22 into the drift layer 11. That is, current flows from the collector electrode 23 toward the emitter electrode 15 and operates as an IGBT.

  As shown in FIG. 5, the operation of the semiconductor device 10 is similar to that in the terminal portion of the semiconductor device 10, electrons e flow from the emitter layer 19 to the drift layer 11 and holes from the collector layer 22 to the drift layer 11. h flows in. That is, current flows from the collector electrode 23 toward the emitter electrode 15 and operates as an IGBT.

  6 and 7 are explanatory diagrams for explaining the movement of holes and electrons when the IGBT is off. FIG. 6 shows the movement of holes and electrons in the central part of the device, and FIG. 7 shows the movement of holes and electrons in the terminal part of the device.

  When the IGBT is turned on and no voltage is applied to the gate electrode 14, as shown in FIG. 6, the collector electrode 23-emitter electrode 15 is generated by the electromotive force of a motor or the like (not shown) connected to the semiconductor device 10. A bias −V ′ is applied between them. As a result, holes h flow from the base layer 17 to the drift layer 11, and electrons e flow from the buffer layer 21 to the drift layer 11. That is, a current flows from the emitter electrode 15 toward the collector electrode 23 and operates as a reverse conducting diode.

  As shown in FIG. 7, the operation of the semiconductor device 10 is similar to that in the terminal portion of the semiconductor device 10, holes h flow from the guard ring layer 16 to the drift layer 11 and from the buffer layer 21 to the drift layer 11. Electrons e flow in. That is, a current flows from the emitter electrode 15 toward the collector electrode 23 and operates as a reverse conducting diode.

  As described above, the semiconductor device 10 can be operated as an IGBT or a diode for reverse conduction by operating the gate voltage 14.

  According to the semiconductor device 10 according to the first embodiment described above, the second trench 13 is provided, and the emitter electrode 15 is formed inside the trench 13. Therefore, the distance from the emitter electrode 15 to the junction surface S of the base layer 17 and the drift layer 11 can be partially shortened. Therefore, the total amount of impurities contained in the base layer 17 between the emitter electrode 15 and the bonding surface S can be reduced while maintaining the impurity concentration of the base layer 17 at a desired high concentration. As a result, since the amount of holes that need to be supplied from the emitter electrode 15 to the base layer 17 can be reduced, a semiconductor device having a high switching speed while keeping the gate threshold voltage at a desired value is provided. Can do.

  Further, according to the semiconductor device 10 according to the first embodiment, since the distance from the emitter electrode 15 to the bonding surface S is partially shorter than that of the conventional semiconductor device, the resistance of the base layer 17 can be reduced. Therefore, it is possible to provide a semiconductor device that is difficult to latch up and has a high latch-up resistance when the IGBT is turned off.

  That is, in the semiconductor device 10, a thyristor is configured by the p + -type collector layer 22, the n + -type buffer layer 21, the n − -type drift layer 11, the p-type base layer 17, and the n − -type emitter layer 19. When a high voltage such as a surge voltage is applied between the collector electrode 23 and the emitter electrode 15, most of the high voltage is formed at the boundary between the n − type drift layer 11 and the p type base layer 17. Applied to the depletion layer. When a high voltage is applied to the depletion layer, an electron avalanche occurs in the depletion layer. Due to this electron avalanche, a large current continues to flow from the collector electrode 23 toward the emitter electrode 15, and the semiconductor device 10 enters a latch-up state. The latch-up is caused by an electron avalanche generated in the depletion layer formed at the boundary portion between the n − -type drift layer 11 and the p-type base layer 17 as described above. The larger the is, the more likely it is to occur. The depletion layer width is more likely to increase as the impurity concentration of the p-type base layer 17 or the n − -type drift layer is lower, that is, as the resistance of the p-type base layer 17 or the n − -type drift layer 11 is higher. According to the semiconductor device 10 according to the present embodiment, since the resistance of the p-type base layer 17 can be reduced, depletion formed at the boundary portion between the n − -type drift layer and the p-type base layer 17. Electronic avalanches hardly occur in the layer. Therefore, latch-up is unlikely to occur and the latch-up resistance is increased.

In the semiconductor device 10 according to the present embodiment, as described above, the total impurity amount Qb of the base layer 17 between the bottom of the second trench 13 and the junction surface S of the base layer 17 and the drift layer 11 is set as follows. By setting Qb> εsEc / q = 1.31E ¹² cm ⁻² , it is possible to suppress the base layer 17 from being fully depleted when the IGBT is turned off, and to suppress a decrease in the breakdown voltage of the semiconductor device 10. Can do. The reason for this will be described with reference to FIGS. FIG. 8 shows a semiconductor device 10 in which the total impurity amount Qb of the base layer 17 between the bottom of the second trench 13 and the junction surface S of the base layer 17 and the drift layer 11 is reduced, and the IGBT is turned off. It is sectional drawing which shows the semiconductor device 10 at the time. FIG. 9 shows a semiconductor device 10 in which the total impurity amount Qb of the base layer 17 between the bottom of the second trench 13 and the junction surface S of the base layer 17 and the drift layer 11 is increased. It is sectional drawing which shows the semiconductor device 10 at the time of OFF.

  If the total impurity amount Qb of the base layer 17 between the bottom of the second trench 13 and the junction surface S of the base layer 17 and the drift layer 11 is lowered, the impurity concentration of the base layer 17 is lowered accordingly. Therefore, the depletion layer formed at the boundary portion between the emitter layer 19 and the base layer 17 when the IGBT is turned off is easily spread. As shown in FIG. 8, when the depletion layer D ′ spreads and the base layer 17 is completely depleted, that is, the depletion layer D ′ formed at the boundary between the emitter layer 19 and the base layer 17 extends over the entire base layer 17. When spread, since the width W ′ of the depletion layer D ′ is wide, even if a small voltage is applied to the depletion layer D ′, an electron avalanche occurs, and the emitter layer 19 and the base layer 17 are always in a conductive state. Become. Accordingly, when the total impurity amount Qb of the base layer 17 is reduced and the base layer 17 is completely depleted, the voltage value that can be applied between the emitter electrode 15 and the collector electrode 23 becomes low. That is, the breakdown voltage of the semiconductor device 10 is lowered.

  On the other hand, when the total impurity amount Qb of the base layer 17 between the bottom of the second trench 13 and the junction surface S of the base layer 17 and the drift layer 11 is increased, the base layer 17 Since the impurity concentration increases, the depletion layer formed at the boundary between the emitter layer 19 and the base layer 17 when the IGBT is off is difficult to spread. As shown in FIG. 9, when the depletion layer D does not spread and the base layer 17 is not completely depleted, that is, since the width W of the depletion layer D is narrow, an electron avalanche hardly occurs in the depletion layer D, and the emitter layer 19 Even if a large voltage is applied to the depletion layer D formed at the boundary between the base layer 17 and the base layer 17, an electron avalanche is unlikely to occur. Accordingly, when the total impurity amount Qb of the base layer 17 is increased and the base layer 17 is prevented from being fully depleted, a decrease in the voltage value that can be applied between the emitter electrode 15 and the collector electrode 23 is suppressed. . That is, a decrease in the breakdown voltage of the semiconductor device 10 is suppressed.

(Second Embodiment)
FIG. 10 is an enlarged cross-sectional view illustrating a part of the terminal portion of the semiconductor device according to the second embodiment. The terminal portion of the semiconductor device 30 according to the second embodiment differs from the semiconductor device 10 according to the first embodiment in that the third trench 31 is formed in the guard ring layer 16. Hereinafter, differences from the semiconductor device 10 according to the first embodiment will be described. The central portion of the semiconductor device 30 according to the second embodiment has the same configuration as that of the semiconductor device 10 according to the first embodiment shown in FIG.

  As shown in FIG. 10, a third trench 31 is formed in the guard ring layer 16 at the terminal portion of the semiconductor device 30 according to the second embodiment. The third trench 31 is formed to be a strip pattern on the upper surface of the guard ring layer 16, and the strip pattern is formed to be parallel to the strip pattern of the second trench 13. Yes. Further, the third trench 31 is formed so as not to penetrate the guard ring layer 16 in the depth direction.

  The emitter electrode 32 is formed on the upper surface of the drift layer 11 so as to fill the inside of the second trench 13 and the inside of the third trench 31.

  The semiconductor device 30 configured as described above operates as a diode or an IGBT similarly to the semiconductor device 10 according to the first embodiment.

  Even in the semiconductor device 30 according to the second embodiment described above, the configuration of the central portion is the same as that of the semiconductor device 10 according to the first embodiment, and thus the semiconductor according to the first embodiment. Similar to the device 10, it is possible to provide a semiconductor device that has a high switching speed while maintaining a gate threshold voltage at a desired value, and that is difficult to latch up and has a high latch-up tolerance when the IGBT is turned off. it can.

  Furthermore, according to the semiconductor device 30 according to the second embodiment, the third trench 31 is formed in the guard ring layer 16, and the emitter electrode 32 is formed inside the trench 31, so that the emitter electrode The distance from 32 to the joint surface S ′ of the guard ring layer 16 and the drift layer 11 can be shortened. As a result, since it is possible to reduce the amount of holes that need to be supplied from the emitter electrode 15 to the guard ring layer 16, it is possible to provide a semiconductor device with a higher switching speed.

(Third embodiment)
FIG. 11 is an enlarged cross-sectional view illustrating a part of the central portion of the semiconductor device according to the third embodiment. The central portion of the semiconductor device 40 according to the third embodiment is different from the semiconductor device 10 according to the first embodiment in that a second insulating film 41 is formed on the inner surface of the second trench 13. . Hereinafter, differences from the semiconductor device 10 according to the first embodiment will be described. In addition, the termination | terminus part of the semiconductor device 40 which concerns on 3rd Embodiment is the structure similar to the semiconductor device 10 which concerns on 1st Embodiment shown by FIG.

  As shown in FIG. 11, in the semiconductor device 30 according to the third embodiment, a second insulating film 41 is formed on the inner surface of the second trench 13 formed between the first trenches 12. ing. Note that the second insulating film 41 is not formed on the bottom surface of the second trench 13.

  The emitter electrode 42 is formed inside the second trench 13 in which the second insulating film 41 is formed.

  The semiconductor device 40 configured as described above operates as a diode or an IGBT similarly to the semiconductor device 10 according to the first embodiment.

  Even in the semiconductor device 40 according to the third embodiment described above, the second trench 13 is formed in the base layer 17, and the emitter electrode 42 is formed in the trench 13. Similar to the semiconductor device 10 according to the first embodiment, the semiconductor device has a high switching speed while keeping the gate threshold voltage at a desired value, and is difficult to latch up and has a high latch-up withstand capability when the IGBT is turned off. A semiconductor device can be provided.

  Furthermore, according to the semiconductor device 40 according to the third embodiment, since the second insulating film 41 is formed on the inner surface of the second trench 13, the emitter electrode 42 transmits holes to the second trench 13. Supply to the base layer 17 from the side surface of the trench 13 can be suppressed. Therefore, the semiconductor device 40 according to the third embodiment is different from the semiconductor device 10 according to the first embodiment from the emitter electrode 42 to the junction surface S of the emitter electrode 42 and the base layer 17 and the drift layer 11. The holes can be efficiently supplied to the base layer 17 between them. Therefore, a semiconductor device with a higher switching speed can be provided.

(Fourth embodiment)
FIG. 12 is an enlarged cross-sectional view showing a part of the terminal portion of the semiconductor device according to the fourth embodiment. In the terminal portion of the semiconductor device 50 according to the fourth embodiment, the third trench 31 is formed in the guard ring layer 16, and the third insulating film 51 is formed on the inner surface of the third trench 31. This is different from the semiconductor device 10 according to the first embodiment. Hereinafter, differences from the semiconductor device 10 according to the first embodiment will be described. The central portion of the semiconductor device 50 according to the fourth embodiment has the same configuration as that of the semiconductor device 10 according to the first embodiment shown in FIG.

  As shown in FIG. 12, in the semiconductor device 50 according to the fourth embodiment, a third trench 31 is formed in the guard ring layer 16. The third trench 31 is formed to be a strip pattern on the upper surface of the guard ring layer 16, and the strip pattern is formed to be parallel to the strip pattern of the second trench 13. Yes. Further, the third trench 31 is formed so as not to penetrate the guard ring layer 16 in the depth direction.

  A third insulating film 51 is formed on the inner side surface of the third trench 31. Note that the third insulating film 51 is not formed on the bottom surface of the third trench 31.

  The emitter electrode 52 is formed on the upper surface of the drift layer 11 so as to fill the inside of the third trench 31 in which the third insulating film 51 is formed.

  The semiconductor device 50 configured as described above operates as a diode or an IGBT similarly to the semiconductor device 10 according to the first embodiment.

  Even in the semiconductor device 50 according to the fourth embodiment described above, the configuration of the central portion is the same as that of the semiconductor device 10 according to the first embodiment, and thus the semiconductor according to the first embodiment. Similar to the device 10, it is possible to provide a semiconductor device that has a high switching speed while maintaining a gate threshold voltage at a desired value, and that is difficult to latch up and has a high latch-up tolerance when the IGBT is turned off. it can.

  Even in the semiconductor device 50 according to the fourth embodiment, the third trench 31 is formed in the guard ring layer 16 and the emitter electrode 52 is formed so as to fill the trench 31. Like the semiconductor device 30 according to the second embodiment, a semiconductor device with a higher switching speed can be provided.

  Furthermore, according to the semiconductor device 50 according to the fourth embodiment, since the third insulating film 51 is formed on the inner surface of the third trench 31, the emitter electrode 52 transmits holes to the third trenches 31. Supplying to the guard ring layer 16 from the side surface of the trench 31 can be suppressed. Therefore, the semiconductor device 50 according to the fourth embodiment is different from the semiconductor device 30 according to the second embodiment in that the emitter electrode 52, the emitter electrode 52, the guard ring layer 16, and the drift layer 11 are joined. Holes can be efficiently supplied to the guard ring layer 16 between S ′ and S ′. Therefore, a semiconductor device with a higher switching speed can be provided.

  Although the embodiment of the present invention has been described above, this embodiment is presented as an example and is not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  For example, the third trench 31 and the third insulating film 51 formed in the semiconductor device 50 according to the fourth embodiment may be applied to the semiconductor device 40 according to the third embodiment. In this case, a semiconductor device having a higher switching speed than the semiconductor device 40 according to the third embodiment can be provided.

10, 30, 40, 50 ... Semiconductor device 11 ... Semiconductor substrate (drift layer)
12 ... 1st trench 13, 31 ... 2nd trench 14 ... Gate electrode 15, 32, 42, 52 ... Emitter electrode 16 ... Guard ring layer 17 ... Base layer 18 ... Gate insulation film (first insulation film)
19 ... Emitter layer 20 ... Insulating film 21 ... n + high concentration impurity layer (buffer layer)
22 ... p + high concentration impurity layer (collector layer)
23 ... Collector electrode 31 ... Third trench 41 ... Second insulating film 51 ... Third insulating film

Claims (7)

A first semiconductor layer comprising a semiconductor substrate of a first conductivity type;
A second semiconductor layer of a second conductivity type formed on the top surface of the first semiconductor layer;
A plurality of first trenches disposed so as to be parallel and spaced apart from each other and formed so as to penetrate the second semiconductor layer;
A first electrode formed in each of the plurality of first trenches via a first insulating film;
A plurality of first conductivity type third semiconductor layers disposed on and in contact with each of the plurality of first electrodes via the first insulating film and formed on the top surface of the second semiconductor layer When,
A second trench disposed between each of the plurality of first trenches and formed so as not to penetrate the second semiconductor layer;
A second electrode formed on an upper surface of the second semiconductor layer including the inside of the plurality of second trenches so as to be insulated from the first electrode;
A fourth impurity layer of the first conductivity type formed on the lower surface of the first semiconductor layer;
A plurality of second conductivity type fifth impurity layers selectively formed on a lower surface of the fourth impurity layer;
A third electrode formed on a lower surface of the fourth impurity layer including the plurality of fifth impurity layers;
A semiconductor device comprising: A sixth semiconductor layer of a second conductivity type formed on an upper surface of the first semiconductor layer so as to surround the plurality of first trenches and the plurality of second trenches;
A third trench formed so as not to penetrate the sixth semiconductor layer;
Further comprising
The semiconductor device according to claim 1, wherein the second electrode is formed so as to fill the inside of the third trench. A second insulating film formed on the inner surface of the second trench;
3. The semiconductor device according to claim 1, wherein the second electrode is formed so as to fill the inside of the second trench through the second insulating film. A third insulating film formed on the inner surface of the third trench;
4. The semiconductor device according to claim 2, wherein the second electrode is formed so as to fill the inside of the third trench through the third insulating film. 5.   The plurality of fifth semiconductor layers include a lower portion between the plurality of first trenches and a portion between the first trench and the sixth semiconductor layer on a lower surface of the fourth semiconductor layer. The semiconductor device according to claim 2, wherein the semiconductor device is formed below the sixth semiconductor layer. The plurality of first trenches are arranged to form a plurality of strip-like patterns that are parallel and spaced apart from each other on the upper surface of the second semiconductor layer,
The plurality of second trenches are arranged to form a plurality of strip patterns on the upper surface of the second semiconductor layer, and each of the strip patterns is disposed between the strip patterns of the first trench. 6. The semiconductor device according to claim 1, wherein the semiconductor device is formed.   The third trench is disposed so as to be a belt-like pattern on the upper surface of the sixth semiconductor layer, and the belt-like pattern is disposed so as to be parallel to the belt-like pattern of the second trench. The semiconductor device according to claim 6.

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