JP2018186208A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate the need for a step of simply connecting a surface electrode and an electrode pad.SOLUTION: A semiconductor device includes a semiconductor region formed at a position facing a part of a surface of a semiconductor substrate 10, a surface electrode 12 conducting with the semiconductor region and formed on the surface of the semiconductor substrate 10, a conductor 44 in dummy trench filling a dummy trench 40 extending from the surface of the semiconductor substrate 10 in a range where the semiconductor region is not formed to a deep part, an electrode pad 16 conducting with the conductor 44 in the dummy trench and formed on the surface of the semiconductor substrate 10, a set of the semiconductor region and the surface electrode 12, insulation films 13, 42, 52 insulating between the set of the conductor 44 in the dummy trench and the electrode pad 16, and a metal plate 18 extending across the surface of the surface electrode 12 and the surface of the electrode pad 16. The semiconductor region, the surface electrode 12, the electrode pad 16 and the conductor 44 in the dummy trench are conducted by means of the metal plate 18.SELECTED DRAWING: Figure 3

Description

  The technology disclosed in this specification relates to a semiconductor device having a dummy trench.

  Patent Document 1 discloses an RC-IGBT (Reverse Conducting-Insulated Gate Bipolar Transistor). The RC-IGBT includes an emitter region formed at a position facing a part of the surface of the semiconductor substrate, a surface electrode formed on the surface of the semiconductor substrate and conducting to the emitter region, and an emitter region. A dummy trench extending deep from the surface of the semiconductor substrate that is not formed, a conductor embedded in the dummy trench, and formed on the surface of the semiconductor substrate and conducting to the conductor in the dummy trench Electrode pads (referred to as dummy trench screening pads in Patent Document 1). The conductor in the dummy trench is insulated from the semiconductor substrate by an insulating film formed on the wall surface of the dummy trench. When this RC-IGBT is actually used, the emitter region, the surface electrode, and the dummy trench conductor are used at the same potential. The use of a dummy trench conductor maintained at the same potential as the emitter region improves the breakdown voltage of the semiconductor device.

  In the manufacturing process of this RC-IGBT, it is necessary to inspect whether the insulating film formed on the conductor in the dummy trench and the wall surface of the dummy trench is appropriately manufactured. In this case, the inspection needs to be performed in a state where the emitter region and the surface electrode are at the same potential, the conductor in the dummy trench and the electrode pad are at the same potential, and both are insulated.

JP 2014-035552 A

  In the above-mentioned RC-IGBT, after passing the inspection, a step of connecting the electrode pad to the surface electrode or the surface electrode pad conducting to the surface electrode with a wire is required.

  In the above description, the RC-IGBT is exemplified, but besides that, a semiconductor region (for example, an emitter region or a source region) formed in a range facing a part of the surface of the semiconductor substrate and the semiconductor region are electrically connected. A surface electrode, a conductor embedded in a dummy trench extending deeply from the surface of the semiconductor substrate in a region where no semiconductor region is formed, and an electrode pad conducting to the conductor. In this case, there is a semiconductor device in which the conductor in the dummy trench and the electrode pad are insulated from the surface electrode, and the electrode pad and the surface electrode are connected after inspection. In these semiconductor devices, a process only for connecting the electrode pad and the surface electrode is required after the inspection. In the present specification, a technique for disabling the process of simply connecting the electrode pad and the surface electrode is disclosed.

  The semiconductor device disclosed in this specification includes a semiconductor region formed at a position facing a part of the surface of the semiconductor substrate, a surface electrode that is conductive to the semiconductor region and formed on the surface of the semiconductor substrate, A dummy trench conductor filled in a dummy trench extending deeply from the surface of the semiconductor substrate in a range where no semiconductor region is formed, and a conductor in the dummy trench that is conductive and formed on the surface of the semiconductor substrate. Electrode pads, a pair of semiconductor region and surface electrode, an insulating film that insulates between a pair of conductors in the dummy trench and the electrode pad, and a metal plate that extends from the surface electrode surface to the electrode pad surface It has. The semiconductor region, the surface electrode, the electrode pad, and the conductor in the dummy trench are conducted by the metal plate.

  In the case of a semiconductor device having a surface electrode, a current plate and / or a heat transfer path may be completed by joining a metal plate to the surface electrode. In the technique of this specification, the surface electrode and the electrode pad are electrically connected using the metal plate. Thereby, the process of only connecting a surface electrode and an electrode pad can be made unnecessary.

  Details and further improvements of the technology disclosed in this specification will be described in the following “DETAILED DESCRIPTION”.

It is a top view of the semiconductor device of an example. It is sectional drawing of the semiconductor device along the II-II line | wire of FIG. It is sectional drawing of the semiconductor device along the III-III line of FIG.

  A semiconductor device 2 which is an RC-IGBT will be described with reference to the drawings. FIG. 1 is a top view of the semiconductor device 2. Two surface electrodes 12, signal electrode pads 15 a, 15 b, 15 c and an electrode pad 16 are provided on the surface of the semiconductor substrate 10 of the semiconductor device 2, and the other portions are covered with the insulating film 13. Yes. The surface electrode 12 is disposed on the element region of the semiconductor substrate 10, and the element region is partitioned into an IGBT region 14a and a diode region 14b. A trench structure is formed in the element region. In order to help understanding, in FIG. 1, the trench structure in the element region is indicated by a broken line. In the semiconductor device 2, a metal plate 18 to be described later is bonded on the surface of the semiconductor substrate 10, but the metal plate 18 is not shown in FIG. 1.

  The signal electrode pads 15 a, 15 b, 15 c are provided at the outer peripheral end of the surface of the semiconductor substrate 10. The signal electrode pad 15 a is a gate pad of the semiconductor substrate 10. The signal electrode pad 15 b is an electrode pad for outputting a voltage indicating the temperature of the semiconductor substrate 10, and the signal electrode pad 15 c is an electrode pad for outputting a voltage indicating a current value flowing through the semiconductor substrate 10. is there.

  The electrode pad 16 is disposed between the two surface electrodes 12. The electrode pad 16 is used for inspecting whether or not a trench structure (specifically, a dummy trench 40 described later) formed in the diode region 14b is appropriately formed.

  Next, the structure of the semiconductor device 2 will be described in detail with reference to FIGS. FIG. 2 is a cross-sectional view of the semiconductor device 2 taken along line II-II in FIG. FIG. 3 is a cross-sectional view of the semiconductor device 2 taken along line III-III in FIG.

  As shown in FIG. 2, the semiconductor device 2 includes a semiconductor substrate 10, a surface electrode 12 that covers the upper surface of the semiconductor substrate 10, a lower electrode 20 that covers the lower surface of the semiconductor substrate 10, and a metal plate 18. The front electrode 12 is a single layer electrode of Al or AlSi, or a laminated electrode of AlSi (or Al) / Ti / Ni / Au, and the lower electrode 20 is AlSi (or Al) / Ti / Ni / Au or Ti / Ni / Au laminated electrode. The metal plate 18 is made of, for example, copper or other metal. The metal plate 18 is joined to the surface electrode 12 via the solder 54 and functions as a part of the current path and heat transfer path of the semiconductor device 2. The metal plate 18 also functions as a spacer for securing a space necessary for connecting wires to the signal electrode pads 15a, 15b, and 15c.

  As described above, the semiconductor substrate 10 is partitioned into the IGBT region 14a in which the IGBT structure is provided and the diode region 14b in which the diode structure is provided. The semiconductor device 2 further includes a gate trench 30 provided in the IGBT region 14a, a dummy trench 40 provided in the diode region 14b, and an interlayer insulating film 52 partially provided on the upper surface of the semiconductor substrate 10. Prepare.

The semiconductor substrate 10 includes a p-type collector region 21, an n-type cathode region 22, an n ⁻ -type drift region 23, an n-type barrier region 24, a p-type body region 25, an n-type pillar region 26, n ⁺ A type emitter region 27 is provided.

  The collector region 21 is disposed in the IGBT region 14a. The collector region 21 is provided in a part of the lower layer portion of the semiconductor substrate 10 and is in contact with the lower surface electrode 20. The collector region 21 has a high impurity concentration and is in ohmic contact with the lower surface electrode 20.

  The cathode region 22 is disposed in the diode region 14b. The cathode region 22 is provided in a part of the lower layer portion of the semiconductor substrate 10 and is in contact with the lower surface electrode 20. The cathode region 22 has a high impurity concentration and is in ohmic contact with the lower surface electrode 20.

  The drift region 23 is disposed in the IGBT region 14a and the diode region 14b. The drift region 23 is provided between the collector region 21 and the barrier region 24 in the IGBT region 14a. The drift region 23 is provided between the cathode region 22 and the barrier region 24 in the diode region 14b. The drift region 23 is a remaining portion in which another region is formed in the semiconductor substrate 10, and the impurity concentration is constant in the thickness direction.

  The barrier region 24 is disposed in the IGBT region 14a and the diode region 14b. The barrier region 24 is provided between the drift region 23 and the body region 25. The barrier region 24 disposed in the IGBT region 14 a is provided between the adjacent gate trenches 30 and is in contact with both side surfaces of the adjacent gate trenches 30. The barrier region 24 disposed in the diode region 14 b is provided between the adjacent dummy trenches 40 and is in contact with both side surfaces of the adjacent dummy trenches 40. The barrier region 24 disposed in the diode region 14 b is electrically connected to the surface electrode 12 through the pillar region 26.

  Body region 25 is arranged in IGBT region 14a and diode region 14b. The body region 25 is provided in the upper layer portion of the semiconductor substrate 10 and is in contact with the surface electrode 12. Although the body region 25 has a low impurity concentration, the portion of the body region 25 in contact with the surface electrode 12 has a locally high impurity concentration and is in ohmic contact with the surface electrode 12. The body region 25 disposed in the IGBT region 14 a is provided between the adjacent gate trenches 30 and is in contact with both side surfaces of the adjacent gate trenches 30. The body region 25 arranged in the diode region 14 b is provided between the adjacent dummy trenches 40 and is in contact with both side surfaces of the adjacent dummy trenches 40. The body region 25 arranged in the diode region 14b functions as an anode region.

  The pillar region 26 is disposed in the diode region 14b. The pillar region 26 is provided so as to penetrate the body region 25 from the lower surface of the surface electrode 12 to reach the barrier region 24, and electrically connect the surface electrode 12 and the barrier region 24. The impurity concentration of the pillar region 26 is adjusted so as to make a Schottky contact with the surface electrode 12. The pillar region 26 arranged in the diode region 14 b is provided between the adjacent dummy trenches 40 and is separated from both the adjacent dummy trenches 40 by the body region 25.

  The emitter region 27 is disposed in the IGBT region 14a. The emitter region 27 is provided in the upper layer portion of the semiconductor substrate 10 and is in contact with the surface electrode 12. The emitter region 27 has a high impurity concentration and is in ohmic contact with the surface electrode 12. The emitter region 27 is formed, for example, by introducing arsenic or phosphorus from the upper surface of the semiconductor substrate 10 using an ion implantation technique.

  The gate trench 30 extends in the depth direction so as to penetrate the emitter region 27, the body region 25, and the barrier region 24 and reach the drift region 23 in the IGBT region 14a. The emitter region 27, the body region 25, and the barrier region 24 are in contact with the side surface of the gate trench 30. The drift region 23 is in contact with the side surface and the bottom surface of the gate trench 30. The inner surface of the gate trench 30 is covered with a gate trench insulating film 32 and the inside of the gate trench conductor 34 is filled. The gate trench inner conductor 34 is insulated from the semiconductor substrate 10 by the gate trench insulating film 32 and insulated from the surface electrode 12 by the interlayer insulating film 52.

  The dummy trench 40 extends in the depth direction so as to penetrate the body region 25 and the barrier region 24 and reach the drift region 23. The body region 25 and the barrier region 24 are in contact with the side surface of the dummy trench 40. The drift region 23 is in contact with the side surface and the bottom surface of the dummy trench 40. The inner surface of the dummy trench 40 is covered with a dummy trench insulating film 42 and the inside of the dummy trench conductor 44 is filled. The dummy trench inner conductor 44 is insulated from the semiconductor substrate 10 by the dummy trench insulating film 42 and insulated from the surface electrode 12 by the interlayer insulating film 52.

  Further, as shown in FIG. 3, the dummy trench 40 extends to the vicinity of the central portion of the semiconductor device 2. Near the end of the dummy trench 40, a connection portion 44 a is formed in which the upper surface of the dummy trench conductor 44 is not in contact with the interlayer insulating film 52. The dummy trench inner conductor 44 is connected to the wiring 17 at the connection portion 44a.

  The wiring 17 is a wiring for connecting the electrode pad 16 and the dummy trench conductor 44. The wiring 17 is insulated from the semiconductor substrate 10 by the dummy trench insulating film 42 and insulated from the surface electrode 12 by the interlayer insulating film 52. A contact portion 17 a that is not covered with the interlayer insulating film 52 is formed on the wiring 17. The wiring 17 is connected to the electrode pad 16 at the contact portion 17a.

  The electrode pad 16 is provided on the surface of the semiconductor substrate 10 and is insulated from the surface electrode 12 by the insulating film 13. However, the metal plate 18 is bonded to the upper surface of the electrode pad 16 via the solder 54. Thereby, the electrode pad 16 is electrically connected to the surface electrode 12 via the metal plate 18.

  Next, an inspection procedure for the dummy trench 40 of the semiconductor device 2 will be described. The inspection for the dummy trench 40 is performed in a state where the surface electrode 12 and the dummy trench inner conductor 44 are not conductive, that is, in a state of a semi-finished product before the metal plate 18 is bonded to the semiconductor substrate 10.

  By applying a constant potential to the electrode pad 16, a constant potential is applied to the dummy trench inner conductor 44 via the wiring 17. Thereby, it is possible to inspect whether or not the dummy trench inner conductor 44 and the dummy trench insulating film 42 are appropriately manufactured. When the dummy trench 40 is appropriately manufactured, the metal plate 18 is bonded to the upper surface of the semiconductor substrate 10 so that the surface electrode 12 and the electrode pad 16 are electrically connected. As a result, the front electrode 12 and the dummy trench conductor 44 can be used as the same potential.

(Effect of this embodiment)
In this embodiment, the surface electrode 12 and the electrode pad 16 are electrically connected via the metal plate 18. Since the metal plate 18 is a member that functions as a part of the current path and heat transfer path of the semiconductor device 2 and as a spacer, a process only for connecting the surface electrode 12 and the electrode pad 16 is not necessary. There is no need to provide an additional member only for connecting the electrode 12 and the electrode pad 16. Therefore, a process only for connecting the surface electrode 12 and the electrode pad 16 can be eliminated.

  Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

2: Semiconductor device 10: Semiconductor substrate 12: Surface electrode 13: Insulating film 14a: IGBT region 14b: Diode regions 15a, 15b, 16c: Signal electrode pad 16: Electrode pad 17: Wiring 17a: Contact portion 18: Metal plate 20 : Bottom electrode 21: collector region 22: cathode region 23: drift region 24: barrier region 25: body region 26: pillar region 27: emitter region 30: gate trench 32: gate trench insulating film 34: conductor in gate trench 40: dummy Trench 42: dummy trench insulating film 44: dummy trench conductor 44a: connecting portion 52: interlayer insulating film 54: solder

Claims (1)

A semiconductor region formed at a position facing a part of the surface of the semiconductor substrate;
A surface electrode that is electrically connected to the semiconductor region and is formed on the surface of the semiconductor substrate;
A conductor in a dummy trench filled in a dummy trench extending deeply from the surface of the semiconductor substrate in a range where the semiconductor region is not formed;
An electrode pad formed on the surface of the semiconductor substrate and electrically connected to the conductor in the dummy trench;
A set of the semiconductor region and the surface electrode; an insulating film that insulates between the set of the conductor in the dummy trench and the electrode pad;
Comprising a metal plate extending across the surface of the electrode pad from the surface electrode surface,
A semiconductor device in which the semiconductor region, the surface electrode, the electrode pad, and the conductor in the dummy trench are electrically connected by the metal plate.

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