JP2008270367A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of improving an ESD resistance in a configuration, having a plurality of lateral-type DMOS elements. <P>SOLUTION: In the semiconductor device with a plurality of LDMOS elements, a first conductivity-type high-concentration layer having an impurity concentration higher than that of a semiconductor layer is formed on an opposite surface of the well forming surface of the semiconductor layer, together with the semiconductor layer as a forming region for the plurality of LDMOS elements in a semiconductor substrate. In the semiconductor device, a drain electrode is formed directly over the opposite surface of a boundary, with the semiconductor layer of at least the high-concentration layer as the rear of a gate electrode forming surface in the semiconductor substrate, and the drain electrode and each of a plurality of drain regions are electrically connected. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device including a plurality of lateral DMOS elements (Lateral Double Diffusion MOS-FETs).

  In recent years, as a power IC used for controlling a vehicle control ECU (Electric Control Unit) and various consumer devices, for example, a horizontal DMOS element (hereinafter referred to as an LDMOS element) in terms of process consistency with other elements such as a CMOS. ) Is widely used. When increasing the breakdown voltage of this LDMOS device, the length of the drift layer is increased or the impurity concentration of the drift layer is decreased. With such a configuration, surge current due to ESD (Electro Static Discharge) is transferred to the outside of the device. It becomes difficult to escape, and the element is easily destroyed by heat.

On the other hand, the structure which improves ESD tolerance is proposed. For example, in the configuration shown in Patent Document 1, an anode layer having a conductivity type opposite to the drain layer is formed on the surface layer of the active layer (semiconductor layer) adjacent to the drain layer (drain region). This anode layer, together with the source layer (source region), base layer (well region), and active layer, forms a parasitic thyristor during ESD, thereby reducing the holding voltage between the source and drain at a large current. Like to do. In Patent Document 1, the gate electrode, the source electrode, and the drain electrode are formed on one surface of the active layer on the surface layer where the drain layer is formed.
JP 2001-320047 A

  By the way, in the case where a plurality of LDMOS elements are provided, particularly when the element area is increased in accordance with an increase in breakdown voltage and an increase in current, it is difficult to ensure the ESD tolerance even with the configuration shown in Patent Document 1.

  As the cause, the following can be considered. When a plurality of LDMOS elements are provided, a drain electrode is connected to the drain region of each element via a contact hole, and each drain electrode is connected to a common pad via a wiring or a via hole (or a through hole). ing. Each hole described above is filled with a connecting member. When the element area is increased, the wiring becomes high impedance. Therefore, the influence of the wiring length difference on the surge transmission becomes large, the transmission of the surge current from the pad to the element (drain region) becomes different, and the surge current tends to concentrate on the element having a low current path resistance value. Conceivable. In addition to the wiring, height differences such as via holes and contact holes and manufacturing variations also affect the transmission of surge currents and cause differences.

  In view of the above problems, an object of the present invention is to provide a semiconductor device capable of improving ESD tolerance in a configuration including a plurality of lateral DMOS elements.

  In order to achieve the above object, a semiconductor device according to claim 1 includes a first conductivity type semiconductor layer as a part of a semiconductor substrate and a first conductivity type opposite to the first conductivity type formed on a surface layer of the semiconductor layer. A second conductivity type well region; a first conductivity type source region formed in a surface layer of the well region; a first conductivity type drain region formed in a surface layer of the semiconductor layer apart from the well region; and a source Between the region and the drain region, a gate electrode formed on the well region via a gate insulating film, a source electrode formed on the well region and the source region, and a drain electrically connected to the drain region A semiconductor device including a plurality of lateral DMOS elements (hereinafter referred to as LDMOS elements) having electrodes. A first conductive type high concentration layer having a higher impurity concentration than the semiconductor layer is formed on the surface opposite to the well formation surface of the semiconductor layer together with the semiconductor layer as a formation region of the plurality of LDMOS elements in the semiconductor substrate. A drain electrode is directly formed on the entire surface of the semiconductor substrate opposite to the boundary with the semiconductor layer of the high concentration layer at the back surface of the gate electrode formation surface, and the drain electrode and the plurality of drain regions are respectively It is electrically connected.

  As described above, according to the present invention, the drain electrode on the side into which the surge current due to ESD flows through the pad is common to each element, and therefore the path between the pad and the drain electrode is also common, and the surge It is not affected by wiring or through holes during transmission. In addition, since the drain electrode is formed on the entire surface of the high-concentration layer, surge current easily flows, and even if there is a difference in the path length to each element in the drain electrode, the influence is conventional (connection structure by each wiring). Can also be reduced. Furthermore, the drain electrode is formed directly on the entire surface of the high concentration layer without using a contact hole. Therefore, the surge current due to ESD flows into each element almost uniformly, and the ESD tolerance can be improved as compared with the conventional case.

  Specifically, as described in claim 2, a first conductivity type connection region having an impurity concentration higher than that of the semiconductor layer is formed in the semiconductor layer, and a plurality of drain electrodes and a plurality of drain electrodes are connected via the connection region and the high concentration layer. The drain regions are preferably electrically connected to each other. With such a configuration, surge current is mainly discharged out of the device in the order of the pad, drain electrode, high concentration layer, connection region, drain region, semiconductor layer, well region, source region, and source electrode. Become. With the above configuration, even if resistance variation in the connection region occurs depending on the element, a parasitic diode composed of the semiconductor layer and the well region is activated during ESD, and surge current is discharged in the entire formation region of each element. It can be carried out. Therefore, ESD tolerance can be improved.

  In the invention described in claim 2, as described in claim 3, in the formation region of one LDMOS element, the facing distance between the connection region and the well region is larger than the facing distance between the drain region and the well region. A lengthened configuration is preferred. With such a configuration, the so-called drift length is determined by the facing distance between the drain region and the well region, so that a predetermined drift length is ensured and a decrease in breakdown voltage (drain-source breakdown voltage) is suppressed. Can do. In addition, while the connection region is present, the drain current can flow mainly in the horizontal direction, and the vertical operation can be suppressed.

  For example, as described in claim 4, in the direction perpendicular to the stacking direction of the semiconductor layer and the high concentration layer, the cross-sectional area of the connection region is made smaller than the cross-sectional area of the drain region. It can be. As described in claim 5, when the cross-sectional area of the connection region decreases from the high concentration layer toward the drain region in the direction perpendicular to the stacking direction of the semiconductor layer and the high concentration layer, The connection region can be reduced in resistance without affecting the operation.

  In the invention according to any one of claims 2 to 5, as described in claim 6, the second conductivity type diffusion region is formed between the high concentration layer, the connection region, and the semiconductor layer. Also good. With such a configuration, it is possible to suppress a leakage current in a normal operation while ensuring a withstand voltage.

  In the invention according to any one of claims 2 to 5, as described in claim 7, an isolation trench for insulating and separating the connection region and the semiconductor layer is formed around the connection region. good. With such a configuration, it is possible to suppress a parasitic element from being formed between the connection region and the portion of the semiconductor substrate excluding the connection region. In addition, since the connection region surrounded by the isolation trench does not affect the operation of the LDMOS element, it is possible to increase the cross-sectional area and lower the resistance of the connection region.

  The far isolation trench may be configured to be formed from the surface on the drain electrode forming side of the high concentration layer to the bottom of the drain region, for example. According to a ninth aspect of the present invention, the isolation trench is formed from the surface on the drain electrode formation side of the high concentration layer to the surface of the semiconductor layer through the drain region, and on the surface of the semiconductor layer, the isolation trench is formed. A connection wiring that electrically connects the connection region in the far isolation trench and the drain region outside the far isolation trench may be formed. According to invention of Claim 8, a structure can be simplified. According to the ninth aspect of the present invention, although the configuration is complicated, the formation of the far isolation trench and the formation of the trench in a portion other than the far isolation trench formation portion (for example, other than the LDMOS element formation region) in the semiconductor substrate. Can be carried out in the same process.

  Next, in the invention described in claim 1, as described in claim 10, a trench is formed in the semiconductor substrate on the surface opposite to the well formation surface of the semiconductor layer, and the drain electrode is formed in the trench. The high concentration layer may be formed on the surface, and may be formed around the formation surface of the trench so as to be in contact with the drain region. With such a configuration, the ESD resistance can be improved without forming a connection region. Note that a structure in which a part of the trench is filled with the drain electrode may be used, or a structure in which the trench is completely filled with the drain electrode may be used.

  In the invention according to any one of claims 1 to 10, for example, as described in claim 11, in the semiconductor substrate, the formation region of the LDMOS element and the region excluding the formation region of the LDMOS element are insulated and separated, The drain electrode may be formed on the entire back surface of the gate electrode formation surface of the semiconductor substrate. In this manner, a drain electrode can be formed on the entire surface of one surface of the semiconductor substrate. However, in the semiconductor substrate, when the substrate potential at a portion having an operating voltage different from that of the LDMOS element is different from that of the LDMOS element, the region where the LDMOS element is formed in the semiconductor substrate according to claim 12. The region except for the drain electrode and the drain electrode may be insulated from each other. In addition, the drain electrode may be formed only on the surface of the high concentration layer (the surface of the formation region of the LDMOS element) in the back surface of the gate electrode formation surface of the semiconductor substrate.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(First embodiment)
FIG. 1 is a cross-sectional view showing a schematic configuration of part of an LDMOS element formation region in the semiconductor device according to the first embodiment of the present invention. In FIG. 1, a protective film and a pad are omitted for convenience.

  As shown in FIG. 1, the semiconductor device 100 includes a plurality of lateral DMOS elements 101 (Lateral Double Diffusion MOS-FETs, hereinafter referred to as LDMOS elements 101) formed on a semiconductor substrate 110.

The semiconductor substrate 110 has, for example, an N conductivity type (N−) semiconductor layer 111 having an impurity concentration of about 1 × 10 ¹⁶ cm ⁻³ , the same conductivity type as the semiconductor layer 111, and a higher impurity concentration than the semiconductor layer 111. The high-concentration layer 112 of N conductivity type (N +) is laminated. The high concentration layer 112 is a contact region with the drain electrode 170 in the semiconductor substrate 110, and the impurity concentration may be a concentration that can ensure ohmic characteristics with the drain electrode 170. In consideration of the point that it also functions as a part of the current transmission path between the drain electrode 170 and the drain region 140, in the present embodiment, it is about 1 × 10 ²⁰ cm ⁻³ .

  The semiconductor substrate 110 having such a configuration can be configured by various methods by a known semiconductor process. In the present embodiment, the N conductivity type impurity is introduced into the surface layer of the formation region of the LDMOS element 101 from one surface side of the N conductivity type (N−) substrate, whereby the N conductivity type impurity is introduced into one surface of the substrate. The portion is a high concentration layer 112 and the remaining portion is a semiconductor layer 111. In addition, the high concentration layer 112 may be used as a substrate, and the semiconductor layer 111 may be provided on the high concentration layer 112 by epi growth.

The semiconductor layer 111 includes a P conductivity type (P−) having an impurity concentration of about 1 × 10 ¹⁷ cm ⁻³ , for example, on a part of a surface layer (surface layer of the semiconductor substrate 110) opposite to the boundary with the high concentration layer 112. ) Well region 120 is formed. An N conductivity type (N +) source region 130 is formed in the well region 120, which is a surface layer of the semiconductor substrate 110. The source region 130 is a contact region with the source electrode 160 in the semiconductor substrate 110, and the impurity concentration may be a concentration that can ensure ohmic characteristics with the source electrode 160. In this embodiment, it is about 1 × 10 ²⁰ cm ⁻³ . Further, an N conductivity type (N +) drain region 140 having an impurity concentration of about 1 × 10 ²⁰ cm ⁻³ is formed in the surface layer of the semiconductor layer 111 apart from the well region 120. A portion of the well region 120 sandwiched between the source region 130 and the drain region 140 is a channel formation region of the LDMOS element 101. That is, in the present embodiment, an N-channel type LDMOS element is formed as the LDMOS element 101.

  On the surface of the semiconductor substrate 110 on the side where the drain region 140 and the like are formed (on the surface of the semiconductor layer 111), on the portion of the well region 120 sandwiched between the source region 130 and the drain region 140 (channel formation region) Above, a gate electrode 150 is formed via a gate insulating film 151. A source electrode 160 is formed on part of the well region 120 and the source region 130. In the present embodiment, as shown in FIG. 1, the source electrodes 160 of the plurality of LDMOS elements 101 are integrated to form a solid common source electrode 161, and a part of the common source electrode 161 is a protective film ( A source pad (not shown) is exposed from (not shown). However, as in the prior art, the source electrode 160 of each LDMOS element 101 may be connected to a common pad via a wiring portion such as a wiring or a through hole. In FIG. 1, reference numeral 152 denotes an insulating film interposed between the gate electrode 150 and the source electrode 160, reference numeral 153 denotes an interlayer insulating film between the source electrode 160 and the common source electrode 161, and reference numeral 154 denotes The contact hole 155 formed in the insulating film 152 is a via hole formed in the interlayer insulating film 153.

  In addition, a solid drain electrode 170 is directly formed on at least the entire surface of the high concentration layer 112 on the back surface of the semiconductor substrate 110 (on the surface opposite to the boundary between the high concentration layer 112 and the semiconductor layer 111). Yes. That is, the drain electrode 170 of each LDMOS element 101 is integrated into a solid shape. In the present embodiment, the drain electrode 170 is formed only on the entire surface of the high-concentration layer 112 (only the region where the LDMOS element 101 is formed) out of the back surface of the semiconductor substrate 110. A part of the drain electrode 170 is electrically connected to a drain pad (not shown) exposed from the protective film (not shown) via a wiring part (wiring, a connection via hole or the like). ing.

Further, in the present embodiment, a connection region 180 is formed in at least the semiconductor layer 111 of the semiconductor substrate 110 in order to electrically connect the drain electrode 170 and the drain region 140. The connection region 180 functions as a current transmission path between the drain electrode 170 and the drain region 140 together with the high concentration layer 112, and has the same conductivity type as the semiconductor layer 111 and is higher than the semiconductor layer 111. It is configured as an N conductivity type (N +) region having a high impurity concentration. In the present embodiment, the impurity concentration is about 1 × 10 ²⁰ cm ⁻³ . In the present embodiment, the connection region 180 is formed only in the semiconductor layer 111 and is configured so as to function as a current transmission path between the drain electrode 170 and the drain region 140 together with the high concentration layer 112. ing. However, only the connection region 180 may serve as a current transmission path between the drain electrode 170 and the drain region 140 (configuration in which the connection region 180 is formed in the semiconductor layer 111 and the high concentration layer 112). .

  As shown in FIG. 1, in the formation region of one LDMOS element 101, the facing distance (shortest distance) h2 between the connection region 180 and the well region 120 is the facing distance (shortest distance) between the drain region 140 and the well region 120. Distance) longer than h1. More specifically, by making the cross-sectional area of the connection region 180 smaller than the cross-sectional area of the drain region 140 in the direction perpendicular to the stacking direction of the semiconductor layer 111 and the high-concentration layer 112, the facing distance h2 is made smaller than the facing distance h1. It is long. With such a configuration, since the facing distance h1 between the drain region 140 and the well region 120 becomes a so-called drift length, a predetermined drift length can be secured and a decrease in breakdown voltage (drain-source breakdown voltage) can be suppressed. . In addition, while the connection region 180 exists, the drain current flow can be mainly set in the horizontal direction (surface layer of the semiconductor layer 111), and the operation in the vertical direction can be suppressed. In the present embodiment, the cross-sectional area of the connection region 180 is substantially constant along the stacking direction of the semiconductor layer 111 and the high concentration layer 112.

  The semiconductor device 100 configured as described above can be formed using a known semiconductor process. For example, an N conductivity type (N−) substrate is prepared, and an N conductivity type (N +) connection region 180 reaching from one surface of the substrate to its back surface is formed by ion implantation. Next, a P conductivity type (P−) well region 120 is formed in the surface layer on the position surface side of the substrate, and then an N conductivity type (N +) source region 130 and a drain region 140 are formed. Note that the connection region 180 may be formed after the source region 130 and the drain region 140 are formed. Next, of the back surface of the surface on which the drain region 140 and the like of the substrate are formed, the entire region where the LDMOS element 101 is formed is an N conductivity type (N +) high concentration layer 112. The high concentration layer 112 can be formed by ion implantation, phosphorus deposition, epi growth, wafer bonding, or the like. Then, the drain electrode 170 is formed on the entire surface of the high concentration layer 112 by sputtering or the like. In addition, the semiconductor device 100 can be formed by forming the gate electrode 150, the source electrode 160, and the like on the surface side of the substrate where the drain region 140 and the like are formed.

  Next, the effect of the semiconductor device 100 having such a configuration will be described with reference to FIGS. FIG. 2 is a schematic diagram showing a current path from a drain pad to a drain region of an LDMOS element in a conventional semiconductor device as a comparison target. FIG. 3 is a schematic diagram showing a current path from the drain pad to the drain region of the LDMOS element in the semiconductor device according to the present embodiment. 2 and 3, as an example, the number of LDMOS elements 101 is three. Also for the conventional semiconductor device shown in FIG. 2, the same reference numerals are assigned to the same elements as those of the semiconductor device according to the present embodiment.

  As shown in FIG. 2, in the conventional semiconductor device 100, the drain electrode 170 of each LDMOS element 101 is connected to a common drain pad 190 via a wiring portion 200 such as a wiring or a via hole filled with a connecting member. It is connected to the. In addition, the drain electrode 170 of each LDMOS element 101 is connected to a corresponding drain region 140 formed in the semiconductor substrate 110 through a contact hole 210.

  In such a configuration, it is difficult to make the electric resistance from the drain pad 190 to the drain region 140 of each LDMOS element 101 constant. For example, the larger the element area, the higher the impedance of the wiring, and the resistance of each wiring section 200 varies depending on the length of the wiring. Further, as the number of wirings is increased, more wirings and via holes are provided as each wiring part 200. The resistance of each wiring part 200 is not only due to the difference in wiring length due to the wiring, but also due to manufacturing variations of the wirings and via holes. Will be different. In addition, a difference in resistance occurs due to manufacturing variations of the contact hole 210 that connects the drain electrode 170 and the drain region 140. Therefore, when a surge current due to ESD flows through the pad 190, a difference occurs in the transmission of the surge current from the pad 190 to the drain region 140, and the surge current is concentrated on the LDMOS element 101 having a low resistance value in the current path. The element 101 is destroyed.

  On the other hand, in the semiconductor device 100 according to the present embodiment, as described above, the drain electrode 170 of each LDMOS element 101 is integrated into a solid electrode. Therefore, as shown in FIG. 3, each element 101 has a common wiring portion 200 such as a wiring connecting the drain pad 190 and the drain electrode 170 and a connecting via hole. That is, each LDMOS element 101 has a configuration in which there is no difference in current transmission between the pad 190 and the drain electrode 170. The drain electrode 170 is formed in a solid shape on the back surface of the semiconductor substrate 110 and is connected to the drain region 140 of each LDMOS element 101 by the high concentration layer 112 and the connection region 180.

  In such a configuration, the difference in distance from the connection point of the solid drain electrode 170 to the wiring part 200 to the part corresponding to the connection region 180 of each LDMOS element 101 is an element that affects the transmission of surge current. Can be considered. However, in this embodiment, since the drain electrode 170 has a solid shape that covers the entire surface of the high concentration layer 112, current flows more easily than the conventional wiring described above, and the difference in distance contributes to the transmission of surge current. The effect is small.

  In addition, in order to form the high breakdown voltage LDMOS element 101, it is necessary to increase the thickness of the semiconductor substrate 110 (semiconductor layer 111) (for example, several μm or more). In this case, the length of the connection region 180 is several times larger than the length of a general via hole (for example, about 1 μm), thereby increasing the resistance of the connection region 180. Therefore, in addition to the distance difference, it is necessary to consider the manufacturing variation (resistance variation) of the connection region 180 as an element that affects the transmission of surge current. On the other hand, in the present embodiment, the drain electrode 170 is disposed over the entire surface of the high concentration layer 112 (the entire region where the LDMOS element 101 is formed), so that it is possible to reduce the influence of resistance variations in the connection region 180. . For example, when a part of the plurality of connection regions 180 has a higher resistance value than the others, the surge current transmitted through the high resistance connection region 180 is reduced and the potential in the vicinity thereof is locally increased. The surge current flowing into the semiconductor substrate 110 from the peripheral portion of the drain electrode 170 corresponding to the connection region 180 increases. This surge current passes through the P conductivity type well region 120 and the source electrode 160. To be discharged. As described above, in the semiconductor device 100 according to the present embodiment, it can be considered that a diode having an extremely larger area than the connection region 180 is inserted in parallel with the LDMOS element 101. The parasitic diode composed of the N-conductivity type semiconductor layer 111 and the P-conductivity type well region 120 operates at several tens to several hundreds volts, which is the peak of ESD, and operates in the normal operation of the LDMOS device 101. Therefore, it does not cause a leakage current.

  As described above, according to the semiconductor device 100 according to the present embodiment, the drain electrode 170 into which surge current due to ESD flows through the pad 190 is common to the LDMOS elements 101. A drain electrode 170 is formed on the entire surface of the high concentration layer 112. Furthermore, the drain electrode 170 is formed directly on the entire surface of the high concentration layer 112 without using a contact hole. Even if the resistance variation of the connection region 180 occurs due to the LDMOS element 101, a parasitic diode composed of the semiconductor layer 111 and the well region 120 is activated during ESD, and surge current is discharged in the formation region of each LDMOS element 101. Can be done in total. Therefore, the surge current due to ESD flows into each LDMOS element 101 almost uniformly, and the ESD tolerance can be improved as compared with the conventional case.

  In addition, in the direction perpendicular to the stacking direction of the semiconductor layer 111 and the high concentration layer 112, the cross-sectional area of the connection region 180 is made smaller than the cross-sectional area of the drain region 140, so The facing distance h <b> 2 between the region 180 and the well region 120 is longer than the facing distance h <b> 1 between the drain region 140 and the well region 120. Therefore, it is possible to secure a predetermined drift length and suppress a decrease in breakdown voltage. Further, while the connection region 180 exists, the drain current can flow mainly in the horizontal direction, and the vertical operation can be suppressed.

  In the present embodiment, an example in which the source electrode 160 is disposed on the front surface side of the semiconductor substrate 110 and the drain electrode 170 is disposed in a solid shape on the back surface side of the semiconductor substrate 110 is shown. On the other hand, it is also conceivable that the drain electrode 170 is disposed on the front surface side of the semiconductor substrate 110 and the source electrode 160 is disposed in a solid shape on the back surface side of the semiconductor substrate 110. However, even if the drain electrode 170 has a solid shape in such a configuration, since the drain electrode 170 is connected to the semiconductor substrate 110 (drain region 140) through the contact hole, due to manufacturing variation (resistance variation) of the contact hole, There may be a difference in the transmission of surge current. Therefore, as shown in the present embodiment, it is preferable that the drain electrode 170 on the side into which the surge current flows is arranged on the back side of the semiconductor substrate 110.

  In a vertical power MOS device typified by a VDMOS device, the source electrode is disposed on the front surface side of the semiconductor substrate, and the drain electrode is disposed on the back surface side of the semiconductor substrate. However, since the vertical power MOS device has design factors in the thickness direction of the semiconductor substrate, it is difficult to integrate it with other devices such as CMOS. On the other hand, according to the semiconductor device 100 including the LDMOS element 101 as shown in the present embodiment, process consistency with other elements such as CMOS is good, and integration is easy.

  Further, in the present embodiment, an example is shown in which the cross-sectional area of the connection region 180 is substantially constant along the stacking direction of the semiconductor layer 111 and the high concentration layer 112. However, the form of the connection region 180 can be adopted as long as the drain current flows in the horizontal direction and the operation in the vertical direction can be suppressed. For example, as shown in FIG. 4, the cross-sectional area of the connection region 180 may decrease from the high concentration layer 112 toward the drain region 140 in a direction perpendicular to the stacking direction of the semiconductor layer 111 and the high concentration layer 112. . With such a configuration, the resistance of the connection region 180 can be reduced without affecting the operation of the LDMOS element 101. FIG. 4 is a cross-sectional view showing a modification.

  In the present embodiment, an example in which the semiconductor substrate 110 includes the semiconductor layer 111 including the connection region 180 and the high concentration layer 112 has been described. However, for example, as shown in FIG. 5, between the high concentration layer 112 and the semiconductor layer 111 and between the connection region 180 and the semiconductor layer 111, a P conductivity type (P− ) Diffusion region 220 may be formed. Such a configuration can be obtained by forming the high concentration layer 112 after the diffusion region 220 is formed. With such a configuration, it is possible to secure a withstand voltage with respect to the semiconductor substrate 110 and to make it difficult to generate a leakage current in normal operation. FIG. 5 is a cross-sectional view showing a modification.

  In the present embodiment, the drain electrode 170 is connected to the pad 190 through the wiring part 200. However, a configuration in which a part of the drain electrode 170 is exposed from the protective film to form the pad 190 may be adopted. Even with such a configuration, not only can the same effect as the above-described configuration be exhibited, but also a surge current can easily flow because the wiring portion 200 can be omitted.

(Second Embodiment)
Next, a second embodiment of the present invention will be described based on FIG. FIG. 6 is a cross-sectional view showing a schematic configuration of part of the LDMOS element formation region in the semiconductor device according to the second embodiment.

  Since the semiconductor device according to the second embodiment is often in common with the semiconductor device shown in the first embodiment, the detailed description of the common parts will be omitted below, and different parts will be described mainly. In addition, the same code | symbol shall be provided to the element same as the element shown in 1st Embodiment.

  As shown in FIG. 6, the present embodiment is characterized in that an isolation trench 230 is formed around the connection region 180 so as to insulate and isolate the connection region 180 and the semiconductor layer 111. In the present embodiment, trenches are formed substantially vertically over a range from the surface of the high concentration layer 112 on the drain electrode formation side (surface where the drain electrode 170 is disposed) to the bottom of the drain region 140, and many trenches are formed in the trench. An isolation trench 230 is formed by filling crystalline silicon, silicon oxide, or the like. Note that the cross-sectional area of the connection region 180 surrounded by the isolation trench 230 in the direction perpendicular to the stacking direction of the semiconductor layer 111 and the high-concentration layer 112 is slightly smaller than the cross-sectional area of the drain region 140, but It is larger than the cross-sectional area shown in one embodiment.

  As described above, according to the semiconductor device 100 according to the present embodiment, the distant isolation trench 230 prevents a parasitic element from being formed between the connection region 180 and the portion of the semiconductor substrate 110 excluding the connection region 180. be able to. Therefore, it is suitable for high temperature and can cope with a finer layout.

  Further, since the connection region 180 surrounded by the far isolation trench 230 does not affect the operation of the LDMOS element 101, the cross-sectional area can be increased and the resistance of the connection region 180 can be further reduced. That is, the ESD resistance can be improved while reducing the on-resistance.

  In the present embodiment, the example in which the far isolation trench 230 is formed over the range from the surface on the drain electrode formation side of the high concentration layer 112 to the bottom of the drain region 140 is shown. However, the far isolation trench 230 can be adopted as long as it does not impair the function of the LDMOS element 101 while insulatingly separating the connection region 180 and the semiconductor layer 111. For example, as shown in FIG. 7, an isolation trench 230 is formed from the surface on the drain electrode formation side of the high concentration layer 112 to the surface of the semiconductor layer 111 through the drain region 140, and on the surface of the semiconductor layer 111. Alternatively, a connection wiring 240 that electrically connects the connection region 180 in the far isolation trench 230 and the drain region 140 outside the far isolation trench 230 may be formed. As described above, the configuration in which the isolation trench 230 penetrates over the front and back surfaces of the semiconductor substrate 110 is more complicated than the above configuration, but the formation of the isolation trench 230 and the isolation in the semiconductor substrate 110 are performed. Trench formation in a part other than the isolation trench formation part (for example, other than the LDMOS element formation region) can be performed in the same process. FIG. 7 is a cross-sectional view showing a modification.

(Third embodiment)
Next, a third embodiment of the present invention will be described with reference to FIG. FIG. 8 is a cross-sectional view showing a schematic configuration of part of the LDMOS element formation region in the semiconductor device according to the third embodiment.

  Since the semiconductor device according to the third embodiment is common in common with the semiconductor device shown in the first embodiment, a detailed description of the common parts will be omitted below, and different parts will be described mainly. In addition, the same code | symbol shall be provided to the element same as the element shown in 1st Embodiment.

  In each of the embodiments described above, the drain electrode 170 and the drain region 140 are electrically connected via the high concentration layer 112 and the connection region 180. On the other hand, in the present embodiment, for example, as shown in FIG. 8, a trench 113 is formed in the semiconductor substrate 110 so as to open on the surface opposite to the well formation surface of the semiconductor layer 111, and the drain electrode 170 is It is also formed on the formation surface, and is characterized in that the high concentration layer 112 is formed around the formation surface of the trench and is in contact with the drain region 140. That is, the drain electrode 170 and the drain region 140 are electrically connected through only the high concentration layer 112. In this configuration, after forming the trench 113 having a depth that does not reach the drain region 140 from the back surface side of the semiconductor substrate 110, the LDMOS element 101 including the trench 113 is formed on the back surface of the semiconductor substrate 110. A high concentration layer 112 that reaches the drain region 140 is formed on the entire region by ion implantation or the like. Then, it can be obtained by forming the drain electrode 170 on at least the entire surface of the high concentration layer 112 on the back surface of the semiconductor substrate 110.

  Thus, according to the semiconductor device 100 according to the present embodiment, the ESD tolerance can be improved without forming the connection region 180.

  In the present embodiment, as shown in FIG. 8, the example in which the concave portion 171 is provided on the surface of the drain electrode 170 corresponding to the trench 113 is shown. That is, a configuration in which a part of the trench 113 is filled with the drain electrode 170 is shown. However, as shown in FIG. 9, the trench 113 may be completely filled with the drain electrode 170. FIG. 9 is a cross-sectional view showing a modification.

  The preferred embodiments of the present invention have been described above. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention.

  In the present embodiment, as an example having a plurality of LDMOS elements, the example in which the semiconductor device 100 has a plurality of N-channel type LDMOS elements 101 is shown. However, the configurations of the above-described embodiments can also be applied to the P-channel type LDMOS element 101. Further, it may be configured to have the N-channel type and P-channel type LDMOS elements 101, respectively.

  In the present embodiment, in the semiconductor device 100, the configuration other than the LDMOS element 101 is not particularly mentioned. However, in actual applications, they are often integrated with other elements having different operating voltages, such as CMOS and bipolar. In such a case, the drain electrode 170 may be disposed in a solid form at least on the entire surface of the high concentration layer 112, but if the insulation from the portion other than the LDMOS element 101 can be ensured, the drain electrode 170 may be disposed on the entire back surface of the semiconductor substrate 110. It is also possible to arrange the drain electrode 170. However, it may not be desirable to make the substrate potential of a portion having a different operating voltage, such as a circuit portion, the same as that of the LDMOS element 101. In this case, for example, as shown in FIG. 10, an insulating film 250 is formed in a portion corresponding to a portion other than the LDMOS element 101 (the circuit portion 102 in FIG. 10) on the back surface of the semiconductor substrate 110, thereby The semiconductor substrate 110 and the drain electrode 170 may be insulated and separated. With such a configuration, the back surface potential other than the LDMOS element 101 can be appropriately controlled to a predetermined potential. Note that, in such a semiconductor device 100, for example, after the insulating film 250 is removed only in the formation region of the LDMOS element 101 and a high concentration layer 112 is selectively formed on a wafer provided with a buried oxide film as the insulating film 250. The drain electrode 170 can be formed on the entire back surface of the semiconductor substrate 110. Also, in the case where electrical insulation with the side surface of the formation region of the LDMOS element 101 is a problem, as shown in FIG. 10, as shown in FIG. A conductive P conductivity type (P−) region 260 may be formed. FIG. 10 is a cross-sectional view showing another modification.

  When capacitive coupling between the drain electrode 170 and the portion other than the LDMOS element 101 in the semiconductor substrate 110 via the insulating film 250 becomes a problem, as shown in this embodiment, the back surface of the semiconductor substrate 110 is used. Of these, the drain electrode 170 may be formed only in the formation region of the LDMOS 101 (only the surface of the high concentration layer 112). Further, if necessary, an ESD protection element such as a diode may be formed in a portion of the semiconductor substrate 110 other than the LDMOS element 101, and the insulating film 250 in this portion may be removed.

  Further, as shown in FIG. 11, instead of the insulating film 250, a P conductivity type (P−) region 270 having a conductivity type opposite to that of the semiconductor substrate 110 may be formed. That is, a potential barrier may be formed. When the LDMOS potential is low, the insulating film 250 can be dispensed with and can be formed at a lower cost. FIG. 11 is a cross-sectional view showing another modification.

1 is a cross-sectional view showing a schematic configuration of a part of an LDMOS element formation region in a semiconductor device according to a first embodiment. It is a schematic diagram showing a current path from a drain pad to a drain region of an LDMOS element in a conventional semiconductor device as a comparison target. FIG. 4 is a schematic diagram showing a current path from a drain pad to a drain region of an LDMOS element in the semiconductor device according to the present embodiment. It is sectional drawing which shows a modification. It is sectional drawing which shows a modification. It is sectional drawing which shows schematic structure of a part of LDMOS element formation area among the semiconductor devices which concern on 2nd Embodiment. It is sectional drawing which shows a modification. It is sectional drawing which shows schematic structure of a part of LDMOS element formation area among the semiconductor devices which concern on 3rd Embodiment. It is sectional drawing which shows a modification. It is sectional drawing which shows another modification. It is sectional drawing which shows another modification.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... Semiconductor device 101 ... LDMOS element 110 ... Semiconductor substrate 111 ... Semiconductor layer 112 ... High concentration layer 120 ... Well region 130 ... Source region 140 ... Drain region 170 ... Drain electrode 180 ... Connection region 190 ... Drain pad 200 ... Wiring part 210 ... Contact part

Claims (12)

A first conductivity type semiconductor layer as a part of the semiconductor substrate;
A well region of a second conductivity type opposite to the first conductivity type formed in a surface layer of the semiconductor layer;
A first conductivity type source region formed in a surface layer of the well region;
A drain region of a first conductivity type formed in a surface layer of the semiconductor layer apart from the well region;
A gate electrode formed on the well region via a gate insulating film between the source region and the drain region;
A source electrode formed on the well region and the source region;
A semiconductor device comprising a plurality of lateral DMOS elements each having a drain electrode electrically connected to the drain region,
As a formation region of the plurality of lateral DMOS elements in the semiconductor substrate, a first conductivity type high impurity concentration higher than that of the semiconductor layer is formed on the surface opposite to the well formation surface of the semiconductor layer together with the semiconductor layer. A concentration layer is formed,
The drain electrode is directly formed on the entire surface of the semiconductor substrate opposite to the boundary with the semiconductor layer of the high-concentration layer on the back surface of the gate electrode formation surface,
The semiconductor device, wherein the drain electrode and the plurality of drain regions are electrically connected to each other. A connection region of a first conductivity type having a higher impurity concentration than the semiconductor layer is formed in the semiconductor layer,
The semiconductor device according to claim 1, wherein the drain electrode and the plurality of drain regions are electrically connected to each other through the connection region and the high concentration layer.   3. The semiconductor according to claim 2, wherein in one formation region of the lateral DMOS element, a facing distance between the connection region and the well region is longer than a facing distance between the drain region and the well region. apparatus.   4. The semiconductor device according to claim 3, wherein a cross-sectional area of the connection region is smaller than that of the drain region in a direction perpendicular to a stacking direction of the semiconductor layer and the high concentration layer.   4. The cross-sectional area of the connection region decreases from the high concentration layer toward the drain region in a direction perpendicular to the stacking direction of the semiconductor layer and the high concentration layer. Item 5. The semiconductor device according to Item 4.   6. The semiconductor device according to claim 2, wherein a diffusion region of a second conductivity type is formed between the high-concentration layer and the connection region and the semiconductor layer.   7. The semiconductor device according to claim 2, wherein an isolation trench that insulates and isolates the connection region from the semiconductor layer is formed around the connection region.   The semiconductor device according to claim 7, wherein the far isolation trench is formed from a surface of the high concentration layer on a drain electrode forming side to a bottom of the drain region. The distant isolation trench is formed from the surface on the drain electrode forming side of the high concentration layer to the surface of the semiconductor layer through the drain region,
8. A connecting wiring for electrically connecting a connection region in the far isolation trench and a drain region outside the far isolation trench is formed on the surface of the semiconductor layer. A semiconductor device according to 1. In the semiconductor substrate, a trench is formed that opens on a surface opposite to the well formation surface of the semiconductor layer,
The drain electrode is also formed on the formation surface of the trench,
The semiconductor device according to claim 1, wherein the high-concentration layer is formed around a formation surface of the trench and is in contact with the drain region. In the semiconductor substrate, the formation region of the lateral DMOS element and the region excluding the formation region of the lateral DMOS element are insulated and separated.
The semiconductor device according to claim 1, wherein the drain electrode is formed on the entire back surface of the gate electrode forming surface of the semiconductor substrate.   The semiconductor device according to claim 11, wherein a region of the semiconductor substrate excluding the formation region of the lateral DMOS element and the drain electrode are insulated and separated.

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