WO2016194419A1

WO2016194419A1 - Semiconductor device and method for manufacturing semiconductor device

Info

Publication number: WO2016194419A1
Application number: PCT/JP2016/055982
Authority: WO
Inventors: 史郎日野; 康史貞松; 英之八田; 泰宏香川; 勝俊菅原
Original assignee: 三菱電機株式会社
Priority date: 2015-06-04
Filing date: 2016-02-29
Publication date: 2016-12-08
Also published as: JP2018120879A

Abstract

This semiconductor device (101) has, when viewed in plan, an active region (R1) and a termination region (R2) that is in a region different from the active region (R1). The semiconductor device (101) comprises a first electrode (80), a second electrode (81) and a metal electrode film (87S). The first electrode (80) is arranged in the active region (R1). The second electrode (81) is arranged in the termination region (R2), and is separated from the first electrode (80). The metal electrode film (87S) electrically connects the first electrode (80) and the second electrode (81).

Description

Semiconductor device and manufacturing method of semiconductor device

The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

It is known that the forward voltage increases when a forward current continues to flow through a pn diode using silicon carbide (SiC) (for example, see Non-Patent Document 1 below). This is due to the recombination energy when minority carriers injected through the pn diode recombine with the majority carriers, starting from basal plane dislocations existing in the silicon carbide substrate, and so on. This is considered to be due to the fact that the stacking fault is also expanded into the crystal (for example, see Non-Patent Document 2 below). The increase in the forward voltage of the pn diode is thought to be because the triangular stacking fault hinders the flow of current. This increase in forward voltage can cause reliability degradation.

There is a report that such a forward voltage shift occurs in a similar manner in a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) using silicon carbide (for example, see Non-Patent Document 3 below). The MOSFET structure has a parasitic pn diode (body diode) between the source and the drain, and when a forward current flows through the body diode, reliability degradation similar to that of the pn diode is caused. This problem is alleviated when a Schottky barrier diode chip having a low forward voltage is connected in parallel as a free wheel diode to the MOSFET chip. However, when a diode is externally attached, the number of parts of the device increases. On the other hand, when the MOSFET body diode is responsible for all or part of the function as a freewheeling diode, the above-described reliability degradation can reach the MOSFET chip.

As a method for dealing with this problem, for example, as mentioned in the following Patent Document 1, a stress test is performed in which a forward current is passed through a pn diode structure for a long time and a change in forward voltage before and after this is measured. is there. Higher reliability can be ensured by excluding (screening) elements with large deterioration from the product in the stress test. The amount of fluctuation in the forward voltage that is noticed for determining the presence or absence of deterioration is proportional to the area of the stacking fault. The expansion rate of this area is approximately proportional to the integrated amount of minority carriers injected through the pn diode. This integrated amount depends on the magnitude of the current and the time during which the current is applied. If the current is excessively increased in order to finish the test in a short time, the diode or the test apparatus may be damaged due to excessive heat generation of the diode element. On the other hand, when the current is reduced, a long time is required for the test, and as a result, there are practical problems such as an increase in chip cost.

On the other hand, in a semiconductor chip as a unipolar transistor such as a MOSFET, a diode that conducts electricity only by majority carriers, that is, a unipolar diode, is incorporated as a freewheeling diode in place of a pn diode that can lead to reliability deterioration as described above. Is possible. For example, in Patent Documents 2 and 3 below, a SBD (Schottky Barrier Diode) is built in a MOSFET unit cell as a unipolar diode. A unipolar diode having an operating voltage lower than the operating voltage of the body diode is built in the unit cell as the active region of the unipolar transistor, so that a forward current is supplied to the body diode in the active region in actual use. It can be prevented from flowing. Thereby, characteristic deterioration of the active region can be suppressed.

However, in regions other than the active region, particularly in the termination region around the active region, there are places where unipolar diodes cannot be placed in view of the structure or function of the region, although parasitic diodes exist. If a starting point such as a basal plane dislocation exists at this location, the triangular stacking fault expands and the characteristics of the transistor deteriorate. Specifically, the voltage drop when the source / drain current is applied increases. As a result, there is a concern that the device may be destroyed due to thermal runaway during actual use. For this reason, even if the SBD is incorporated in the unipolar transistor, it is useful for screening by a stress test. Here, since the operating voltage of the SBD is lower than the operating voltage of the parasitic diode, most of the stress current used for the stress test mainly passes through the built-in SBD, not the parasitic diode that needs to be tested. . The current passing through the built-in SBD also causes Joule heat that causes the element to generate heat. Therefore, it is necessary to reduce the stress current to such an extent that thermal damage of the chip or the evaluation facility due to the heat generation of the element can be prevented. As a result, the test time becomes long.

Furthermore, when the amount of stress current flowing through the active region is large, current begins to flow through the parasitic pn diode in the active region. As a result, stacking faults are generated in the active region that originally does not require a stress test. This stacking fault may cause the forward voltage of the MOSFET to fluctuate. If the forward voltage out of specification is removed, the chip manufacturing yield will be low.

As described above, a transistor having a built-in unipolar diode has a problem that a stress test for screening requires a long time. In addition, there is a problem in that the transistor characteristics greatly vary due to the stress test. The generation of triangular stacking faults that cause these problems is well known for SiC, but can also occur in other wide bandgap semiconductors.

In order to solve such a problem, the present inventors have electrically connected both the first well region provided on the drift layer in the active region and the second well region provided on the drift layer in the termination region. Prior to forming the connected source electrode, it has been considered to provide first and second electrodes connected to each of the first well region in the active region and the second well region in the termination region. By causing the stress current to flow only to the second electrode instead of the first electrode, the stress current mainly flows to the second well region, not the first well region. As a result, the stress current selectively flows mainly in the termination region, not in the active region. Therefore, it is possible to increase the stress current density to the pn diode formed by the second well region and the drift layer in the termination region while suppressing the amount of heat generated in the chip being tested. Thereby, the required screening time can be shortened. Moreover, yield reduction can be suppressed by suppressing fluctuations in the characteristics of the active region during screening. Thereby, an inexpensive chip is realized by reducing the screening cost.

In actual use, the first electrode and the second electrode are preferably short-circuited. If the potential of the second well region is not properly maintained at the source potential (the potential of the first electrode) due to the short circuit not being performed, a high potential can be generated in the second well region during a switching operation or the like. There is a concern that this high potential destroys the insulating film on the second well region. Therefore, it is desirable to connect between the first electrode and the second electrode after the stress test.

As described above, not only in a unipolar transistor in which a unipolar diode is incorporated in an active region, but also in a semiconductor device, it may be necessary to connect a plurality of electrodes after performing an inspection or a stress test. is there. For example, in Patent Document 4 described below, first, a plurality of semiconductor elements are inspected, whereby a good semiconductor element and a defective semiconductor element are discriminated. Thereafter, only the source electrode pad of the non-defective semiconductor element is connected to the source electrode terminal by wire bonding. Thereby, a semiconductor device having a plurality of semiconductor elements can be manufactured at a low cost while ensuring a high yield. However, the following two problems occur in the method of connecting by wire bonding.

First, the chip cost increases. In order to perform wire bonding, the pad area requires a relatively large size. This pad region is not an active region, and is not a region where a unit cell having an original function as an element can be disposed. For this reason, if a pad region for wire bonding is provided, the size of a chip having a predetermined element resistance is increased. The cost increases as the chip size increases, and this problem is particularly noticeable when a single crystal substrate made of a wide band gap semiconductor such as silicon carbide is used. In addition, it may be necessary to hit a large number of bonding wires, which increases process costs.

Second, problems can arise due to the parasitic impedance of the bonding wire. For example, when the connection between the first and second electrodes is performed by wire bonding, the termination region and the active region are different from the case where the termination region and the active region are connected by a single source electrode. Are connected via a large parasitic inductance. The parasitic inductance increases as the bonding wires are longer, and as each bonding wire is thinner and the number of bonding wires is smaller. Due to this parasitic impedance, the potential of the second well region deviates from the source potential. For example, when the source current or displacement current flowing through the second electrode changes with time during the transient response of the semiconductor device, the counter electromotive force according to the product of the parasitic inductance (Ls) and the time change of the current (di / dt). Occurrence of the potential causes the potential of the second well region to deviate from the source potential, thereby causing various problems. Specifically, the insulating film on the second well region may be destroyed, or oscillation may occur due to a combination of parasitic inductance and parasitic capacitance in the semiconductor. For this reason, when the parasitic inductance is large, there arises a problem that the switching speed must be kept low. In a power semiconductor device, the switching loss tends to increase as the switching speed is low. Therefore, the restriction on the switching speed may lead to an increase in power loss.

On the other hand, in Patent Document 5 below, a plurality of semiconductor chips are formed, and an electrode in a defective chip area determined to be unable to realize desired characteristics is covered with a mask portion made of an insulating material. In other regions, the electrodes are connected to each other by a wiring layer penetrating the insulating protective layer. This technique requires formation of an insulating protective layer and patterning by photolithography and etching to form an opening that penetrates the insulating protective layer. This increases the process cost. In addition, since the process of forming the insulating protective layer generally requires heating to a high temperature, it may adversely affect the already formed structure, and in particular may cause oxidation of the formed electrode. is there. In addition, the etching process may adversely affect the electrode, and in particular, there may be a concern that the wet etching etchant may adversely affect the electrode. Further, depending on the structure in which the wiring layer passes through the through hole, parasitic impedance can be a problem.

The present invention has been made to solve the above-described problems, and one object of the present invention is to perform an inspection or a stress test involving a process of making the potentials of a plurality of electrodes different from each other, and then the electrodes are connected to each other. Is to provide a semiconductor device that can be short-circuited with low impedance.

The semiconductor device according to one aspect of the present invention has an active region and a termination region in a region different from the active region in plan view. The semiconductor device has a first electrode, a second electrode, and a metal electrode film. The first electrode is disposed in the active region. The second electrode is disposed in the termination region and is separated from the first electrode. The metal electrode film electrically connects the first electrode and the second electrode.

A semiconductor device according to another aspect of the present invention includes a first electrode, a second electrode, and a metal electrode film. The first electrode has a first side surface. The second electrode is separated from the first electrode in plan view, and has a second side surface facing the first side surface. The metal electrode film connects between the first side surface of the first electrode and the second side surface of the second electrode.

The method for manufacturing a semiconductor device of the present invention includes the following steps. A first electrode and a second electrode separated from the first electrode are formed. A predetermined potential is applied to the first electrode. A potential different from the potential of the first electrode is applied to the second electrode. After a potential different from the potential of the first electrode is applied to the second electrode, a metal electrode film that electrically connects the first electrode and the second electrode is formed.

According to the semiconductor device according to one aspect of the present invention, the second electrode located in the termination region is provided separately from the first electrode located in the active region. An inspection or stress test on the termination region by applying a potential different from the potential of the first electrode to the second electrode can be performed using the second electrode. Thereby, the current flowing through the active region can be suppressed. Therefore, in the inspection or stress test, first, the amount of heat generated in the active region becomes smaller. Accordingly, since a larger current can be used, the inspection or the stress test can be performed in a shorter time. Secondly, the influence on the active region by the inspection or the stress test is suppressed. This makes it difficult for the semiconductor characteristics to vary due to the inspection or the stress test. As described above, the time for the inspection or stress test can be shortened, and fluctuations in the semiconductor characteristics due to the inspection or stress test can be suppressed. Further, the first electrode and the second electrode are short-circuited with low impedance by the metal electrode film straddling the first electrode and the second electrode.

According to the semiconductor device according to another aspect of the present invention, the inspection or stress test by applying a potential different from the potential of the first electrode to the second electrode is performed using the second electrode before forming the metal electrode film. Can do. As a result, the current flowing in the vicinity of the first electrode can be suppressed. Therefore, in the inspection or stress test, first, the amount of heat generated in the vicinity of the first electrode becomes smaller. Accordingly, since a larger current can be used, the inspection or the stress test can be performed in a shorter time. Second, the influence on the vicinity of the first electrode due to the inspection or the stress test is suppressed. This makes it difficult for the semiconductor characteristics to vary due to the inspection or the stress test. As described above, the time for the inspection or stress test can be shortened, and fluctuations in the semiconductor characteristics due to the inspection or stress test can be suppressed. Further, the first electrode and the second electrode are short-circuited with low impedance by the metal electrode film connecting the first side surface of the first electrode and the second side surface of the second electrode facing each other.

According to the method for manufacturing a semiconductor device of the present invention, an inspection or stress test by applying a potential different from the potential of the first electrode to the second electrode can be performed using the second electrode before forming the metal electrode film. it can. As a result, the current flowing in the vicinity of the first electrode can be suppressed. Therefore, in the inspection or stress test, first, the amount of heat generated in the vicinity of the first electrode becomes smaller. Accordingly, since a larger current can be used, the inspection or the stress test can be performed in a shorter time. Second, the influence on the vicinity of the first electrode due to the inspection or the stress test is suppressed. This makes it difficult for the semiconductor characteristics to vary due to the inspection or the stress test. As described above, the time for the inspection or stress test can be shortened, and fluctuations in the semiconductor characteristics due to the inspection or stress test can be suppressed. Further, the first electrode and the second electrode are short-circuited with low impedance by the metal electrode film straddling the first electrode and the second electrode.

The objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description and the accompanying drawings.

JP 2004-289023 A JP 2003-017701 A International Publication No. 2014/038110 JP 2010-251772 A JP 2013-149805 A

1 is a plan view schematically showing a configuration of a semiconductor device in a first embodiment of the present invention. FIG. 2 is a schematic partial sectional view taken along line II-II in FIG. It is a top view which shows roughly 1 process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention. It is a top view which shows roughly the structure of the semiconductor device of a comparative example. FIG. 5 is a schematic partial sectional view taken along line VV in FIG. 3. FIG. 4 is a schematic partial sectional view taken along line VI-VI in FIG. 3. It is a fragmentary sectional view which shows the modification of FIG. It is a top view which shows roughly the structure of the semiconductor device in Embodiment 2 of this invention. FIG. 9 is a schematic partial cross-sectional view taken along line IX-IX in FIG. 8.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<Embodiment 1>
(Constitution)
First, the configuration of MOSFET 101 (semiconductor device) of the present embodiment will be described with reference to FIGS. MOSFET 101 has an active region R1 (FIG. 2) and a termination region R2 in addition to the active region R1 in plan view. Unit cells are periodically arranged in the active region R1. Each unit cell is provided with a MOSFET element as a semiconductor element. Further, the MOSFET 101 has a built-in SBD, which will be described in detail later. The unit cell is not arranged in the termination region R2. The termination region R2 is typically disposed between the active region R1 and the outer end (right end in FIG. 2) of the substrate 10, and is provided with a configuration for improving the breakdown voltage characteristics of the MOSFET 101. The termination region R2 preferably surrounds the active region R1, and more preferably completely surrounds the termination region R1.

The MOSFET 101 includes an n-type (first conductivity type) substrate 10 (semiconductor substrate), a semiconductor layer on the substrate 10, a gate insulating film 50, a field insulating film 52, an interlayer insulating film 55, and a source electrode 80. (First electrode), test electrode 81 (second electrode), metal film 87, gate electrode 82 (separation electrode), ohmic electrode 79, and drain electrode 85 (third electrode). The semiconductor layer includes an n-type drift layer 20, a plurality of first well regions 30 having a p-type (second conductivity type different from the first conductivity type), a second well region 31 having a p-type, A source region 40 having an n-type and a JTE (Junction Termination Extension) region 37 having a p-type are included.

The substrate 10 is made of a semiconductor, for example, silicon carbide having a 4H polytype. The impurity concentration of the substrate 10 is preferably higher than the impurity concentration of the drift layer 20. The surface orientation of one surface (upper surface in FIG. 2) of the substrate 10 is, for example, a surface inclined by about 4 ° from the (0001) surface.

The drain electrode 85 is provided on the other surface (the lower surface in FIG. 2) of the substrate 10 via an ohmic electrode 79. The ohmic electrode 79 is in contact with the lower surface of the substrate 10. Thus, the drain electrode 85 is electrically ohmically connected to the substrate 10.

The drift layer 20 is provided on the substrate 10. Drift layer 20 is made of a wide band gap semiconductor. In the present embodiment, drift layer 20 is made of silicon carbide having a hexagonal crystal structure. In the present embodiment, the entire semiconductor layer on substrate 10 is made of silicon carbide as a wide band gap semiconductor. That is, the semiconductor layer is a silicon carbide layer.

The plurality of first well regions 30 are disposed in the active region R1 and are provided on the drift layer 20 so as to be separated from each other. Accordingly, the first separation region 21 or the second separation region 22 made of the drift layer 20 is provided between the first well regions 30 adjacent to each other on the semiconductor layer. For example, the first separation region 21 and the second separation region 22 are alternately arranged. On the drift layer 20, the plurality of first well regions 30 may be provided so as to be separated from each other in a sectional view in one plane as shown in FIG. They may be connected to each other at places other than vision.

The source region 40 is provided on each of the first well regions 30 in the surface layer portion of the semiconductor layer. The depth of the source region 40 is shallower than the depth of the first well region 30, and the source region 40 is separated from the drift layer 20 by the first well region 30. For example, nitrogen (N) is used as a conductive impurity (donor impurity) for imparting n-type to the source region 40.

The first well region 30 is disposed in each of unit cells provided periodically in the MOSFET 101. Therefore, the plurality of first well regions 30 are periodically arranged. Each of the first well regions 30 has a p-type first high concentration region 35 between the source region 40 and the second separation region 22 in the surface layer portion of the semiconductor layer. The first high concentration region 35 has a higher impurity concentration than the impurity concentration of other regions of the first well region 30. Therefore, the first high concentration region 35 has a lower electrical resistance than other portions in the first well region 30.

The second well region 31 is disposed in the termination region R2 around the active region R1, and is provided on the drift layer 20 so as to be separated from the plurality of first well regions 30. The width of the separation region between the first well region 30 and the second well region 31 is approximately the same as the width of the first separation region 21. The area of the second well region 31 is larger than the area of the single first well region 30. The second well region 31 projects outward from the source electrode 80 (on the right side in FIG. 2) in the planar layout. The second well region 31 has a second high concentration region 36 located in the surface layer portion of the semiconductor layer. The second high concentration region 36 has a higher impurity concentration than the impurity concentration of other regions of the second well region 31. Therefore, the second high concentration region 36 has a lower electrical resistance than other portions in the second well region 31.

The second well region 31 preferably has the same concentration profile due to the same type of conductive impurities as the first well region 30. In this case, the first well region 30 and the second well region 31 are simultaneously formed. Can be formed. The second high concentration region 36 preferably has the same concentration profile due to the same type of conductive impurities as the first high concentration region 35. In this case, the first

high concentration regions

35 and 36 are simultaneously formed. Can be formed. As a conductive impurity (acceptor impurity) for imparting p-type to the first well region 30 and the second well region 31, for example, aluminum (Al) is used.

The JTE region 37 is arranged on the outer peripheral side (the right side in FIG. 2) of the second well region 31 and is connected to the second well region 31. The JTE region 37 has an impurity concentration lower than that of the second well region 31.

The gate insulating film 50 is provided on the first well region 30 and straddles the first well region 30 between the source region 40 and the first separation region 21. The gate insulating film 50 is preferably made of silicon oxide, for example, a thermal oxide film.

The gate electrode 82 has a gate electrode part 60 and a gate wiring layer 82 w in contact with the gate electrode part 60. The gate electrode portion 60 is provided on the gate insulating film 50 and straddles the first well region 30 between the source region 40 and the first separation region 21 via the gate insulating film 50. With this configuration, a portion of the first well region 30 that faces the gate electrode portion 60 through the gate insulating film 50 between the first separation region 21 and the source region 40 functions as a channel region. The channel region is a region where an inversion layer is formed when the MOSFET 101 is turned on by controlling the potential of the gate electrode unit 60. The resistivity of the material of the gate wiring layer 82w is preferably lower than the resistivity of the material of the gate electrode portion 60. The gate electrode 82 is electrically insulated from the source electrode 80 and the test electrode 81. In other words, the gate electrode 82 is not short-circuited with the source electrode 80 and the test electrode 81.

The field insulating film 52 is provided on the semiconductor layer in the termination region R2. Therefore, the field insulating film 52 is provided on the second well region 31 separately from the first well region 30. The thickness of the field insulating film 52 is larger than the thickness of the gate insulating film 50. The field insulating film 52 is disposed on the outer peripheral side of the gate insulating film 50. Gate electrode portion 60 has a portion extending onto field insulating film 52. In the configuration shown in FIG. 2, the field insulating film 52 has an inner peripheral end in contact with the outer peripheral end of the gate insulating film 50. The inner peripheral edge of the field insulating film 52 is preferably closer to the active region R1 than the end of the second high concentration region 36 on the active region R1 side. This is because, when the gate insulating film 50 is formed up to the second high concentration region 36, the second high concentration region 36 has a high impurity concentration, and therefore, the insulating characteristics of the gate insulating film 50 to be formed. This is because the value becomes lower on the second high concentration region 36. The inner peripheral edge of the field insulating film 52 is preferably in a plan view of the second well region 31, that is, on the second well region 31.

The interlayer insulating film 55 covers the gate electrode portion 60 provided on the gate insulating film 50 and the field insulating film 52. Interlayer insulating film 55 is preferably made of silicon oxide. The interlayer insulating film 55 is provided with a gate contact hole 95 exposing the gate electrode portion 60 in the termination region R2. The gate wiring layer 82 w of the gate electrode 82 is connected to the gate electrode portion 60 in the gate contact hole 95. The gate contact hole 95 and the gate wiring layer 82w of the gate electrode 82 are included in the second well region 31 in the planar layout. This is because the high voltage applied to the drain electrode 85 is shielded by the second well region 31 maintained at the source potential, so that the insulation under the gate wiring layer 82w having a remarkably low potential with respect to the drain voltage. This is to prevent a high voltage from being applied to the film (the field insulating film 52 in the configuration of FIG. 2).

An active region contact hole 90 is provided in the insulating layer having the gate insulating film 50 and the interlayer insulating film 55. The active region contact hole 90 partially exposes the surface of the active region R1 of the semiconductor layer. Specifically, a part of the source region 40, the first high concentration region 35, and the second separation region 22 are exposed. And exposed. A termination region test electrode contact hole 92 is provided in the insulating layer having the field insulating film 52 and the interlayer insulating film 55. Termination region test electrode contact hole 92 partially exposes the surface of termination region R2 of the semiconductor layer. In the present embodiment, second high concentration region 36 of second well region 31 is partially exposed. is doing.

The source electrode 80 is provided on a structure having the gate insulating film 50, the gate electrode portion 60, and the interlayer insulating film 55. The source electrode 80 is disposed in the active region R1, and includes the active region R1 in a planar layout. The source electrode 80 includes a Schottky electrode 75, a first ohmic contact portion 70, and a source wiring layer 80w. Schottky electrode 75 and first ohmic contact portion 70 are short-circuited to each other by source wiring layer 80w. The source electrode 80 has a side surface S1 (first side surface) on the termination region R2 side on the interlayer insulating film 55.

The Schottky electrode 75 is disposed at the bottom of the active region contact hole 90 and is connected to the drift layer 20 between the first well regions 30. In other words, the Schottky electrode 75 is in contact with the drift layer 20 in the second separation region 22. Thus, the source electrode 80 is Schottky connected to the drift layer 20 in the second separation region 22. With this configuration, the Schottky electrode 75 exhibits a diode characteristic that allows unipolar conduction with the drain electrode 85. That is, the SBD is incorporated in the active region R1 of the MOSFET 101. Therefore, the source electrode 80 has a diode characteristic that allows unipolar current flow to the drift layer 20 between the first well regions 30. The diffusion potential of this SBD is lower than the diffusion potential of the pn junction formed by the drift layer 20 and the first well region 30. The Schottky electrode 75 preferably includes the surface of the second separation region 22, but may not include it. On the other hand, no SBD is built in the termination region R2 of the MOSFET 101.

The first ohmic contact portion 70 is disposed at the bottom of the active region contact hole 90 and is in contact with the source region 40. As a result, the source electrode 80 is electrically ohmically connected to the source region 40. The first ohmic contact portion 70 is also in contact with the first high concentration region 35 of the first well region 30 in the active region contact hole 90. Thus, the source electrode 80 is ohmically connected to the first high concentration region 35 of the first well region 30. Since the first ohmic contact portion 70 is in contact with the first high concentration region 35, transfer of electrons or holes between the first ohmic contact portion 70 and the first well region 30 becomes easier.

The test electrode 81 is separated from the gate electrode 82 and the source electrode 80. The test electrode 81 has a third ohmic contact portion 72 and a test wiring layer 81w. The third ohmic contact portion 72 is disposed at the bottom of the termination region test electrode contact hole 92 and is in contact with the second high concentration region 36 of the second well region 31. As a result, the third ohmic contact portion 72 is electrically ohmically connected to the second high concentration region 36 of the second well region 31. With this configuration, the test electrode 81 is in contact with the second well region 31 and is ohmically connected to the second well region 31. The ohmic connection here refers to a connection exhibiting electrical characteristics such that electrons and holes can be easily exchanged between the second well region 31 and the test electrode 81. In the planar layout, the test electrode 81 is arranged in the termination region R2, and preferably surrounds the active region R1 as completely as possible, but does not have to be completely surrounded. The boundary between the field insulating film 52 and the gate insulating film 50 is located closer to the active region R1 than the termination region test electrode contact hole 92. As a result, the termination region test electrode contact hole 92 penetrates not only the interlayer insulating film 55 but also the field insulating film 52. Therefore, the third ohmic contact portion 72 is disposed in the termination region test electrode contact hole 92 provided in the field insulating film 52. On the interlayer insulating film 55, the test electrode 81 has a side surface S2 (second side surface) facing the side surface S1 of the source electrode 80 on the active region R1 side.

The second high concentration region 36 extends not only directly under the third ohmic contact portion 72 but also over a wide range in the second well region 31. This serves to lower the resistance of the second well region 31 in the chip plane direction, that is, the sheet resistance. In the second high-concentration region 36, the gate insulating film 50 or the field insulating film 52 over the second well region 31 is destroyed due to a change in potential inside the second well region 31 during the switching operation of the MOSFET 101. It plays a role to prevent that. For example, during the turn-off operation of the MOSFET 101, the reverse bias applied to the pn junction between the second well region 31 and the drift layer 20 rapidly increases due to the potential of the drain electrode 85 rapidly increasing. At this time, in the second well region 31, holes released due to acceptor depletion move in the second well region 31 in the chip plane direction, pass through the termination region test electrode contact hole 92, and become 0V. It is discharged toward the grounded source electrode 80. This is the displacement current, which increases as the switching speed increases. The potential at each location in the second well region 31 increases by a voltage corresponding to the product of the magnitude of the displacement current and the resistance of the current path. In order to reduce this and prevent the breakdown of the insulating film on the second well region 31, it is preferable to form the second high concentration region 36 over a wide range as described above.

Note that an n-type region may be formed on the second well region 31. That is, the n-type region may be disposed between the second well region 31 and the insulating film above the second well region 31.

The metal film 87 includes a source metal electrode film 87S (metal electrode film) and a gate metal electrode film 87G. The metal film 87 is a plating film in the present embodiment. The source metal electrode film 87S at least partially covers each of the source electrode 80 and the test electrode 81. The source metal electrode film 87 S extends over the source electrode 80 and the test electrode 81 to electrically connect the source electrode 80 and the test electrode 81. The source metal electrode film 87 S connects the side surface S 1 of the source electrode 80 and the side surface S 2 of the test electrode 81. The gate metal electrode film 87G at least partially covers the gate electrode 82. The source metal electrode film 87S and the gate metal electrode film 87G are separated from each other. Therefore, the gate electrode 80 covered with the gate metal electrode film 87G is an electrode (separation electrode) electrically separated from the source electrode 80 and the test electrode 81 covered with the source metal electrode film 87S. The source metal electrode film 87S is used as a source pad, and the gate metal electrode film 87G is used as a gate pad.

Referring to FIG. 1, a source electrode 80, a test electrode 81, and a gate electrode 82 are provided on the upper surface of MOSFET 101. These electrodes are separated from each other. In the present embodiment, the source electrode 80 and the test electrode 81 are separated from each other in a plan view (in a two-dimensional layout in the field of view of FIG. 1). However, it is only necessary that the source electrode 80 and the test electrode 81 in the region exposed on the interlayer insulating film 55 are separated from each other, and these electrodes are, for example, interposed via a part of the interlayer insulating film 55 in the stacking direction. They may overlap each other. That is, it is only necessary that the source electrode 80 and the test electrode 81 are electrically insulated before the source metal electrode film 87S is formed.

The shortest distance between the source electrode 80 and the test electrode 81, in other words, the shortest distance between the side surfaces S1 and S2 (FIG. 2) is preferably 1 μm or more and 100 μm or less. When this distance is less than 1 μm, there is a high possibility that a process failure in which the source electrode 80 and the test electrode 81 are not properly separated will occur. Desirably, the thickness is larger than half of the thickness of the source electrode 80. Here, the thickness of the source electrode 80 is the thickness of the portion of the source electrode 80 formed on the interlayer insulating film 55. When the distance is 100 μm or less, even if the source metal electrode film 87S has a relatively small thickness, a portion that grows from the side surface S1 and a portion that grows from the side surface S2 during the plating growth of the source metal electrode film 87S Become easier to connect. That is, the source electrode 80 and the test electrode 81 are easily connected. More preferably, this distance is smaller than twice the film thickness of the source metal electrode film 87S.

It is preferable that the source electrode 80 and the test electrode 81 are sufficiently close to each other in the MOSFET 101. Thus, the distance between the side surfaces S1 and S2 (FIG. 2) is sufficiently small everywhere in the MOSFET 101. Therefore, when the source metal electrode film 87S is grown, the portion grown from the side surface S1 and the portion grown from the side surface S2 are easily connected everywhere in the MOSFET 101. That is, the source electrode 80 and the test electrode 81 are easily connected everywhere in the MOSFET 101. When the source electrode 80 and the test electrode 81 are connected everywhere in the MOSFET 101, the parasitic impedance between the source electrode 80 and the test electrode 81 is extremely small, and both can be regarded as a single source electrode. it can.

However, the source electrode 80 and the test electrode 81 may be connected by the source metal electrode film 87 S at at least a part of the MOSFET 101, and the source electrode 80 and the test electrode 81 may be connected at a part of the MOSFET 101. Both may be separated due to the large distance between them.

The shortest distance between the gate electrode 82 and the source electrode 80 or the test electrode 81 is made larger than the shortest distance between the source electrode 80 and the test electrode 81. As a result, contact between the gate metal electrode film 87G and the source metal electrode film 87S can be more easily avoided.

The source electrode 80 is larger than the test electrode 81 in plan view. Thereby, the area which functions as a MOSFET element which is a semiconductor element can be widened. Preferably, the source electrode 80 is twice or more larger than the test electrode 81.

The test electrode 81 preferably has a portion located between the source electrode 80 and the gate electrode 82. Thus, the source electrode 80 and the test electrode 81 can be prevented from being separated by the gate electrode 82 in the planar layout. Therefore, the source metal electrode film 87S can connect the source electrode 80 and the test electrode 81 in a wider range.

The test electrode 81 is provided with a first probe electrode portion 81P. The “probe electrode portion” is a region of the electrode that has a function as a probe electrode portion, that is, a region that is large enough to allow contact with a probe needle, and has a size of 30 μm square or more. It is preferable. In the plan view of FIG. 1, the test electrode 81 has a first probe electrode portion 81P and a portion extending linearly with a width smaller than the width of the probe electrode portion. By reducing the width of the portion of the test electrode 81 other than the first probe electrode portion 81P as described above, the size of the termination region R2 (FIG. 2) where the test electrode 81 is provided can be suppressed. As a result, the chip size can be suppressed while maintaining the size of the active region R1 directly connected to the device performance such as the on-resistance of the MOSFET 101. The shape of the probe electrode portion is not limited to that shown in FIG. 1. If the test electrode 81 has a region of 30 μm square or more in plan view, this region functions as a probe electrode portion.

The source electrode 80 is preferably provided with a second probe electrode portion 80P. The gate electrode 82 is preferably provided with a third probe electrode portion 82P. Since the source electrode 80 and the gate electrode 82 typically have a region of 30 μm square or more, it can be said that the second probe electrode portion 80P and the third probe electrode portion 82P are usually provided.

Although details will be described later, a high potential is applied to the parasitic pn diode formed between the second well region 31 and the drift layer 20 by applying a potential higher than the drain electrode 85 to the test electrode 81 before the metal film 87 is formed. A stress test is conducted to pass a stress current of density. The first probe electrode portion 81 P has a probe mark generated by applying a probe needle to apply this potential.

(Production method)
Referring to FIG. 3, in order to obtain MOSFET 101 (FIG. 2), semi-finished product 101 P that does not have metal film 87 is first formed.

First, a semiconductor layer is formed on one surface of the substrate 10. This semiconductor layer is a layer including a portion that becomes the drift layer 20 as it is. Specifically, silicon carbide doped with a donor impurity at an impurity concentration of 1 × 10 ¹⁵ cm ⁻³ to 1 × 10 ¹⁷ cm ⁻³ by a chemical vapor deposition (CVD) method is 5 μm to 50 μm. It is epitaxially grown on the substrate 10 with a thickness of about.

Next, an implantation mask is formed on the surface of the semiconductor layer with a photoresist or the like. Using this implantation mask, Al ions are selectively implanted as acceptor impurities. At this time, the depth of Al ion implantation is about 0.5 μm to 3 μm which does not exceed the thickness of the semiconductor layer. Further, the impurity concentration of Al to be ion-implanted is higher than the donor concentration of the semiconductor layer in the range of 1 × 10 ¹⁷ cm ⁻³ to 1 × 10 ¹⁹ cm ⁻³ . Thereafter, the implantation mask is removed. The regions into which Al is ion-implanted by this step become the first well region 30 and the second well region 31. Therefore, the first well region 30 and the second well region 31 can be formed together.

Next, another implantation mask is formed on the surface of the semiconductor layer with a photoresist or the like. Using this implantation mask, Al ions are selectively implanted as acceptor impurities. At this time, the depth of Al ion implantation is about 0.5 μm to 3 μm which does not exceed the thickness of the semiconductor layer. Further, the impurity concentration of Al to be ion-implanted is higher than the first impurity concentration of the semiconductor layer in the range of 1 × 10 ¹⁶ cm ⁻³ to 1 × 10 ¹⁸ cm ⁻³ and the Al concentration of the first well region 30. Lower than that. Thereafter, the implantation mask is removed. A region into which Al is ion-implanted by this step becomes the JTE region 37.

Next, another implantation mask is formed on the surface of the semiconductor layer with a photoresist or the like. N, which is a donor impurity, is selectively ion-implanted using this implantation mask. The ion implantation depth of N is shallower than the thickness of the first well region 30. Further, the impurity concentration of the ion-implanted N exceeds the acceptor concentration of the first well region 30 in the range of 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ . Of the regions implanted with N in this step, the n-type region is the source region 40.

Next, another implantation mask is formed on the surface of the semiconductor layer with a photoresist or the like. Al, which is an acceptor impurity, is ion-implanted using this implantation mask. Thereafter, the implantation mask is removed. The regions into which Al is implanted by this step become the first

high concentration regions

35 and 36. The ion implantation of the acceptor impurity is preferably performed while heating the substrate 10 or the semiconductor layer to 150 ° C. or higher for the purpose of reducing the resistance of the first

high concentration regions

35 and 36.

The order of the ion implantation steps described above is arbitrary. Next, annealing is performed at 1300 to 1900 ° C. for 30 seconds to 1 hour in an inert gas atmosphere such as argon (Ar) gas by a heat treatment apparatus. As a result, the ion-implanted conductive impurities are electrically activated. Of the semiconductor layer, an n-type region into which impurity ions are not implanted corresponds to the drift layer 20.

Subsequently, a field insulating film 52 made of a silicon dioxide film having a thickness of about 0.5 to 2 μm is formed in a region other than the position substantially corresponding to the active region R1. For example, after the field insulating film 52 is formed on the entire surface by the CVD method, the field insulating film 52 at a position substantially corresponding to the active region R1 is removed by using a photolithography technique and an etching technique.

Subsequently, by thermally oxidizing the surface of the silicon carbide not covered with the field insulating film 52, a gate insulating film 50 having a desired thickness made of silicon oxide is formed. Next, a polycrystalline silicon film having conductivity is formed on the gate insulating film 50 by low pressure CVD, and the gate electrode portion 60 is formed by patterning this film. Subsequently, an interlayer insulating film 55 is formed by a low pressure CVD method. Subsequently, an opening that exposes a portion of the semiconductor layer where the first ohmic contact portion 70 is to be formed is formed in the interlayer insulating film 55 and the gate insulating film 50. In addition, an opening that exposes a portion of the semiconductor layer where the third ohmic contact 72 is to be formed is formed in the interlayer insulating film 55 and the field insulating film 52.

Next, a metal layer mainly composed of nickel (Ni) is formed by sputtering or the like. Subsequently, the film is heat-treated at a temperature of 600 ° C. to 1100 ° C. Thereby, silicide is formed between the silicon carbide layer and the metal layer in the opening. Subsequently, the remaining portion of the metal layer that is not silicided is removed. This removal can be performed, for example, by wet etching using any one of sulfuric acid, nitric acid, hydrochloric acid, or a mixed solution of these with hydrogen peroxide. Thus, the first ohmic contact part 70 and the third ohmic contact part 72 are formed.

Subsequently, a metal layer mainly composed of Ni is formed on the lower surface of the substrate 10. The ohmic electrode 79 is formed on the back side of the substrate 10 by heat-treating the metal layer.

Next, the gate insulating film 50 and the interlayer insulating film 55 on the second separation region 22 and the interlayer insulating film 55 at the position where the gate contact hole 95 is provided are removed by a patterning technique using a photoresist or the like. As a removal method, wet etching that does not damage the silicon carbide surface that becomes the SBD interface is preferable.

Subsequently, a Schottky electrode 75 is deposited by sputtering or the like. The deposited material is preferably titanium (Ti), molybdenum (Mo) or nickel (Ni).

Thereafter, a wiring metal layer such as Al is formed on the surface of the substrate 10 processed so far by sputtering or vapor deposition, and this is processed into a predetermined shape by photolithography. Accordingly, the source wiring layer 80w that contacts the first ohmic contact portion 70 and the Schottky electrode 75, the test wiring layer 81w that contacts the third ohmic contact portion 72, and the gate wiring layer 82w that contacts the gate electrode portion 60. And are formed. Further, a drain electrode 85 that is a metal layer is formed on the surface of the ohmic electrode 79 formed on the lower surface of the substrate 10.

As described above, the substrate 10, the above-described semiconductor layer on the substrate 10, the gate insulating film 50, the field insulating film 52, the interlayer insulating film 55, the source electrode 80, the test electrode 81, the gate electrode 82, A semi-finished product 101P of the MOSFET 101 having the drain electrode 85 is formed. In the semi-finished product 101P, the first probe electrode portion 81P, the second probe electrode portion 80P, and the third probe electrode portion 82P (FIG. 1) are exposed on the surface.

Next, a stress test is performed on the semi-finished product 101P. For this purpose, a predetermined potential is applied to the source electrode 80, and a potential different from the potential of the source electrode 80 is applied to the test electrode 81. Specifically, by increasing the potential of the test electrode 81 with respect to the drain electrode 85, a forward bias is applied to the pn junction formed by the second well region 31 and the drift layer 20. In order to apply this potential, the probe needle is brought into contact with the first probe electrode portion 81P (FIG. 1) of the test electrode 81. At this time, in order to reduce the contact resistance between the probe needle and the first probe electrode portion 81P, the probe needle needs to be sunk into the first probe electrode portion 81P. As a result, the first probe electrode Probe marks are formed on the portion 81P. Here, the probe trace is a trace in which the probe needle is indented into the surface of the first probe electrode portion 81P. For example, the surface shape of the first probe electrode portion 81P is uneven. At this time, the first probe electrode part 81P may be formed with a pattern shape in a lower layer than the first probe electrode part 81P, that is, surface irregularities formed by steps, but the first probe electrode part The surface irregularities of the first probe electrode portion 81P that do not depend on the pattern shape in the lower layer than 81P are probe marks.

In the above stress test, the voltage applied between the test electrode 81 and the drain electrode 85 is set lower than the voltage between the source electrode 80 and the drain electrode 85. In other words, the potential of the source electrode 80 is made lower than the potential of the test electrode 81. Preferably, the potential of the source electrode 80 is set to a potential that does not exceed the diffusion potential of the parasitic pn diode with respect to the potential of the drain electrode 85. The potential of the source electrode 80 may be a floating potential without applying a potential from the outside. Even in that case, the potential of the source electrode 80 is between the potential of the test electrode 81 and the potential of the drain electrode 85, and thus is lower than the potential of the test electrode 81.

When a potential is applied as described above, it is formed between the second well region 31 and the drift layer 20 as compared with the parasitic pn diode formed between the first well region 30 and the drift layer 20. A stress current flows preferentially to the parasitic pn diode formed. When applying the above potential, the potential of the gate electrode 82 is preferably equal to that of the test electrode 81 or lower than that of the test electrode 81 in order to reliably turn off the channel.

When a stress current is applied to the parasitic pn diode formed between the second well region 31 and the drift layer 20, if a defect origin such as a basal plane dislocation exists at the parasitic pn diode, Triangular stacking faults expand. The extension of the defects affects the current-carrying characteristics between the source electrode 80 or the test electrode 81 and the drain electrode 85.

After conducting this stress test, the current-carrying characteristics between each electrode are measured, and abnormal products are excluded. That is, after a plurality of semi-finished products 101P are formed, screening by a stress test is performed on these. The energization characteristic may be a resistance value or a withstand voltage characteristic. For example, a current is passed between the test electrode 81 and the drain electrode 85, and elements having a large voltage drop are eliminated. Further, the same measurement may be performed before the stress test, and the necessity of exclusion may be determined from the characteristic fluctuation amount before and after the stress test.

Referring again to FIG. 2, after applying energizing stress to the parasitic pn diode as described above, the metal film 87 is formed by a plating method. Preferably, the plating method is an electroless plating method. In the electroless plating method, the metal film 87 is selectively formed on the exposed source electrode 80, test electrode 81, and gate electrode 82.

The metal film 87 isotropically grows from the source electrode 80, the test electrode 81, and the gate electrode 82 by using the plating method. That is, the metal film 87 grows not only on the upper surfaces of the source electrode 80, the test electrode 81 and the gate electrode 82 but also on the side surfaces. For this reason, between the side surface S1 of the source electrode 80 and the side surface S2 of the test electrode 81 that are close to each other, the growth surfaces of the plating films formed on both side surfaces come into contact with each other, A metal film 87 is formed to connect the side surface S2. On the other hand, the distance between each of the source electrode 80 and the test electrode 81 and the gate electrode 82 is larger than the distance between the source electrode 80 and the test electrode 81. Therefore, each of the source electrode 80 and the test electrode 81 and the gate electrode 82 are not short-circuited by the metal film 87. In other words, the metal film 87 is formed as a source metal electrode film 87S and a gate metal electrode film 87G which are separated from each other.

The material of the metal film 87 formed by the electroless plating method is preferably Al, Cu, Ni or Au. The film thickness of the metal film 87 needs to be larger than half the distance between the source electrode 80 and the test electrode 81 in order to connect the source electrode 80 and the test electrode 81. On the other hand, this film thickness is desirably 20 μm or less from the viewpoint of ease of processing.

Thus, MOSFET 101 is obtained.

(Reflux operation during actual use)
When the potential of the source electrode 80 exceeds the potential of the drain electrode 85, the MOSFET 101 performs a reflux operation. In the active region R1, since a current flows through the built-in SBD, no forward current flows through the pn diode formed by the first well region 30 and the drift layer 20. On the other hand, since no SBD is built in the termination region R2, a forward current flows through the pn diode formed by the second well region 31 and the drift layer 20.

If a defect origin such as a basal plane dislocation exists at the location of the pn diode formed by the second well region 31 and the drift layer 20 in the termination region R2, the triangular stacking fault expands, so that the transistor The characteristics will deteriorate. Since MOSFET 101 of the present embodiment has undergone the screening described above, such characteristic deterioration is unlikely to occur.

(Comparative example)
The comparative MOSFET 199 (FIGS. 4 to 6) does not have the test electrode 81 described above. For this reason, the potential application in the stress test must be performed using the source electrode 80. Here, the source electrode 80 is also in contact with the active region R1 in which the SBD having a lower operating voltage than the pn diode is built. For this reason, most of the stress current flows into the active region R1 that does not require a stress test. The current flowing through the SBD built in the active region R1 also generates Joule heat corresponding to the voltage drop in the device, thereby causing the element to generate heat. In order to prevent thermal damage to the chip or evaluation equipment due to this heat generation, it is necessary to suppress the amount of current to be applied. As a result, the stress current density to the pn diode formed by the second well region 31 and the drift layer 20 in the termination region R2 is reduced. Therefore, the time required for the stress test becomes long.

Furthermore, when the amount of stress current flowing through the active region R1 is large, current also starts to flow through the parasitic pn diode formed between the first well region 30 and the drift layer 20 in the active region R1. This is because the forward voltage applied to the pn diode increases as the voltage drop generated in the second separation region 22 increases as the current density of the SBD increases. As a result, stacking faults may be generated in the active region R1 that originally does not require a stress test, which may change the forward voltage of the MOSFET 199 and the like. If such products are excluded by screening, the manufacturing yield will be reduced.

(effect)
According to the present embodiment, the test electrode 81 electrically connected to the second well region 31 located in the termination region R2 is separated from the source electrode 80 in contact with the first well region 30 located in the active region R1. Provided. A stress test in which a forward bias is applied to the pn junction formed by the second well region 31 and the drift layer 20 is performed using the test electrode 81 before the metal film 87 is formed. Thereby, the stress current flowing through the active region R1 can be suppressed. Therefore, first, the amount of heat generated in the active region R1 during the stress test becomes smaller. Therefore, since a larger current can be used for the stress test, the stress test can be performed in a shorter time. Second, the generation of stacking faults in the active region R1 during the stress test is suppressed. This makes it difficult for the transistor characteristics to vary due to the stress test. As described above, the stress test time can be shortened, and fluctuations in transistor characteristics due to the stress test can be suppressed.

A stress current can be easily applied from the outside by the first probe electrode portion 81P. In particular, a probe needle for applying a stress current can be easily applied. When the first probe electrode portion 81P has a probe mark, it can be identified that a stress current has already been applied.

After the stress test, the source electrode 80 and the test electrode 81 are short-circuited by the source metal electrode film 87S, so that the potential of the second well region 31 is prevented from becoming a floating potential. Specifically, the source electrode 80 and almost the same potential. Thereby, it is possible to prevent a high voltage from being applied to the gate insulating film 50 and the field insulating film 52 on the second well region 31.

For the short-circuit connection between the source electrode 80 and the test electrode 81, a source metal electrode film 87S extending over these is used. Thereby, compared with the case where a bonding wire is used, the impedance of a short circuit connection can be made low. Impedance reduction is particularly advantageous for high speed operation of MOSFET 101. Further, since it is not necessary to secure an area for wire bonding for the short-circuit connection between the source electrode 80 and the test electrode 81, the chip size is further reduced. Thereby, manufacturing cost can be reduced.

The source metal electrode film 87S connects between the side surface S1 (first side surface) of the source electrode 80 and the side surface S2 (second side surface) of the test electrode 81 facing each other. Thereby, since the source electrode 80 and the test electrode 81 are connected at a short distance, the impedance of the short-circuit connection can be further reduced. The electrical path for this short-circuit connection is provided between the side surface S1 of the source electrode and the side surface S2 of the test electrode facing each other. Thereby, there is no need to form a contact hole for arranging the electrical path and an insulating film provided with the contact hole. Therefore, since the manufacturing process is simplified, the manufacturing cost of MOSFET 101 can be reduced.

The source metal electrode film 87S is formed by a plating method. Thus, if the shortest distance between each of the source electrode 80 and the test electrode 81 and the gate electrode 82 is sufficiently large, the source metal electrode film 87S that does not contact the gate electrode 82 can be formed without the patterning step. Can do.

(Modification)
Referring to FIG. 7, in MOSFET 101 a (semiconductor device) of the modification, termination region source electrode contact hole 91 is provided in the insulating layer having field insulating film 52 and interlayer insulating film 55. Termination region source electrode contact hole 91 partially exposes the surface of termination region R2 of the semiconductor layer, and in the present embodiment, second high concentration region 36 of second well region 31 is partially exposed. is doing. Termination region source electrode contact hole 91 is arranged closer to active region R1 than termination region test electrode contact hole 92.

In the MOSFET 101 a, the source electrode 80 includes a second ohmic contact portion 71. Second ohmic contact portion 71 is short-circuited to each of Schottky electrode 75 and first ohmic contact portion 70 by source wiring layer 80w. The second ohmic contact portion 71 is disposed at the bottom of the termination region source electrode contact hole 91 and is in ohmic contact with the second high concentration region 36 of the second well region 31. Thus, the source electrode 80 is ohmically connected to the second high concentration region 36 of the second well region 31. Since the second ohmic contact portion 71 is in contact with the second high-concentration region 36, transfer of electrons or holes between the second ohmic contact portion 71 and the second well region 31 becomes easier.

According to the present modification, the potential of the second well region 31 is further increased to the potential of the source electrode 80 by electrical connection via the termination region source electrode contact hole 91 even in a location where the test electrode 81 is not provided. You can get closer. This is particularly useful when the test electrode 81 does not completely surround the source electrode 80, unlike FIG.

It should be noted that this modification also has the effect of suppressing the current flowing through the active region R1 during the stress test, although it does not reach the configuration of FIG. This is because the sheet resistance of the second well region 31 (particularly the second high-concentration region 36), which is an electrical path between the test electrode 81 and the source electrode 80 during the stress test before the metal film 87 is formed, is a metal resistance. This is because the stress current leaking from the test electrode 81 toward the active region R1 can be made sufficiently small compared to the sheet resistance of the film 87.

In the planar layout, the termination region source electrode contact hole 91 is preferably formed so as to completely surround the active region R1, and the test electrode 81 is preferably formed so as to surround the active region R1 as completely as possible.

In the present embodiment, the second well region 31 completely surrounds the active region R1, but may not be surrounded. As shown in FIG. 1, the second well region 31 may be formed below the third probe electrode portion 82P in the gate electrode 82, and may be formed in a region different from the active region R1. That's fine.

In this embodiment, a planar MOSFET cell is disposed in the active region R1, but a trench MOSFET may be disposed.

Furthermore, the structure of the MOSFET cell may be polygonal or comb-shaped.

In the present embodiment, the case where a MOSFET cell is disposed as a unipolar device in the active region R1 has been described. However, a Schottky barrier diode may be disposed in the active region R1. That is, as another example of the semiconductor device according to the present embodiment, the semiconductor device may be a Schottky barrier diode. In this case, no MOSFET cell is arranged in the active region R1, and a Schottky barrier diode is formed. In the termination region R2, a p-type region such as JTE or FLR (Field Limiting Ring) is formed as an electric field relaxation region, and the anode electrode of the Schottky barrier diode and at least a part of the p-type region are electrically connected. . Since this p-type region corresponds to the second well region 31, the same effect as in the present embodiment can be obtained.

<Embodiment 2>
Referring to FIG. 8, gate electrode 82 of MOSFET 102 (semiconductor device) of the present embodiment is added to a region (corresponding to the entire gate electrode 82 in FIG. 1) as third probe electrode portion 82P in plan view. Thus, the terminal area R2 has a wiring area extending linearly from the third probe electrode section 82P with a width smaller than the width of the third probe electrode section 82P.

Further, referring to FIG. 9, MOSFET 102 has a surface protective layer 57 partially formed on gate electrode 82. The surface protective layer 57 exposes a portion of the gate electrode 82 that requires electrical contact with the outside, such as the third probe electrode portion 82P, and extends from the third probe electrode portion 82P. It is preferable to cover. The surface protective layer 57 exposes each of the source electrode 80 and the test electrode 81 at least partially, and is preferably provided apart from the source electrode 80 and the test electrode 81.

The surface protective layer 57 is made of an insulator. The material of the surface protective layer 57 is preferably one that can be formed at a temperature of 500 ° C. or lower. Specifically, the material of the surface protective layer 57 is preferably an organic material, and particularly preferably polyimide.

In the present embodiment, the metal film 87 is selectively formed only on a portion of the source electrode 80, the test electrode 81, and the gate electrode 82 that is not covered with the surface protective layer 57.

The thickness of the surface protective layer 57 is preferably selected so that the upper surface of the surface protective layer 57 (the upper surface in FIG. 9) is higher than the upper surface of the metal film 87. From the viewpoint of ease of processing, the thickness of the surface protective layer 57 is preferably 30 μm or less.

In the manufacturing method of the MOSFET 102, the surface protective layer 57 is formed after the source electrode 80, the test electrode 81, and the gate electrode 82 are formed and before the metal film 87 is formed. In the subsequent formation of the metal film 87, the plating film as the metal film 87 does not grow on the portion of the source electrode 80, the test electrode 81, and the gate electrode 82 that is covered with the surface protective layer 57. Preferably, the step of forming the surface protective layer 57 is performed before the stress test described above. As a result, the MOSFET 102 is protected by the surface protective layer 57 from disturbance that may occur in the stress test.

The surface protective layer 57 is formed as follows, for example. First, polyimide is applied. Thereafter, a pattern of the surface protective layer 57 is formed by patterning using photolithography. Next, the polyimide is cured by heat treatment at a temperature of 150 ° C. to 500 ° C.

Since the configuration other than the above is substantially the same as the configuration of the first embodiment described above, the same or corresponding elements are denoted by the same reference numerals, and description thereof is not repeated.

According to the present embodiment, by providing the surface protective layer 57 before the metal film 87 is formed, the metal film 87 grows so as to connect the source electrode 80 or the test electrode 81 and the gate electrode 82. Is more reliably prevented. Thereby, the distance between the source electrode 80 or the test electrode 81 and the gate electrode 82 can be further reduced. Therefore, the chip size can be further reduced. Thereby, the manufacturing cost can be reduced.

When the surface protective layer 57 is made of an organic material, the surface protective layer 57 can be formed at a relatively low temperature. Thereby, damage caused by heat applied to the structure before the formation of the surface protective layer 57 can be suppressed.

Further, by providing the surface protective layer 57, an unintended short circuit between the source electrode 80 or the test electrode 81 and the gate electrode 82 can be prevented. When the electrode is stretched by a disturbance such as a scratch at the boundary between the source electrode 80 or the test electrode 81 and the gate electrode 82, the short circuit as described above may occur without the surface protective layer 57.

It should be noted that the electrode layout of the MOSFET provided with the surface protective layer 57 is not limited to that shown in FIG. 8, and may be, for example, that shown in FIG. In this case, the surface protective layer 57 is provided, for example, on a portion of the gate electrode 82 that is close to the test electrode 81. Thereby, the gate electrode 82 and the test electrode 81 are prevented from being short-circuited by the metal film 87. Conversely, as an electrode layout in the case where the surface protective layer 57 is not provided (that is, the first embodiment), a wiring region extending from the third probe electrode portion 82P is provided in the gate electrode 82 as shown in FIG. 8, for example. Other configurations may be used.

<Embodiment 3>
In the present embodiment, instead of the plating method, the metal film 87 is formed by a deposition method through a shadow mask as follows.

First, a shadow mask is prepared. The shadow mask has an opening corresponding to the pattern of the metal film 87. The shadow mask is a metal plate made of, for example, stainless steel.

Next, the shadow mask is overlaid on the MOSFET being created. In this overlay, the shadow mask opening includes a region that spans both the source electrode 80 and the test electrode 81 (FIG. 1).

Next, a metal thin film is deposited corresponding to the pattern of the opening by a deposition method such as sputtering or vapor deposition in a vacuum atmosphere. Thereby, a metal film 87 is formed.

According to the present embodiment, unlike the first embodiment, the pattern of the metal film 87 in plan view can be arbitrarily determined by the pattern of the opening of the shadow mask. Thereby, first, even if the distance between the source electrode 80 and the test electrode 81 is large, the source metal electrode film 87S that connects the source electrode 80 and the test electrode 81 can be formed. By increasing the distance between the source electrode 80 and the test electrode 81, it is possible to suppress a decrease in manufacturing yield due to the occurrence of poor separation between the source electrode 80 and the test electrode 81. Therefore, manufacturing cost can be reduced.

Second, the metal film 87 can be formed only on an arbitrary portion of the exposed portions of the source electrode 80, the test electrode 81, and the gate electrode 82. Therefore, part of the source electrode 80, the test electrode 81, and the gate electrode 82 can be left exposed even when the MOSFET is completed. This exposed portion can be used as a terminal portion for establishing electrical connection with the outside of the MOSFET. This terminal part can be used, for example, as a part for connecting a bonding wire for electrical connection with the outside of the MOSFET. In this case, the metal film 87 is formed only in the vicinity of the separation region between the source electrode 80 and the test electrode 81, for example. When such a terminal portion is provided, the material of the metal film 87 may not be suitable as a material for the terminal portion. Therefore, the material of the metal film 87 can be more freely selected from various metal materials different from the materials of the source electrode 80, the test electrode 81, and the gate electrode 82.

In each of the above embodiments, the first conductivity type is n-type and the second conductivity type is p-type. Conversely, the first conductivity type is p-type and the second conductivity type is n-type. It may be a type. In this case, the above-described content of the potential level is also opposite.

In each of the above embodiments, the Schottky electrode 75 and the source electrode 80 may be made of the same material. In this case, the Schottky electrode 75 and the source electrode 80 can be formed collectively.

In each of the above embodiments, the MOSFET has been described as the semiconductor device. However, a material other than an oxide may be used as the material of the gate insulating film. In other words, the semiconductor device may be a MISFET (Metal Insulator Semiconductor Field Effect Transistor) other than the MOSFET. The semiconductor device is not limited to the MISFET, and may be another unipolar transistor with a built-in unipolar diode. The unipolar transistor may be, for example, a JFET (Junction Field Effect Transistor).

In each of the above embodiments, the SBD is incorporated in the unipolar transistor, but instead of incorporating the SBD element, a diode characteristic capable of conducting unipolar current to the drift layer 20 between the first well regions 30 is provided as a source. The electrode 80 may have. Specifically, instead of incorporating the SBD, for example, an FET having a channel characteristic that allows energization only in the direction from the source to the drain while an off potential is applied to the gate may be used. That is, a structure in which an n-type channel region is formed on the channel region sandwiched between the source region 40 and the drift layer 20 in the first well region 30 may be used. Since a channel region is formed between the first well region 30 and the gate insulating film 50, the source electrode 80 is made higher than the drain electrode 85 even if no voltage is applied to the gate electrode portion 60. Unipolar energization is possible in the direction from the drain to the drain. Note that the channel region may be formed by epitaxial growth or ion implantation.

Further, in each of the above embodiments, silicon carbide is used as the wide band gap semiconductor that is the material of the drift layer 20, but other wide band gap semiconductors may be used. A wide-gap semiconductor having a recombination energy larger than that of silicon, not limited to silicon carbide, may generate crystal defects when a forward current flows through the parasitic pn diode. A wide band gap semiconductor is defined as a semiconductor having a band gap of about twice the band gap of silicon (1.12 eV), for example. If the purpose of the inspection or stress test is not related to the generation of the crystal defect, the material of the drift layer can be any semiconductor.

In this specification, a connection with an electrically low resistance is referred to as an “ohmic connection”, and a structure for realizing the connection is referred to as an “ohmic contact portion” or an “ohmic electrode”. “Connection with low resistance” means, for example, a connection having a contact resistance of 100 Ωcm ² or less, and it is not necessary to satisfy a narrowly defined ohmic characteristic having perfect linearity as a current / voltage characteristic.

In each of the above-described embodiments, the case where the SBD element and the MOSFET element are provided in the active region surrounded by the termination region has been described. However, other semiconductor elements may be formed in the active region. Even in such a case, the second electrode located in the termination region can be provided separately from the first electrode located in the active region. An inspection or stress test on the termination region by applying a potential different from the potential of the first electrode to the second electrode can be performed using the second electrode before forming the metal electrode film. Thereby, the current flowing through the active region can be suppressed. Therefore, in the inspection or stress test, first, the amount of heat generated in the active region becomes smaller. Accordingly, since a larger current can be used, the inspection or the stress test can be performed in a shorter time. Secondly, the influence on the active region by the inspection or the stress test is suppressed. This makes it difficult for the semiconductor characteristics to vary due to the inspection or the stress test. As described above, the time for the inspection or stress test can be shortened, and fluctuations in the semiconductor characteristics due to the inspection or stress test can be suppressed. Further, the first electrode and the second electrode are short-circuited with low impedance by the metal electrode film straddling the first electrode and the second electrode. Such a connection method can be applied to various applications as a method of short-circuiting a plurality of electrodes with a low impedance after giving a test or stress test with different potentials in a state where a plurality of electrodes are separated from each other, Benefit from low cost and high speed operation.

In each of the above-described embodiments, the case where each of the first electrode and the second electrode is disposed in the active region and the termination region has been described. However, the locations where the first electrode and the second electrode are disposed are other than these. There may be. Even in such a case, an inspection or a stress test by applying a potential different from the potential of the first electrode to the second electrode can be performed using the second electrode before forming the metal electrode film. As a result, the current flowing in the vicinity of the first electrode can be suppressed. Therefore, in the inspection or stress test, first, the amount of heat generated in the vicinity of the first electrode becomes smaller. Accordingly, since a larger current can be used, the inspection or the stress test can be performed in a shorter time. Second, the influence on the vicinity of the first electrode due to the inspection or the stress test is suppressed. This makes it difficult for the semiconductor characteristics to vary due to the inspection or the stress test. As described above, the time for the inspection or stress test can be shortened, and fluctuations in the semiconductor characteristics due to the inspection or stress test can be suppressed. Further, the first electrode and the second electrode are short-circuited with low impedance by the metal electrode film connecting the first side surface of the first electrode and the second side surface of the second electrode facing each other.

In the present invention, it is possible to freely combine the respective embodiments within the scope of the invention, and to appropriately modify and omit the respective embodiments. Although the present invention has been described in detail, the above description is illustrative in all aspects, and the present invention is not limited thereto. It is understood that countless variations that are not illustrated can be envisaged without departing from the scope of the present invention.

R1 active region, R2 termination region, 10 substrate (semiconductor substrate), 20 drift layer, 21 first separation region, 22 second separation region, 30 first well region, 31 second well region, 35 first high concentration region, 36, second high concentration region, 40 source region, 50 gate insulating film, 52 field insulating film, 55 interlayer insulating film, 57 surface protective layer, 60 gate electrode portion, 70 first ohmic contact portion, 71 second ohmic contact portion, 72 3rd ohmic contact, 75 Schottky electrode, 79 ohmic electrode, 80 source electrode (first electrode), 80P second probe electrode, 80w source wiring layer, 81w test wiring layer, 82w gate wiring layer, 81 test Electrode (second electrode), 81P first probe electrode, 82 gate Electrode (separation electrode), 82P third probe electrode section, 85 drain electrode (third electrode), 87 metal film, 87G gate metal electrode film, 87S source metal electrode film (metal electrode film), 89 wiring section, 90 active Area contact hole, 91 termination area source electrode contact hole, 92 termination area test electrode contact hole, 95 gate contact hole, 101, 101a, 102 MOSFET (semiconductor device), 101P semi-finished product.

Claims

A semiconductor device (101, 101a, 102) having an active region (R1) and a termination region (R2) in a region different from the active region (R1) in plan view,
A first electrode (80) disposed in the active region (R1);
A second electrode (81) disposed in the termination region (R2) and separated from the first electrode (80);
A semiconductor device (101, 101a, 102) comprising a metal electrode film (87S) that electrically connects the first electrode (80) and the second electrode (81).
The semiconductor device (101, 101a, 102) according to claim 1, wherein the termination region (R2) surrounds the active region (R1).
A first electrode (80) having a first side surface (S1);
A second electrode (81) having a second side surface (S2) separated from the first electrode (80) in plan view and facing the first side surface (S1);
A semiconductor device (101) comprising a metal electrode film (87S) that connects between the first side surface (S1) of the first electrode (80) and the second side surface (S2) of the second electrode (81). , 101a, 102).
The semiconductor device (101, 101a, 102) according to any one of claims 1 to 3, wherein the probe electrode portion provided on the second electrode (81) has a probe mark.
5. The semiconductor device (101, 101 a, 102) according to claim 4, wherein the probe electrode portion includes a 30 μm square region in the plan view.
The semiconductor device (101, 101a, 102) according to any one of claims 1 to 5, wherein the first electrode (80) is larger than the second electrode (81) in the plan view.
The shortest distance between the first electrode (80) and the second electrode (81) is smaller than twice the film thickness of the metal electrode film (87S), according to any one of claims 1 to 6. The semiconductor device described (101, 101a, 102).
A separation electrode (82) separated from the first electrode (80) and the second electrode (81);
The semiconductor device (102) according to any one of claims 1 to 7, further comprising a surface protective layer (57) formed partially on the separation electrode (82) and made of an insulator.
The semiconductor device (102) according to claim 8, wherein the surface protective layer (57) is made of an organic material.
A semiconductor substrate (10) having a first conductivity type;
A drift layer (20) provided on the semiconductor substrate (10), made of a wide bandgap semiconductor and having the first conductivity type;
A plurality of first well regions (30) provided on the drift layer (20) and having a second conductivity type different from the first conductivity type;
A source region (40) provided on each of the first well regions (30), separated from the drift layer (20) by the first well region (30) and having the first conductivity type;
An isolation electrode (82) opposed to the first well region (30) through a gate insulating film (50);
At least one second well region (31) provided on the drift layer (20) and having the second conductivity type;
A third electrode (85) electrically connected to the semiconductor substrate (10),
The first electrode (80) has an ohmic contact part (70) electrically connected to the source region (40),
The second electrode (81) is electrically connected to the second well region (31) and separated from the first electrode (80).
The semiconductor device (101, 101a, 102) according to any one of claims 1 to 7.
The first electrode (80) is connected to the drift layer (20) between the plurality of first well regions (30), and can be unipolarly energized with the third electrode (85). The semiconductor device (101, 101a, 102) according to claim 10, comprising a Schottky electrode (75) exhibiting diode characteristics.
The semiconductor device (101, 101a, 102) according to claim 10 or 11, comprising the channel region of the first conductivity type between the first well region (30) and the gate insulating film (50).
Forming a first electrode (80) and a second electrode (81) separated from the first electrode (80);
Applying a predetermined potential to the first electrode (80);
Applying a potential different from the potential of the first electrode (80) to the second electrode (81);
A metal electrode that electrically connects the first electrode (80) and the second electrode (81) after applying a potential different from the potential of the first electrode (80) to the second electrode (81). Forming a film (87S). A method for manufacturing a semiconductor device (101, 101a, 102).
The method of manufacturing a semiconductor device (101, 101a, 102) according to claim 13, wherein the step of forming the metal electrode film (87S) is performed by a plating method.
The method of manufacturing a semiconductor device (101, 101a, 102) according to claim 13, wherein the step of forming the metal electrode film (87S) is performed by a deposition method through a shadow mask.
A semiconductor substrate (10) having a first conductivity type, a drift layer (20) provided on the semiconductor substrate (10) and made of a wide band gap semiconductor, having the first conductivity type, and the drift layer ( 20) provided on each of a plurality of first well regions (30) having a second conductivity type different from the first conductivity type and the first well regions (30), and The source region (40) separated from the drift layer (20) by the well region (30) and having the first conductivity type is opposed to the first well region (30) via the gate insulating film (50). An isolation electrode (82) and at least one second well region (31) provided on the drift layer (20) and having the second conductivity type, and electrically connected to the semiconductor substrate (10) Third electrode (8 ) And further comprises a step of forming a
The first electrode (80) is electrically connected to the source region (40), and between the plurality of first well regions (30) between the third electrode (85) and the first electrode (80). It has a diode characteristic that allows unipolar conduction through the drift layer (20),
The second electrode (81) is electrically connected to the second well region (31) and separated from the first electrode (80);
The step of applying a potential different from the potential of the first electrode (80) to the second electrode (81) includes the first electrode (85) between the second electrode (81) and the third electrode (85). 80) and applying a voltage lower than the voltage between the third electrode (85),
The method for manufacturing a semiconductor device (101, 101a, 102) according to any one of claims 13 to 15.