JP2020038986A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device having an IGBT which can suppress the increase of ON-state voltage while improving the voltage withstanding.SOLUTION: A semiconductor device 1 includes: a plurality of gate trenches 8 formed on a semiconductor substrate 2; a gate electrode 20 embedded in the gate trenches 8 through a gate insulator film 22; an ntype emitter region 13, a p type base region 10, an ntype drift region 6, and a ptype collector region 4, formed on the semiconductor substrate 2 by contacting with each other; an emitter trench 14 formed between gate trenches 8 adjacent to each other; and an embedded electrode 21 embedded in the emitter trench 14 through an insulator film 19. A p type floating region 15 underlying the emitter trench 14 is formed in the semiconductor device 1, the p type floating region 15 including an overlap portion 17 containing an end part 18 situated closer to the gate trench 8 with respect to the center of the emitter trench 14 in the width direction.SELECTED DRAWING: Figure 1

Description

The present invention relates to a semiconductor device having an IGBT (Insulated Gate Bipolar Transistor).

Conventionally, a trench-type IGBT having a high collector-emitter saturation voltage V _CE (sat) and short-circuit tolerance has a p-type floating layer. The p-type floating layer is generally formed in the same step as the p-type base layer. Thus, the p-type floating layer has the same depth as the p-type base layer.

Satoru Machida, Takahide Sugiyama, Masayasu Ishiko, Satoshi Yasuda, Jun Saito, Kimimori Hamada, "Analysis of Switching Loss and Device Capacitance of IGBT", IEICE Electronics Materials Workshop (EFM-09, 16-26, 28- 29), p. 55-59 Satoshi Watanabe, Mutsuhiro Mori, Daiatsu Arai, Torusuke Ishibashi, Yasushi Toyoda, Tetsuo Oda, Taku Harada, Katsuaki Saito, "Low-loss, low-noise, highly reliable 1.7kV trench IGBT with floating p-layer separated from gate" Materials of the Institute of Electrical Engineers of Japan, EDD-11, 66-83, p. 67-71 Japanese Patent No. 4785334

However, in the conventional structure, when the p-type floating layer is deeply diffused to maintain the breakdown voltage of the device, the breakdown voltage is maintained, but the p-type base layer becomes thicker and the on-voltage increases. is there. On the other hand, if the p-type base layer is thinned to reduce the ON voltage, it is difficult to maintain a sufficient withstand voltage.
Therefore, an object of the present invention is to provide a semiconductor device including an IGBT that can suppress an increase in on-voltage while improving the withstand voltage.

In order to achieve the above object, a semiconductor device of the present invention has a semiconductor layer and a plurality of semiconductor layers formed so as to extend in a first direction and formed in the semiconductor layer in a second direction orthogonal to the first direction. A repeating structure of a trench, a plurality of gate electrodes buried in the plurality of trenches via an insulating film and adjacent to each other in the second direction, and a plurality of emitter electrodes adjacent to each other along the second direction; An n ⁺ -type emitter region, a p-type base region, and an n ⁻ side are arranged in the depth direction of the trench from the surface side of the semiconductor layer in a region between the adjacent gate electrodes on a side of the electrode. A drift region and a region between the emitter electrodes adjacent to each other, formed deeper than the p-type base region,
A p-type floating region including an overlap portion which goes under the emitter electrode;
Wherein n ^- a p ⁺ -type collector region disposed on the back side of the relative type drift region semiconductor layer, and the p-type base region and the n ^- interface between type drift region, the central portion of the trench Or it is set at the top.

FIG. 1 is a schematic sectional view of the semiconductor device according to the first embodiment of the present invention. FIG. 2 is a perspective view for explaining the internal structure of the semiconductor device of FIG. FIG. 3A is a diagram illustrating a manufacturing step of the semiconductor device in FIG. 1. FIG. 3B is a diagram showing a step subsequent to that of FIG. 3A. FIG. 3C is a diagram showing a step subsequent to that in FIG. 3B. FIG. 3D is a diagram showing a step subsequent to that in FIG. 3C. FIG. 3E is a diagram showing a step subsequent to that in FIG. 3D. FIG. 3F is a diagram showing a step subsequent to that in FIG. 3E. FIG. 3G is a diagram showing a step subsequent to that in FIG. 3F. FIG. 3H is a diagram showing a step subsequent to that in FIG. 3F. FIG. 3I is a view showing a step subsequent to that in FIG. 3F. FIG. 4 is a schematic sectional view of a semiconductor device according to the second embodiment of the present invention. 5A and 5B are views for explaining the internal structure of the semiconductor device of FIG. 4, in which FIG. 5A is a perspective view, and FIG. 5B is a plan view. FIG. 6 is a schematic sectional view of a semiconductor device according to the third embodiment of the present invention. FIG. 7 is an enlarged view of a portion surrounded by a broken line in FIG. FIG. 8A is a diagram illustrating a manufacturing step of the semiconductor device in FIG. 7. FIG. 8B is a diagram showing a step subsequent to that in FIG. 8A. FIG. 8C is a diagram showing a step subsequent to that in FIG. 8B. FIG. 8D is a diagram showing a step subsequent to that in FIG. 8C. FIG. 8E is a diagram showing a step subsequent to that in FIG. 8D. FIG. 8F is a diagram showing a step subsequent to that in FIG. 8E. FIG. 8G is a diagram showing a step subsequent to that in FIG. 8F. FIG. 8H is a diagram showing a step subsequent to that in FIG. 8G. FIG. 8I is a diagram showing a step subsequent to that of FIG. 8H. FIG. 8J is a diagram showing a step subsequent to that in FIG. 8I. FIG. 8K is a diagram showing a step subsequent to that of FIG. 8J. FIG. 9 is a schematic sectional view of a semiconductor device according to the fourth embodiment of the present invention. FIG. 10 is an enlarged view of a portion surrounded by a broken line in FIG. FIG. 11 is a graph showing the V _CE -I _Cf characteristics of the device.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a schematic sectional view of a semiconductor device 1 according to the first embodiment of the present invention. FIG.
FIG. 2 is a perspective view illustrating an internal structure of the semiconductor device of FIG. 1.
The semiconductor device 1 is a device including an IGBT, and includes a semiconductor substrate 2 as an example of a semiconductor layer of the present invention. The semiconductor substrate 2 has a thickness of, for example, n ^{− of} 50 μm to 200 μm.
It may be a shaped silicon substrate.

The semiconductor substrate 2 has a structure in which ap ⁺ -type collector region 4, an n-type buffer region 5, and an n ⁻ -type drift region 6 are sequentially stacked from the back surface 3 side. The p ⁺ type collector region 4 is exposed on the entire back surface 3 of the semiconductor substrate 2, and the n ⁻ type drift region 6 is selectively exposed on a part of the front surface 7 of the semiconductor substrate 2.
As the p-type dopant of the p ⁺ -type collector region 4, for example, B (boron), Al (aluminum), or the like can be used (the same applies hereinafter). On the other hand, N (nitrogen), P (phosphorus), As (arsenic), or the like can be used as the n-type dopant in n-type buffer region 5 and n ⁻ -type drift region 6 (the same applies hereinafter).

The dopant concentration of p ⁺ -type collector region 4 is, for example, 1 × 10 ¹⁵ cm ⁻³ to
It is 2 × 10 ¹⁹ cm ⁻³ . On the other hand, the dopant concentration of n-type buffer region 5 is, for example, 1 × 10 ¹⁵ cm ^{−3 to} 5 × 10 ¹⁷ cm ⁻³ , and the dopant concentration of n ⁻ -type drift region 6 is 1 × 10 ¹³ cm ^−3. ５5 × 10 ¹⁴ cm ⁻³ .
A plurality of gate trenches 8 are formed on the front surface 7 side of the semiconductor substrate 2. In this embodiment, the plurality of gate trenches 8 are formed, for example, in a stripe shape, and are arranged as a pair of trench units 9 in the lateral direction along the surface 7 of the semiconductor substrate 2. Pitch _{P 1} of the trench unit 9 adjacent to each other, for example, a 4Myuemu～20myuemu. Further, in the pair of gate trenches 8, a pitch P between one gate trench 8 and the other gate trench 8 is set.
₂ (distance between center points of gate trench 8) is, for example, 2 μm to 7 μm, and interval L ₁ (distance between side surfaces of gate trench 8) is, for example, 1 μm to 6 μm.

A p-type base region 10 is formed between the pair of gate trenches 8. The p-type base region 10 is shared by one gate trench 8 and the other gate trench 8. In this embodiment, the interface between the p-type base region 10 and the n ⁻ -type drift region 6 is set at the center or upper part of the gate trench 8, and the p-type base region 10 The diffusion is formed shallowly.

In the p-type base region 10, a contact trench 11 dug down from the surface 7 of the semiconductor substrate 2 is formed. The contact trench 11 is formed with a constant width along the longitudinal direction of the gate trench 8. A p ⁺ type base contact region 12 is formed on the bottom surface of the contact trench 11.
An n ⁺ -type emitter region 13 is formed on the surface of the p-type base region 10 between the contact trench 11 and one and the other gate trench 8. The n ⁺ -type emitter regions 13 are provided one on each side of the contact trench 11, and each is exposed on the side surface of the contact trench 11.

The dopant concentration of the p-type base region 10 is, for example, 1 × 10 ¹⁶ cm ⁻³ to 1
× 10 ¹⁸ cm ⁻³ . The dopant concentration of p ⁺ -type base contact region 12 is, for example, 5 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²⁰ cm ⁻³ . The dopant concentration of the n ⁺ -type emitter region 13 is 1 × 10 ¹⁹ cm ^{−3 to} 5 × 10 ²⁰ cm ⁻³ .
A plurality of gate trenches 8 are provided between the pair of gate trenches 8 on the front surface 7 side of the semiconductor substrate 2 (FIG. 1).
In this case, two (2) emitter trenches 14 are formed. In this embodiment, the plurality of emitter trenches 14 are formed, for example, in a stripe shape (parallel to the gate trench 8), and are arranged at equal intervals in the lateral direction along the surface 7 of the semiconductor substrate 2. The distance L ₂ between adjacent emitter trenches 14 (distance between side surfaces of the emitter trenches 14) is, for example, 3 μm or less, preferably 0.8 μm to 3 μm. Further, the plurality of emitter trenches 14 are formed at the same depth as the gate trench 8. Thus, the emitter trench 14 can be formed in the same step as the gate trench 8, so that the manufacturing process can be simplified.

Of the plurality of emitter trenches 14, a trench adjacent to the gate trench 8 (a trench opposed to the gate trench 8 without a trench) via the n ⁻ -type drift region 6 between the trench and the gate trench 8. They are arranged at an interval L _{3 of} 2 μm or less (the distance between the side surface of the emitter trench 14 and the side surface of the gate trench 8). That is, the n ⁻ -type drift region 6 is interposed between the emitter trench 14 and the gate trench 8 over the entire region in the depth direction.

A p-type floating region 15 is formed between each of the plurality of emitter trenches 14. The p-type floating region 15 is a semiconductor region in which an electrically floating state is maintained, and is separated from the gate trench 8 by the emitter trench 14 adjacent to the gate trench 8. In this embodiment, the p-type floating region 15 is formed deeper than the p-type base region 10.

The p-type floating region 15 has a bottom portion 16 bulging toward the back surface 3 of the semiconductor substrate 2 with respect to a bottom portion of the emitter trench 14, and an overlap portion 17 extending below the emitter trench 14 adjacent to the gate trench 8. are doing. The overlap portion 17 has an end portion 18 located closer to the gate trench 8 than the center of the emitter trench 14 in the width direction. It is preferable that the end 18 does not protrude toward the gate trench 8 with respect to the emitter trench 14.

The dopant concentration of the p-type floating region 15 is, for example, 5 × 10 ¹⁵ cm.
⁻³ to 1 × 10 ¹⁸ cm ⁻³ .
A gate electrode 20 and a buried electrode 21 are buried in the gate trench 8 and the emitter trench 14 via an insulating film 19 (for example, silicon oxide (SiO ₂ )). Gate electrode 20 and buried electrode 21 are made of, for example, a conductive material such as polysilicon. The insulating film 19 is formed integrally along the inner surface of the gate trench 8, the surface 7 of the semiconductor substrate 2, and the inner surface of the emitter trench 14. The portion of the insulating film 19 inside the gate trench 8 functions as the gate insulating film 22. The plurality of buried electrodes 21 of the emitter trench 14 are electrically connected to an emitter electrode 25 described later.

On the surface 7 of the semiconductor substrate 2, an interlayer film 23 made of an insulating material such as boron phosphorus silicate glass (BPSG) or silicon oxide (SiO ₂ ) is laminated. Interlayer film 23
A contact hole 24 for selectively exposing the n ⁺ -type emitter region 13 and the p ⁺ -type base contact region 12 via the contact trench 11 is formed.
On the interlayer film 23, an emitter electrode 25 is laminated. The emitter electrode 25 enters the contact trench 11 and is connected to the n ⁺ -type emitter region 13 on a side surface of the contact trench 11. Further, on the bottom surface of the contact trench 11, it is connected to the p-type base region 10 via the p ⁺ -type base contact region 12.

Next, a method for manufacturing the semiconductor device 1 will be described. 3A to 3I are views for explaining the manufacturing process of the semiconductor device 1 of FIG. 1 in the order of processes.
In order to manufacture the semiconductor device 1, as shown in FIG. 3A, a mask 28 is formed on the surface 7 of the n ⁻ type semiconductor substrate 2 (n ⁻ type drift region 6). The mask 28 has p
An opening for selectively exposing a region to be formed in the mold floating region 15 is formed. Then, a p-type dopant is ion-implanted into the surface 7 of the semiconductor substrate 2 through the mask 28. Thus, an ion implantation region 26 is formed.

Next, as shown in FIG. 3B, by selectively etching the semiconductor substrate 2,
Gate trench 8 and emitter trench 14 are formed simultaneously.
Next, as shown in FIG. 3C, the sacrificial oxide film 27 is formed on the entire surface including the inner surfaces of the gate trench 8 and the emitter trench 14 by thermally oxidizing the semiconductor substrate 2.
Then, by annealing the semiconductor substrate 2 covered with the sacrificial oxide film 27, the p-type dopant in the ion implantation region 26 is diffused (drive-in). This annealing process
This is performed under the condition that the p-type dopant goes under the emitter trench 14. This allows
A p-type floating region 15 is formed. At this time, since the semiconductor substrate 2 is covered with the sacrificial oxide film 27, it is possible to prevent the escape of ions from the substrate surface, so that the p-type dopant can be efficiently diffused.

Next, as shown in FIG. 3D, the sacrificial oxide film 27 is peeled off.
Next, as shown in FIG. 3E, the semiconductor substrate 2 is thermally oxidized to cover the entire surface including the inner surfaces of the gate trench 8 and the emitter trench 14 with the insulating film 19 (the gate insulating film 22).
) Is formed.
Next, as shown in FIG. 3F, an electrode material such as polysilicon is buried in the gate trench 8 and the emitter trench 14. Thereby, the gate electrode 20 and the buried electrode 21
Are simultaneously formed.

Next, as shown in FIG. 3G, the n-type and p-type dopants are selectively ion-implanted and diffused with respect to the surface 7 of the semiconductor substrate 2 so that the p-type base region 10 and the n ⁺ -type emitter region 13 are formed. Are sequentially formed.
Next, as shown in FIG. 3H, an interlayer film 23 is formed on the surface 7 of the semiconductor substrate 2 by depositing an insulating material such as boron phosphorus silicate glass (BPSG) and silicon oxide (SiO ₂ ). . Next, the interlayer film 23 is selectively etched to form the contact hole 2.
After the formation of the semiconductor substrate 2, the semiconductor substrate 2 exposed from the contact hole 24 is selectively etched. Thereby, the contact trench 11 is formed.

Next, as shown in FIG. 3I, the p-type dopant is selectively ion-implanted and diffused into the bottom of the contact trench 11 through the contact hole 24, thereby forming p ^+.
A mold base contact region 12 is formed.
Thereafter, after the emitter electrode 24 and the like are formed on the surface 7 side of the semiconductor substrate 2, the semiconductor substrate 2
The n-type buffer region 5 and the p ⁺ -type collector region 4 are sequentially formed by ion-implanting and diffusing the n-type and p-type dopants selectively into the back surface 3 of the substrate.

Through the steps described above, the semiconductor device 1 shown in FIG. 1 is obtained. 3A to 3I show only a part of the manufacturing process of the semiconductor device 1, and the manufacturing process may include a process not shown in FIGS. 3A to 3I.
According to the semiconductor device 1, the emitter trench 14 (with the embedded electrode 21 embedded therein) (
Since the p-type floating region 15 (overlap portion 17) is formed up to the bottom of the "emitter junction trench", the collector-emitter voltage applied to the emitter junction trench during the switching-off operation can be reduced. . Therefore, destruction of the device can be prevented with respect to a steep voltage change (dv / dt).

The breakdown voltage can be improved by the p-type floating region 15 which is deeper than the p-type base region 10. On the other hand, since the p-type base region 10 may be shallow, the channel is designed by appropriately designing the depth of the p-type base region 10. The length (the length in the depth direction of the gate trench 8) can be reduced to suppress an increase in on-voltage.
Further, the gate trench 8 in which the gate electrode 20 is embedded (hereinafter, referred to as “gate junction trench”) is separated from the p-type floating region 15 by the emitter junction trench. Thereby, the junction between the p-type floating region 15 and the gate junction trench can be prevented. Therefore, the stray capacitance between the gate junction trench and the p-type floating region 15 can be eliminated.

On the other hand, n ⁻ type drift region 6 in which the gate junction trench is joined over the entire region in the depth direction
Are grounded together with the p ⁺ -type collector region 4. Therefore, at the time of the switching operation, the capacitance change between the gate junction trench and the n ⁻ -type drift region 6 is stabilized, so that noise hardly occurs. As a result, generation of noise and switching loss at the time of switching operation can be reduced.

In addition, since the distance L between the emitter junction trench and the gate junction trench is 2 μm or less, the withstand voltage can be maintained well.
Further, since the side surface of the contact trench 11 can be effectively utilized as an area for contact with the n ⁺ -type emitter region 13, the junction area of the emitter electrode 25 for the n ⁺ -type emitter region 13 can be sufficiently ensured . Thereby, the n ⁺ type emitter region 1
Since the flat plane area of 3 can be sacrificed, and refining the gap L ₁ of one and the other of the gate trenches 8 in the pair of gate trenches 8, to form a fine p-type base region 10 as compared with the conventional Can be. As a result of the miniaturization of the gate trench 8, the trade-off relationship between the short-circuit withstand capability of the device and the on-voltage can be improved, and the charge promotion effect can be improved. Therefore, V _CE (sat) in a low current region can be improved.

FIG. 4 is a schematic sectional view of a semiconductor device 31 according to the second embodiment of the present invention. 5A and 5B are views for explaining the internal structure of the semiconductor device of FIG. 4, in which FIG.
(B) has shown the top view, respectively. 4 and 5, parts corresponding to the respective parts shown in FIG. 1 are given the same reference numerals.
In the above-described first embodiment, the gate trenches 8 are formed as a pair of trench units 9, and the common p-type base region 10 is formed between one and the other gate trenches 8. On the other hand, the semiconductor device 31 of the second embodiment has a plurality of gate trenches 33 formed as one trench unit 32 in the lateral direction along the surface 7 of the semiconductor substrate 2, and both sides of each gate trench 33 ( A p-type base region 34 formed in the region between the emitter trenches 14) and an n ⁺ -type emitter region 35 formed on the surface of each p-type base region 34. The n ⁺ -type emitter regions 35 are formed one by one along both side surfaces of the gate trench 33,
It is exposed on the surface 7 of the semiconductor substrate 2.

On the surface of the p-type base region 34, ap ⁺ -type base contact region 37 is formed on the side of the n ⁺ -type emitter region 35 (on the side opposite to the gate trench 33). The dopant concentration of the p ⁺ -type base contact region 37 is, for example, 5 × 10 ¹⁸ cm ⁻³ to 1 × 10 ^2.
0 cm ⁻³ .
As shown in FIGS. 5A and 5B, the n ⁺ -type emitter region 35 selectively has a lead portion 38 that is drawn laterally along the surface 7 of the semiconductor substrate 2 from the side surface of the gate trench 33. ing. The lead portions 38 are arranged at regular intervals along the longitudinal direction of the gate trench 33, for example. As in this embodiment, a pair of n
^{When the +} type emitter region 35 is provided, the lead portion 38 of each n ⁺ type emitter region 35 has one end and the other end facing each other with the gate trench 33 interposed therebetween, as shown in FIG. May be arranged, or the end of one lead-out portion 38 and the end of the other lead-out portion 38 may be alternately arranged along the longitudinal direction of the gate trench 33 (not shown). . Thereby, the lead portion 38 in the p ⁺ type base contact region 37
The portion adjacent to is a sandwiching portion 39 which is selectively narrower than the other portions.

Further, the p ⁺ type base contact region 37 and the n ⁺ type emitter region 3
A contact hole 36 for selectively exposing 5 is formed. n ⁺ type emitter region 3
In 5, the lead portion 38 is selectively exposed from the contact hole 36. Emitter electrode 25 is connected to p ⁺ -type base contact region 37 and n ⁺ -type emitter region 35 via contact hole 36.

This semiconductor device 31 can also achieve the same effect as the semiconductor device 1 of the first embodiment.
FIG. 6 is a schematic sectional view of a semiconductor device according to the third embodiment of the present invention. FIG. 7 is an enlarged view of a portion surrounded by a broken line in FIG.
The semiconductor device 101 is a device including an IGBT, and includes a semiconductor substrate 102 as an example of a semiconductor layer of the present invention. The semiconductor substrate 102 is, for example, 50 μm to 200 μm
N ^- type silicon substrate having a thickness of

The semiconductor substrate 102 has a structure in which ap ⁺ -type collector region 104, an n-type buffer region 105, and an n ^-- type drift region 106 are stacked in this order from the back surface 103 side. The p ⁺ type collector region 104 is exposed on the entire back surface 103 of the semiconductor substrate 102, and the n ⁻ type drift region 106 is selectively exposed on a part of the front surface 107 of the semiconductor substrate 102.
As the p-type dopant of the p ⁺ -type collector region 104, for example, B (boron), Al
(Aluminum) or the like (hereinafter the same). On the other hand, as the n-type dopant of the n-type buffer region 105 and the n ⁻ -type drift region 106, for example, N (nitrogen), P (phosphorus), As (arsenic) and the like can be used (the same applies hereinafter).

The dopant concentration of p ⁺ -type collector region 104 is, for example, 1 × 10 ¹⁵ cm ^{−
It is 3 to} 2 × 10 ¹⁹ cm ⁻³ . On the other hand, the dopant concentration of the n-type buffer region 105 is
For example, it is 1 × 10 ¹⁵ cm ^{−3 to} 5 × 10 ¹⁷ cm ⁻³ , and n ⁻ type drift region 1
The dopant concentration of 06 is 1 × 10 ¹³ cm ^{−3 to} 5 × 10 ¹⁴ cm ⁻³ .
On the surface 107 side of the semiconductor substrate 102, a plurality of gate trenches 108 and a plurality of dummy trenches 109 are formed adjacent to each other. In this embodiment, a plurality of trench units 110 including a pair of dummy trenches 109 and a gate trench 108 sandwiched between the pair of dummy trenches 109 are spaced apart in the horizontal direction along the surface 107 of the semiconductor substrate 102. Are located. Thereby, the gate trench 108 and the dummy trench 109 are formed.
Are formed in a stripe shape as a whole.

Pitch _{P 1} of the trench units 110 adjacent to each other, for example, a 2Myuemu～7myuemu. In each of the trench units 110, the distance L ₁ between the gate trench 108 and the dummy trench 109 on both sides thereof (the distance between the side surface of the gate trench 108 and the side surface of the dummy trench 109) is preferably 2 μm or less.
In each trench unit 110, both sides of each gate trench 108 (each dummy trench 10
9), a p-type base region 111 is formed, and the p-type base region 111 is further formed.
The n ⁺ -type emitter region 112 and the p ⁺ -type base contact region 113 are formed on the surface of the substrate (see FIG. 7). In this embodiment, the interface between the p-type base region 111 and the n ⁻ -type drift region 106 is set at the center or above the gate trench 108, and the p-type base region 111 is relatively shallow in the semiconductor substrate 102. The diffusion is formed.

The n ⁺ -type emitter region 112 and the p ⁺ -type base contact region 113 are arranged adjacent to each other in a region between the gate trench 108 and the dummy trench 109.
Specifically, n ⁺ -type emitter regions 112 are formed one by one along both side surfaces 114 of gate trench 108, and p ⁺ -type base contact regions 113 are formed one by one along side surfaces 115 of each dummy trench 109. Have been. Thereby, n ⁺ -type emitter region 112 is exposed on surface 107 of semiconductor substrate 102 and side surface 114 of gate trench 108.
On the other hand, p ⁺ type base contact region 113 is exposed on surface 107 of semiconductor substrate 102 and side surface 115 of dummy trench 109.

The dopant concentration of the p-type base region 111 is, for example, 1 × 10 ¹⁶ cm ⁻³ to
It is 1 × 10 ¹⁸ cm ⁻³ . The dopant concentration of the n ⁺ -type emitter region 112 is 1 × 10
^{It is 19} cm ^{-3 to} 5 × 10 ²⁰ cm ^-3 . The dopant concentration of p ⁺ -type base contact region 113 is, for example, 5 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²⁰ cm ⁻³ .
A plurality of (three in FIG. 6) emitter trenches 116 are formed between adjacent trench units 110 on the surface 107 side of the semiconductor substrate 102. In this embodiment, the plurality of emitter trenches 116 are formed, for example, in a stripe shape (parallel to the gate trenches 108 and the dummy trenches 109), and are arranged at equal intervals in the lateral direction along the surface 107 of the semiconductor substrate 102. I have. Emitter trenches 116 adjacent to each other
Distance _{L 2} (the distance between the side surfaces of the emitter trench 116), for example, 3 [mu] m or less, preferably 0.8Myuemu～3myuemu. The plurality of emitter trenches 116 are formed at the same depth as the gate trench 108 and the dummy trench 109. Thus, the emitter trench 116 can be formed in the same step as the gate trench 108 and the dummy trench 109, so that the manufacturing process can be simplified.

Of the plurality of emitter trenches 116, a trench L ₃ adjacent to the dummy trench 109 (a trench facing the dummy trench 109 without a trench) is 0.5 μm to 20 μm apart from the dummy trench 109. (The distance between the side surface of the emitter trench 116 and the side surface of the dummy trench 109).
Further, a p-type floating region 117 is formed in the semiconductor substrate 102. The p-type floating region 117 extends to a region opposed by the emitter trench 116 and sandwiched between the dummy trenches 109 of the adjacent trench units 110. The p-type floating region 117 is a semiconductor region in which an electrically floating state is maintained.
The dummy trench 109 adjacent to the gate trench 108 allows the gate trench 108
And are separated. The p-type floating region 117 is formed deeper than the p-type base region 111 in this embodiment.

The p-type floating region 117 has a bottom portion 118 bulging toward the back surface 103 of the semiconductor substrate 102 with respect to a bottom portion of the emitter trench 116, and an overlap portion 119 extending below the dummy trench 109. The overlap portion 119 has an end 120 located on the side closer to the gate trench 108 with respect to the center of the dummy trench 109 in the width direction. It is preferable that the end 120 does not protrude toward the gate trench 108 with respect to the emitter trench 116.

The dopant concentration of the p-type floating region 117 is, for example, 5 × 10 ¹⁵ c
m ⁻³ to 1 × 10 ¹⁸ cm ⁻³ .
A gate electrode 122, a first buried electrode 123, and a second buried electrode 124 are buried in the gate trench 108, the dummy trench 109, and the emitter trench 116 via an insulating film 121 (for example, silicon oxide (SiO ₂ )). I have. The gate electrode 122, the first buried electrode 123, and the second buried electrode 124 are made of, for example, a conductive material such as polysilicon. The insulating film 121 is integrally formed along the inner surface of the gate trench 108, the inner surface of the dummy trench 109, the surface 107 of the semiconductor substrate 102, and the inner surface of the emitter trench 116. The portion of the insulating film 121 inside the gate trench 108 is
It functions as the gate insulating film 125. The first buried electrode 123 and the second buried electrode 124 are electrically connected to an emitter electrode 132 described later.

Further, in this embodiment, the gate electrode 122 and the second buried electrode 124 bury the trenches 108 and 116 to the opening ends, whereas the first buried electrode 1
Numeral 23 is buried back halfway in the depth direction of the dummy trench 109. Thus, a space without an electrode is formed in the dummy trench 109 in a region above the first buried electrode 123. Then, a buried insulating film 126 is buried in the dummy trench 109 so as to bury this space to the opening end.

The buried insulating film 126 is made of an insulating material such as boron phosphorus silicate glass (BPSG) or silicon oxide (SiO ₂ ), and has a thickness of 0.5 μm or more. The buried insulating film 126 and the insulating film 121 thereunder have side surfaces 115 of the dummy trench 109.
The removal portion 127 for exposing the p ⁺ -type base contact region 113 is selectively formed. That is, the buried insulating film 126 selectively has an upper surface 128 at a position lower than the surface 107 of the semiconductor substrate 102 so as to be continuous with the side surface 115 of the dummy trench 109, and between the upper surface 128 and the surface 107. The p ⁺ type base contact region 113 is exposed in the region of the side surface 115 of the dummy trench 109.

On the surface 107 of the semiconductor substrate 102, for example, boron phosphorus silicate glass (BPS)
G), an interlayer film 129 made of an insulating material such as silicon oxide (SiO ₂ ) is laminated.
The interlayer film 129 is formed integrally with the buried insulating film 126. In the interlayer film 129,
A contact hole 130 is formed over the surface 107 of the semiconductor substrate 102 and the opening end of the dummy trench 109. This contact hole 130 exposes n ⁺ -type emitter region 112 and p ⁺ -type base contact region 113 on surface 107 of semiconductor substrate 102, and p ⁺ -type base contact region 1 on side surface 115 (removed portion 127) of dummy trench 109.
13 is exposed. That is, the p ⁺ type base contact region 113 is
It is exposed at the corner 131 of the dummy trench 109 formed by the intersection with 15. Note that the n ⁺ -type emitter region 112 extends from the side surface 114 of the gate trench 108 to the semiconductor substrate 1.
02 may be selectively provided with a lead portion drawn out in the horizontal direction along the surface 107, and only this lead portion may be selectively exposed from the contact hole 130.

On the interlayer film 129, an emitter electrode 132 as an example of the contact electrode of the present invention is laminated. The emitter electrode 132 enters the contact hole 130, is connected to the n ⁺ -type emitter region 112 on the surface 107 of the semiconductor substrate 102, and
Nine corners 131 are connected to p ⁺ type base contact region 113.
Next, a method for manufacturing the semiconductor device 101 will be described. 8A to 8K are views for explaining a manufacturing process of the semiconductor device 101 of FIGS. 6 and 7 in the order of processes. In addition, FIG.
8F shows a cross section corresponding to FIG. 6, and FIGS. 8G to 8K show cross sections corresponding to FIG.

To manufacture the semiconductor device 101, as shown in FIG. 8A, an n ⁻ type semiconductor substrate 102 (
A mask 160 is formed on the surface 107 of the n ⁻ -type drift region 106). The mask 160 has an opening for selectively exposing a region to be formed in the p-type floating region 117 on the surface 107. Then, a p-type dopant is ion-implanted (implanted) into the surface 107 of the semiconductor substrate 102 through the mask 160. Thereby, an ion implantation region 161 is formed.

Next, as shown in FIG. 8B, by selectively etching the semiconductor substrate 102, a gate trench 108, a dummy trench 109, and an emitter trench 116 are simultaneously formed.
Next, as shown in FIG. 8C, sacrificial oxide film 162 is formed on the entire surface including the inner surfaces of gate trench 108, dummy trench 109 and emitter trench 116 by thermally oxidizing semiconductor substrate 102. Then, the semiconductor substrate 1 covered with the sacrificial oxide film 162
By performing the annealing process on 02, the p-type dopant in the ion implantation region 161 is diffused (drive-in). This annealing is performed under the condition that the p-type dopant goes under the dummy trench 109. As a result, a p-type floating region 117 is formed. At this time, since the semiconductor substrate 102 is covered with the sacrificial oxide film 162, the escape of ions from the substrate surface can be prevented, so that the p-type dopant can be diffused efficiently.

Next, as shown in FIG. 8D, the sacrificial oxide film 162 is peeled off.
Next, as shown in FIG. 8E, by thermally oxidizing the semiconductor substrate 102, an insulating film 121 (gate insulating film 125) is formed on the entire surface including the inner surfaces of the gate trench 108, the dummy trench 109, and the emitter trench 116. Is done.
Next, as shown in FIG. 8F, an electrode material such as polysilicon is buried in the gate trench 108, the dummy trench 109, and the emitter trench 116. Thereby, the gate electrode 122, the first buried electrode 123, and the second buried electrode 124 are formed simultaneously.

Next, as shown in FIG. 8G, the n-type and p-type dopants are selectively ion-implanted and diffused with respect to the surface 107 of the semiconductor substrate 102, so that the p-type base region 111 and the n ⁺ -type emitter region 112 are formed. Are sequentially formed.
Next, as shown in FIG. 8H, by etching the first buried electrode 123 from the upper surface, only the first buried electrode 123 is selectively formed while the buried state of the gate electrode 122 and the second buried electrode 124 is maintained. You can delve into it.

Next, as shown in FIG. 8I, an insulating material such as boron phosphorus silicate glass (BPSG) or silicon oxide (SiO ₂ ) is deposited on the surface 107 of the semiconductor substrate 102 so as to be above the first embedded electrode 123. The space is backfilled with the insulating material and the surface 10
7 is covered with the insulating material. Thereby, the buried insulating film 126 and the interlayer film 129 are simultaneously formed.

Next, as shown in FIG. 8J, by selectively etching the interlayer film 129 and the buried insulating film 126, the contact hole 130 and the removed portion 127 are simultaneously formed.
Next, as shown in FIG. 8K, a p-type dopant is selectively ion-implanted and diffused into surface 107 of semiconductor substrate 102 exposed in contact hole 130. As a result, ap ⁺ type base contact region 113 is formed.

Then, after the emitter electrode 132 and the like are formed on the front surface 107 side of the semiconductor substrate 102, the n-type and p-type dopants are selectively ion-implanted and diffused into the back surface 103 of the semiconductor substrate 102, so that the n-type Buffer region 105 and p ⁺ type collector region 104
Are sequentially formed.
Through the above steps, the semiconductor device 101 shown in FIGS. 6 and 7 is obtained. 8A to 8K only show a part of the manufacturing process of the semiconductor device 101.
The manufacturing process may include a process not shown in FIGS. 8A to 8K.

According to the semiconductor device 101, the side surface 115 of the dummy trench 109 can be effectively used as the p ⁺ -type base contact region 113, so that the junction area of the emitter electrode 132 to the p-type base region 111 can be reduced. Sufficiently can be secured on both sides of the side surface 115 of the dummy trench 109 and 107. Thus, it is possible to sacrifice planar area of the p-type base region 111, the distance L ₁ between the gate trench 108 and the dummy trench 109 is miniaturized, form fine p-type base region 111 as compared with the conventional can do. In addition, since the dummy trench 109 can be formed using the same mask as that of the gate trench 108, no displacement occurs with respect to the gate trench 108. Since the alignment of the emitter electrode 132 may be adjusted to the area including the planar area of the dummy trench 109, the alignment can be easily performed.

Specifically, first, the gate trench 108, the dummy trench 109, and the emitter trench 116 are simultaneously formed by etching the semiconductor substrate 102 using the same mask (FIG. 8B). Next, the gate electrode 122, the first buried electrode 123, and the second buried electrode 124 are formed by burying polysilicon in the trenches 108, 109, and 116 (FIG. 8F). Next, a mask for selectively exposing the dummy trench 109 is formed on the semiconductor substrate 102, and an upper portion of the polysilicon in the dummy trench 109 is selectively removed by etching through the mask. Thereby, the dummy trench 10
A space is formed above the first embedded electrode 123 (FIG. 8H). Then, for example, C
By depositing an insulating material such as BPSG on the semiconductor substrate 102 by the VD method, an interlayer film 129 is formed (FIG. 8I). Part of the insulating material enters the dummy trench 109 as a buried insulating film 126. Next, a mask for forming the contact hole 130 is aligned with the semiconductor substrate 102. At this time, since the end of the contact hole 130 may cover the dummy trench 109, alignment can be performed in a wide area including the plane area of the surface 107 of the semiconductor substrate 102 and the dummy trench 109. Then, the interlayer film 129 and the buried insulating film 126 are continuously etched through the mask. Thereby, the contact hole 130 and the removed portion 127 are formed simultaneously (FIG. 8J). Thereafter, a p-type dopant is ion-implanted using the interlayer
^{If the +} type base contact region 113 is formed in a self-aligned manner, the p ⁺ type base contact region 113 can be reliably formed at the corner 131 of the dummy trench 109 (FIG. 8K).
. Moreover, since the contact hole 130 can be formed relatively wide, a part of the emitter electrode 132 made of aluminum (Al) or the like can be used as a plug without using a plug having good embedding properties such as tungsten (W). Can be.

As a result of the miniaturization of the trench structure as described above, the trade-off relationship between the short-circuit withstand voltage of the device and the on-voltage can be improved, so that the charge promotion effect can be improved. Therefore, V _CE (sat) in a low current region can be improved.
According to the semiconductor device 101, the gate trench 108 in which the gate electrode 122 is buried (hereinafter referred to as “gate junction trench”) is buried in the first buried electrode 123 connected to the n ⁺ -type emitter region 112. A dummy trench 109 (hereinafter referred to as an “emitter junction trench”) separates the p-type floating region 117 from the p-type floating region 117. Thereby, the junction between the p-type floating region 117 and the gate junction trench can be prevented. Therefore, the floating capacitance between the gate junction trench and the p-type floating region 117 can be eliminated.

On the other hand, n ⁻ type drift region 106 in which the gate junction trench is joined in the depth direction
Are grounded together with the p ⁺ -type collector region 104. Therefore, at the time of the switching operation, the capacitance change between the gate junction trench and the n ⁻ -type drift region 106 is stabilized, so that noise hardly occurs. As a result, generation of noise and switching loss at the time of switching operation can be reduced.

Further, the emitter junction trench, the spacing L ₁ between the gate junction trench is 2μm or less, may be satisfactorily hold the breakdown voltage.
Further, according to the semiconductor device 101, since the p-type floating region 117 (overlap portion 119) is formed up to the bottom of the emitter junction trench, the collector-emitter voltage applied to the emitter junction trench during the switching-off operation is reduced. can do. Therefore, destruction of the device can be prevented with respect to a steep voltage change (dv / dt).

The breakdown voltage can be improved by the p-type floating region 117 deeper than the p-type base region 111. On the other hand, the p-type base region 111 may be shallower. Length (length in the depth direction of the gate trench 108)
Can be reduced to suppress an increase in on-voltage.
FIG. 9 is a schematic sectional view of a semiconductor device 141 according to the fourth embodiment of the present invention. FIG.
0 is an enlarged view of a portion surrounded by a broken line in FIG. 9 and 10, parts corresponding to the respective parts shown in FIGS. 6 and 7 are denoted by the same reference numerals.

In the third embodiment, the trench unit 110 includes the pair of dummy trenches 109 and the gate trench 108 interposed between the pair of dummy trenches 109. On the other hand, the semiconductor device 141 of the fourth embodiment has a trench unit 144 including a pair of gate trenches 142 and a dummy trench 143 interposed between the pair of gate trenches 142. In this case, the distance L ₃ between the gate trench 142 and the emitter trench 116 (the distance between the side surface of the gate trench 142 and the side surface of the emitter trench 116) is preferably 2 μm or less.

In each trench unit 144, both sides of each dummy trench 143 (each gate trench 14
2), a p-type base region 145 is formed, and the p-type base region 145 is further formed.
The n ⁺ -type emitter region 146 and the p ⁺ -type base contact region 147 are formed on the surface of the substrate (see FIG. 10). In this embodiment, the interface between the p-type base region 145 and the n ⁻ -type drift region 106 is set at the center or the upper part of the gate trench 142, and the p-type base region 145 is relatively shallow in the semiconductor substrate 102. The diffusion is formed.

N ⁺ -type emitter region 146 and p ⁺ -type base contact region 147 are arranged adjacent to each other in a region between gate trench 142 and dummy trench 143.
Specifically, n ⁺ -type emitter regions 146 are formed one by one along the side surface 148 of each gate trench 142, and p ⁺ -type base contact regions 147 are formed one by one along both side surfaces 149 of the dummy trench 143. Have been. Thus, n ⁺ -type emitter region 146 is exposed on surface 107 of semiconductor substrate 102 and side surface 148 of gate trench 142.
On the other hand, p ⁺ type base contact region 147 is exposed on surface 107 of semiconductor substrate 102 and side surface 149 of dummy trench 143.

Further, a p-type floating region 150 is formed in the semiconductor substrate 102. The p-type floating region 150 extends between each of the plurality of emitter trenches 116. p
The mold floating region 150 is a semiconductor region kept electrically floating, and is separated from the gate trench 142 by the emitter trench 116 adjacent to the gate trench 142. In this embodiment, the p-type floating region 150 is formed deeper than the p-type base region 145.

The p-type floating region 150 has a bottom 151 bulging toward the back surface 103 of the semiconductor substrate 102 with respect to a bottom of the emitter trench 116, and an overlap 152 wrapping around the emitter trench 116 adjacent to the gate trench 142. are doing. The overlap portion 152 is formed between the gate trench 14 and the center of the emitter trench 116 in the width direction.
2 has an end 153 located on the near side. This end 153 is formed in the emitter trench 1
It is preferable that the protrusion 16 does not protrude toward the gate trench 142.

Such a p-type floating region 150 can be formed, for example, in the same manner as the p-type floating region 117 described above.
A first buried electrode 154 is buried in the dummy trench 143 via the insulating film 121. The first embedded electrode 154 is made of a conductive material such as polysilicon, for example.
It is electrically connected to the gate electrode 122. In addition, the first buried electrode 154 is buried back halfway in the depth direction of the dummy trench 143. Thereby, the dummy trench 143
A space without an electrode is formed in a region above the first embedded electrode 154. And
A buried insulating film 155 is buried in the dummy trench 143 so as to bury this space to the opening end.

The buried insulating film 155 is made of an insulating material such as boron phosphorus silicate glass (BPSG) and silicon oxide (SiO ₂ ), and has a thickness of 0.5 μm or more. In the buried insulating film 155 and the insulating film 121 thereunder, both side surfaces 14 of the dummy trench 143 are formed.
9, a removed portion 156 exposing the p ⁺ type base contact region 147 is selectively formed. That is, the buried insulating film 155 is formed on both sides 149 of the dummy trench 143.
The upper surface 157 at a position lower than the surface 107 of the semiconductor substrate 102 is selectively provided so as to be continuous with the side surfaces 149 of the dummy trench 143 between the upper surface 157 and the surface 107.
The p ⁺ type base contact region 147 is exposed in the region of FIG.

A contact hole 158 is formed in the interlayer film 129 so as to extend over the p-type base region 145 facing the dummy trench 143. This contact hole 158 is formed on the surface 107 of the semiconductor substrate 102 by the n ⁺ -type emitter region 146 and the p ⁺ -type base contact region 1.
47 are exposed, and the p ⁺ -type base contact region 147 is exposed at both side surfaces 149 (removed portions 156) of the dummy trench 143. That is, the p ⁺ type base contact region 147 is formed at both corners 159 of the dummy trench 143 formed by the intersection of the surface 107 and the side surface 149.
It is exposed to. The n ⁺ type emitter region 146 is formed on the side surface 14 of the gate trench 142.
8 may be selectively provided with a lead portion drawn out in the lateral direction along the surface 107 of the semiconductor substrate 102, and only this lead portion may be selectively exposed from the contact hole 158.

Then, the emitter electrode 132 enters the contact hole 158 and the semiconductor substrate 10
2 is connected to the n ⁺ -type emitter region 146 at the surface 107, and is connected to the p ⁺ -type base contact region 147 at both corners 159 of the dummy trench 143.
According to the semiconductor device 141, the same effect as the semiconductor device 101 of the third embodiment can be achieved.

The embodiments of the present invention have been described above, but the present invention can be embodied in other forms.
For example, the above features ascertained from the disclosure of each of the above embodiments can be combined with each other even in different embodiments.
Further, in the above-described embodiment, only the configuration of the IGBT included in the semiconductor devices 1, 31, 101, and 141 is illustrated.
FET, diode, etc.) may be provided in a region different from the IGBT formation region.

In addition, various design changes can be made within the scope of the matters described in the claims.
From the description of the specification and the drawings, the following features can be extracted in addition to the invention described in the claims.
(Claim 1) A semiconductor layer, a gate trench formed in the semiconductor layer, a gate electrode buried in the gate trench via a gate insulating film, and formed at a predetermined interval on a side of the gate trench. And an n ⁺ -type emitter region, a p-type base region, and an n ⁺ -type emitter region that are sequentially arranged in a depth direction of the gate trench from a surface side of the semiconductor layer in a region between the dummy trench and the gate trench and the dummy trench. n ^- -type drift region, the n ^-
A p ⁺ -type collector region disposed on the back side of the semiconductor layer with respect to a mold drift region, and a buried buried in the dummy trench, the top surface being on the bottom side of the dummy trench with respect to the surface of the semiconductor layer. A buried insulating film that selectively exposes a part of the p-type base region as a contact region in a part of the side surface of the dummy trench from the surface to the upper surface; A contact electrode embedded in an upper region of the film and connected to the contact region on the side surface of the dummy trench.

According to this configuration, the side surface of the dummy trench can be effectively used as a contact region, so that a sufficient contact area of the contact electrode with the p-type base region can be ensured. Thus, the planar area of the p-type base region can be sacrificed, so that the distance between the gate trench and the dummy trench can be reduced to form a p-type base region that is finer than in the related art. In addition, since the dummy trench can be formed using the same mask as the gate trench, no displacement occurs with respect to the gate trench. And
The alignment of the contact electrode can be easily performed because it is sufficient to match the area including the plane area of the dummy trench.

In addition, as a result of the miniaturization of the trench structure, a trade-off relationship between the short-circuit withstand voltage of the device and the on-voltage can be improved, so that the charge promoting effect can be improved. Therefore,
V _CE (sat) in a low current region can be improved.
(Item 2) The semiconductor device according to item 1, wherein the semiconductor device further includes a first buried electrode buried in a region below the buried insulating film in the dummy trench via an insulating film.

(Item 3) The semiconductor device according to item 2, wherein the semiconductor device has a trench unit including a pair of the dummy trenches and a gate trench sandwiched between the pair of dummy trenches.
(Item 4) The semiconductor device according to item 3, wherein the first buried electrode is electrically connected to the n ⁺ -type emitter region.
(Claim 5) The plurality of trench units are formed in a lateral direction along the surface of the semiconductor layer, and the semiconductor device includes a plurality of emitter trenches formed between the adjacent trench units. A second buried electrode buried in the emitter trench via an insulating film and electrically connected to the n ⁺ -type emitter region; the dummy trench in the trench unit; and the dummy trench in the trench unit adjacent thereto. Item 5. The semiconductor device according to item 4, further comprising a p-type floating region formed between the two.

(Item 6) The semiconductor device according to item 5, wherein the p-type floating region is formed deeper than the p-type base region and includes an overlap portion that goes under the dummy trench.
According to this configuration, the p-type floating region (overlap portion) is formed up to the bottom of the dummy trench (hereinafter, referred to as “emitter junction trench”) in which the first buried electrode connected to the n ⁺ -type emitter region is buried. Therefore, the collector-emitter voltage applied to the emitter junction trench during the switching-off operation can be reduced. Therefore, destruction of the device can be prevented with respect to a steep voltage change (dv / dt).

Also, the withstand voltage can be improved by the p-type floating region deeper than the p-type base region, but the p-type base region may be shallow. Therefore, by appropriately designing the depth of the p-type base region, an increase in on-voltage can be prevented. It can also be suppressed.
(Item 7) The semiconductor device according to item 6, wherein the overlap portion has an end located closer to the gate trench with respect to the center of the dummy trench in the width direction.

With this configuration, the collector-emitter voltage applied to the emitter junction trench can be more favorably reduced.
(Item 8) The semiconductor device according to item 2, wherein the semiconductor device has a trench unit including a pair of the gate trenches and a dummy trench interposed between the pair of the gate trenches.

(Item 9) The semiconductor device according to item 8, wherein the first buried electrode is electrically connected to the gate electrode.
(Item 10) The plurality of trench units are formed in a lateral direction along the surface of the semiconductor layer, and the semiconductor device includes a plurality of emitter trenches formed between the adjacent trench units. A second buried electrode buried in the emitter trench via an insulating film and electrically connected to the n ⁺ -type emitter region; and a p-type floating region formed between the plurality of emitter trenches. Item 10. The semiconductor device according to item 9.

(Item 11) The p-type floating region is formed deeper than the p-type base region,
Item 11. The semiconductor device according to item 10, including an overlap portion that goes under the emitter trench.
According to this configuration, a p-type floating region (overlap portion) is formed up to the bottom of the emitter trench (hereinafter referred to as “emitter junction trench”) in which the second buried electrode connected to the n ⁺ -type emitter region is buried. Therefore, the collector-emitter voltage applied to the emitter junction trench during the switching-off operation can be reduced. for that reason,
The device can be prevented from being destroyed by a steep voltage change (dv / dt).

Also, the withstand voltage can be improved by the p-type floating region deeper than the p-type base region, but the p-type base region may be shallow. Therefore, by appropriately designing the depth of the p-type base region, an increase in on-voltage can be prevented. It can also be suppressed.
(Item 12) The semiconductor device according to item 11, wherein the overlap portion has an end located closer to the gate trench with respect to the center in the width direction of the emitter trench.

With this configuration, the collector-emitter voltage applied to the emitter junction trench can be more favorably reduced.
(Item 13) The semiconductor device according to any one of Items 1 to 12, wherein the buried insulating film has a thickness of 0.5 μm or more.
(Item 14) The semiconductor device according to any one of Items 1 to 13, wherein the dummy trench is arranged at a distance of 2 μm or less from the gate trench.

(Item 15) The n ⁺ -type emitter region is 1 × 10 ¹⁹ cm ^{−3 to} 5 × 10 ²⁰ cm ^−3.
Item 15. The semiconductor device according to any one of Items 1 to 14, having an n-type dopant concentration of:
(Item 16) The p-type base region has a p-type base region of 1 × 10 ¹⁶ cm ⁻³ to 1 × 10 ¹⁸ cm ⁻³ .
Item 16. The semiconductor device according to any one of Items 1 to 15, having a type dopant concentration.
(Item 17) The n ⁻ -type drift region is 1 × 10 ¹³ cm ^{−3 to} 5 × 10 ¹⁴ cm ^−3.
The semiconductor device according to any one of Items 1 to 16, having an n-type dopant concentration of:

(Item 18) The p ⁺ -type collector region is 1 × 10 ¹⁵ cm ⁻³ to 2 × 10 ¹⁹ cm ^−3.
Item 18. The semiconductor device according to any one of Items 1 to 17, having a p-type dopant concentration of:
(Claim 19) A semiconductor layer, a plurality of gate trenches formed in the semiconductor layer, a gate electrode embedded in the plurality of gate trenches via a gate insulating film, and a side of each of the gate trenches, An n ⁺ -type emitter region, a p-type base region, and an n ⁻ -type drift region which are sequentially arranged in a depth direction of the gate trench from a front surface side of the semiconductor layer, and a back surface of the semiconductor layer with respect to the n ⁻ -type drift region a p ⁺ -type collector region disposed on the side, a plurality of emitter trench formed between said plurality of gate trenches adjacent to each other, in the surface portion of the p-type base region, the relative n ⁺ -type emitter region A p ⁺ -type base contact region formed on the opposite side of the gate trench, and the n ⁺ -type embedded in the plurality of emitter trenches via an insulating film; A buried electrode electrically connected to the emitter region, a p-type floating region formed between the plurality of emitter trenches, and an interlayer film formed on the semiconductor layer, wherein the p-type floating region is Is formed deeper than the p-type base region, wraps below an emitter trench closest to the gate trench among the plurality of emitter trenches, and is located on a side closer to the gate trench with respect to a center in the width direction of the emitter trench. An overlap portion having an end portion, the p-type base region is exposed on the surface of the semiconductor layer between the p ⁺ -type base contact region and the emitter trench, and the interlayer film is It is formed so as to cover a part of the whole of the n ⁺ -type emitter region and the p ⁺ -type base contact region Semiconductor device.

According to this configuration, the p-type floating region (overlap portion) is formed up to the bottom of the emitter trench (hereinafter, referred to as “emitter junction trench”) in which the buried electrode is buried. Thereby, the collector-emitter voltage applied to the emitter junction trench during the switching-off operation can be reduced. Therefore, a sharp voltage change (dv / dt)
) Can prevent the destruction of the device.

Also, since the breakdown voltage can be improved by the p-type floating region deeper than the p-type base region, the p-type base region may be shallow. Therefore, the channel length can be reduced by appropriately designing the depth of the p-type base region. As a result, an increase in the ON voltage can be suppressed.
(Item 20) The p-type floating region may have a bottom bulging toward the back side of the semiconductor layer with respect to the bottom of the emitter trench.

(Item 21) Preferably, the emitter trench is formed at the same depth as the gate trench.
In this case, since the emitter trench can be formed in the same process as the gate trench, the manufacturing process can be simplified.
(Claim 22) The n ⁺ type emitter region is 1 × 10 ¹⁹ cm ^{−3 to} 5 × 10 ²⁰ cm ^−3.
May be provided.

(Claim 23) The p-type base region has a p-type base region of 1 × 10 ¹⁶ cm ⁻³ to 1 × 10 ¹⁸ cm ⁻³ .
It may have a type dopant concentration.
(Item 24) The n ^- type drift region is 1 × 10 ¹³ cm ^{−3 to} 5 × 10 ¹⁴ cm ^−3.
May be provided.
(Item 25) The p ⁺ -type collector region is 1 × 10 ¹⁵ cm ⁻³ to 2 × 10 ¹⁹ cm ^−3.
May be provided.

(Item 26) It is preferable that the n ⁺ -type emitter region has a lead portion selectively drawn laterally along a surface of the semiconductor layer from a side surface of the gate trench.
(Section 27) A semiconductor layer, a plurality of gate trenches formed in the semiconductor layer, a gate electrode embedded in the plurality of gate trenches via a gate insulating film, and a side of each of the gate trenches, An n ⁺ -type emitter region, a p-type base region, and an n ⁻ -type drift region which are sequentially arranged in a depth direction of the gate trench from a front surface side of the semiconductor layer, and a back surface of the semiconductor layer with respect to the n ⁻ -type drift region a p ⁺ -type collector region disposed on the side, embedded through a plurality of emitter trench formed between said plurality of gate trenches adjacent to each other, the insulating film on the plurality of emitter trench, the n ⁺ -type A buried electrode electrically connected to the emitter region; a p-type floating region formed between the plurality of emitter trenches; The n ⁺ -type emitter region between the wrench, the p-type base region and the n ^- As -type drift region is formed, and the dummy trench formed at a predetermined interval laterally of said gate trench A buried insulating film buried in the dummy trench and having an upper surface on the bottom side of the dummy trench with respect to the surface of the semiconductor layer, wherein a portion of the side surface of the dummy trench from the surface to the upper surface is a buried insulating film for selectively exposing a part of the p-type base region as a contact region; and a buried insulating film in the dummy trench above the buried insulating film and connected to the contact region on the side surface of the dummy trench. A contact electrode, wherein the p-type floating region is formed deeper than the p-type base region. A semiconductor including an overlap portion which wraps below an emitter trench closest to the gate trench among the plurality of emitter trenches and has an end located closer to the gate trench with respect to a center in the width direction of the emitter trench; apparatus.

According to this configuration, the side surface of the dummy trench can be effectively used as a contact region, so that a sufficient contact area of the contact electrode with the p-type base region can be ensured. Thus, the planar area of the p-type base region can be sacrificed, so that the distance between the gate trench and the dummy trench can be reduced to form a p-type base region that is finer than in the related art. In addition, since the dummy trench can be formed using the same mask as the gate trench, no displacement occurs with respect to the gate trench. And
The alignment of the contact electrode can be easily performed because it is sufficient to match the area including the plane area of the dummy trench.

In addition, as a result of the miniaturization of the trench structure, a trade-off relationship between the short-circuit withstand voltage of the device and the on-voltage can be improved, so that the charge promoting effect can be improved. Therefore,
V _CE (sat) in a low current region can be improved.
(Item 28) The semiconductor device may further include a first buried electrode buried in a region below the buried insulating film in the dummy trench via an insulating film.

(Item 29) The semiconductor device may have a trench unit including a pair of the dummy trenches and a gate trench sandwiched between the pair of the dummy trenches.
(Item 30) It is preferable that the dummy trench also serves as the emitter trench when the first buried electrode is electrically connected to the n ⁺ -type emitter region.
(Item 31) The semiconductor device may have a trench unit including a pair of the gate trenches and a dummy trench interposed between the pair of the gate trenches.

In this case, it is preferable that the first buried electrode is electrically connected to the gate electrode.
(Item 33) The buried insulating film preferably has a thickness of 0.5 μm or more.

Next, the present invention will be described based on examples, but the present invention is not limited to the following examples.
Respect to the structure of the semiconductor device 101 shown in FIG. 6, the distance between the effect of improving the trade-off between short-circuit capacity and the ON voltage (V _CE) is the gate trench 108 and the dummy trench 109 L
To see how it changed by _1, the distance _{L 1} was examined _V CE _{-I Cf} characteristics of four different devices. The results are shown in FIG. In FIG. 11, device A (trench interval L ₁ = 2 μm dot-dash line) and device C (trench interval L ₁ = 3)
. 5 μm broken line).

According to FIG. 11, the narrower the trench distance _{L 1,} the rise of the _V CE (sat) is low, it steady loss is low it can be confirmed (see the lower right enlarged view of FIG. 11). In the high current region of I _Cf, the saturation current density was reduced due to the miniaturization of the trench (reduction in the volume of the p-type base region 111), and it was confirmed that the short-circuit withstand capability was improved.

REFERENCE SIGNS LIST 1 semiconductor device 2 semiconductor substrate 3 back surface 4 p ⁺ type collector region 5 n type buffer region 6 n ⁻ type drift region 7 surface 8 gate trench 10 p type base region 13 n ⁺ type emitter region 14 emitter trench 15 p type floating region 16 Bottom part 17 Overlap part 18 End part 19 Insulating film 20 Gate electrode 21 Embedded electrode 22 Gate insulating film 31 Semiconductor device 33 Gate trench 34 P-type base region 35 n ⁺ type emitter region 38 Leader 101 Semiconductor device 102 Semiconductor substrate 103 Back surface 104 p ⁺ -type collector region 106 n ^- -type drift region 107 surface 108 gate trenches 109 dummy trench 110 trench unit 111 p-type base region 112 n ⁺ -type emitter region 113 p ⁺ -type base contact region 11 Side surface 115 Side surface 116 Emitter trench 117 p-type floating region 118 bottom 119 overlap portion 120 end 121 insulating film 122 gate electrode 123 first buried electrode 124 second buried electrode 125 gate insulating film 126 buried insulating film 127 removed portion 128 top surface 132 Emitter electrode 141 Semiconductor device 142 Gate trench 143 Dummy trench 144 Trench unit 145 P-type base region 146 n ⁺ -type emitter region 147 p ⁺ -type base contact region 148 Side surface 149 Side surface 150 P-type floating region 151 Bottom 152 Overlap 153 End 154 first buried electrode 155 buried insulating film 156 removed part 157 top surface 159 corner

The present invention relates to a semi-conductor device.

  A semiconductor device according to an embodiment of the present invention includes a semiconductor layer and a tray formed on the semiconductor layer. An embedded electrode embedded in the trench via an insulating film; and the embedded electrode. On the side of the semiconductor layer, the first layer is arranged in the depth direction of the trench in order from the surface side of the semiconductor layer. A first region of one conductivity type, a second region of second conductivity type, and the first conductivity type; A third region having an impurity concentration lower than one region, and the second region with respect to the trench. Is formed on the opposite side, and is formed of a flow of the second conductivity type formed deeper than the second region. And a contour formed in the second region by dug down from the surface of the semiconductor layer. Contact trench, and formed at the bottom of the contact trench and higher than the second region. A contact region of the second conductivity type having a low impurity concentration and a surface side of the semiconductor layer. And entered the contact trench, and on the side of the contact trench Connected to the first region, and connected to the contact region at the bottom of the contact trench. Surface electrode provided.

Claims (11)

A semiconductor layer;
A plurality of trenches formed in the semiconductor layer so as to extend in the first direction and arranged in the second direction orthogonal to the first direction;
A repetitive structure of a plurality of gate electrodes buried in the plurality of trenches via an insulating film and adjacent to each other in the second direction and a plurality of emitter electrodes adjacent to each other along the second direction;
An n ⁺ -type emitter region which is arranged in order in a depth direction of the trench from a surface side of the semiconductor layer in a region between the adjacent gate electrodes on a side of the gate electrode;
a p-type base region and an n ⁻ -type drift region;
A p-type floating region which is formed in a region between the adjacent emitter electrodes, is formed deeper than the p-type base region, and includes an overlap portion which goes under the emitter electrode;
A p ⁺ -type collector region disposed on the back side of the semiconductor layer with respect to the n ⁻ -type drift region;
A semiconductor device, wherein an interface between the p-type base region and the n ⁻ -type drift region is set at a central portion or an upper portion of the trench. 2. The semiconductor device according to claim 1, wherein the p-type floating region has a bottom bulging toward a back surface of the semiconductor layer with respect to a bottom of the trench. 3. 3. The semiconductor device according to claim 1, wherein the overlap portion of the p-type floating region has an end located on a gate electrode side with respect to a center in a width direction of the emitter electrode. 4. The bottom of the trench is formed in a curved shape so that the center in the width direction is the most convex,
The semiconductor device according to claim 3, wherein an end of the overlap portion is located beyond a center in the width direction. The semiconductor device according to claim 1, wherein an n-type buffer layer is formed between the n ⁻ -type drift region and the p ⁺ -type collector region. The semiconductor device according to claim 1, wherein the n ⁺ -type emitter region has an n-type dopant concentration of 1 × 10 ¹⁹ cm ^{−3 to} 5 × 10 ²⁰ cm ⁻³ . The semiconductor device according to claim 1, wherein the p-type base region has a p-type dopant concentration of 1 × 10 ¹⁶ cm ⁻³ to 1 × 10 ¹⁸ cm ⁻³ . The semiconductor device according to claim 1, wherein the n ⁻ type drift region has an n type dopant concentration of 1 × 10 ¹³ cm ^{−3 to} 5 × 10 ¹⁴ cm ⁻³ . The semiconductor device according to claim 1, wherein the p ⁺ -type collector region has a p-type dopant concentration of 1 × 10 ¹⁵ cm ⁻³ to 2 × 10 ¹⁹ cm ⁻³ . A contact portion dug down from the surface of the semiconductor substrate is formed in the p-type base region,
The p ⁺ type base contact region is formed on a bottom surface of the contact portion.
10. The semiconductor device according to any one of claims 9 to 9. The semiconductor device according to claim 1, wherein the p-type floating region and the gate electrode are formed so as to be separated from each other and not to overlap.

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