US20210126117A1 - Trench-type insulated gate semiconductor device including an emitter trench and an overlapped floating region - Google Patents
Trench-type insulated gate semiconductor device including an emitter trench and an overlapped floating region Download PDFInfo
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- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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Definitions
- the present invention relates to a semiconductor device including IGBTs (Insulated Gate Bipolar Transistors).
- IGBTs Insulated Gate Bipolar Transistors
- a trench-type IGBT having a high saturation voltage V CE (sat) and short-circuit capacity between the collector and emitter has a p-type floating layer.
- the p-type floating layer is generally formed by the same step as that for a p-type base layer.
- the p-type floating layer therefore has the same depth as the p-type base layer.
- FIG. 1 is a schematic sectional view of a semiconductor device according to a first embodiment of the present invention.
- FIG. 2 is a perspective view for explaining an internal structure of the semiconductor device of FIG. 1 .
- FIG. 3A is a view for explaining a manufacturing step of the semiconductor device of FIG. 1 .
- FIG. 3B is a view showing a following step of FIG. 3A .
- FIG. 3C is a view showing a following step of FIG. 3B .
- FIG. 3D is a view showing a following step of FIG. 3C .
- FIG. 3E is a view showing a following step of FIG. 3D .
- FIG. 3F is a view showing a following step of FIG. 3E .
- FIG. 3G is a view showing a following step of FIG. 3F .
- FIG. 3H is a view showing a following step of FIG. 3F .
- FIG. 3I is a view showing a following step of FIG. 3F .
- FIG. 4 is a schematic sectional view of a semiconductor device according to a second embodiment of the present invention.
- FIG. 5A and FIG. 5B are views for explaining an internal structure of the semiconductor device of FIG. 4 , wherein FIG. 5A shows a perspective view, and FIG. 5B shows a plan view.
- FIG. 6 is a schematic sectional view of a semiconductor device according to a third embodiment of the present invention.
- FIG. 7 is an enlarged view of a part enclosed by a broken line of FIG. 6 .
- FIG. 8A is a view for explaining a manufacturing step of the semiconductor device of FIG. 7 .
- FIG. 8B is a view showing a following step of FIG. 8A .
- FIG. 8C is a view showing a following step of FIG. 8B .
- FIG. 8D is a view showing a following step of FIG. 8C .
- FIG. 8E is a view showing a following step of FIG. 8D .
- FIG. 8F is a view showing a following step of FIG. 8E .
- FIG. 8G is a view showing a following step of FIG. 8F .
- FIG. 8H is a view showing a following step of FIG. 8G .
- FIG. 8I is a view showing a following step of FIG. 8H .
- FIG. 8J is a view showing a following step of FIG. 8I .
- FIG. 8K is a view showing a following step of FIG. 8J .
- FIG. 9 is a schematic sectional view of a semiconductor device according to a fourth embodiment of the present invention.
- FIG. 10 is an enlarged view of a part enclosed by a broken line of FIG. 9 .
- FIG. 11 is a graph showing V CE -I Cf characteristics of devices.
- a semiconductor device of the present invention includes a semiconductor layer, a plurality of gate trenches formed in the semiconductor layer, a gate electrode filled via a gate insulating film in the plurality of gate trenches, an n + -type emitter region, a p-type base region, and an n ⁇ -type drift region disposed, lateral to each gate trench, in order in a depth direction of the gate trench from a front surface side of the semiconductor layer, a p + -type collector region disposed on a back surface side of the semiconductor layer with respect to the n ⁇ -type drift region, a plurality of emitter trenches formed between the plurality of gate trenches adjacent to each other, a buried electrode filled via an insulating film in the plurality of emitter trenches, electrically connected with the n + -type emitter region, and a p-type floating region formed between the plurality of emitter trenches, and the p-type floating region is formed deeper than the p-type base region,
- the p-type floating region (overlap portion) is formed up to a bottom portion of the emitter trench filled with the buried electrode (hereinafter, referred to as an “emitter junction trench”).
- a collector-emitter voltage to be loaded on the emitter junction trench at switching-off operation can thereby be relieved. Therefore, a device breakdown can be prevented against a steep voltage change (dv/dt).
- the channel length can also be reduced to suppress a rise in ON-voltage by appropriately designing the depth of the p-type base region.
- the p-type floating region may have a bottom portion that bulges to a back surface side of the semiconductor layer with respect to a bottom portion of the emitter trench.
- the emitter trench is preferably formed at the same depth as that of the gate trench.
- the emitter trench is formed by the same step as that for the gate trench, the manufacturing process can be simplified.
- the gate trenches may be disposed one pair each in a transverse direction along the front surface of the semiconductor layer, and the pair of gate trenches may be opposed in the transverse direction via the p-type base region that is common thereto.
- one of the pair of gate trenches may be disposed at an interval of 2 ⁇ m to 7 ⁇ m with respect to the other.
- the n + -type emitter region may have an n-type dopant concentration of 1 ⁇ 10 19 cm ⁇ 3 to 5 ⁇ 10 20 cm ⁇ 3 .
- the p-type base region may have a p-type dopant concentration of 1 ⁇ 10 16 cm ⁇ 3 to 1 ⁇ 10 18 cm ⁇ 3 .
- the n ⁇ -type drift region may have an n-type dopant concentration of 1 ⁇ 10 13 cm ⁇ 3 to 5 ⁇ 10 14 cm ⁇ 3 .
- the p + -type collector region may have a p-type dopant concentration of 1 ⁇ 10 15 cm ⁇ 3 to 2 ⁇ 10 19 cm ⁇ 3 .
- the n + -type emitter region preferably selectively has a pullout portion pulled out in a transverse direction along the front surface of the semiconductor layer from a side surface of the gate trench.
- the semiconductor device preferably includes a dummy trench formed spaced at a predetermined interval lateral to the gate trench so that the n + -type emitter region, the p-type base region, and the n ⁇ -type drift region are formed between the dummy trench and the gate trench, a buried insulating film being a buried insulating film filled in the dummy trench and having an upper surface on a bottom side of the dummy trench with respect to the front surface of the semiconductor layer, for selectively exposing as a contact region a part of the p-type base region at a part from the front surface to the upper surface in a side surface of the dummy trench, and a contact electrode filled in a region over the buried insulating film of the dummy trench, connected to the contact region on the side surface of the dummy trench.
- the side surface of the dummy trench can be effectively used as the contact region, a junction area of the contact electrode with respect to the p-type base region can be sufficiently secured. Because a plane area of the p-type base region can thereby be sacrificed, the interval between the gate trench and the dummy trench can be miniaturized to form a p-type base region more minute than the conventional p-type base region. Furthermore, because the dummy trench can be formed using the same mask as that for the gate trench, misalignment with respect to the gate trench does not occur. Moreover, alignment of the contact electrode, for which alignment with an area including a plane area of the dummy trench suffices, can thus be easily attained.
- V CE (sat) in a low-current range can hence be improved.
- the semiconductor device may further include a first buried electrode filled via an insulating film in a region under the buried insulating film of the dummy trench.
- the semiconductor device may have a trench unit including a pair of the dummy trenches and a gate trench sandwiched between the pair of dummy trenches.
- the dummy trench preferably serves also as the emitter trench as a result of the first buried electrode being electrically connected with the n + -type emitter region.
- the semiconductor device may have a trench unit including a pair of the gate trenches and a dummy trench sandwiched between the pair of gate trenches.
- the first buried electrode is preferably electrically connected with the gate electrode.
- the buried insulating film preferably has a thickness of 0.5 ⁇ m or more.
- FIG. 1 is a schematic sectional view of a semiconductor device 1 according to a first embodiment of the present invention.
- FIG. 2 is a perspective view for explaining an internal structure of the semiconductor device 1 of FIG. 1 .
- the semiconductor device 1 is a device including IGBTs, and includes a semiconductor substrate 2 as an example of a semiconductor layer of the present invention.
- the semiconductor substrate 2 may be, for example, an n′′-type silicon substrate having a thickness of 50 ⁇ m to 200 ⁇ m.
- the semiconductor substrate 2 has a structure in which a p + -type collector region 4 , an n-type buffer region 5 , and an n ⁇ -type drift region 6 are stacked in order from the side of its back surface 3 .
- the p + -type collector region 4 is exposed over the entire back surface 3 of the semiconductor substrate 2
- the n ⁇ -type drift region 6 is selectively exposed on a part of a front surface 7 of the semiconductor substrate 2 .
- a p-type dopant of the p + -type collector region 4 for example, B (boron), Al (aluminum), and others can be used (the same applies to the following).
- an n-type dopant of the n-type buffer region 5 and the n ⁇ -type drift region 6 for example, N (nitrogen), P (phosphorus), As (arsenic), and others can be used (the same applies to the following).
- the dopant concentration of the p + -type collector region 4 is, for example, 1 ⁇ 10 15 cm ⁇ 3 to 2 ⁇ 10 19 cm ⁇ 3 .
- the dopant concentration of the n-type buffer region 5 is, for example, 1 ⁇ 10 15 cm ⁇ 3 to 5 ⁇ 10 17 cm ⁇ 3
- the dopant concentration of the n ⁇ -type drift region 6 is 1 ⁇ 10 13 cm ⁇ 3 to 5 ⁇ 10 14 cm ⁇ 3 .
- a plurality of gate trenches 8 are formed on the side of the front surface 7 of the semiconductor substrate 2 .
- the plurality of gate trenches 8 are formed in, for example, a stripe form, and disposed as trench units 9 of one pair each in the transverse direction along the front surface 7 of the semiconductor substrate 2 .
- the pitch P 1 of mutually adjacent trench units 9 is, for example, 4 ⁇ m to 20 ⁇ m.
- the pitch P 2 of one gate trench 8 and the other gate trench 8 is, for example, 2 ⁇ m to 7 ⁇ m
- the interval L 1 is, for example, 1 ⁇ m to 6 ⁇ m.
- a p-type base region 10 is formed between a pair of gate trenches 8 .
- the p-type base region 10 is shared by one gate trench 8 and the other gate trench 8 .
- an interface between the p-type base region 10 and the n ⁇ -type drift region 6 is set in a central portion or upper portion of the gate trenches 8 , so that the p-type base region 10 is formed by diffusion at a relatively shallow position of the semiconductor substrate 2 .
- a contact trench 11 dug down from the front surface 7 of the semiconductor substrate 2 is formed.
- the contact trench 11 is formed with a fixed width along the longitudinal direction of the gate trench 8 .
- a p + -type base contact region 12 is formed on a bottom surface of the contact trench 11 .
- an n + -type emitter region 13 is formed in a front surface portion of the p-type base region 10 between the contact trench 11 and one and the other gate trenches 8 .
- the n + -type emitter regions 13 are formed one each on both side surfaces of the contact trench 11 , and are respectively exposed on side surfaces of the contact trench 11 .
- the dopant concentration of the p-type base region 10 is, for example, 1 ⁇ 10 16 cm ⁇ 3 to 1 ⁇ 10 18 cm ⁇ 3 .
- the dopant concentration of the p + -type base contact region 12 is, for example, 5 ⁇ 10 18 cm ⁇ 3 to 1 ⁇ 10 20 cm ⁇ 3 .
- the dopant concentration of the n + -type emitter region 13 is 1 ⁇ 10 19 cm ⁇ 3 to 5 ⁇ 10 20 cm ⁇ 3 .
- a plurality of (in FIG. 1 , two) emitter trenches 14 are formed between a pair of gate trenches 8 on the side of the front surface 7 of the semiconductor substrate 2 .
- the plurality of emitter trenches 14 are formed in, for example, a stripe form (parallel to the gate trenches 8 ), and disposed spaced at mutually equal intervals in the transverse direction along the front surface 7 of the semiconductor substrate 2 .
- the interval L 2 of mutually adjacent emitter trenches 14 is, for example, 3 ⁇ m or less, and preferably, 0.8 ⁇ m to 3 ⁇ m.
- the plurality of emitter trenches 14 are formed at the same depth as that of the gate trenches 8 . Because the emitter trenches 14 and the gate trenches 8 can thereby be formed by the same step, the manufacturing process can be simplified.
- a trench that is adjacent to the gate trench 8 (trench that is opposed to the gate trench 8 via no trench therewith) is disposed at an interval L 3 (distance between the side surface of the emitter trench 14 and the side surface of the gate trench 8 ) of 2 ⁇ m or less via the n ⁇ -type drift region 6 with the gate trench 8 . That is, between said emitter trench 14 and the gate trench 8 , the n ⁇ -type drift region 6 is interposed across the entire area in the depth direction.
- a p-type floating region 15 is formed in each section between the plurality of emitter trenches 14 .
- the p-type floating region 15 is a semiconductor region where a floating state is electrically maintained, and is separated from the gate trench 8 by the emitter trench 14 that is adjacent to the gate trench 8 .
- the p-type floating region 15 is, in the present embodiment, formed deeper than the p-type base region 10 .
- the p-type floating region 15 has a bottom portion 16 that bulges to the side of the back surface 3 of the semiconductor substrate 2 with respect to a bottom portion of the emitter trenches 14 and an overlap portion 17 that goes around to the lower side of the emitter trench 14 adjacent to the gate trench 8 .
- the overlap portion 17 has an end portion 18 positioned on a side closer to the gate trench 8 with respect to the center in the width direction of said emitter trench 14 .
- the end portion 18 is preferably not projecting to the side of the gate trench 8 with respect to the emitter trench 14 .
- the dopant concentration of the p-type floating region 15 is, for example, 5 ⁇ 10 15 cm ⁇ 3 to 1 ⁇ 10 18 cm ⁇ 3 .
- gate electrodes 20 and buried electrodes 21 are filled, respectively, via an insulating film 19 (for example, silicon oxide (SiO 2 )).
- the gate electrodes 20 and the buried electrodes 21 are made of, for example, a conductive material such as polysilicon.
- the insulating film 19 is integrally formed along inner surfaces of the gate trenches 8 , the front surface 7 of the semiconductor substrate 2 , and inner surfaces of the emitter trenches 14 .
- the part of the insulating film 19 in the gate trench 8 serves as a gate insulating film 22 .
- a plurality of buried electrodes 21 of the emitter trenches 14 are electrically connected to an emitter electrode 25 to be described later.
- an interlayer film 23 made of, for example, an insulating material such as boron phosphorus silicate glass (BPSG) or silicon oxide (SiO 2 ) is stacked.
- BPSG boron phosphorus silicate glass
- SiO 2 silicon oxide
- an emitter electrode 25 is stacked on the interlayer film 23 .
- the emitter electrode 25 enters the contact trench 11 , and is connected to the n + -type emitter region 13 on the side surface of the contact trench 11 . Also, on the bottom surface of the contact trench 11 , the emitter electrode 25 is connected to the p-type base region 10 via the p + -type base contact region 12 .
- FIG. 3 A to FIG. 3I are views for explaining the manufacturing process of the semiconductor device 1 of FIG. 1 in the order of steps.
- a mask 28 is formed on the front surface 7 of the n ⁇ -type semiconductor substrate 2 (n ⁇ -type drift region 6 ).
- the mask 28 there is formed an opening to selectively expose a region that needs to be formed into the p-type floating region 15 in the front surface 7 .
- a p-type dopant is ion-implanted into the front surface 7 of the semiconductor substrate 2 .
- An ion-implanted region 26 is thereby formed.
- the gate trenches 8 and the emitter trenches 14 are simultaneously formed.
- a sacrificial oxide film 27 is formed on the entire area of the front surface including the inner surfaces of the gate trenches 8 and the emitter trenches 14 . Then, by annealing the semiconductor substrate 2 covered with the sacrificial oxide film 27 , the p-type dopant in the ion-implanted region 26 is diffused (driven in). The annealing treatment is performed on a condition that the p-type dopant goes around to the lower side of the emitter trench 14 . The p-type floating region 15 is thereby formed. In this case, because the semiconductor substrate 2 is covered with the sacrificial oxide film 27 , ion seeping from the front surface of the substrate can be prevented, so that the p-type dopant can be efficiently diffused.
- the sacrificial oxide film 27 is stripped.
- the insulating film 19 (gate insulating film 22 ) is formed on the entire area of the front surface including the inner surfaces of the gate trenches 8 and the emitter trenches 14 .
- an electrode material such as polysilicon is filled in the gate trenches 8 and the emitter trenches 14 .
- the gate electrodes 20 and the buried electrodes 21 are thereby simultaneously formed.
- the p-type base regions 10 and the n + -type emitter regions 13 are formed in order.
- the interlayer film 23 is formed.
- the semiconductor substrate 2 exposed from said contact hole 24 is selectively etched.
- the contact trench 11 is thereby formed.
- the p + -type base contact regions 12 are formed.
- n-type and p-type dopants being selectively ion-implanted and diffused into the back surface 3 of the semiconductor substrate 2 after the emitter electrode 24 and the like being formed on the side of the front surface 7 of the semiconductor substrate 2 , the n-type buffer region 5 and the p + -type collector region 4 are formed in order.
- FIG. 3A to FIG. 3I merely represent a part of the manufacturing process of the semiconductor device 1 , and said manufacturing process may include steps not shown by FIG. 3A to FIG. 3I .
- the p-type floating region 15 (overlap portion 17 ) is formed up to a bottom portion of the emitter trench 14 filled with the buried electrode 21 (hereinafter, referred to as an “emitter junction trench”), a collector-emitter voltage to be loaded on the emitter junction trench at switching-off operation can be relieved. Therefore, a device breakdown can be prevented against a steep voltage change (dv/dt).
- the channel length (length in the depth direction of the gate trench 8 ) can also be reduced to suppress a rise in ON-voltage by appropriately designing the depth of the p-type base region 10 .
- the gate trench 8 filled with the gate electrode 20 (hereinafter, referred to as a “gate junction trench”) is separated from the p-type floating region 15 by the emitter junction trench.
- the p-type floating region 15 and the gate junction trench can thereby be prevented from joining.
- a stray capacitance between the gate junction trench and the p-type floating region 15 can therefore be eliminated.
- the n ⁇ -type drift region 6 which the gate junction trench joins across the entire area in the depth direction is to be grounded together with the p + -type collector region 4 . Therefore, at switching operation, a capacitance change between the gate junction trench and the n ⁇ -type drift region 6 is stabilized, so that noise does not easily occur. As a result thereof, generation of noise and switching loss at switching operation can be reduced.
- the interval L 3 between the emitter junction trench and the gate junction trench is 2 ⁇ m or less, withstand voltage can also be satisfactorily maintained.
- the side surface of the contact trench 11 can be effectively used as a region for contact with the n + -type emitter region 13 , a junction area of the emitter electrode 25 with respect to the n + -type emitter region 13 can be sufficiently secured. Because a plane area of the n + -type emitter region 13 can thereby be sacrificed, the interval L 1 between one and the other gate trenches 8 of a pair of gate trenches 8 can be miniaturized to form a p-type base region 10 more minute than the conventional p-type base region. As a result of miniaturization of the gate trench 8 , a trade-off relationship between the short-circuit capacity and ON-voltage of the device can be improved, so that a charge enhancement effect can be increased. V CE (sat) in a low-current range can hence be improved.
- FIG. 4 is a schematic sectional view of a semiconductor device 31 according to a second embodiment of the present invention.
- FIG. 5A and FIG. 5B are views for explaining an internal structure of the semiconductor device 31 of FIG. 4 , wherein FIG. 5A shows a perspective view, and FIG. 5B shows a plan view.
- FIG. 4 and FIG. 5A and FIG. 5B parts corresponding to the respective portions shown in FIG. 1 described above will be denoted by the same reference signs.
- the gate trenches 8 are formed as trench units 9 of one pair each, and a common p-type base region 10 is formed between one and the other gate trenches 8 .
- the semiconductor device 31 of the second embodiment includes a plurality of gate trenches 33 formed as trench units 32 of one each in the transverse direction along the front surface 7 of the semiconductor substrate 2 , p-type base regions 34 formed on both sides of each gate trench 33 (regions between the same and the emitter trenches 14 ), and n + -type emitter regions 35 formed in front surface portions of the respective p-type base regions 34 .
- the n + -type emitter regions 35 are formed one each along both side surfaces of the gate trench 33 , and are exposed on the front surface 7 of the semiconductor substrate 2 .
- a p + -type base contact region 37 is formed lateral to the n + -type emitter region 35 (on the opposite side to the gate trench 33 ).
- the dopant concentration of the p + -type base contact region 37 is, for example, 5 ⁇ 10′′cm ⁇ 3 to 1 ⁇ 10 20 cm ⁇ 3 .
- the n + -type emitter region 35 selectively has a pullout portion 38 pulled out in the transverse direction along the front surface 7 of the semiconductor substrate 2 from the side surface of the gate trench 33 .
- the pullout portion 38 is, for example, disposed spaced at fixed intervals along the longitudinal direction of the gate trench 33 .
- the pullout portions 38 of the respective n + -type emitter regions 35 may be, as shown in FIG.
- end portions of one pullout portion 38 and end portions of the other pullout portion 38 may be disposed alternately along the longitudinal direction of the gate trench 33 (not shown).
- a part adjacent to the pullout region 38 in the p + -type base contact region 37 serves as a constricted portion 39 selectively having a narrower width than that of the remaining part.
- a contact hole 36 is formed to selectively expose the p + -type base contact region 37 and the n + -type emitter region 35 .
- the n + -type emitter region 35 is selectively exposed at the pullout portion 38 from the contact hole 36 .
- the emitter electrode 25 is connected to the p + -type base contact region 37 and the n + -type emitter region 35 via the contact hole 36 .
- FIG. 6 is a schematic sectional view of a semiconductor device 101 according to a third embodiment of the present invention.
- FIG. 7 is an enlarged view of a part enclosed by a broken line of FIG. 6 .
- the semiconductor device 101 is a device including IGBTs, and includes a semiconductor substrate 102 as an example of a semiconductor layer of the present invention.
- the semiconductor substrate 102 may be, for example, an n ⁇ -type silicon substrate having a thickness of 50 ⁇ m to 200 ⁇ m.
- the semiconductor substrate 102 has a structure in which a p + -type collector region 104 , an n-type buffer region 105 , and an n ⁇ -type drift region 106 are stacked in order from the side of its back surface 103 .
- the p + -type collector region 104 is exposed over the entire back surface 103 of the semiconductor substrate 102
- the n ⁇ -type drift region 106 is selectively exposed on a part of a front surface 107 of the semiconductor substrate 102 .
- a p-type dopant of the p + -type collector region 104 for example, B (boron), Al (aluminum), and others can be used (the same applies to the following).
- an n-type dopant of the n-type buffer region 105 and the n ⁇ -type drift region 106 for example, N (nitrogen), P (phosphorus), As (arsenic), and others can be used (the same applies to the following).
- the dopant concentration of the p + -type collector region 104 is, for example, 1 ⁇ 10 15 cm ⁇ 3 to 2 ⁇ 10 19 cm ⁇ 3 .
- the dopant concentration of the n-type buffer region 105 is, for example, 1 ⁇ 10 15 cm ⁇ 3 to 5 ⁇ 10 17 cm ⁇ 3
- the dopant concentration of the n ⁇ -type drift region 106 is 1 ⁇ 10 13 cm ⁇ 3 to 5 ⁇ 10 14 cm ⁇ 3 .
- a plurality of gate trenches 108 and a plurality of dummy trenches 109 are formed adjacent to each other.
- a trench unit 110 including a pair of dummy trenches 109 and a gate trench 108 sandwiched between the pair of dummy trenches 109 is disposed in plural numbers spaced at intervals in the transverse direction along the front surface 107 of the semiconductor substrate 102 .
- the gate trenches 108 and the dummy trenches 109 are thereby formed in a stripe form as a whole.
- the pitch P 1 of mutually adjacent trench units 110 is, for example, 2 ⁇ m to 7 ⁇ m. Also, in each trench unit 110 , the intervals L 1 between the gate trench 108 and the dummy trenches 109 on both sides thereof (distances between side surfaces of the gate trench 108 and side surfaces of the dummy trenches 109 ) are preferably respectively 2 ⁇ m or less.
- a p-type base region 111 is formed, and further, an n + -type emitter region 112 and a p + -type base contact region 113 are formed in a front surface portion of the p-type base region 111 (refer to FIG. 7 ).
- an interface between the p-type base region 111 and the n ⁇ -type drift region 106 is set in a central portion or upper portion of the gate trench 108 , and the p-type base region 111 is formed by diffusion at a relatively shallow position of the semiconductor substrate 102 .
- n + -type emitter region 112 and the p + -type base contact region 113 are disposed adjacent to each other in the region between the gate trench 108 and the dummy trench 109 .
- n + -type emitter regions 112 are formed one each along both side surfaces 114 of the gate trench 108
- p + -type base contact regions 113 are formed one each along side surfaces 115 of the respective dummy trenches 109 .
- the n + -type emitter regions 112 are thereby exposed on the front surface 107 of the semiconductor substrate 102 and the side surfaces 114 of the gate trenches 108 .
- the p + -type base contact regions 113 are exposed on the front surface 107 of the semiconductor substrate 102 and the side surfaces 115 of the dummy trenches 109 .
- the dopant concentration of the p-type base region 111 is, for example, 1 ⁇ 10 16 cm ⁇ 3 to 1 ⁇ 10 18 cm ⁇ 3 .
- the dopant concentration of the n + -type emitter region 112 is 1 ⁇ 10 19 cm ⁇ 3 to 5 ⁇ 10 20 cm ⁇ 3 .
- the dopant concentration of the p + -type base contact region 113 is, for example, 5 ⁇ 10 18 cm ⁇ 3 to 1 ⁇ 10 20 cm ⁇ 3 .
- a plurality of (in FIG. 6 , three) emitter trenches 116 are formed between trench units 110 adjacent on the side of the front surface 107 of the semiconductor substrate 102 .
- the plurality of emitter trenches 116 are formed in, for example, a stripe form (parallel to the gate trenches 108 and the dummy trenches 109 ), and disposed spaced at mutually equal intervals in the transverse direction along the front surface 107 of the semiconductor substrate 102 .
- the interval L 2 of mutually adjacent emitter trenches 116 is, for example, 3 ⁇ m or less, and preferably, 0.8 ⁇ m to 3 ⁇ m.
- the plurality of emitter trenches 116 are formed at the same depth as that of the gate trenches 108 and the dummy trenches 109 . Because the emitter trenches 116 can thereby be formed by the same step as that for the gate trenches 108 and the dummy trenches 109 , the manufacturing process can be simplified.
- a trench that is adjacent to the dummy trench 109 (trench that is opposed to the dummy trench 109 via no trench therewith) is disposed at an interval L 3 (distance between the side surface of the emitter trench 116 and the side surface of the dummy trench 109 ) of 0.5 ⁇ m to 20 ⁇ m with the dummy trench 109 .
- a p-type floating region 117 is formed in the semiconductor substrate 102 .
- the p-type floating region 117 spreads over a region sandwiched by the dummy trenches 109 of mutually adjacent trench units 110 , opposed via the emitter trenches 116 .
- the p-type floating region 117 is a semiconductor region where a floating state is electrically maintained, and is separated from the gate trench 108 by the dummy trench 109 that is adjacent to the gate trench 108 .
- the p-type floating region 117 is, in the present embodiment, formed deeper than the p-type base region 111 .
- the p-type floating region 117 has a bottom portion 118 that bulges to the side of the back surface 103 of the semiconductor substrate 102 with respect to a bottom portion of the emitter trenches 116 and an overlap portion 119 that goes around to the lower side of the dummy trench 109 .
- the overlap portion 119 has an end portion 120 positioned on a side closer to the gate trench 108 with respect to the center in the width direction of said dummy trench 109 .
- the end portion 120 is preferably not projecting to the side of the gate trench 108 with respect to the emitter trench 116 .
- the dopant concentration of the p-type floating region 117 is, for example, 5 ⁇ 10 15 cm ⁇ 3 to 1 ⁇ 10 18 cm ⁇ 3 .
- gate electrodes 122 , first buried electrodes 123 , and second buried electrodes 124 are filled, respectively, via an insulating film 121 (for example, silicon oxide (SiO 2 )).
- the gate electrodes 122 , the first buried electrodes 123 , and the second buried electrodes 124 are made of, for example, a conductive material such as polysilicon.
- the insulating film 121 is integrally formed along inner surfaces of the gate trenches 108 , inner surfaces of the dummy trenches 109 , the front surface 107 of the semiconductor substrate 102 , and inner surfaces of the emitter trenches 116 .
- the part of the insulating film 121 in the gate trench 108 serves as a gate insulating film 125 .
- the first buried electrodes 123 and the second buried electrodes 124 are electrically connected to an emitter electrode 132 to be described later.
- the gate electrode 122 and the second buried electrode 124 fill back their respective trenches 108 and 116 up to the opening ends, whereas the first buried electrode 123 fills back the dummy trench 109 halfway in the depth direction thereof.
- a space without an electrode is thereby formed in a region over the first buried electrode 123 .
- a buried insulating film 126 is filled in the dummy trench 109 so as to fill back the space up to the opening end.
- the buried insulating film 126 is made of, for example, an insulating material such as boron phosphorus silicate glass (BPSG) or silicon oxide (SiO 2 ), and has a thickness of 0.5 ⁇ m or more.
- BPSG boron phosphorus silicate glass
- SiO 2 silicon oxide
- a removal portion 127 is selectively formed to expose the p + -type base contact region 113 on the side surface 115 of the dummy trench 109 .
- the buried insulating film 126 selectively has an upper surface 128 that is at a position lower than that of the front surface 107 of the semiconductor substrate 102 so as to be continuous from the side surface 115 of the dummy trench 109 , and the p + -type base contact region 113 is exposed in a region of the side surface 115 of the dummy trench 109 between the upper surface 128 and the front surface 107 .
- an interlayer film 129 made of, for example, an insulating material such as boron phosphorus silicate glass (BPSG) or silicon oxide (SiO 2 ) is stacked.
- the interlayer film 129 is formed integrally with the buried insulating film 126 .
- a contact hole 130 is formed extending across the front surface 107 of the semiconductor substrate 102 and the opening end of the dummy trench 109 .
- the contact hole 130 exposes the n + -type emitter region 112 and the p + -type base contact region 113 at the front surface 107 of the semiconductor substrate 102 , and exposes the p + -type base contact region 113 at the side surface 115 (removal portion 127 ) of the dummy trench 109 . That is, the p + -type base contact region 113 is exposed in a corner portion 131 of the dummy trench 109 defined by intersection of the front surface 107 and the side surface 115 .
- n + -type emitter region 112 may selectively have a pullout portion pulled out in the transverse direction along the front surface 107 of the semiconductor substrate 102 from the side surface 114 of the gate trench 108 , and only the pullout portion may be selectively exposed from the contact hole 130 .
- an emitter electrode 132 as an example of a contact electrode of the present invention is stacked.
- the emitter electrode 132 enters the contact hole 130 , and is connected to the n + -type emitter region 112 on the front surface 107 of the semiconductor substrate 102 , and is connected to the p + -type base contact region 113 in the corner portion 131 of the dummy trench 109 .
- FIG. 8A to FIG. 8K are views for explaining the manufacturing process of the semiconductor device 101 of FIG. 6 and the FIG. 7 in the order of steps.
- FIG. 8A to FIG. 8F show sections corresponding to FIG. 6
- FIG. 8G to FIG. 8K show sections corresponding to FIG. 7 .
- a mask 160 is formed on the front surface 107 of the n ⁇ -type semiconductor substrate 102 (n ⁇ -type drift region 106 ).
- the mask 160 there is formed an opening to selectively expose a region that needs to be formed into the p-type floating region 117 in the front surface 107 .
- a p-type dopant is ion-implanted into the front surface 107 of the semiconductor substrate 102 .
- An ion-implanted region 161 is thereby formed.
- the gate trenches 108 , the dummy trenches 109 , and the emitter trenches 116 are simultaneously formed.
- a sacrificial oxide film 162 is formed on the entire area of the front surface including the inner surfaces of the gate trenches 108 , the dummy trenches 109 , and the emitter trenches 116 .
- the p-type dopant in the ion-implanted region 161 is diffused (driven in).
- the annealing treatment is performed on a condition that the p-type dopant goes around to the lower side of the dummy trench 109 .
- the p-type floating region 117 is thereby formed.
- the semiconductor substrate 102 is covered with the sacrificial oxide film 162 , ion seeping from the front surface of the substrate can be prevented, so that the p-type dopant can be efficiently diffused.
- the sacrificial oxide film 162 is stripped.
- the insulating film 121 (gate insulating film 125 ) is formed on the entire area of the front surface including the inner surfaces of the gate trenches 108 , the dummy trenches 109 , and the emitter trenches 116 .
- an electrode material such as polysilicon is filled in the gate trenches 108 , the dummy trenches 109 , and the emitter trenches 116 .
- the gate electrodes 122 , the first buried electrodes 123 , and the second buried electrodes 124 are thereby simultaneously formed.
- the p-type base regions 111 and the n + -type emitter regions 112 are formed in order.
- the filled states of the gate electrodes 122 and the second buried electrodes 124 are kept maintained, while only the first buried electrodes 123 are selectively dug down.
- insulating material such as boron phosphorus silicate glass (BPSG) or silicon oxide (SiO 2 )
- BPSG boron phosphorus silicate glass
- SiO 2 silicon oxide
- the contact holes 130 and the removal portions 127 are simultaneously formed.
- a p-type dopant is selectively ion-implanted and diffused into the front surface 107 of the semiconductor substrate 102 exposed in the contact holes 130 .
- the p + -type base contact regions 113 are thereby formed.
- n-type and p-type dopants being selectively ion-implanted and diffused into the back surface 103 of the semiconductor substrate 102 after the emitter electrode 132 and the like being formed on the side of the front surface 107 of the semiconductor substrate 102 , the n-type buffer region 105 and the p + -type collector region 104 are formed in order.
- FIG. 8A to FIG. 8K merely represent a part of the manufacturing process of the semiconductor device 101 , and said manufacturing process may include steps not shown by FIG. 8A to FIG. 8K .
- a junction area of the emitter electrode 132 with respect to the p-type base region 111 can be sufficiently secured by both surfaces of the front surface 107 of the semiconductor substrate 102 and the side surface 115 of the dummy trench 109 . Because a plane area of the p-type base region 111 can thereby be sacrificed, the interval L 1 between the gate trench 108 and the dummy trench 109 can be miniaturized to form a p-type base region 111 more minute than the conventional p-type base region.
- the dummy trenches 109 can be formed using the same mask as that for the gate trenches 108 , misalignment with respect to the gate trenches 108 does not occur. Moreover, alignment of the emitter electrode 132 , for which alignment with an area including a plane area of the dummy trenches 109 suffices, can thus be easily attained.
- the gate trenches 108 , the dummy trenches 109 , and the emitter trenches 116 are simultaneously formed ( FIG. 8B ).
- the gate electrodes 122 , the first buried electrodes 123 , and the second buried electrodes 124 are formed ( FIG. 8F ).
- a mask to selectively expose the dummy trenches 109 is formed on the semiconductor substrate 102 , and via the mask, an upper portion of the polysilicon in the dummy trenches 109 is selectively removed by etching.
- the interlayer film 129 is formed by depositing on the semiconductor substrate 102 an insulating material such as BPSG by, for example, a CVD method ( FIG. 8I ). A part of the insulating material enters into the dummy trenches 109 as the buried insulating film 126 . Next, a mask to form the contact holes 130 is aligned with respect to the semiconductor substrate 102 .
- end portions of the contact holes 130 may cover the dummy trenches 109 , the alignment can be attained in a wide area including the front surface 107 of the semiconductor substrate 102 and a plane area of the dummy trenches 109 . Then, via said mask, the interlayer film 129 and the buried insulating film 126 are continuously etched. The contact holes 130 and the removal portions 127 are thereby simultaneously formed ( FIG. 8J ).
- the p + -type base contact regions 113 can be reliably formed in the corner portions 131 of the dummy trenches 109 ( FIG. 8K ). Furthermore, because the contact holes 130 can be formed relatively wide, a part of the emitter electrode 132 using aluminum (Al) or the like can be used as plugs, even without using plugs excellent in filling ability, such as tungsten (W).
- the gate trench 108 filled with the gate electrode 122 (hereinafter, referred to as a “gate junction trench”) is separated from the p-type floating region 117 by the dummy trench 109 filled with the first buried electrode 123 connected to the n + -type emitter region 112 (hereinafter, referred to as an “emitter junction trench”).
- the p-type floating region 117 and the gate junction trench can thereby be prevented from joining. A stray capacitance between the gate junction trench and the p-type floating region 117 can therefore be eliminated.
- the n ⁇ -type drift region 106 which the gate junction trench joins across the depth direction is to be grounded together with the p + -type collector region 104 . Therefore, at switching operation, a capacitance change between the gate junction trench and the n ⁇ -type drift region 106 is stabilized, so that noise does not easily occur. As a result thereof, generation of noise and switching loss at switching operation can be reduced.
- the interval L 1 between the emitter junction trench and the gate junction trench is 2 ⁇ m or less, withstand voltage can also be satisfactorily maintained.
- the p-type floating region 117 (overlap portion 119 ) is formed up to a bottom portion of the emitter junction trench, a collector-emitter voltage to be loaded on the emitter junction trench at switching-off operation can be relieved. Therefore, a device breakdown can be prevented against a steep voltage change (dv/dt).
- the channel length (length in the depth direction of the gate trench 108 ) can also be reduced to suppress a rise in ON-voltage by appropriately designing the depth of the p-type base region 111 .
- FIG. 9 is a schematic sectional view of a semiconductor device 141 according to a fourth embodiment of the present invention.
- FIG. 10 is an enlarged view of a part enclosed by a broken line of FIG. 9 .
- parts corresponding to the respective portions shown in FIG. 6 and FIG. 7 described above will be denoted by the same reference signs.
- the trench unit 110 includes a pair of dummy trenches 109 and a gate trench 108 sandwiched between the pair of dummy trenches 109 .
- the semiconductor device 141 of the fourth embodiment has a trench unit 144 including a pair of gate trenches 142 and a dummy trench 143 sandwiched between the pair of gate trenches 142 .
- the interval L 3 between the gate trench 142 and the emitter trench 116 is preferably 2 ⁇ m or less.
- a p-type base region 145 is formed, and further, an n + -type emitter region 146 and a p + -type base contact region 147 are formed in a front surface portion of the p-type base region 145 (refer to FIG. 10 ).
- an interface between the p-type base region 145 and the n ⁇ -type drift region 106 is set in a central portion or upper portion of the gate trench 142 , and the p-type base region 145 is formed by diffusion at a relatively shallow position of the semiconductor substrate 102 .
- n + -type emitter region 146 and the p + -type base contact region 147 are disposed adjacent to each other in the region between the gate trench 142 and the dummy trench 143 .
- n + -type emitter regions 146 are formed one each along side surfaces 148 of the respective gate trenches 142
- p + -type base contact regions 147 are formed one each along both side surfaces 149 of the dummy trench 143 .
- the n + -type emitter regions 146 are thereby exposed on the front surface 107 of the semiconductor substrate 102 and the side surfaces 148 of the gate trenches 142 .
- the p + -type base contact regions 147 are exposed on the front surface 107 of the semiconductor substrate 102 and the side surfaces 149 of the dummy trenches 143 .
- a p-type floating region 150 is formed in the semiconductor substrate 102 .
- the p-type floating region 150 spreads over each section between the plurality of emitter trenches 116 .
- the p-type floating region 150 is a semiconductor region where a floating state is electrically maintained, and is separated from the gate trench 142 by the emitter trench 116 that is adjacent to the gate trench 142 .
- the p-type floating region 150 is, in the present embodiment, formed deeper than the p-type base region 145 .
- the p-type floating region 150 has a bottom portion 151 that bulges to the side of the back surface 103 of the semiconductor substrate 102 with respect to a bottom portion of the emitter trenches 116 and an overlap portion 152 that goes around to the lower side of the emitter trench 116 adjacent to the gate trench 142 .
- the overlap portion 152 has an end portion 153 positioned on a side closer to the gate trench 142 with respect to the center in the width direction of said emitter trench 116 .
- the end portion 153 is preferably not projecting to the side of the gate trench 142 with respect to the emitter trench 116 .
- Such a p-type floating region 150 can be formed, for example, in the same manner as the foregoing p-type floating region 117 .
- a first buried electrode 154 is filled via an insulating film 121 .
- the first buried electrode 154 is made of, for example, a conductive material such as polysilicon, and is electrically connected to the gate electrode 122 .
- the first buried electrode 154 fills back the dummy trench 143 halfway in the depth direction thereof.
- a space without an electrode is thereby formed in a region over the first buried electrode 154 .
- a buried insulating film 155 is filled in the dummy trench 143 so as to fill back the space up to the opening end.
- the buried insulating film 155 is made of, for example, an insulating material such as boron phosphorus silicate glass (BPSG) or silicon oxide (SiO 2 ), and has a thickness of 0.5 ⁇ m or more.
- BPSG boron phosphorus silicate glass
- SiO 2 silicon oxide
- a removal portion 156 is selectively formed to expose the p + -type base contact regions 147 on both side surfaces 149 of the dummy trench 143 .
- the buried insulating film 155 selectively has an upper surface 157 that is at a position lower than that of the front surface 107 of the semiconductor substrate 102 so as to be continuous from both side surfaces 149 of the dummy trench 143 , and the p + -type base contact regions 147 are exposed in a region of both side surfaces 149 of the dummy trench 143 between the upper surface 157 and the front surface 107 .
- a contact hole 158 is formed extending across the p-type base regions 145 opposed across the dummy trench 143 .
- the contact hole 158 exposes the n + -type emitter regions 146 and the p + -type base contact regions 147 at the front surface 107 of the semiconductor substrate 102 , and exposes the p + -type base contact regions 147 at both side surfaces 149 (removal portion 156 ) of the dummy trench 143 . That is, the p + -type base contact regions 147 are exposed in both corner portions 159 of the dummy trench 143 defined by intersection of the front surface 107 and the side surfaces 149 .
- n + -type emitter region 146 may selectively have a pullout portion pulled out in the transverse direction along the front surface 107 of the semiconductor substrate 102 from the side surface 148 of the gate trench 142 , and only the pullout portion may be selectively exposed from the contact hole 158 .
- the emitter electrode 132 enters the contact hole 158 , and is connected to the n + -type emitter regions 146 on the front surface 107 of the semiconductor substrate 102 , and is connected to the p + -type base contact regions 147 in both corner portions 159 of the dummy trench 143 .
- a semiconductor device of the present invention may include elements other than IGBTs (for example, MOSFETs, diodes, and the like) in a region different from a forming region of IGBTs.
- a semiconductor device including a semiconductor layer, a gate trench formed in the semiconductor layer, a gate electrode filled via a gate insulating film in the gate trench, a dummy trench formed spaced at a predetermined interval lateral to the gate trench, an n + -type emitter region, a p-type base region, and an n ⁇ -type drift region disposed, in a region between the gate trench and the dummy trench, in order in a depth direction of the gate trench from a front surface side of the semiconductor layer, a p + -type collector region disposed on a back surface side of the semiconductor layer with respect to the n ⁇ -type drift region, a buried insulating film being a buried insulating film filled in the dummy trench and having an upper surface at a bottom side of the dummy trench with respect to the front surface of the semiconductor layer, for selectively exposing as a contact region a part of the p-type base region at a part from the front surface to the upper surface
- the side surface of the dummy trench can be effectively used as the contact region, a junction area of the contact electrode with respect to the p-type base region can be sufficiently secured. Because a plane area of the p-type base region can thereby be sacrificed, the interval between the gate trench and the dummy trench can be miniaturized to form a p-type base region more minute than the conventional p-type base region. Furthermore, because the dummy trench can be formed using the same mask as that for the gate trench, misalignment with respect to the gate trench does not occur. Moreover, alignment of the contact electrode, for which alignment with an area including a plane area of the dummy trench suffices, can thus be easily attained.
- V CE (sat) in a low-current range can hence be improved.
- (Section 5) The semiconductor device according to section 4, wherein the trench unit is formed in plural numbers in a transverse direction along the front surface of the semiconductor layer, and the semiconductor device further includes a plurality of emitter trenches formed between the trench units adjacent to each other, a second buried electrode filled via an insulating film in the emitter trench, electrically connected with the n + -type emitter region, and a p-type floating region formed between the dummy trench of the trench unit and the dummy trench of the trench unit next thereto.
- the p-type floating region (overlap portion) is formed up to a bottom portion of the dummy trench filled with the first buried electrode connected to the n + -type emitter region (hereinafter, referred to as an “emitter junction trench”), a collector-emitter voltage to be loaded on the emitter junction trench at switching-off operation can be relieved. Therefore, a device breakdown can be prevented against a steep voltage change (dv/dt).
- withstand voltage can be increased by the p-type floating region that is deeper than the p-type base region, while the p-type base region may be shallow, a rise in ON-voltage can also be suppressed by appropriately designing the depth of the p-type base region.
- a collector-emitter voltage to be applied to the emitter junction trench can be more satisfactorily relieved.
- the p-type floating region (overlap portion) is formed up to a bottom portion of the emitter trench filled with the second buried electrode connected to the n + -type emitter region (hereinafter, referred to as an “emitter junction trench”)
- the p-type floating region overlap portion
- the second buried electrode connected to the n + -type emitter region hereinafter, referred to as an “emitter junction trench”
- a collector-emitter voltage to be loaded on the emitter junction trench at switching-off operation can be relieved. Therefore, a device breakdown can be prevented against a steep voltage change (dv/dt).
- withstand voltage can be increased by the p-type floating region that is deeper than the p-type base region, while the p-type base region may be shallow, a rise in ON-voltage can also be suppressed by appropriately designing the depth of the p-type base region.
- a collector-emitter voltage to be applied to the emitter junction trench can be more satisfactorily relieved.
- V CE -I Cf characteristics of four types of devices that are mutually different in the interval L 1 between the gate trench 108 and the dummy trench 109 were examined, regarding the structure of the semiconductor device 101 shown in FIG. 6 , in order to confirm how the effect to improve the trade-off relationship between the short-circuit capacity and ON-voltage (V CE ) changes depending on said interval L 1 .
- FIG. 11 it could be confirmed that the narrower the trench interval L 1 , the lower V CE (sat) at rising and the lower steady loss (refer to the lower right enlarged view of FIG. 11 ). Also, it could be confirmed that in a high-current range of I Cf , the saturation current density has been lowered by trench miniaturization (a reduction in volume of the p-type base region 111 ), and the short-circuit capacity has been increased.
Abstract
Description
- This is a Continuation of U.S. application Ser. No. 16/050,416, filed on Jul. 31, 2018 (Atty. Dkt. No. ROHM61-34384), which is a Continuation of U.S. application Ser. No. 15/378,016, filed on Dec. 13, 2016, and allowed on Apr. 30, 2018, which was a Continuation of U.S. application Ser. No. 13/969,697, filed on Aug. 19, 2013 (issued on Jan. 10, 2017, as a U.S. Pat. No. 9,543,421), which claimed the benefit of priority of Japanese application No. 2012-182170, filed on Aug. 21, 2012, Japanese application No. 2012-182169, filed on Aug. 21, 2012, and Japanese application No. 2013-167478, filed on Aug. 12, 2013. The disclosures of these prior U.S. and foreign applications are incorporated herein by reference.
- The present invention relates to a semiconductor device including IGBTs (Insulated Gate Bipolar Transistors).
- Conventionally, a trench-type IGBT having a high saturation voltage VCE(sat) and short-circuit capacity between the collector and emitter has a p-type floating layer. The p-type floating layer is generally formed by the same step as that for a p-type base layer. The p-type floating layer therefore has the same depth as the p-type base layer.
- However, in the conventional structure, there is a problem that withstand voltage is maintained when the p-type floating layer is deeply diffused for maintaining the withstand voltage of a device, but the p-type base layer is accordingly thickened to raise ON-voltage. On the other hand, if the p-type base layer is thinned for a reduction in ON-voltage, it conversely becomes difficult to maintain a sufficient withstand voltage.
- It is an object of the present invention to provide a semiconductor device including IGBTs capable of increasing withstand voltage while suppressing a rise in ON-voltage.
-
FIG. 1 is a schematic sectional view of a semiconductor device according to a first embodiment of the present invention. -
FIG. 2 is a perspective view for explaining an internal structure of the semiconductor device ofFIG. 1 . -
FIG. 3A is a view for explaining a manufacturing step of the semiconductor device ofFIG. 1 . -
FIG. 3B is a view showing a following step ofFIG. 3A . -
FIG. 3C is a view showing a following step ofFIG. 3B . -
FIG. 3D is a view showing a following step ofFIG. 3C . -
FIG. 3E is a view showing a following step ofFIG. 3D . -
FIG. 3F is a view showing a following step ofFIG. 3E . -
FIG. 3G is a view showing a following step ofFIG. 3F . -
FIG. 3H is a view showing a following step ofFIG. 3F . -
FIG. 3I is a view showing a following step ofFIG. 3F . -
FIG. 4 is a schematic sectional view of a semiconductor device according to a second embodiment of the present invention. -
FIG. 5A andFIG. 5B are views for explaining an internal structure of the semiconductor device ofFIG. 4 , whereinFIG. 5A shows a perspective view, andFIG. 5B shows a plan view. -
FIG. 6 is a schematic sectional view of a semiconductor device according to a third embodiment of the present invention. -
FIG. 7 is an enlarged view of a part enclosed by a broken line ofFIG. 6 . -
FIG. 8A is a view for explaining a manufacturing step of the semiconductor device ofFIG. 7 . -
FIG. 8B is a view showing a following step ofFIG. 8A . -
FIG. 8C is a view showing a following step ofFIG. 8B . -
FIG. 8D is a view showing a following step ofFIG. 8C . -
FIG. 8E is a view showing a following step ofFIG. 8D . -
FIG. 8F is a view showing a following step ofFIG. 8E . -
FIG. 8G is a view showing a following step ofFIG. 8F . -
FIG. 8H is a view showing a following step ofFIG. 8G . -
FIG. 8I is a view showing a following step ofFIG. 8H . -
FIG. 8J is a view showing a following step ofFIG. 8I . -
FIG. 8K is a view showing a following step ofFIG. 8J . -
FIG. 9 is a schematic sectional view of a semiconductor device according to a fourth embodiment of the present invention. -
FIG. 10 is an enlarged view of a part enclosed by a broken line ofFIG. 9 . -
FIG. 11 is a graph showing VCE-ICf characteristics of devices. - A semiconductor device of the present invention includes a semiconductor layer, a plurality of gate trenches formed in the semiconductor layer, a gate electrode filled via a gate insulating film in the plurality of gate trenches, an n+-type emitter region, a p-type base region, and an n−-type drift region disposed, lateral to each gate trench, in order in a depth direction of the gate trench from a front surface side of the semiconductor layer, a p+-type collector region disposed on a back surface side of the semiconductor layer with respect to the n−-type drift region, a plurality of emitter trenches formed between the plurality of gate trenches adjacent to each other, a buried electrode filled via an insulating film in the plurality of emitter trenches, electrically connected with the n+-type emitter region, and a p-type floating region formed between the plurality of emitter trenches, and the p-type floating region is formed deeper than the p-type base region, and includes an overlap portion that goes around to a lower side of an emitter trench closest to the gate trench out of the plurality of emitter trenches and has an end portion positioned on a side closer to the gate trench with respect to a center in a width direction of the emitter trench.
- According to this arrangement, the p-type floating region (overlap portion) is formed up to a bottom portion of the emitter trench filled with the buried electrode (hereinafter, referred to as an “emitter junction trench”). A collector-emitter voltage to be loaded on the emitter junction trench at switching-off operation can thereby be relieved. Therefore, a device breakdown can be prevented against a steep voltage change (dv/dt).
- Also, because withstand voltage can be increased by the p-type floating region that is deeper than the p-type base region, while the p-type base region may be shallow, the channel length can also be reduced to suppress a rise in ON-voltage by appropriately designing the depth of the p-type base region.
- The p-type floating region may have a bottom portion that bulges to a back surface side of the semiconductor layer with respect to a bottom portion of the emitter trench.
- Also, the emitter trench is preferably formed at the same depth as that of the gate trench. In this case, the emitter trench is formed by the same step as that for the gate trench, the manufacturing process can be simplified.
- Also, the gate trenches may be disposed one pair each in a transverse direction along the front surface of the semiconductor layer, and the pair of gate trenches may be opposed in the transverse direction via the p-type base region that is common thereto. In this case, one of the pair of gate trenches may be disposed at an interval of 2 μm to 7 μm with respect to the other.
- The n+-type emitter region may have an n-type dopant concentration of 1×1019 cm−3 to 5×1020 cm−3. The p-type base region may have a p-type dopant concentration of 1×1016 cm−3 to 1×1018 cm−3. The n−-type drift region may have an n-type dopant concentration of 1×1013 cm−3 to 5×1014 cm−3. The p+-type collector region may have a p-type dopant concentration of 1×1015 cm−3 to 2×1019 cm−3.
- Also, the n+-type emitter region preferably selectively has a pullout portion pulled out in a transverse direction along the front surface of the semiconductor layer from a side surface of the gate trench.
- Also, the semiconductor device preferably includes a dummy trench formed spaced at a predetermined interval lateral to the gate trench so that the n+-type emitter region, the p-type base region, and the n−-type drift region are formed between the dummy trench and the gate trench, a buried insulating film being a buried insulating film filled in the dummy trench and having an upper surface on a bottom side of the dummy trench with respect to the front surface of the semiconductor layer, for selectively exposing as a contact region a part of the p-type base region at a part from the front surface to the upper surface in a side surface of the dummy trench, and a contact electrode filled in a region over the buried insulating film of the dummy trench, connected to the contact region on the side surface of the dummy trench.
- According to this arrangement, because the side surface of the dummy trench can be effectively used as the contact region, a junction area of the contact electrode with respect to the p-type base region can be sufficiently secured. Because a plane area of the p-type base region can thereby be sacrificed, the interval between the gate trench and the dummy trench can be miniaturized to form a p-type base region more minute than the conventional p-type base region. Furthermore, because the dummy trench can be formed using the same mask as that for the gate trench, misalignment with respect to the gate trench does not occur. Moreover, alignment of the contact electrode, for which alignment with an area including a plane area of the dummy trench suffices, can thus be easily attained.
- Also, as a result of miniaturization of the trench structure, a trade-off relationship between the short-circuit capacity and ON-voltage of the device can be improved, so that a charge enhancement effect can be increased. VCE(sat) in a low-current range can hence be improved.
- The semiconductor device may further include a first buried electrode filled via an insulating film in a region under the buried insulating film of the dummy trench.
- Also, the semiconductor device may have a trench unit including a pair of the dummy trenches and a gate trench sandwiched between the pair of dummy trenches.
- Also, the dummy trench preferably serves also as the emitter trench as a result of the first buried electrode being electrically connected with the n+-type emitter region.
- Also, the semiconductor device may have a trench unit including a pair of the gate trenches and a dummy trench sandwiched between the pair of gate trenches. In this case, the first buried electrode is preferably electrically connected with the gate electrode.
- Also, the buried insulating film preferably has a thickness of 0.5 μm or more.
- Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
-
FIG. 1 is a schematic sectional view of asemiconductor device 1 according to a first embodiment of the present invention.FIG. 2 is a perspective view for explaining an internal structure of thesemiconductor device 1 ofFIG. 1 . - The
semiconductor device 1 is a device including IGBTs, and includes asemiconductor substrate 2 as an example of a semiconductor layer of the present invention. Thesemiconductor substrate 2 may be, for example, an n″-type silicon substrate having a thickness of 50 μm to 200 μm. - The
semiconductor substrate 2 has a structure in which a p+-type collector region 4, an n-type buffer region 5, and an n−-type drift region 6 are stacked in order from the side of itsback surface 3. The p+-type collector region 4 is exposed over theentire back surface 3 of thesemiconductor substrate 2, and the n−-type drift region 6 is selectively exposed on a part of afront surface 7 of thesemiconductor substrate 2. - As a p-type dopant of the p+-
type collector region 4, for example, B (boron), Al (aluminum), and others can be used (the same applies to the following). On the other hand, as an n-type dopant of the n-type buffer region 5 and the n−-type drift region 6, for example, N (nitrogen), P (phosphorus), As (arsenic), and others can be used (the same applies to the following). - Also, the dopant concentration of the p+-
type collector region 4 is, for example, 1×1015 cm−3 to 2×1019 cm−3. On the other hand, the dopant concentration of the n-type buffer region 5 is, for example, 1×1015 cm−3 to 5×1017 cm−3, and the dopant concentration of the n−-type drift region 6 is 1×1013 cm−3 to 5×1014 cm−3. - On the side of the
front surface 7 of thesemiconductor substrate 2, a plurality of gate trenches 8 are formed. In the present embodiment, the plurality of gate trenches 8 are formed in, for example, a stripe form, and disposed astrench units 9 of one pair each in the transverse direction along thefront surface 7 of thesemiconductor substrate 2. The pitch P1 of mutuallyadjacent trench units 9 is, for example, 4 μm to 20 μm. Also, in a pair of gate trenches 8, the pitch P2 of one gate trench 8 and the other gate trench 8 (distance of center points of the gate trenches 8) is, for example, 2 μm to 7 μm, and the interval L1 (distance between side surfaces of the gate trenches 8) is, for example, 1 μm to 6 μm. - Between a pair of gate trenches 8, a p-
type base region 10 is formed. The p-type base region 10 is shared by one gate trench 8 and the other gate trench 8. Also, in the present embodiment, an interface between the p-type base region 10 and the n−-type drift region 6 is set in a central portion or upper portion of the gate trenches 8, so that the p-type base region 10 is formed by diffusion at a relatively shallow position of thesemiconductor substrate 2. - In the p-
type base region 10, acontact trench 11 dug down from thefront surface 7 of thesemiconductor substrate 2 is formed. Thecontact trench 11 is formed with a fixed width along the longitudinal direction of the gate trench 8. On a bottom surface of thecontact trench 11, a p+-typebase contact region 12 is formed. - Also, in a front surface portion of the p-
type base region 10 between thecontact trench 11 and one and the other gate trenches 8, an n+-type emitter region 13 is formed. The n+-type emitter regions 13 are formed one each on both side surfaces of thecontact trench 11, and are respectively exposed on side surfaces of thecontact trench 11. - Also, the dopant concentration of the p-
type base region 10 is, for example, 1×1016 cm−3 to 1×1018 cm−3. The dopant concentration of the p+-typebase contact region 12 is, for example, 5×1018 cm−3 to 1×1020 cm−3. The dopant concentration of the n+-type emitter region 13 is 1×1019 cm−3 to 5×1020 cm−3. - Also, between a pair of gate trenches 8 on the side of the
front surface 7 of thesemiconductor substrate 2, a plurality of (inFIG. 1 , two)emitter trenches 14 are formed. In the present embodiment, the plurality ofemitter trenches 14 are formed in, for example, a stripe form (parallel to the gate trenches 8), and disposed spaced at mutually equal intervals in the transverse direction along thefront surface 7 of thesemiconductor substrate 2. The interval L2 of mutually adjacent emitter trenches 14 (distance between side surfaces of the emitter trenches 14) is, for example, 3 μm or less, and preferably, 0.8 μm to 3 μm. Also, the plurality ofemitter trenches 14 are formed at the same depth as that of the gate trenches 8. Because theemitter trenches 14 and the gate trenches 8 can thereby be formed by the same step, the manufacturing process can be simplified. - Out of the plurality of
emitter trenches 14, a trench that is adjacent to the gate trench 8 (trench that is opposed to the gate trench 8 via no trench therewith) is disposed at an interval L3 (distance between the side surface of theemitter trench 14 and the side surface of the gate trench 8) of 2 μm or less via the n−-type drift region 6 with the gate trench 8. That is, between saidemitter trench 14 and the gate trench 8, the n−-type drift region 6 is interposed across the entire area in the depth direction. - Also, in each section between the plurality of
emitter trenches 14, a p-type floating region 15 is formed. The p-type floating region 15 is a semiconductor region where a floating state is electrically maintained, and is separated from the gate trench 8 by theemitter trench 14 that is adjacent to the gate trench 8. The p-type floating region 15 is, in the present embodiment, formed deeper than the p-type base region 10. - The p-
type floating region 15 has abottom portion 16 that bulges to the side of theback surface 3 of thesemiconductor substrate 2 with respect to a bottom portion of theemitter trenches 14 and anoverlap portion 17 that goes around to the lower side of theemitter trench 14 adjacent to the gate trench 8. Theoverlap portion 17 has anend portion 18 positioned on a side closer to the gate trench 8 with respect to the center in the width direction of saidemitter trench 14. Theend portion 18 is preferably not projecting to the side of the gate trench 8 with respect to theemitter trench 14. - Also, the dopant concentration of the p-
type floating region 15 is, for example, 5×1015 cm−3 to 1×1018 cm−3. - In the gate trenches 8 and the
emitter trenches 14,gate electrodes 20 and buriedelectrodes 21 are filled, respectively, via an insulating film 19 (for example, silicon oxide (SiO2)). Thegate electrodes 20 and the buriedelectrodes 21 are made of, for example, a conductive material such as polysilicon. The insulatingfilm 19 is integrally formed along inner surfaces of the gate trenches 8, thefront surface 7 of thesemiconductor substrate 2, and inner surfaces of theemitter trenches 14. The part of the insulatingfilm 19 in the gate trench 8 serves as agate insulating film 22. Also, a plurality of buriedelectrodes 21 of theemitter trenches 14 are electrically connected to anemitter electrode 25 to be described later. - On the
front surface 7 of thesemiconductor substrate 2, aninterlayer film 23 made of, for example, an insulating material such as boron phosphorus silicate glass (BPSG) or silicon oxide (SiO2) is stacked. In theinterlayer film 23, acontact hole 24 is formed to selectively expose the n+-type emitter region 13 and the p+-typebase contact region 12 via thecontact trench 11. - On the
interlayer film 23, anemitter electrode 25 is stacked. Theemitter electrode 25 enters thecontact trench 11, and is connected to the n+-type emitter region 13 on the side surface of thecontact trench 11. Also, on the bottom surface of thecontact trench 11, theemitter electrode 25 is connected to the p-type base region 10 via the p+-typebase contact region 12. - Next, a manufacturing method of the
semiconductor device 1 will be explained. FIG. 3A toFIG. 3I are views for explaining the manufacturing process of thesemiconductor device 1 ofFIG. 1 in the order of steps. - For manufacturing the
semiconductor device 1, as shown inFIG. 3A , amask 28 is formed on thefront surface 7 of the n−-type semiconductor substrate 2 (n−-type drift region 6). In themask 28, there is formed an opening to selectively expose a region that needs to be formed into the p-type floating region 15 in thefront surface 7. Then, via themask 28, a p-type dopant is ion-implanted into thefront surface 7 of thesemiconductor substrate 2. An ion-implanted region 26 is thereby formed. - Next, as shown in
FIG. 3B , by thesemiconductor substrate 2 being selectively etched, the gate trenches 8 and theemitter trenches 14 are simultaneously formed. - Next, as shown in
FIG. 3C , by thesemiconductor substrate 2 being thermally oxidized, asacrificial oxide film 27 is formed on the entire area of the front surface including the inner surfaces of the gate trenches 8 and theemitter trenches 14. Then, by annealing thesemiconductor substrate 2 covered with thesacrificial oxide film 27, the p-type dopant in the ion-implanted region 26 is diffused (driven in). The annealing treatment is performed on a condition that the p-type dopant goes around to the lower side of theemitter trench 14. The p-type floating region 15 is thereby formed. In this case, because thesemiconductor substrate 2 is covered with thesacrificial oxide film 27, ion seeping from the front surface of the substrate can be prevented, so that the p-type dopant can be efficiently diffused. - Next, as shown in
FIG. 3D , thesacrificial oxide film 27 is stripped. - Next, as shown in
FIG. 3E , by thesemiconductor substrate 2 being thermally oxidized, the insulating film 19 (gate insulating film 22) is formed on the entire area of the front surface including the inner surfaces of the gate trenches 8 and theemitter trenches 14. - Next, as shown in
FIG. 3F , an electrode material such as polysilicon is filled in the gate trenches 8 and theemitter trenches 14. Thegate electrodes 20 and the buriedelectrodes 21 are thereby simultaneously formed. - Next, as shown in
FIG. 3G , by n-type and p-type dopants being selectively ion-implanted and diffused into thefront surface 7 of thesemiconductor substrate 2, the p-type base regions 10 and the n+-type emitter regions 13 are formed in order. - Next, as shown in
FIG. 3H , by depositing an insulating material such as boron phosphorus silicate glass (BPSG) or silicon oxide (SiO2) on thefront surface 7 of thesemiconductor substrate 2, theinterlayer film 23 is formed. Next, after theinterlayer film 23 is selectively etched to form acontact hole 24, thesemiconductor substrate 2 exposed from saidcontact hole 24 is selectively etched. Thecontact trench 11 is thereby formed. - Next, as shown in
FIG. 3I , by a p-type dopant being selectively ion-implanted and diffused into bottom portions of thecontact trenches 11 via the contact holes 24, the p+-typebase contact regions 12 are formed. - Thereafter, by n-type and p-type dopants being selectively ion-implanted and diffused into the
back surface 3 of thesemiconductor substrate 2 after theemitter electrode 24 and the like being formed on the side of thefront surface 7 of thesemiconductor substrate 2, the n-type buffer region 5 and the p+-type collector region 4 are formed in order. - Through the steps as above, the
semiconductor device 1 shown inFIG. 1 is obtained. However,FIG. 3A toFIG. 3I merely represent a part of the manufacturing process of thesemiconductor device 1, and said manufacturing process may include steps not shown byFIG. 3A toFIG. 3I . - According to this
semiconductor device 1, because the p-type floating region 15 (overlap portion 17) is formed up to a bottom portion of theemitter trench 14 filled with the buried electrode 21 (hereinafter, referred to as an “emitter junction trench”), a collector-emitter voltage to be loaded on the emitter junction trench at switching-off operation can be relieved. Therefore, a device breakdown can be prevented against a steep voltage change (dv/dt). - Also, because withstand voltage can be increased by the p-
type floating region 15 that is deeper than the p-type base region 10, while the p-type base region 10 may be shallow, the channel length (length in the depth direction of the gate trench 8) can also be reduced to suppress a rise in ON-voltage by appropriately designing the depth of the p-type base region 10. - Also, the gate trench 8 filled with the gate electrode 20 (hereinafter, referred to as a “gate junction trench”) is separated from the p-
type floating region 15 by the emitter junction trench. The p-type floating region 15 and the gate junction trench can thereby be prevented from joining. A stray capacitance between the gate junction trench and the p-type floating region 15 can therefore be eliminated. - On the other hand, the n−-
type drift region 6 which the gate junction trench joins across the entire area in the depth direction is to be grounded together with the p+-type collector region 4. Therefore, at switching operation, a capacitance change between the gate junction trench and the n−-type drift region 6 is stabilized, so that noise does not easily occur. As a result thereof, generation of noise and switching loss at switching operation can be reduced. - Also, because the interval L3 between the emitter junction trench and the gate junction trench is 2 μm or less, withstand voltage can also be satisfactorily maintained.
- Further, because the side surface of the
contact trench 11 can be effectively used as a region for contact with the n+-type emitter region 13, a junction area of theemitter electrode 25 with respect to the n+-type emitter region 13 can be sufficiently secured. Because a plane area of the n+-type emitter region 13 can thereby be sacrificed, the interval L1 between one and the other gate trenches 8 of a pair of gate trenches 8 can be miniaturized to form a p-type base region 10 more minute than the conventional p-type base region. As a result of miniaturization of the gate trench 8, a trade-off relationship between the short-circuit capacity and ON-voltage of the device can be improved, so that a charge enhancement effect can be increased. VCE(sat) in a low-current range can hence be improved. -
FIG. 4 is a schematic sectional view of asemiconductor device 31 according to a second embodiment of the present invention.FIG. 5A andFIG. 5B are views for explaining an internal structure of thesemiconductor device 31 ofFIG. 4 , whereinFIG. 5A shows a perspective view, andFIG. 5B shows a plan view. InFIG. 4 andFIG. 5A andFIG. 5B , parts corresponding to the respective portions shown inFIG. 1 described above will be denoted by the same reference signs. - In the foregoing first embodiment, the gate trenches 8 are formed as
trench units 9 of one pair each, and a common p-type base region 10 is formed between one and the other gate trenches 8. In contrast, thesemiconductor device 31 of the second embodiment includes a plurality ofgate trenches 33 formed astrench units 32 of one each in the transverse direction along thefront surface 7 of thesemiconductor substrate 2, p-type base regions 34 formed on both sides of each gate trench 33 (regions between the same and the emitter trenches 14), and n+-type emitter regions 35 formed in front surface portions of the respective p-type base regions 34. The n+-type emitter regions 35 are formed one each along both side surfaces of thegate trench 33, and are exposed on thefront surface 7 of thesemiconductor substrate 2. - Also, in the front surface portion of the p-
type base region 34, a p+-typebase contact region 37 is formed lateral to the n+-type emitter region 35 (on the opposite side to the gate trench 33). The dopant concentration of the p+-typebase contact region 37 is, for example, 5×10″cm−3 to 1×1020 cm−3. - The n+-
type emitter region 35, as shown inFIG. 5A andFIG. 5B , selectively has apullout portion 38 pulled out in the transverse direction along thefront surface 7 of thesemiconductor substrate 2 from the side surface of thegate trench 33. Thepullout portion 38 is, for example, disposed spaced at fixed intervals along the longitudinal direction of thegate trench 33. When a pair of n+-type emitter regions 35 are provided for thegate trench 33 as in the present embodiment, thepullout portions 38 of the respective n+-type emitter regions 35 may be, as shown inFIG. 5B , disposed so that one and the other end portions are opposed to each other across thegate trench 33, or end portions of onepullout portion 38 and end portions of theother pullout portion 38 may be disposed alternately along the longitudinal direction of the gate trench 33 (not shown). Thereby, a part adjacent to thepullout region 38 in the p+-typebase contact region 37 serves as aconstricted portion 39 selectively having a narrower width than that of the remaining part. - Also, in the
interlayer film 23, acontact hole 36 is formed to selectively expose the p+-typebase contact region 37 and the n+-type emitter region 35. The n+-type emitter region 35 is selectively exposed at thepullout portion 38 from thecontact hole 36. Theemitter electrode 25 is connected to the p+-typebase contact region 37 and the n+-type emitter region 35 via thecontact hole 36. - Also by this
semiconductor device 31, the same effects as those of thesemiconductor device 1 of the first embodiment can be achieved. -
FIG. 6 is a schematic sectional view of asemiconductor device 101 according to a third embodiment of the present invention.FIG. 7 is an enlarged view of a part enclosed by a broken line ofFIG. 6 . - The
semiconductor device 101 is a device including IGBTs, and includes asemiconductor substrate 102 as an example of a semiconductor layer of the present invention. Thesemiconductor substrate 102 may be, for example, an n−-type silicon substrate having a thickness of 50 μm to 200 μm. - The
semiconductor substrate 102 has a structure in which a p+-type collector region 104, an n-type buffer region 105, and an n−-type drift region 106 are stacked in order from the side of itsback surface 103. The p+-type collector region 104 is exposed over theentire back surface 103 of thesemiconductor substrate 102, and the n−-type drift region 106 is selectively exposed on a part of afront surface 107 of thesemiconductor substrate 102. - As a p-type dopant of the p+-
type collector region 104, for example, B (boron), Al (aluminum), and others can be used (the same applies to the following). On the other hand, as an n-type dopant of the n-type buffer region 105 and the n−-type drift region 106, for example, N (nitrogen), P (phosphorus), As (arsenic), and others can be used (the same applies to the following). - Also, the dopant concentration of the p+-
type collector region 104 is, for example, 1×1015 cm−3 to 2×1019 cm−3. On the other hand, the dopant concentration of the n-type buffer region 105 is, for example, 1×1015 cm−3 to 5×1017 cm−3, and the dopant concentration of the n−-type drift region 106 is 1×1013 cm−3 to 5×1014 cm−3. - On the side of the
front surface 107 of thesemiconductor substrate 102, a plurality ofgate trenches 108 and a plurality ofdummy trenches 109 are formed adjacent to each other. In the present embodiment, atrench unit 110 including a pair ofdummy trenches 109 and agate trench 108 sandwiched between the pair ofdummy trenches 109 is disposed in plural numbers spaced at intervals in the transverse direction along thefront surface 107 of thesemiconductor substrate 102. Thegate trenches 108 and thedummy trenches 109 are thereby formed in a stripe form as a whole. - The pitch P1 of mutually
adjacent trench units 110 is, for example, 2 μm to 7μm. Also, in eachtrench unit 110, the intervals L1 between thegate trench 108 and thedummy trenches 109 on both sides thereof (distances between side surfaces of thegate trench 108 and side surfaces of the dummy trenches 109) are preferably respectively 2 μm or less. - In each
trench unit 100, on both sides of the gate trench 108 (regions between the same and the respective dummy trenches 109), a p-type base region 111 is formed, and further, an n+-type emitter region 112 and a p+-typebase contact region 113 are formed in a front surface portion of the p-type base region 111 (refer toFIG. 7 ). In the present embodiment, an interface between the p-type base region 111 and the n−-type drift region 106 is set in a central portion or upper portion of thegate trench 108, and the p-type base region 111 is formed by diffusion at a relatively shallow position of thesemiconductor substrate 102. - The n+-
type emitter region 112 and the p+-typebase contact region 113 are disposed adjacent to each other in the region between thegate trench 108 and thedummy trench 109. Specifically, n+-type emitter regions 112 are formed one each along both side surfaces 114 of thegate trench 108, and p+-typebase contact regions 113 are formed one each along side surfaces 115 of therespective dummy trenches 109. The n+-type emitter regions 112 are thereby exposed on thefront surface 107 of thesemiconductor substrate 102 and the side surfaces 114 of thegate trenches 108. On the other hand, the p+-typebase contact regions 113 are exposed on thefront surface 107 of thesemiconductor substrate 102 and the side surfaces 115 of thedummy trenches 109. - Also, the dopant concentration of the p-
type base region 111 is, for example, 1×1016 cm−3 to 1×1018 cm−3. The dopant concentration of the n+-type emitter region 112 is 1×1019 cm−3 to 5×1020 cm−3. The dopant concentration of the p+-typebase contact region 113 is, for example, 5×1018 cm−3 to 1×1020 cm−3. - Also, between
trench units 110 adjacent on the side of thefront surface 107 of thesemiconductor substrate 102, a plurality of (inFIG. 6 , three)emitter trenches 116 are formed. In the present embodiment, the plurality ofemitter trenches 116 are formed in, for example, a stripe form (parallel to thegate trenches 108 and the dummy trenches 109), and disposed spaced at mutually equal intervals in the transverse direction along thefront surface 107 of thesemiconductor substrate 102. The interval L2 of mutually adjacent emitter trenches 116 (distance between side surfaces of the emitter trenches 116) is, for example, 3 μm or less, and preferably, 0.8 μm to 3 μm. Also, the plurality ofemitter trenches 116 are formed at the same depth as that of thegate trenches 108 and thedummy trenches 109. Because theemitter trenches 116 can thereby be formed by the same step as that for thegate trenches 108 and thedummy trenches 109, the manufacturing process can be simplified. - Out of the plurality of
emitter trenches 116, a trench that is adjacent to the dummy trench 109 (trench that is opposed to thedummy trench 109 via no trench therewith) is disposed at an interval L3 (distance between the side surface of theemitter trench 116 and the side surface of the dummy trench 109) of 0.5 μm to 20 μm with thedummy trench 109. - Also, in the
semiconductor substrate 102, a p-type floating region 117 is formed. The p-type floating region 117 spreads over a region sandwiched by thedummy trenches 109 of mutuallyadjacent trench units 110, opposed via theemitter trenches 116. The p-type floating region 117 is a semiconductor region where a floating state is electrically maintained, and is separated from thegate trench 108 by thedummy trench 109 that is adjacent to thegate trench 108. The p-type floating region 117 is, in the present embodiment, formed deeper than the p-type base region 111. - The p-
type floating region 117 has abottom portion 118 that bulges to the side of theback surface 103 of thesemiconductor substrate 102 with respect to a bottom portion of theemitter trenches 116 and anoverlap portion 119 that goes around to the lower side of thedummy trench 109. Theoverlap portion 119 has anend portion 120 positioned on a side closer to thegate trench 108 with respect to the center in the width direction of saiddummy trench 109. Theend portion 120 is preferably not projecting to the side of thegate trench 108 with respect to theemitter trench 116. - Also, the dopant concentration of the p-
type floating region 117 is, for example, 5×1015 cm−3 to 1×1018 cm−3. - In the
gate trenches 108, thedummy trenches 109, and theemitter trenches 116,gate electrodes 122, first buriedelectrodes 123, and second buriedelectrodes 124 are filled, respectively, via an insulating film 121 (for example, silicon oxide (SiO2)). Thegate electrodes 122, the first buriedelectrodes 123, and the second buriedelectrodes 124 are made of, for example, a conductive material such as polysilicon. The insulatingfilm 121 is integrally formed along inner surfaces of thegate trenches 108, inner surfaces of thedummy trenches 109, thefront surface 107 of thesemiconductor substrate 102, and inner surfaces of theemitter trenches 116. The part of the insulatingfilm 121 in thegate trench 108 serves as agate insulating film 125. Also, the first buriedelectrodes 123 and the second buriedelectrodes 124 are electrically connected to anemitter electrode 132 to be described later. - Also, in the present embodiment, the
gate electrode 122 and the second buriedelectrode 124 fill back theirrespective trenches electrode 123 fills back thedummy trench 109 halfway in the depth direction thereof. In thedummy trench 109, a space without an electrode is thereby formed in a region over the first buriedelectrode 123. Moreover, a buried insulatingfilm 126 is filled in thedummy trench 109 so as to fill back the space up to the opening end. - The buried insulating
film 126 is made of, for example, an insulating material such as boron phosphorus silicate glass (BPSG) or silicon oxide (SiO2), and has a thickness of 0.5 μm or more. In the buried insulatingfilm 126 and the insulatingfilm 121 thereunder, aremoval portion 127 is selectively formed to expose the p+-typebase contact region 113 on theside surface 115 of thedummy trench 109. That is, the buried insulatingfilm 126 selectively has anupper surface 128 that is at a position lower than that of thefront surface 107 of thesemiconductor substrate 102 so as to be continuous from theside surface 115 of thedummy trench 109, and the p+-typebase contact region 113 is exposed in a region of theside surface 115 of thedummy trench 109 between theupper surface 128 and thefront surface 107. - On the
front surface 107 of thesemiconductor substrate 102, aninterlayer film 129 made of, for example, an insulating material such as boron phosphorus silicate glass (BPSG) or silicon oxide (SiO2) is stacked. Theinterlayer film 129 is formed integrally with the buried insulatingfilm 126. In theinterlayer film 129, acontact hole 130 is formed extending across thefront surface 107 of thesemiconductor substrate 102 and the opening end of thedummy trench 109. Thecontact hole 130 exposes the n+-type emitter region 112 and the p+-typebase contact region 113 at thefront surface 107 of thesemiconductor substrate 102, and exposes the p+-typebase contact region 113 at the side surface 115 (removal portion 127) of thedummy trench 109. That is, the p+-typebase contact region 113 is exposed in acorner portion 131 of thedummy trench 109 defined by intersection of thefront surface 107 and theside surface 115. In addition, the n+-type emitter region 112 may selectively have a pullout portion pulled out in the transverse direction along thefront surface 107 of thesemiconductor substrate 102 from theside surface 114 of thegate trench 108, and only the pullout portion may be selectively exposed from thecontact hole 130. - On the
interlayer film 129, anemitter electrode 132 as an example of a contact electrode of the present invention is stacked. Theemitter electrode 132 enters thecontact hole 130, and is connected to the n+-type emitter region 112 on thefront surface 107 of thesemiconductor substrate 102, and is connected to the p+-typebase contact region 113 in thecorner portion 131 of thedummy trench 109. - Next, a manufacturing method of the
semiconductor device 101 will be explained.FIG. 8A toFIG. 8K are views for explaining the manufacturing process of thesemiconductor device 101 ofFIG. 6 and theFIG. 7 in the order of steps. In addition,FIG. 8A toFIG. 8F show sections corresponding toFIG. 6 , andFIG. 8G toFIG. 8K show sections corresponding toFIG. 7 . - For manufacturing the
semiconductor device 101, as shown inFIG. 8A , amask 160 is formed on thefront surface 107 of the n−-type semiconductor substrate 102 (n−-type drift region 106). In themask 160, there is formed an opening to selectively expose a region that needs to be formed into the p-type floating region 117 in thefront surface 107. Then, via themask 160, a p-type dopant is ion-implanted into thefront surface 107 of thesemiconductor substrate 102. An ion-implantedregion 161 is thereby formed. - Next, as shown in
FIG. 8B , by thesemiconductor substrate 102 being selectively etched, thegate trenches 108, thedummy trenches 109, and theemitter trenches 116 are simultaneously formed. - Next, as shown in
FIG. 8C , by thesemiconductor substrate 102 being thermally oxidized, a sacrificial oxide film 162 is formed on the entire area of the front surface including the inner surfaces of thegate trenches 108, thedummy trenches 109, and theemitter trenches 116. Then, by annealing thesemiconductor substrate 102 covered with the sacrificial oxide film 162, the p-type dopant in the ion-implantedregion 161 is diffused (driven in). The annealing treatment is performed on a condition that the p-type dopant goes around to the lower side of thedummy trench 109. The p-type floating region 117 is thereby formed. In this case, because thesemiconductor substrate 102 is covered with the sacrificial oxide film 162, ion seeping from the front surface of the substrate can be prevented, so that the p-type dopant can be efficiently diffused. - Next, as shown in
FIG. 8D , the sacrificial oxide film 162 is stripped. - Next, as shown in
FIG. 8E , by thesemiconductor substrate 102 being thermally oxidized, the insulating film 121 (gate insulating film 125) is formed on the entire area of the front surface including the inner surfaces of thegate trenches 108, thedummy trenches 109, and theemitter trenches 116. - Next, as shown in
FIG. 8F , an electrode material such as polysilicon is filled in thegate trenches 108, thedummy trenches 109, and theemitter trenches 116. Thegate electrodes 122, the first buriedelectrodes 123, and the second buriedelectrodes 124 are thereby simultaneously formed. - Next, as shown in
FIG. 8G , by n-type and p-type dopants being selectively ion-implanted and diffused into thefront surface 107 of thesemiconductor substrate 102, the p-type base regions 111 and the n+-type emitter regions 112 are formed in order. - Next, as shown in
FIG. 8H , by etching the first buriedelectrodes 123 from upper surfaces, the filled states of thegate electrodes 122 and the second buriedelectrodes 124 are kept maintained, while only the first buriedelectrodes 123 are selectively dug down. - Next, as shown in
FIG. 8I , by depositing an insulating material such as boron phosphorus silicate glass (BPSG) or silicon oxide (SiO2) on thefront surface 107 of thesemiconductor substrate 102, the spaces over the first buriedelectrodes 123 are filled back with said insulating material, and thefront surface 107 is covered with said insulating material. The buried insulatingfilm 126 and theinterlayer film 129 are thereby simultaneously formed. - Next, as shown in
FIG. 8J , by selectively etching theinterlayer film 129 and the buried insulatingfilm 126, the contact holes 130 and theremoval portions 127 are simultaneously formed. - Next, as shown in
FIG. 8K , a p-type dopant is selectively ion-implanted and diffused into thefront surface 107 of thesemiconductor substrate 102 exposed in the contact holes 130. The p+-typebase contact regions 113 are thereby formed. - Thereafter, by n-type and p-type dopants being selectively ion-implanted and diffused into the
back surface 103 of thesemiconductor substrate 102 after theemitter electrode 132 and the like being formed on the side of thefront surface 107 of thesemiconductor substrate 102, the n-type buffer region 105 and the p+-type collector region 104 are formed in order. - Through the steps as above, the
semiconductor device 101 shown inFIG. 6 andFIG. 7 is obtained. However,FIG. 8A toFIG. 8K merely represent a part of the manufacturing process of thesemiconductor device 101, and said manufacturing process may include steps not shown byFIG. 8A toFIG. 8K . - According to this
semiconductor device 101, because theside surface 115 of thedummy trench 109 can be effectively used as the p+-typebase contact region 113, a junction area of theemitter electrode 132 with respect to the p-type base region 111 can be sufficiently secured by both surfaces of thefront surface 107 of thesemiconductor substrate 102 and theside surface 115 of thedummy trench 109. Because a plane area of the p-type base region 111 can thereby be sacrificed, the interval L1 between thegate trench 108 and thedummy trench 109 can be miniaturized to form a p-type base region 111 more minute than the conventional p-type base region. Furthermore, because thedummy trenches 109 can be formed using the same mask as that for thegate trenches 108, misalignment with respect to thegate trenches 108 does not occur. Moreover, alignment of theemitter electrode 132, for which alignment with an area including a plane area of thedummy trenches 109 suffices, can thus be easily attained. - Specifically, first, by etching the
semiconductor substrate 102 using the same mask, thegate trenches 108, thedummy trenches 109, and theemitter trenches 116 are simultaneously formed (FIG. 8B ). Next, by filling polysilicon in thetrenches gate electrodes 122, the first buriedelectrodes 123, and the second buriedelectrodes 124 are formed (FIG. 8F ). Next, a mask to selectively expose thedummy trenches 109 is formed on thesemiconductor substrate 102, and via the mask, an upper portion of the polysilicon in thedummy trenches 109 is selectively removed by etching. Spaces are thereby formed in regions over the first buriedelectrodes 123 of the dummy trenches 109 (FIG. 8H ). Next, theinterlayer film 129 is formed by depositing on thesemiconductor substrate 102 an insulating material such as BPSG by, for example, a CVD method (FIG. 8I ). A part of the insulating material enters into thedummy trenches 109 as the buried insulatingfilm 126. Next, a mask to form the contact holes 130 is aligned with respect to thesemiconductor substrate 102. In this case, because end portions of the contact holes 130 may cover thedummy trenches 109, the alignment can be attained in a wide area including thefront surface 107 of thesemiconductor substrate 102 and a plane area of thedummy trenches 109. Then, via said mask, theinterlayer film 129 and the buried insulatingfilm 126 are continuously etched. The contact holes 130 and theremoval portions 127 are thereby simultaneously formed (FIG. 8J ). Thereafter, by ion-implanting a p-type dopant using theinterlayer film 129 as a mask to form the p+-typebase contact regions 113 in a self-aligned manner, the p+-typebase contact regions 113 can be reliably formed in thecorner portions 131 of the dummy trenches 109 (FIG. 8K ). Furthermore, because the contact holes 130 can be formed relatively wide, a part of theemitter electrode 132 using aluminum (Al) or the like can be used as plugs, even without using plugs excellent in filling ability, such as tungsten (W). - As a result of miniaturization of the trench structure as above, a trade-off relationship between the short-circuit capacity and ON-voltage of the device can be improved, so that a charge enhancement effect can be increased. VCE(sat) in a low-current range can hence be improved.
- Also, according to this
semiconductor device 101, thegate trench 108 filled with the gate electrode 122 (hereinafter, referred to as a “gate junction trench”) is separated from the p-type floating region 117 by thedummy trench 109 filled with the first buriedelectrode 123 connected to the n+-type emitter region 112 (hereinafter, referred to as an “emitter junction trench”). The p-type floating region 117 and the gate junction trench can thereby be prevented from joining. A stray capacitance between the gate junction trench and the p-type floating region 117 can therefore be eliminated. - On the other hand, the n−-
type drift region 106 which the gate junction trench joins across the depth direction is to be grounded together with the p+-type collector region 104. Therefore, at switching operation, a capacitance change between the gate junction trench and the n−-type drift region 106 is stabilized, so that noise does not easily occur. As a result thereof, generation of noise and switching loss at switching operation can be reduced. - Also, because the interval L1 between the emitter junction trench and the gate junction trench is 2 μm or less, withstand voltage can also be satisfactorily maintained.
- Further, according to this
semiconductor device 101, because the p-type floating region 117 (overlap portion 119) is formed up to a bottom portion of the emitter junction trench, a collector-emitter voltage to be loaded on the emitter junction trench at switching-off operation can be relieved. Therefore, a device breakdown can be prevented against a steep voltage change (dv/dt). - Also, because withstand voltage can be increased by the p-
type floating region 117 that is deeper than the p-type base region 111, while the p-type base region 111 may be shallow, the channel length (length in the depth direction of the gate trench 108) can also be reduced to suppress a rise in ON-voltage by appropriately designing the depth of the p-type base region 111. -
FIG. 9 is a schematic sectional view of asemiconductor device 141 according to a fourth embodiment of the present invention.FIG. 10 is an enlarged view of a part enclosed by a broken line ofFIG. 9 . InFIG. 9 andFIG. 10 , parts corresponding to the respective portions shown inFIG. 6 andFIG. 7 described above will be denoted by the same reference signs. - In the foregoing third embodiment, the
trench unit 110 includes a pair ofdummy trenches 109 and agate trench 108 sandwiched between the pair ofdummy trenches 109. In contrast, thesemiconductor device 141 of the fourth embodiment has atrench unit 144 including a pair ofgate trenches 142 and adummy trench 143 sandwiched between the pair ofgate trenches 142. In this case, the interval L3 between thegate trench 142 and the emitter trench 116 (distance between the side surface of thegate trench 142 and the side surface of the emitter trench 116) is preferably 2 μm or less. - In each
trench unit 144, on both sides of the dummy trench 143 (regions between the same and the respective gate trenches 142), a p-type base region 145 is formed, and further, an n+-type emitter region 146 and a p+-typebase contact region 147 are formed in a front surface portion of the p-type base region 145 (refer toFIG. 10 ). In the present embodiment, an interface between the p-type base region 145 and the n−-type drift region 106 is set in a central portion or upper portion of thegate trench 142, and the p-type base region 145 is formed by diffusion at a relatively shallow position of thesemiconductor substrate 102. - The n+-
type emitter region 146 and the p+-typebase contact region 147 are disposed adjacent to each other in the region between thegate trench 142 and thedummy trench 143. Specifically, n+-type emitter regions 146 are formed one each along side surfaces 148 of therespective gate trenches 142, and p+-typebase contact regions 147 are formed one each along both side surfaces 149 of thedummy trench 143. The n+-type emitter regions 146 are thereby exposed on thefront surface 107 of thesemiconductor substrate 102 and the side surfaces 148 of thegate trenches 142. On the other hand, the p+-typebase contact regions 147 are exposed on thefront surface 107 of thesemiconductor substrate 102 and the side surfaces 149 of thedummy trenches 143. - Also, in the
semiconductor substrate 102, a p-type floating region 150 is formed. The p-type floating region 150 spreads over each section between the plurality ofemitter trenches 116. The p-type floating region 150 is a semiconductor region where a floating state is electrically maintained, and is separated from thegate trench 142 by theemitter trench 116 that is adjacent to thegate trench 142. The p-type floating region 150 is, in the present embodiment, formed deeper than the p-type base region 145. - The p-type floating region 150 has a bottom portion 151 that bulges to the side of the
back surface 103 of thesemiconductor substrate 102 with respect to a bottom portion of theemitter trenches 116 and anoverlap portion 152 that goes around to the lower side of theemitter trench 116 adjacent to thegate trench 142. Theoverlap portion 152 has an end portion 153 positioned on a side closer to thegate trench 142 with respect to the center in the width direction of saidemitter trench 116. The end portion 153 is preferably not projecting to the side of thegate trench 142 with respect to theemitter trench 116. - Such a p-type floating region 150 can be formed, for example, in the same manner as the foregoing p-
type floating region 117. - In the
dummy trench 143, a first buriedelectrode 154 is filled via an insulatingfilm 121. The first buriedelectrode 154 is made of, for example, a conductive material such as polysilicon, and is electrically connected to thegate electrode 122. Also, the first buriedelectrode 154 fills back thedummy trench 143 halfway in the depth direction thereof. In thedummy trench 143, a space without an electrode is thereby formed in a region over the first buriedelectrode 154. Moreover, a buried insulatingfilm 155 is filled in thedummy trench 143 so as to fill back the space up to the opening end. - The buried insulating
film 155 is made of, for example, an insulating material such as boron phosphorus silicate glass (BPSG) or silicon oxide (SiO2), and has a thickness of 0.5 μm or more. In the buried insulatingfilm 155 and the insulatingfilm 121 thereunder, a removal portion 156 is selectively formed to expose the p+-typebase contact regions 147 on both side surfaces 149 of thedummy trench 143. That is, the buried insulatingfilm 155 selectively has an upper surface 157 that is at a position lower than that of thefront surface 107 of thesemiconductor substrate 102 so as to be continuous from both side surfaces 149 of thedummy trench 143, and the p+-typebase contact regions 147 are exposed in a region of both side surfaces 149 of thedummy trench 143 between the upper surface 157 and thefront surface 107. - In the
interlayer film 129, a contact hole 158 is formed extending across the p-type base regions 145 opposed across thedummy trench 143. The contact hole 158 exposes the n+-type emitter regions 146 and the p+-typebase contact regions 147 at thefront surface 107 of thesemiconductor substrate 102, and exposes the p+-typebase contact regions 147 at both side surfaces 149 (removal portion 156) of thedummy trench 143. That is, the p+-typebase contact regions 147 are exposed in bothcorner portions 159 of thedummy trench 143 defined by intersection of thefront surface 107 and the side surfaces 149. In addition, the n+-type emitter region 146 may selectively have a pullout portion pulled out in the transverse direction along thefront surface 107 of thesemiconductor substrate 102 from theside surface 148 of thegate trench 142, and only the pullout portion may be selectively exposed from the contact hole 158. - Moreover, the
emitter electrode 132 enters the contact hole 158, and is connected to the n+-type emitter regions 146 on thefront surface 107 of thesemiconductor substrate 102, and is connected to the p+-typebase contact regions 147 in bothcorner portions 159 of thedummy trench 143. - Also by this
semiconductor device 141, the same effects as those of thesemiconductor device 101 of the third embodiment can be achieved. - The embodiments of the present invention are described above, however, the present invention can also be carried out in other embodiments.
- For example, the above-described features grasped from the disclosures of the respective embodiments described above may be combined with each other even among different embodiments.
- Also, in the foregoing embodiments, only the arrangements of IGBTs included in the
semiconductor devices - Various other design modifications can be made within the scope of the matters described in the claims.
- The embodiments of the present invention are merely specific examples used to clarify the technical contents of the present invention, and the present invention should not be interpreted as being limited to only these specific examples, and the spirit and scope of the present invention shall be limited only by the accompanying claims.
- The present application corresponds to Japanese Patent Application No. 2012-182169 filed on Aug. 21, 2012 in the Japan Patent Office, Japanese Patent Application No. 2012-182170 filed on Aug. 21, 2012 in the Japan Patent Office, and Japanese Patent Application No. 2013-167478 filed on Aug. 12, 2013 in the Japan Patent Office, and the entire disclosures of these applications are incorporated herein by reference.
- In addition, from the description of the specification and drawings, the following features can be extracted besides the inventions described in the claims.
- (Section 1) A semiconductor device including a semiconductor layer, a gate trench formed in the semiconductor layer, a gate electrode filled via a gate insulating film in the gate trench, a dummy trench formed spaced at a predetermined interval lateral to the gate trench, an n+-type emitter region, a p-type base region, and an n−-type drift region disposed, in a region between the gate trench and the dummy trench, in order in a depth direction of the gate trench from a front surface side of the semiconductor layer, a p+-type collector region disposed on a back surface side of the semiconductor layer with respect to the n−-type drift region, a buried insulating film being a buried insulating film filled in the dummy trench and having an upper surface at a bottom side of the dummy trench with respect to the front surface of the semiconductor layer, for selectively exposing as a contact region a part of the p-type base region at a part from the front surface to the upper surface in a side surface of the dummy trench, and a contact electrode filled in a region over the buried insulating film of the dummy trench, connected to the contact region on the side surface of the dummy trench.
- According to this arrangement, because the side surface of the dummy trench can be effectively used as the contact region, a junction area of the contact electrode with respect to the p-type base region can be sufficiently secured. Because a plane area of the p-type base region can thereby be sacrificed, the interval between the gate trench and the dummy trench can be miniaturized to form a p-type base region more minute than the conventional p-type base region. Furthermore, because the dummy trench can be formed using the same mask as that for the gate trench, misalignment with respect to the gate trench does not occur. Moreover, alignment of the contact electrode, for which alignment with an area including a plane area of the dummy trench suffices, can thus be easily attained.
- Also, as a result of miniaturization of the trench structure, a trade-off relationship between the short-circuit capacity and ON-voltage of the device can be improved, so that a charge enhancement effect can be increased. VCE(sat) in a low-current range can hence be improved.
- (Section 2) The semiconductor device according to
section 1, wherein the semiconductor device further includes a first buried electrode filled via an insulating film in a region under the buried insulating film of the dummy trench. - (Section 3) The semiconductor device according to
section 2, wherein the semiconductor device has a trench unit including a pair of the dummy trenches and a gate trench sandwiched between the pair of dummy trenches. - (Section 4) The semiconductor device according to
section 3, wherein the first buried electrode is electrically connected with the n+-type emitter region. - (Section 5) The semiconductor device according to
section 4, wherein the trench unit is formed in plural numbers in a transverse direction along the front surface of the semiconductor layer, and the semiconductor device further includes a plurality of emitter trenches formed between the trench units adjacent to each other, a second buried electrode filled via an insulating film in the emitter trench, electrically connected with the n+-type emitter region, and a p-type floating region formed between the dummy trench of the trench unit and the dummy trench of the trench unit next thereto. - (Section 6) The semiconductor device according to
section 5, wherein the p-type floating region is formed deeper than the p-type base region, and includes an overlap portion that goes around to a lower side of the dummy trench. - According to this arrangement, because the p-type floating region (overlap portion) is formed up to a bottom portion of the dummy trench filled with the first buried electrode connected to the n+-type emitter region (hereinafter, referred to as an “emitter junction trench”), a collector-emitter voltage to be loaded on the emitter junction trench at switching-off operation can be relieved. Therefore, a device breakdown can be prevented against a steep voltage change (dv/dt).
- Also, because withstand voltage can be increased by the p-type floating region that is deeper than the p-type base region, while the p-type base region may be shallow, a rise in ON-voltage can also be suppressed by appropriately designing the depth of the p-type base region.
- (Section 7) The semiconductor device according to
section 6, wherein the overlap portion has an end portion positioned on a side closer to the gate trench with respect to a center in a width direction of the emitter trench. - According to this arrangement, a collector-emitter voltage to be applied to the emitter junction trench can be more satisfactorily relieved.
- (Section 8) The semiconductor device according to
section 2, wherein the semiconductor device has a trench unit including a pair of the gate trenches and a dummy trench sandwiched between the pair of gate trenches. - (Section 9) The semiconductor device according to section 8, wherein the first buried electrode is electrically connected with the gate electrode.
- (Section 10) The semiconductor device according to
section 9, wherein the trench unit is formed in plural numbers in a transverse direction along the front surface of the semiconductor layer, and the semiconductor device further includes a plurality of emitter trenches formed between the trench units adjacent to each other, a second buried electrode filled via an insulating film in the emitter trench, electrically connected with the n+-type emitter region, and a p-type floating region formed between the plurality of emitter trenches. - (Section 11) The semiconductor device according to
section 10, wherein the p-type floating region is formed deeper than the p-type base region, and includes an overlap portion that goes around to a lower side of the emitter trench. - According to this arrangement, because the p-type floating region (overlap portion) is formed up to a bottom portion of the emitter trench filled with the second buried electrode connected to the n+-type emitter region (hereinafter, referred to as an “emitter junction trench”), a collector-emitter voltage to be loaded on the emitter junction trench at switching-off operation can be relieved. Therefore, a device breakdown can be prevented against a steep voltage change (dv/dt).
- Also, because withstand voltage can be increased by the p-type floating region that is deeper than the p-type base region, while the p-type base region may be shallow, a rise in ON-voltage can also be suppressed by appropriately designing the depth of the p-type base region.
- (Section 12) The semiconductor device according to
section 11, wherein the overlap portion has an end portion positioned on a side closer to the gate trench with respect to a center in a width direction of the emitter trench. - According to this arrangement, a collector-emitter voltage to be applied to the emitter junction trench can be more satisfactorily relieved.
- (Section 13) The semiconductor device according to any one of
sections 1 to 12, wherein the buried insulating film has a thickness of 0.5 μm or more. - (Section 14) The semiconductor device according to any one of
sections 1 to 13, wherein the dummy trench is disposed at an interval of 2 μm or less with the gate trench. - (Section 15) The semiconductor device according to any one of
sections 1 to 14, wherein the n+-type emitter region has an n-type dopant concentration of 1×1019 cm−3 to 5×1020 cm−3. - (Section 16) The semiconductor device according to any one of
sections 1 to 15, wherein the p-type base region has a p-type dopant concentration of 1×1016 cm−3 to 1×1018 cm−3. - (Section 17) The semiconductor device according to any one of
sections 1 to 16, wherein the n−-type drift region has an n-type dopant concentration of 1×1013 cm−3 to 5×1014 cm−3. - (Section 18) The semiconductor device according to any one of
sections 1 to 17, wherein the p+-type collector region has a p-type dopant concentration of 1×1015 cm−3 to 2×1019 cm−3. - Next, the present invention will be described based on examples, but the present invention is not limited by the following examples.
- VCE-ICf characteristics of four types of devices that are mutually different in the interval L1 between the
gate trench 108 and thedummy trench 109 were examined, regarding the structure of thesemiconductor device 101 shown inFIG. 6 , in order to confirm how the effect to improve the trade-off relationship between the short-circuit capacity and ON-voltage (VCE) changes depending on said interval L1. The result is shown inFIG. 11 . InFIG. 11 , device A (trench interval L1=2 μm: alternate long and short dashed line) and device C (trench interval L1=3.5 μm: broken line) are shown. - According to
FIG. 11 , it could be confirmed that the narrower the trench interval L1, the lower VCE(sat) at rising and the lower steady loss (refer to the lower right enlarged view ofFIG. 11 ). Also, it could be confirmed that in a high-current range of ICf, the saturation current density has been lowered by trench miniaturization (a reduction in volume of the p-type base region 111), and the short-circuit capacity has been increased.
Claims (20)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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US17/142,410 US20210126117A1 (en) | 2012-08-21 | 2021-01-06 | Trench-type insulated gate semiconductor device including an emitter trench and an overlapped floating region |
Applications Claiming Priority (10)
Application Number | Priority Date | Filing Date | Title |
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JP2012182169 | 2012-08-21 | ||
JP2012182170 | 2012-08-21 | ||
JP2012-182170 | 2012-08-21 | ||
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US20180337270A1 (en) | 2018-11-22 |
US9543421B2 (en) | 2017-01-10 |
US20170110563A1 (en) | 2017-04-20 |
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US10923582B2 (en) | 2021-02-16 |
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