JP6953499B2 - Semiconductor device - Google Patents

Description

The present invention relates to a semi-conductor device.

_{Conventionally, a trench-type IGBT having a high saturation voltage VCE} (sat) between a collector and an emitter and a high short-circuit tolerance has a p-type floating layer. The p-type floating layer is generally formed in the same process as the p-type base layer. As a result, the p-type floating layer has the same depth as the p-type base layer.

Satoru Machida, Takahide Sugiyama, Masayasu Ishiko, Satoshi Yasuda, Jun Saito, Kimimori Hamada, "Analysis of Relationship between Switching Loss of IGBT and Device Capacity", Materials of the Institute of Electrical Engineers of Japan Electronic Materials Study Group (EFM-09, 16-26, 28- 29), p. 55-59 Satoshi Watanabe, Mutshiro Mori, Daika Arai, Tosuke Ishibashi, Yasushi Toyoda, Tetsuo Oda, Taku Harada, Katsuaki Saito, "Low loss, low noise, highly reliable 1.7kV trench IGBT with floating p-layer separated from the gate" , Institute of Electrical Engineers of Japan Electronic Device Study Group Material (EDD-11,66-83), p. 67-71 Japanese Patent No. 4785334

The semiconductor device according to the embodiment of the present invention includes a semiconductor layer and a tray formed on the semiconductor layer. An embedded electrode embedded in the trench via an insulating film, and the embedded electrode. On the side of the semiconductor layer, the first is arranged in order from the surface side of the semiconductor layer in the depth direction of the trench. The first region of the first conductive type, the second region of the second conductive type, and the first conductive type and the first A third region having an impurity concentration lower than that of one region, and the second region with respect to the trench. Is formed on the opposite side, and the flow of the second conductive type formed deeper than the second region. Conta formed in the ting region and the second region by digging from the surface of the semiconductor layer. It is formed on the bottom surface of the kut trench and the contact trench, and is higher than the second region. Formed on the surface side of the semiconductor layer and the second conductive type contact region having a high impurity concentration. And has entered the contact trench, on the side of the contact trench Connected to the first region and connected to the contact region at the bottom of the contact trench. Includes surface electrodes.

FIG. 1 is a schematic cross-sectional view of the semiconductor device according to the first embodiment of the present invention. FIG. 2 is a perspective view for explaining the internal structure of the semiconductor device of FIG. FIG. 3A is a diagram for explaining a manufacturing process of the semiconductor device of FIG. FIG. 3B is a diagram showing the next step of FIG. 3A. FIG. 3C is a diagram showing the next step of FIG. 3B. FIG. 3D is a diagram showing the next step of FIG. 3C. FIG. 3E is a diagram showing the next step of FIG. 3D. FIG. 3F is a diagram showing the next step of FIG. 3E. FIG. 3G is a diagram showing the next step of FIG. 3F. FIG. 3H is a diagram showing the next step of FIG. 3F. FIG. 3I is a diagram showing the next step of FIG. 3F. FIG. 4 is a schematic cross-sectional view of the semiconductor device according to the second embodiment of the present invention. 5A and 5B are views for explaining the internal structure of the semiconductor device of FIG. 4, FIG. 5A is a perspective view, and FIG. 5B is a plan view. FIG. 6 is a schematic cross-sectional view of the semiconductor device according to the third embodiment of the present invention. FIG. 7 is an enlarged view of the portion surrounded by the broken line in FIG. FIG. 8A is a diagram for explaining a manufacturing process of the semiconductor device of FIG. 7. FIG. 8B is a diagram showing the next step of FIG. 8A. FIG. 8C is a diagram showing the next step of FIG. 8B. FIG. 8D is a diagram showing the next step of FIG. 8C. FIG. 8E is a diagram showing the next step of FIG. 8D. FIG. 8F is a diagram showing the next step of FIG. 8E. FIG. 8G is a diagram showing the next step of FIG. 8F. FIG. 8H is a diagram showing the next step of FIG. 8G. FIG. 8I is a diagram showing the next step of FIG. 8H. FIG. 8J is a diagram showing the next step of FIG. 8I. FIG. 8K is a diagram showing the next step of FIG. 8J. FIG. 9 is a schematic cross-sectional view of the semiconductor device according to the fourth embodiment of the present invention. FIG. 10 is an enlarged view of the portion surrounded by the broken line in FIG. Figure 11 is a graph showing the _V CE _{-I Cf} characteristics of the device.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a schematic cross-sectional view of the semiconductor device 1 according to the first embodiment of the present invention. Figure 2 shows
It is a perspective view for demonstrating the internal structure of the semiconductor device of FIG.
The semiconductor device 1 is a device including an IGBT, and includes a semiconductor substrate 2 as an example of the semiconductor layer of the present invention. The semiconductor substrate 2 has, for example, n ^{− having a thickness of 50 μm to 200 μm.}
It may be a type silicon substrate.

^{The semiconductor substrate 2 has a structure in which a p +} type collector region 4, an n-type buffer region 5, and an n ^- type drift region 6 are laminated in this order from the back surface 3 side. The p ⁺ type collector region 4 is exposed on the entire back surface 3 of the semiconductor substrate 2, and the n ⁻ type drift region 6 is selectively exposed on a part of the front surface 7 of the semiconductor substrate 2.
As ^{the p-type dopant in the p +} type collector region 4, for example, B (boron), Al (aluminum), or the like can be used (hereinafter, the same applies). On the other hand, as the n-type dopant in the n-type buffer region 5 and the n ^- type drift region 6, for example, N (nitrogen), P (phosphorus), As (arsenic) and the like can be used (hereinafter, the same applies).

The dopant concentration in the p ⁺ type collector region 4 is, for example, 1 × 10 ¹⁵ cm ^-3 to
It is 2 × 10 ¹⁹ cm ^-3 . On the other hand, the dopant concentration in the n-type buffer region 5 is, for example, 1 × 10 ¹⁵ cm ^{-3 to} 5 × 10 ¹⁷ cm ^-3 , and ^{the dopant concentration in the n −} drift region 6 is 1 × 10 ¹³ cm ^-3. ~ 5 x 10 ¹⁴ cm ^-3 .
A plurality of gate trenches 8 are formed on the surface 7 side of the semiconductor substrate 2. In this embodiment, the plurality of gate trenches 8 are formed in a striped shape, for example, and are arranged as a pair of trench units 9 in the lateral direction along the surface 7 of the semiconductor substrate 2. _{The pitch P 1} of the trench units 9 adjacent to each other is, for example, 4 μm to 20 μm. Further, in the pair of gate trenches 8, the pitch P between one gate trench 8 and the other gate trench 8
₂ (distance between the center points of the gate trench 8) is, for example, 2 μm to 7 μm, and the interval L ₁ (distance between the side surfaces of the gate trench 8) is, for example, 1 μm to 6 μm.

A p-type base region 10 is formed between the pair of gate trenches 8. The p-type base region 10 is shared by one gate trench 8 and the other gate trench 8. Further, in this embodiment, the interface between the p-type base region 10 and the n ^- type drift region 6 is set in the central portion or the upper portion of the gate trench 8, and the p-type base region 10 is relatively the semiconductor substrate 2. It is shallowly diffused.

In the p-type base region 10, a contact trench 11 dug down from the surface 7 of the semiconductor substrate 2 is formed. The contact trench 11 is formed with a constant width along the longitudinal direction of the gate trench 8. ^{A p +} type base contact region 12 is formed on the bottom surface of the contact trench 11.
^{Further, an n +} type emitter region 13 is formed on the surface portion of the p-type base region 10 between the contact trench 11 and one and the other gate trench 8. One n ⁺ type emitter region 13 is provided on each side of the contact trench 11, and each is exposed on the side surface of the contact trench 11.

The dopant concentration in the p-type base region 10 is, for example, 1 × 10 ¹⁶ cm ^-3 to 1.
× 10 ¹⁸ cm ^-3 . The dopant concentration in the p ⁺ type base contact region 12 is, for example, 5 × 10 ¹⁸ cm ^-3 to 1 × 10 ²⁰ cm ^-3 . The dopant concentration in the n ⁺ type emitter region 13 is 1 × 10 ¹⁹ cm ^{-3 to} 5 × 10 ²⁰ cm ^-3 .
Further, on the surface 7 side of the semiconductor substrate 2, a plurality of gate trenches 8 (FIG. 1) are located between the pair of gate trenches 8.
2) Emitter trenches 14 are formed. In this embodiment, the plurality of emitter trenches 14 are formed, for example, in a striped shape (parallel to the gate trench 8), and are arranged at equal intervals in the lateral direction along the surface 7 of the semiconductor substrate 2. The distance between the emitter trenches 14 adjacent to each other L ₂ (distance between the side surfaces of the emitter trench 14) is, for example, 3 μm or less, preferably 0.8 μm to 3 μm. Further, the plurality of emitter trenches 14 are formed at the same depth as the gate trench 8. As a result, the emitter trench 14 can be formed in the same process as the gate trench 8, so that the manufacturing process can be simplified.

Among the plurality of emitter trench 14, (trench facing without going through the trench between the gate trenches 8) trenches adjacent to the gate trench 8, n between the gate trench 8 ^- via a type drift region 6 2μm are arranged at the following intervals L _{3 (the} distance between the side surfaces of the gate trench 8 of the emitter trench 14). In other words, between said emitter trench 14 and the gate trench 8, across the depth direction throughout the n ^- -type drift region 6 is interposed.

Further, a p-type floating region 15 is formed between each of the plurality of emitter trenches 14. The p-type floating region 15 is a semiconductor region that is electrically maintained in a floating state, and is separated from the gate trench 8 by an emitter trench 14 adjacent to the gate trench 8. In this embodiment, the p-type floating region 15 is formed deeper than the p-type base region 10.

The p-type floating region 15 has a bottom portion 16 that bulges toward the back surface 3 side of the semiconductor substrate 2 with respect to the bottom portion of the emitter trench 14, and an overlapping portion 17 that wraps around below the emitter trench 14 adjacent to the gate trench 8. doing. The overlap portion 17 has an end portion 18 located closer to the gate trench 8 with respect to the center in the width direction of the emitter trench 14. It is preferable that the end portion 18 does not protrude toward the gate trench 8 with respect to the emitter trench 14.

The dopant concentration in the p-type floating region 15 is, for example, 5 × 10 ¹⁵ cm.
^-3 to 1 x 10 ¹⁸ cm ^-3 .
The gate electrode 20 and the embedded electrode 21 are respectively embedded in the gate trench 8 and the emitter trench 14 via an insulating film 19 (for example, silicon oxide (SiO _2)). The gate electrode 20 and the embedded electrode 21 are made of a conductive material such as polysilicon. The insulating film 19 is integrally formed along the inner surface of the gate trench 8, the surface 7 of the semiconductor substrate 2, and the inner surface of the emitter trench 14. The portion of the insulating film 19 in the gate trench 8 functions as the gate insulating film 22. Further, the plurality of embedded electrodes 21 of the emitter trench 14 are electrically connected to the emitter electrode 25 described later.

An interlayer film 23 made of an insulating material such as boron phosphide silicate glass (BPSG) or silicon oxide (SiO _{2) is laminated on the surface 7 of the semiconductor substrate 2.} Interlayer film 23
Is formed with a contact hole 24 that selectively exposes ^{the n +} type emitter region 13 and the p ⁺ type base contact region 12 via the contact trench 11.
The emitter electrode 25 is laminated on the interlayer film 23. The emitter electrode 25 enters the contact trench 11 and is connected to the ^{n + type emitter region 13 on the side surface of the contact trench 11.} Further, on the bottom surface of the contact trench 11, it is connected to the p-type base region 10 via ^{the p + type base contact region 12.}

Next, a method of manufacturing the semiconductor device 1 will be described. 3A to 3I are diagrams for explaining the manufacturing process of the semiconductor device 1 of FIG. 1 in process order.
In order to manufacture the semiconductor device 1, as shown in FIG. 3A, a mask 28 is formed on the surface 7 of ^{the n-} type semiconductor substrate 2 (n ^{-type drift region 6).} The mask 28 has p on the surface 7.
An opening is formed in the mold floating region 15 to selectively expose the region to be formed. Then, the p-type dopant is ion-implanted (implanted) on the surface 7 of the semiconductor substrate 2 through the mask 28. As a result, the ion implantation region 26 is formed.

Next, as shown in FIG. 3B, the semiconductor substrate 2 is selectively etched.
The gate trench 8 and the emitter trench 14 are formed at the same time.
Next, as shown in FIG. 3C, the semiconductor substrate 2 is thermally oxidized to form a sacrificial oxide film 27 on the entire surface including the inner surfaces of the gate trench 8 and the emitter trench 14.
Then, by annealing the semiconductor substrate 2 covered with the sacrificial oxide film 27, the p-type dopant in the ion implantation region 26 is diffused (drive-in). This annealing process
This is done under the condition that the p-type dopant wraps around below the emitter trench 14. This will
A p-type floating region 15 is formed. At this time, since the semiconductor substrate 2 is covered with the sacrificial oxide film 27, it is possible to prevent ion escape from the substrate surface, so that the p-type dopant can be efficiently diffused.

Next, as shown in FIG. 3D, the sacrificial oxide film 27 is peeled off.
Next, as shown in FIG. 3E, the semiconductor substrate 2 is thermally oxidized, so that the insulating film 19 (gate insulating film 22) covers the entire surface including the inner surfaces of the gate trench 8 and the emitter trench 14.
) Is formed.
Next, as shown in FIG. 3F, an electrode material such as polysilicon is embedded in the gate trench 8 and the emitter trench 14. As a result, the gate electrode 20 and the embedded electrode 21
Are formed at the same time.

Next, as shown in FIG. 3G, the p-type base region 10 and the n ⁺ -type emitter region 13 are selectively ion-implanted and diffused with respect to the surface 7 of the semiconductor substrate 2. Are formed in order.
Next, as shown in FIG. 3H, the interlayer film 23 is formed by depositing an insulating material such as boron phosphide silicate glass (BPSG) or silicon oxide (SiO _{2) on the surface 7 of the semiconductor substrate 2.} .. Next, the interlayer film 23 is selectively etched to make the contact hole 2
After the formation of 4, the semiconductor substrate 2 exposed from the contact hole 24 is selectively etched. As a result, the contact trench 11 is formed.

Next, as shown in FIG. 3I, the p-type dopant is selectively ion-implanted and diffused into the bottom of the contact trench 11 through the contact hole 24, thereby p ^+.
A mold base contact region 12 is formed.
After that, the emitter electrode 24 and the like are formed on the surface 7 side of the semiconductor substrate 2, and then the semiconductor substrate 2
^{The n-type buffer region 5 and the p +} -type collector region 4 are sequentially formed by ion-implanting and diffusing the n-type and p-type dopants on the back surface 3 of the above.

By going through the above steps, the semiconductor device 1 shown in FIG. 1 can be obtained. It should be noted that FIGS. 3A to 3I show only a part of the manufacturing process of the semiconductor device 1, and the manufacturing process may include a process not shown in FIGS. 3A to 3I.
According to the semiconductor device 1, the emitter trench 14 in which the embedded electrode 21 is embedded (
Since the p-type floating region 15 (overlapping portion 17) is formed up to the bottom of the “emitter-coupled trench”), the collector-emitter voltage applied to the emitter-emittered trench during the switching off operation can be relaxed. .. Therefore, it is possible to prevent the device from being destroyed by a sudden voltage change (dv / dt).

Further, while the withstand voltage can be improved by the p-type floating region 15 deeper than the p-type base region 10, the p-type base region 10 may be shallow, so that the channel can be channeled by appropriately designing the depth of the p-type base region 10. It is also possible to shorten the length (the length of the gate trench 8 in the depth direction) to suppress an increase in the on-voltage.
Further, the gate trench 8 in which the gate electrode 20 is embedded (hereinafter, referred to as “gate-coupled trench”) is separated from the p-type floating region 15 by the emitter-coupled trench. This makes it possible to prevent the p-type floating region 15 from joining the gate joining trench. Therefore, the stray capacitance between the gate junction trench and the p-type floating region 15 can be eliminated.

^{On the other hand, the n-} type drift region 6 in which the gate joining trench is joined over the entire depth direction.
Is ^{grounded together with the p +} type collector area 4. Therefore, during the switching operation, gate junction trench and the n ^- the capacitance change between the type drift region 6 is stabilized, noise hardly occurs. As a result, it is possible to reduce the generation of noise and the switching loss during the switching operation.

Further, since the distance L between the emitter-coupled trench and the gate-coupled trench is 2 μm or less, the withstand voltage can be well maintained.
Further, since the side surface of the contact trench 11 can be effectively utilized as an area for contact with the n ⁺ -type emitter region 13, the junction area of the emitter electrode 25 for the n ⁺ -type emitter region 13 can be sufficiently ensured .. As a result, the n ⁺ type emitter region 1
Since the flat plane area of 3 can be sacrificed, and refining the gap L ₁ of one and the other of the gate trenches 8 in the pair of gate trenches 8, to form a fine p-type base region 10 as compared with the conventional Can be done. As a result of miniaturization of the gate trench 8, the trade-off relationship between the short-circuit tolerance of the device and the on-voltage can be improved, so that the charge promotion effect can be improved. Therefore, it is possible to improve the _V CE (sat) in the low current range.

FIG. 4 is a schematic cross-sectional view of the semiconductor device 31 according to the second embodiment of the present invention. 5A and 5B are views for explaining the internal structure of the semiconductor device of FIG. 4, and FIG. 5A is a perspective view and FIG. 5A.
(B) shows a plan view, respectively. In FIGS. 4 and 5, the parts corresponding to the parts shown in FIG. 1 described above are designated by the same reference numerals.
In the first embodiment described above, the gate trench 8 is formed as a pair of trench units 9, and a common p-type base region 10 is formed between one and the other gate trench 8. On the other hand, in the semiconductor device 31 of the second embodiment, a plurality of gate trenches 33 formed as one trench unit 32 in the lateral direction along the surface 7 of the semiconductor substrate 2 and both sides of each gate trench 33 ( The p-type base region 34 formed in the region between the emitter trench 14 and the n ⁺ -type emitter region 35 formed on the surface portion of each p-type base region 34 is included. The n ⁺ type emitter region 35 is formed one by one along both side surfaces of the gate trench 33.
It is exposed on the surface 7 of the semiconductor substrate 2.

Further, on the surface portion of the p-type base region 34 ^{, a p +} type base contact region 37 is formed on ^{the side of the n +} type emitter region 35 (opposite side of the gate trench 33). The dopant concentration in the p ⁺ type base contact region 37 is, for example, 5 × 10 ¹⁸ cm ^-3 to 1 × 10 ^{2.
It is 0} cm ^-3 .
As ^{shown in FIGS. 5A and 5B, the n +} type emitter region 35 selectively has a lead-out portion 38 drawn out from the side surface of the gate trench 33 in the lateral direction along the surface 7 of the semiconductor substrate 2. ing. The pull-out portions 38 are arranged at regular intervals along the longitudinal direction of the gate trench 33, for example. A pair of n with respect to the gate trench 33 as in this embodiment.
^{When the +} -type emitter region 35 is provided ^{, one and the other end portions of the drawer portions 38 of each n +} -type emitter region 35 face each other with the gate trench 33 interposed therebetween, as shown in FIG. 5 (b). The ends of one drawer 38 and the ends of the other drawer 38 may be arranged alternately along the longitudinal direction of the gate trench 33 (not shown). .. As a result, the drawer 38 in the ^{p + type base contact area 37}
The portion adjacent to the portion is a sandwich portion 39 whose width is selectively narrower than that of the other portions.

Further, in the interlayer film 23, a p ⁺ type base contact region 37 and an n ⁺ type emitter region 3
A contact hole 36 is formed that selectively exposes the 5. n ⁺ type emitter region 3
In No. 5, the drawer portion 38 is selectively exposed from the contact hole 36. The emitter electrode 25 is connected to the p ⁺ type base contact region 37 and the n ⁺ type emitter region 35 via the contact hole 36.

The semiconductor device 31 can also achieve the same effect as the semiconductor device 1 of the first embodiment.
FIG. 6 is a schematic cross-sectional view of the semiconductor device according to the third embodiment of the present invention. FIG. 7 is an enlarged view of the portion surrounded by the broken line in FIG.
The semiconductor device 101 is a device including an IGBT, and includes a semiconductor substrate 102 as an example of the semiconductor layer of the present invention. The semiconductor substrate 102 is, for example, 50 μm to 200 μm.
^{It may be an n-} type silicon substrate having a thickness of.

^{The semiconductor substrate 102 has a structure in which a p +} type collector region 104, an n-type buffer region 105, and an n ^- type drift region 106 are laminated in this order from the back surface 103 side. The p ⁺ type collector region 104 is exposed on the entire back surface 103 of the semiconductor substrate 102, and the n ⁻ type drift region 106 is selectively exposed on a part of the front surface 107 of the semiconductor substrate 102.
Examples of the p-type dopant in the p ⁺ type collector region 104 include B (boron) and Al.
(Aluminum) etc. can be used (hereinafter the same). On the other hand, as the n-type dopant in the n-type buffer region 105 and the n ^- type drift region 106, for example, N (nitrogen), P (phosphorus), As (arsenic) and the like can be used (hereinafter, the same applies).

The dopant concentration in the p ⁺ type collector region 104 is, for example, 1 × 10 ¹⁵ cm ^{−.
3 to} 2 x 10 ¹⁹ cm ^-3 . On the other hand, the dopant concentration in the n-type buffer region 105 is
For example, 1 × 10 ¹⁵ cm ^{-3 to} 5 × 10 ¹⁷ cm ^-3 , and the n ⁻ type drift region 1
The dopant concentration of 06 is 1 × 10 ¹³ cm ^{-3 to} 5 × 10 ¹⁴ cm ^-3 .
A plurality of gate trenches 108 and a plurality of dummy trenches 109 are formed adjacent to each other on the surface 107 side of the semiconductor substrate 102. In this embodiment, a plurality of trench units 110 including a pair of dummy trenches 109 and a gate trench 108 sandwiched between the pair of dummy trenches 109 are spaced apart in the lateral direction along the surface 107 of the semiconductor substrate 102. Have been placed. As a result, the gate trench 108 and the dummy trench 109
Is formed in a striped shape as a whole.

_{The pitch P 1} of the trench units 110 adjacent to each other is, for example, 2 μm to 7 μm. _{Further, in each trench unit 110, the distance L 1} (distance between the side surface of the gate trench 108 and the side surface of the dummy trench 109) between the gate trench 108 and the dummy trench 109 on both sides thereof is preferably 2 μm or less.
In each trench unit 110, both sides of the gate trench 108 (each dummy trench 10)
A p-type base region 111 is formed in the region between 9 and 9), and a p-type base region 111 is further formed.
^{An n +} type emitter region 112 and a p ⁺ type base contact region 113 are formed on the surface portion of the above (see FIG. 7). In this embodiment, the interface between the p-type base region 111 and the n ^- type drift region 106 is set in the central portion or the upper portion of the gate trench 108, and the p-type base region 111 is relatively shallow in the semiconductor substrate 102. It is diffusely formed.

The n ⁺ type emitter region 112 and the p ⁺ type base contact region 113 are arranged adjacent to each other in the region between the gate trench 108 and the dummy trench 109.
Specifically, one n ⁺ type emitter region 112 is formed along both side surfaces 114 of the gate trench 108, and one p ⁺ type base contact region 113 is formed along the side surface 115 of each dummy trench 109. Has been done. As a result, the n ⁺ type emitter region 112 is exposed on the surface 107 of the semiconductor substrate 102 and the side surface 114 of the gate trench 108.
On the other hand, the p ⁺ type base contact region 113 is exposed on the surface 107 of the semiconductor substrate 102 and the side surface 115 of the dummy trench 109.

The dopant concentration in the p-type base region 111 is, for example, 1 × 10 ¹⁶ cm ^-3 to
It is 1 x 10 ¹⁸ cm ^-3 . The dopant concentration in the n ⁺ type emitter region 112 is 1 × 10.
^{It is 19} cm ^{-3 to} 5 × 10 ²⁰ cm ^-3 . The dopant concentration in the p ⁺ type base contact region 113 is, for example, 5 × 10 ¹⁸ cm ^-3 to 1 × 10 ²⁰ cm ^-3 .
Further, a plurality of (three in FIG. 6) emitter trenches 116 are formed between adjacent trench units 110 on the surface 107 side of the semiconductor substrate 102. In this embodiment, the plurality of emitter trenches 116 are formed, for example, in a stripe shape (parallel to the gate trench 108 and the dummy trench 109), and are arranged laterally along the surface 107 of the semiconductor substrate 102 at equal intervals from each other. There is. Emitter trench 116 adjacent to each other
The interval L ₂ (distance between the side surfaces of the emitter trench 116) is, for example, 3 μm or less, preferably 0.8 μm to 3 μm. Further, the plurality of emitter trenches 116 are formed at the same depth as the gate trench 108 and the dummy trench 109. As a result, the emitter trench 116 can be formed in the same process as the gate trench 108 and the dummy trench 109, so that the manufacturing process can be simplified.

Of the plurality of emitter trenches 116, the trench adjacent to the dummy trench 109 (the trench facing the dummy trench 109 without passing through the trench) has a distance L _{3 of 0.5 μm to 20 μm from the dummy trench 109.} It is arranged at a distance (distance between the side surface of the emitter trench 116 and the side surface of the dummy trench 109).
Further, a p-type floating region 117 is formed on the semiconductor substrate 102. The p-type floating region 117 extends to a region sandwiched between dummy trenches 109 of trench units 110 adjacent to each other via the emitter trench 116. The p-type floating region 117 is a semiconductor region in which the floating state is electrically maintained.
By the dummy trench 109 adjacent to the gate trench 108, the gate trench 108
Is separated from. In this embodiment, the p-type floating region 117 is formed deeper than the p-type base region 111.

The p-type floating region 117 has a bottom portion 118 that bulges toward the back surface 103 side of the semiconductor substrate 102 with respect to the bottom portion of the emitter trench 116, and an overlap portion 119 that wraps around below the dummy trench 109. The overlap portion 119 has an end portion 120 located closer to the gate trench 108 with respect to the center in the width direction of the dummy trench 109. It is preferable that the end portion 120 does not protrude toward the gate trench 108 with respect to the emitter trench 116.

The dopant concentration in the p-type floating region 117 is, for example, 5 × 10 ¹⁵ c.
m ^-3 to 1 × 10 ¹⁸ cm ^-3 .
The gate electrode 122, the first embedded electrode 123, and the second embedded electrode 124 are respectively embedded in the gate trench 108, the dummy trench 109, and the emitter trench 116 _{via an insulating film 121 (for example, silicon oxide (SiO 2)).} There is. The gate electrode 122, the first embedded electrode 123, and the second embedded electrode 124 are made of a conductive material such as polysilicon. The insulating film 121 is integrally formed along the inner surface of the gate trench 108, the inner surface of the dummy trench 109, the surface 107 of the semiconductor substrate 102, and the inner surface of the emitter trench 116. The portion of the insulating film 121 inside the gate trench 108 is
It functions as a gate insulating film 125. Further, the first embedded electrode 123 and the second embedded electrode 124 are electrically connected to the emitter electrode 132 described later.

Further, in this embodiment, the gate electrode 122 and the second embedded electrode 124 backfill the trenches 108 and 116 to the open end, whereas the first embedded electrode 1
Reference numeral 23 is backfilled halfway in the depth direction of the dummy trench 109. As a result, in the dummy trench 109, a space without electrodes is formed in the upper region of the first embedded electrode 123. Then, the embedded insulating film 126 is embedded in the dummy trench 109 so as to fill this space back to the open end.

The embedded insulating film 126 is made of an insulating material such as boron phosphide silicate glass (BPSG) or silicon oxide (SiO ₂ ), and has a thickness of 0.5 μm or more. The embedded insulating film 126 and the insulating film 121 below it have a side surface 115 of the dummy trench 109.
The ^{removal portion 127 that exposes the p +} type base contact region 113 in the above is selectively formed. That is, the embedded insulating film 126 selectively has an upper surface 128 at a position lower than the surface 107 of the semiconductor substrate 102 so as to be connected to the side surface 115 of the dummy trench 109, and is between the upper surface 128 and the surface 107. ^{The p +} type base contact region 113 is exposed in the region of the side surface 115 of the dummy trench 109.

On the surface 107 of the semiconductor substrate 102, for example, boron phosphide silicate glass (BPS)
An interlayer film 129 made of an insulating material such as G) and silicon oxide (SiO _{2) is laminated.}
The interlayer film 129 is integrally formed with the embedded insulating film 126. The interlayer film 129 has
A contact hole 130 is formed so as to straddle the surface 107 of the semiconductor substrate 102 and the open end of the dummy trench 109. ^{The contact hole 130 exposes the n +} type emitter region 112 and the p ⁺ type base contact region 113 on the surface 107 of the semiconductor substrate 102, ^{and the p +} type base contact region 1 on the side surface 115 (removal portion 127) of the dummy trench 109.
13 is exposed. That is, the p ⁺ type base contact region 113 has a surface 107 and a side surface 1.
It is exposed at the corner 131 of the dummy trench 109 formed by the intersection with 15. The n ⁺ type emitter region 112 is formed on the semiconductor substrate 1 from the side surface 114 of the gate trench 108.
It may selectively have a drawer portion drawn out in the lateral direction along the surface 107 of 02, and only this drawer portion may be selectively exposed from the contact hole 130.

An emitter electrode 132 as an example of the contact electrode of the present invention is laminated on the interlayer film 129. The emitter electrode 132 enters the contact hole 130, ^{is connected to the n +} type emitter region 112 on the surface 107 of the semiconductor substrate 102, and is connected to the dummy trench 10
^{It is connected to the p +} type base contact region 113 at the corner 131 of 9.
Next, a method of manufacturing the semiconductor device 101 will be described. 8A to 8K are diagrams for explaining the manufacturing process of the semiconductor device 101 of FIGS. 6 and 7 in order of process. In addition, FIG. 8A ~
8F shows a cross section corresponding to FIG. 6, and FIGS. 8G to 8K show a cross section corresponding to FIG. 7.

To manufacture the semiconductor device 101, as shown in FIG. 8A, the n ^- type semiconductor substrate 102 (
n ^- mask 160 on the surface 107 of the mold drift region 106) is formed. The mask 160 is formed with an opening for selectively exposing a region to be formed in the p-type floating region 117 on the surface 107. Then, the p-type dopant is ion-implanted (implanted) on the surface 107 of the semiconductor substrate 102 through the mask 160. As a result, the ion implantation region 161 is formed.

Next, as shown in FIG. 8B, the gate trench 108, the dummy trench 109, and the emitter trench 116 are simultaneously formed by selectively etching the semiconductor substrate 102.
Next, as shown in FIG. 8C, the semiconductor substrate 102 is thermally oxidized to form a sacrificial oxide film 162 on the entire surface including the inner surfaces of the gate trench 108, the dummy trench 109, and the emitter trench 116. Then, the semiconductor substrate 1 covered with the sacrificial oxide film 162
By annealing 02, the p-type dopant in the ion implantation region 161 is diffused (drive-in). This annealing treatment is performed under the condition that the p-type dopant wraps around below the dummy trench 109. As a result, the p-type floating region 117 is formed. At this time, since the semiconductor substrate 102 is covered with the sacrificial oxide film 162, it is possible to prevent ions from escaping from the surface of the substrate, so that the p-type dopant can be efficiently diffused.

Next, as shown in FIG. 8D, the sacrificial oxide film 162 is peeled off.
Next, as shown in FIG. 8E, the semiconductor substrate 102 is thermally oxidized to form an insulating film 121 (gate insulating film 125) over the entire surface including the inner surfaces of the gate trench 108, the dummy trench 109, and the emitter trench 116. Will be done.
Next, as shown in FIG. 8F, electrode materials such as polysilicon are embedded in the gate trench 108, the dummy trench 109, and the emitter trench 116. As a result, the gate electrode 122, the first embedded electrode 123, and the second embedded electrode 124 are formed at the same time.

Next, as shown in FIG. 8G, the p-type base region 111 and the n ⁺ -type emitter region 112 are selectively ion-implanted and diffused with respect to the surface 107 of the semiconductor substrate 102. Are formed in order.
Next, as shown in FIG. 8H, by etching the first embedded electrode 123 from the upper surface, only the first embedded electrode 123 is selectively selected while maintaining the embedded state of the gate electrode 122 and the second embedded electrode 124. It is dug down.

Next, as shown in FIG. 8I, an insulating material such as boron phosphate glass (BPSG) or silicon oxide (SiO ₂ ) is deposited on the surface 107 of the semiconductor substrate 102 to be above the first embedded electrode 123. The space is backfilled with the insulating material and the surface 10
7 is covered with the insulating material. As a result, the embedded insulating film 126 and the interlayer film 129 are formed at the same time.

Next, as shown in FIG. 8J, the contact hole 130 and the removing portion 127 are formed at the same time by selectively etching the interlayer film 129 and the embedded insulating film 126.
Next, as shown in FIG. 8K, the p-type dopant is selectively ion-implanted and diffused onto the surface 107 of the semiconductor substrate 102 exposed in the contact hole 130. As a result, the p ⁺ type base contact region 113 is formed.

Then, after the emitter electrode 132 and the like are formed on the front surface 107 side of the semiconductor substrate 102, the n-type and p-type dopants are selectively ion-implanted and diffused on the back surface 103 of the semiconductor substrate 102 to form the n-type. Buffer area 105 and p ⁺ type collector area 104
Are formed in order.
By going through the above steps, the semiconductor device 101 shown in FIGS. 6 and 7 can be obtained. It should be noted that FIGS. 8A to 8K show only a part of the manufacturing process of the semiconductor device 101.
The manufacturing process may include steps not shown in FIGS. 8A-8K.

According to the semiconductor device 101, the side surface 115 of the dummy trench 109 ^{can be effectively used as the p +} type base contact region 113, so that the bonding area of the emitter electrode 132 with respect to the p-type base region 111 is set to the surface of the semiconductor substrate 102. Sufficiently can be secured on both sides of the side surface 115 of the 107 and the dummy trench 109. As a result, the plane area of the p-type base region 111 can be sacrificed. Therefore, the distance L1 between the gate trench 108 and the dummy trench 109 is made finer to form the p-type base region 111 which is finer than the conventional _one. can do. Moreover, since the dummy trench 109 can be formed by using the same mask as the gate trench 108, the position shift with respect to the gate trench 108 does not occur. Then, the emitter electrode 132 can be easily aligned because it may be aligned with the area including the plane area of the dummy trench 109.

Specifically, first, the semiconductor substrate 102 is etched using the same mask to simultaneously form the gate trench 108, the dummy trench 109, and the emitter trench 116 (FIG. 8B). Next, the gate electrode 122, the first embedded electrode 123, and the second embedded electrode 124 are formed by embedding polysilicon in these trenches 108, 109, 116 (FIG. 8F). Next, a mask for selectively exposing the dummy trench 109 is formed on the semiconductor substrate 102, and the upper portion of polysilicon in the dummy trench 109 is selectively etched and removed through the mask. As a result, the dummy trench 10
A space is formed in the upper region of the first embedded electrode 123 of No. 9 (FIG. 8H). Then, for example, C
An interlayer film 129 is formed by depositing an insulating material such as BPSG on the semiconductor substrate 102 by the VD method (FIG. 8I). A part of the insulating material enters the dummy trench 109 as an embedded insulating film 126. Next, the mask for forming the contact hole 130 is aligned with the semiconductor substrate 102. At this time, since the end portion of the contact hole 130 may cover the dummy trench 109, the alignment can be performed in a wide area including the surface area 107 of the semiconductor substrate 102 and the plane area of the dummy trench 109. Then, the interlayer film 129 and the embedded insulating film 126 are continuously etched through the mask. As a result, the contact hole 130 and the removal portion 127 are formed at the same time (FIG. 8J). After that, the p-type dopant is ion-implanted using the interlayer film 129 as a mask to p.
^{If the +} type base contact region 113 is formed in a self-aligned manner, the p ⁺ type base contact region 113 can be reliably formed at the corner 131 of the dummy trench 109 (FIG. 8K).
.. Moreover, since the contact hole 130 can be formed relatively wide, a part of the emitter electrode 132 made of aluminum (Al) or the like can be used as a plug without using a plug having a good embedding property such as tungsten (W). Can be done.

As a result of the miniaturization of the trench structure as described above, the trade-off relationship between the short-circuit withstand capability of the device and the on-voltage can be improved, so that the charge promotion effect can be improved. Therefore, it is possible to improve the _V CE (sat) in the low current range.
Further, according to the semiconductor device 101, the gate trench 108 in which the gate electrode 122 is embedded (hereinafter referred to as “gate junction trench”) is embedded with the first embedded electrode 123 connected to the ^{n + type emitter region 112.} It is separated from the p-type floating region 117 by a dummy trench 109 (hereinafter, referred to as “emitter-coupled trench”). This makes it possible to prevent the p-type floating region 117 from joining the gate joining trench. Therefore, the stray capacitance between the gate junction trench and the p-type floating region 117 can be eliminated.

^{On the other hand, the n-} type drift region 106 in which the gate joining trench joins in the depth direction.
Is ^{grounded together with the p +} type collector area 104. Therefore, during the switching operation, gate junction trench and the n ^- the capacitance change between the type drift region 106 is stabilized, noise hardly occurs. As a result, it is possible to reduce the generation of noise and the switching loss during the switching operation.

_{Further, since the distance L 1} between the emitter-coupled trench and the gate-coupled trench is 2 μm or less, the withstand voltage can be well maintained.
Further, according to the semiconductor device 101, since the p-type floating region 117 (overlapping portion 119) is formed up to the bottom of the emitter junction trench, the collector-emitter voltage applied to the emitter junction trench during the switching off operation is relaxed. can do. Therefore, it is possible to prevent the device from being destroyed by a sudden voltage change (dv / dt).

Further, while the withstand voltage can be improved by the p-type floating region 117 deeper than the p-type base region 111, the p-type base region 111 may be shallow, so that the channel can be channeled by appropriately designing the depth of the p-type base region 111. Length (length of gate trench 108 in the depth direction)
Can be shortened to suppress an increase in the on-voltage.
FIG. 9 is a schematic cross-sectional view of the semiconductor device 141 according to the fourth embodiment of the present invention. Figure 1
0 is an enlarged view of the portion surrounded by the broken line in FIG. In FIGS. 9 and 10, the parts corresponding to the parts shown in FIGS. 6 and 7 described above are designated by the same reference numerals.

In the third embodiment described above, the trench unit 110 includes a pair of dummy trenches 109 and a gate trench 108 sandwiched between the pair of dummy trenches 109. On the other hand, the semiconductor device 141 of the fourth embodiment has a trench unit 144 including a pair of gate trenches 142 and a dummy trench 143 sandwiched between the pair of gate trenches 142. In this case, the distance L ₃ (distance between the side surface of the gate trench 142 and the side surface of the emitter trench 116) between the gate trench 142 and the emitter trench 116 is preferably 2 μm or less.

In each trench unit 144, both sides of the dummy trench 143 (each gate trench 14)
A p-type base region 145 is formed in the region between 2 and 2), and a p-type base region 145 is further formed.
^{An n +} type emitter region 146 and a p ⁺ type base contact region 147 are formed on the surface portion of the above (see FIG. 10). In this embodiment, the interface between the p-type base region 145 and the n ^- type drift region 106 is set in the central portion or the upper portion of the gate trench 142, and the p-type base region 145 is relatively shallow in the semiconductor substrate 102. It is diffusely formed.

The n ⁺ type emitter region 146 and the p ⁺ type base contact region 147 are arranged adjacent to each other in the region between the gate trench 142 and the dummy trench 143.
Specifically, one n ⁺ type emitter region 146 is formed along the side surface 148 of each gate trench 142, and one p ⁺ type base contact region 147 is formed along both side surfaces 149 of the dummy trench 143. Has been done. As a result, the n ⁺ type emitter region 146 is exposed on the surface 107 of the semiconductor substrate 102 and the side surface 148 of the gate trench 142.
On the other hand, the p ⁺ type base contact region 147 is exposed on the surface 107 of the semiconductor substrate 102 and the side surface 149 of the dummy trench 143.

Further, a p-type floating region 150 is formed on the semiconductor substrate 102. The p-type floating region 150 extends between each of the plurality of emitter trenches 116. p
The type floating region 150 is a semiconductor region that is electrically maintained in a floating state, and is separated from the gate trench 142 by an emitter trench 116 adjacent to the gate trench 142. The p-type floating region 150 is formed deeper than the p-type base region 145 in this embodiment.

The p-type floating region 150 has a bottom portion 151 that bulges toward the back surface 103 side of the semiconductor substrate 102 with respect to the bottom portion of the emitter trench 116, and an overlapping portion 152 that wraps around below the emitter trench 116 adjacent to the gate trench 142. doing. The overlap portion 152 is a gate trench 14 with respect to the center in the width direction of the emitter trench 116.
It has an end 153 located on the side closer to 2. This end 153 is the emitter trench 1
It is preferable that the gate trench 142 does not protrude from the gate trench 142 side with respect to 16.

Such a p-type floating region 150 can be formed in the same manner as the above-mentioned p-type floating region 117, for example.
The first embedded electrode 154 is embedded in the dummy trench 143 via the insulating film 121. The first embedded electrode 154 is made of a conductive material such as polysilicon.
It is electrically connected to the gate electrode 122. Further, the first embedded electrode 154 is backfilled halfway in the depth direction of the dummy trench 143. As a result, dummy trench 143
In, a space without electrodes is formed in the upper region of the first embedded electrode 154. and,
An embedded insulating film 155 is embedded in the dummy trench 143 so as to fill this space back to the end of the opening.

The embedded insulating film 155 is made of an insulating material such as boron phosphide silicate glass (BPSG) or silicon oxide (SiO ₂ ), and has a thickness of 0.5 μm or more. The embedded insulating film 155 and the insulating film 121 below it have both side surfaces 14 of the dummy trench 143.
A removing portion 156 that exposes the ^{p +} type base contact region 147 in 9 is selectively formed. That is, the embedded insulating film 155 has 149 on both side surfaces of the dummy trench 143.
The upper surface 157 at a position lower than the surface 107 of the semiconductor substrate 102 is selectively provided so as to be continuous with the surface 107, and both side surfaces 149 of the dummy trench 143 between the upper surface 157 and the surface 107 are provided.
The p ⁺ type base contact region 147 is exposed in this region.

A contact hole 158 is formed in the interlayer film 129 so as to straddle the p-type base region 145 facing the dummy trench 143. ^{The contact hole 158 is an n +} type emitter region 146 and a p ⁺ type base contact region 1 on the surface 107 of the semiconductor substrate 102.
^{47 is exposed, and the p +} type base contact region 147 is exposed on both side surfaces 149 (removal portion 156) of the dummy trench 143. That is, the p ⁺ type base contact region 147 is 159 at both corners of the dummy trench 143 formed by the intersection of the surface 107 and the side surface 149.
Is exposed to. The n ⁺ type emitter region 146 is the side surface 14 of the gate trench 142.
8 may selectively have a drawer portion drawn out from the semiconductor substrate 102 in the lateral direction along the surface 107 of the semiconductor substrate 102, and only this drawer portion may be selectively exposed from the contact hole 158.

Then, the emitter electrode 132 enters the contact hole 158 and the semiconductor substrate 10
The surface 107 of 2 ^{is connected to the n +} type emitter region 146, and the both corner portions 159 of the dummy trench 143 are connected to the p ⁺ type base contact region 147.
The semiconductor device 141 can also achieve the same effect as the semiconductor device 101 of the third embodiment.

Although the embodiments of the present invention have been described above, the present invention can also be implemented in other embodiments.
For example, the above features identified from the disclosure of each of the above embodiments can be combined with each other even between different embodiments.
Further, in the above-described embodiment, only the configuration of the IGBT included in the semiconductor devices 1, 31, 101, 141 is shown, but the semiconductor device of the present invention has an element other than the IGBT (for example, MOS).
FETs, diodes, etc.) may be provided in a region different from the region where the IGBT is formed.

In addition, various design changes can be made within the scope of the matters described in the claims.
In addition to the inventions described in the claims, the following features can be extracted from the description of the specification and the drawings.
(Item 1) A semiconductor layer, a gate trench formed in the semiconductor layer, a gate electrode embedded in the gate trench via a gate insulating film, and a predetermined interval formed on the side of the gate trench. ^{In the region between the dummy trench and the gate trench and the dummy trench, an n +} type emitter region, a p-type base region, and a p-type base region arranged in order from the surface side of the semiconductor layer in the depth direction of the gate trench. The n ⁻ type drift region and the n ^{−
A p +} type collector region arranged on the back surface side of the semiconductor layer with respect to the mold drift region, and an embedding that is embedded in the dummy trench and has an upper surface on the bottom side of the dummy trench with respect to the front surface of the semiconductor layer. An insulating film, which is an embedded insulating film that selectively exposes a part of the p-type base region as a contact region on a portion of the side surface of the dummy trench from the surface to the upper surface, and the embedded insulating film of the dummy trench. A semiconductor device comprising a contact electrode embedded in an upper region of a film and connected to the contact region on the side surface of the dummy trench.

According to this configuration, the side surface of the dummy trench can be effectively used as a contact region, so that a sufficient bonding area of the contact electrode with respect to the p-type base region can be secured. As a result, the plane area of the p-type base region can be sacrificed, so that the distance between the gate trench and the dummy trench can be made finer to form a finer p-type base region as compared with the conventional case. Moreover, since the dummy trench can be formed by using the same mask as the gate trench, the position shift with respect to the gate trench does not occur. and,
The contact electrodes can be easily aligned because they may be aligned with the area including the plane area of the dummy trench.

Further, as a result of miniaturization of the trench structure, the trade-off relationship between the short-circuit withstand capability of the device and the on-voltage can be improved, so that the charge promotion effect can be improved. Therefore,
It is possible to improve the _V CE (sat) in the low current range.
(Item 2) The semiconductor device according to Item 1, wherein the semiconductor device further includes a first embedded electrode embedded in a lower region of the embedded insulating film of the dummy trench via an insulating film.

Item 3. The semiconductor device according to Item 2, wherein the semiconductor device has a trench unit including a pair of the dummy trenches and a gate trench sandwiched between the pair of dummy trenches.
(Item 4) The semiconductor device according to Item 3, wherein the first embedded electrode is ^{electrically connected to the n + type emitter region.}
(Item 5) A plurality of the trench units are formed in the lateral direction along the surface of the semiconductor layer, and the semiconductor device includes a plurality of emitter trenches formed between the trench units adjacent to each other and the above. A second embedded electrode embedded in the emitter trench via an insulating film ^{and electrically connected to the n +} type emitter region, the dummy trench in the trench unit, and the dummy trench in the trench unit adjacent to the second embedded electrode. Item 4. The semiconductor device according to Item 4, further comprising a p-type floating region formed between the two.

Item 6. The semiconductor device according to Item 5, wherein the p-type floating region is formed deeper than the p-type base region and includes an overlapping portion that wraps around below the dummy trench.
According to this configuration, a p-type floating region (overlap portion) is formed up to the bottom of a dummy trench (hereinafter referred to as “emitter-coupled trench”) in which the first embedded electrode connected ^{to the n + -type emitter region is embedded.} Therefore, the collector-emitter voltage applied to the emitter junction trench during the switching off operation can be relaxed. Therefore, it is possible to prevent the device from being destroyed by a sudden voltage change (dv / dt).

Further, while the withstand voltage can be improved by the p-type floating region deeper than the p-type base region, the p-type base region may be shallow, so that the on-voltage rise can be increased by appropriately designing the depth of the p-type base region. It can also be suppressed.
Item 7. The semiconductor device according to Item 6, wherein the overlapping portion has an end portion located near the gate trench with respect to the center in the width direction of the dummy trench.

With this configuration, the collector-emitter voltage applied to the emitter junction trench can be relaxed better.
Item 8. The semiconductor device according to Item 2, wherein the semiconductor device has a trench unit including a pair of the gate trenches and a dummy trench sandwiched between the pair of the gate trenches.

Item 9. The semiconductor device according to Item 8, wherein the first embedded electrode is electrically connected to the gate electrode.
(Item 10) A plurality of the trench units are formed in the lateral direction along the surface of the semiconductor layer, and the semiconductor device includes a plurality of emitter trenches formed between the trench units adjacent to each other and the above. A second embedded electrode embedded in the emitter trench via an insulating film ^{and electrically connected to the n +} type emitter region, and a p-type floating region formed between the plurality of emitter trenches are further included. Item 9. The semiconductor device according to Item 9.

(Item 11) The p-type floating region is formed deeper than the p-type base region.
Item 10. The semiconductor device according to Item 10, further comprising an overlapping portion that wraps around below the emitter trench.
According to this configuration, a p-type floating region (overlap portion) is formed up to the bottom of the emitter trench (hereinafter referred to as “emitter-coupled trench”) in which the second embedded electrode connected ^{to the n + type emitter region is embedded.} Therefore, the collector-emitter voltage applied to the emitter-emitter trench during the switching-off operation can be relaxed. for that reason,
It is possible to prevent the device from being destroyed by a sudden voltage change (dv / dt).

Further, while the withstand voltage can be improved by the p-type floating region deeper than the p-type base region, the p-type base region may be shallow, so that the on-voltage rise can be increased by appropriately designing the depth of the p-type base region. It can also be suppressed.
Item 12. The semiconductor device according to Item 11, wherein the overlapping portion has an end portion located near the gate trench with respect to the center in the width direction of the emitter trench.

With this configuration, the collector-emitter voltage applied to the emitter junction trench can be relaxed better.
Item 3. The semiconductor device according to any one of Items 1 to 12, wherein the embedded insulating film has a thickness of 0.5 μm or more.
(Item 14) The semiconductor device according to any one of Items 1 to 13, wherein the dummy trench is arranged between the dummy trench and the gate trench at a distance of 2 μm or less.

(Item 15) The n ⁺ type emitter region is 1 × 10 ¹⁹ cm ^{-3 to} 5 × 10 ²⁰ cm ^-3.
Item 2. The semiconductor device according to any one of Items 1 to 14, which has an n-type dopant concentration of.
(Item 16) The p-type base region is a p of 1 × 10 ¹⁶ cm ^-3 to 1 × 10 ¹⁸ cm ^-3 .
Item 2. The semiconductor device according to any one of Items 1 to 15, which has a type dopant concentration.
(Item 17) The n ^- type drift region is 1 × 10 ¹³ cm ^{-3 to} 5 × 10 ¹⁴ cm ^-3.
Item 2. The semiconductor device according to any one of Items 1 to 16, which has an n-type dopant concentration of.

(Item 18) The p ⁺ type collector region is 1 × 10 ¹⁵ cm ^-3 to 2 × 10 ¹⁹ cm ^-3.
Item 2. The semiconductor device according to any one of Items 1 to 17, which has a p-type dopant concentration of.
(Item 19) A semiconductor layer, a plurality of gate trenches formed in the semiconductor layer, a gate electrode embedded in the plurality of gate trenches via a gate insulating film, and the side of each of the gate trenches. ^{The n +} type emitter region, the p-type base region, and the n ^- type drift region arranged in order from the front surface side of the semiconductor layer in the depth direction of the gate trench, and the back surface of the semiconductor layer with respect to the ^{n-type drift region. The p +} type collector region arranged on the side, a plurality of emitter trenches formed between the plurality of gate trenches adjacent to each other, and the surface portion of the p-type base region, with ^{respect to the n +} type emitter region. ^{A p +} type base contact region formed on the opposite side of the gate trench, an embedded electrode embedded in the plurality of emitter trenches via an insulating film, ^{and electrically connected to the n +} type emitter region, and the plurality. The p-type floating region includes a p-type floating region formed between the emitter trenches of the semiconductor layer and an interlayer film formed on the semiconductor layer. The p-type floating region is formed deeper than the p-type base region, and the plurality of p-type floating regions are formed. ^{The p +} type includes an overlapped portion having an end portion of the emitter trench that wraps around below the emitter trench closest to the gate trench and is located closer to the gate trench with respect to the center in the width direction of the emitter trench. Between the base contact region and the emitter trench, the p-type base region is exposed on the surface of the semiconductor layer, and the interlayer film is ^{the entire n +} type emitter region and the p ⁺ type base. A semiconductor device formed so as to cover a part of a contact area.

According to this configuration, a p-type floating region (overlap portion) is formed up to the bottom of the emitter trench (hereinafter, referred to as “emitter-coupled trench”) in which the embedded electrode is embedded. As a result, the collector-emitter voltage applied to the emitter-emitter trench during the switching-off operation can be relaxed. Therefore, a steep voltage change (dv / dt)
), It is possible to prevent the device from being destroyed.

Further, while the withstand voltage can be improved by the p-type floating region deeper than the p-type base region, the p-type base region may be shallow, so that the channel length can be shortened by appropriately designing the depth of the p-type base region. It is also possible to suppress an increase in the on-voltage.
(Item 20) The p-type floating region may have a bottom portion that bulges toward the back surface side of the semiconductor layer with respect to the bottom portion of the emitter trench.

(Item 21) It is preferable that the emitter trench is formed at the same depth as the gate trench.
In this case, since the emitter trench can be formed in the same process as the gate trench, the manufacturing process can be simplified.
(Item 22) The n ⁺ type emitter region is 1 × 10 ¹⁹ cm ^{-3 to} 5 × 10 ²⁰ cm ^-3.
It may have an n-type dopant concentration of.

(Item 23) The p-type base region is a p of 1 × 10 ¹⁶ cm ^-3 to 1 × 10 ¹⁸ cm ^-3 .
It may have a type dopant concentration.
(Item 24) The n ^- type drift region is 1 × 10 ¹³ cm ^{-3 to} 5 × 10 ¹⁴ cm ^-3.
It may have an n-type dopant concentration of.
(Item 25) The p ⁺ type collector region is 1 × 10 ¹⁵ cm ^-3 to 2 × 10 ¹⁹ cm ^-3.
It may have a p-type dopant concentration of.

(Item 26) It is preferable that the n ⁺ type emitter region selectively has a drawing portion drawn out from the side surface of the gate trench in the lateral direction along the surface of the semiconductor layer.
(Item 27) A semiconductor layer, a plurality of gate trenches formed in the semiconductor layer, a gate electrode embedded in the plurality of gate trenches via a gate insulating film, and the side of each of the gate trenches. ^{The n +} type emitter region, the p-type base region, and the n ^- type drift region arranged in order from the front surface side of the semiconductor layer in the depth direction of the gate trench, and the back surface of the semiconductor layer with respect to the ^{n-type drift region. The n +} type collector region arranged on the side, a plurality of emitter trenches formed between the plurality of gate trenches adjacent to each other, and the plurality of emitter trenches embedded via an insulating film, the n ⁺ type. ^{The n +} -type emitter region, the p-type base region, and the p-type floating region formed between the plurality of emitter trenches, the embedded electrode electrically connected to the emitter region, and the gate trench. wherein n ^- way type drift region is formed, and the dummy trench formed at a predetermined interval laterally of said gate trench, buried in the dummy trench, wherein with respect to said surface of said semiconductor layer An embedded insulating film having an upper surface on the bottom side of the dummy trench, which selectively exposes a part of the p-type base region as a contact region on a portion of the side surface of the dummy trench from the surface to the upper surface. The p-type floating region includes a film and a contact electrode embedded in an upper region of the embedded insulating film of the dummy trench and connected to the contact region on the side surface of the dummy trench, and the p-type floating region is the p-type base region. An over having an end formed deeper than the plurality of emitter trenches, wrapping around below the emitter trench closest to the gate trench among the plurality of emitter trenches, and located closer to the gate trench with respect to the center in the width direction of the emitter trench. A semiconductor device including a wrap portion.

According to this configuration, the side surface of the dummy trench can be effectively used as a contact region, so that a sufficient bonding area of the contact electrode with respect to the p-type base region can be secured. As a result, the plane area of the p-type base region can be sacrificed, so that the distance between the gate trench and the dummy trench can be made finer to form a finer p-type base region as compared with the conventional case. Moreover, since the dummy trench can be formed by using the same mask as the gate trench, the position shift with respect to the gate trench does not occur. and,
The contact electrodes can be easily aligned because they may be aligned with the area including the plane area of the dummy trench.

Further, as a result of miniaturization of the trench structure, the trade-off relationship between the short-circuit withstand capability of the device and the on-voltage can be improved, so that the charge promotion effect can be improved. Therefore,
It is possible to improve the _V CE (sat) in the low current range.
(Item 28) The semiconductor device may further include a first embedded electrode embedded in the lower region of the embedded insulating film of the dummy trench via the insulating film.

(Item 29) The semiconductor device may have a trench unit including a pair of the dummy trenches and a gate trench sandwiched between the pair of dummy trenches.
(Item 30) It is preferable that the dummy trench also serves as the emitter trench by electrically connecting ^{the first embedded electrode to the n + type emitter region.}
(Item 31) The semiconductor device may have a trench unit including a pair of the gate trenches and a dummy trench sandwiched between the pair of the gate trenches.

In this case, (Item 32), the first embedded electrode is preferably electrically connected to the gate electrode.
(Item 33) The embedded insulating film preferably has a thickness of 0.5 μm or more.

Next, the present invention will be described based on examples, but the present invention is not limited to the following examples.
Regarding the structure of the semiconductor device 101 shown in FIG. 6, the _{effect of improving the trade-off relationship between the short-circuit withstand voltage and the on-voltage (VCE} ) is the effect of improving the distance L between the gate trench 108 and the dummy trench 109.
To see how it changed by _1, the distance _{L 1} was examined _V CE _{-I Cf} characteristics of four different devices. The results are shown in FIG. In FIG. 11, device A (trench spacing L ₁ = 2 μm alternate long and short dash line) and device C (trench spacing L ₁ = 3).
.. 5 μm dashed line).

According to FIG. 11, the narrower the trench distance _{L 1,} the rise of the _V CE (sat) is low, it steady loss is low it can be confirmed (see the lower right enlarged view of FIG. 11). Further, in _{the high current region of ICf} , it was confirmed that the saturation current density was lowered due to the miniaturization of the trench (volume reduction of the p-type base region 111), and the short-circuit tolerance was improved.

1 Semiconductor device 2 Semiconductor substrate 3 Back surface 4 p ⁺ type collector area 5 n type buffer area 6 n ⁻ type drift area 7 Front surface 8 Gate trench 10 p type base area 13 n ⁺ type emitter area 14 Emitter trench 15 p type floating area 16 Bottom 17 Overlapping 18 End 19 Insulating film 20 Gate electrode 21 Embedded electrode 22 Gate insulating film 31 Semiconductor device 33 Gate trench 34 p-type base area 35 n ⁺ type emitter area 38 Draw-out part 101 Semiconductor device 102 Semiconductor substrate 103 Back side 104 p ⁺ type collector area 106 n ⁻ type drift area 107 Surface 108 Gate trench 109 Dummy trench 110 Trench unit 111 p type base area 112 n ⁺ type emitter area 113 p ⁺ type base contact area 114 Side side 115 Side surface 116 Emitter trench 117 p type Floating region 118 Bottom 119 Overlapping 120 End 121 Insulating film 122 Gate electrode 123 1st embedded electrode 124 2nd embedded electrode 125 Gate insulating film 126 Embedded insulating film 127 Removal part 128 Top surface 132 Emitter electrode 141 Semiconductor device 142 Gate trench 143 Dummy trench 144 Trench unit 145 p-type base area 146 n ⁺ type emitter area 147 p ⁺ type base contact area 148 Side 149 Side 150 p-type floating area 151 Bottom 152 Overlap 153 End 154 First embedded electrode 155 Embedded insulating film 156 Removal part 157 Top surface 159 Corner part

Claims (10)

With the semiconductor layer
The trench formed in the semiconductor layer and
An embedded electrode embedded in the trench via an insulating film,
On the side of the embedded electrode, a first region of the first conductive type, a second region of the second conductive type, and the first conductive type arranged in order from the surface side of the semiconductor layer in the depth direction of the trench. And a third region having an impurity concentration lower than that of the first region,
The second conductive type floating region formed on the side opposite to the second region with respect to the trench and formed deeper than the second region.
A contact trench formed in the second region by digging from the surface of the semiconductor layer,
The second conductive type contact region formed on the bottom surface of the contact trench and having a higher impurity concentration than the second region,
A surface electrode formed on the surface side of the semiconductor layer and entering the contact trench, connected to the first region on the side surface of the contact trench, and connected to the contact region on the bottom surface of the contact trench. Including
The contact trench, the bottom portion is a flat shape, and as the contact area is in contact with the bottom of the bottom portion and the contact trench of the first region, than the bottom of the bottom of said contact trench the first region Formed to be deep,
A semiconductor device in which the bottom of the second region is formed shallower than the trench. The semiconductor device according to claim 1, wherein the floating region is formed deeper than the bottom of the trench. The semiconductor device according to claim 1 or 2, wherein the insulating film extends out of the trench and covers the first region on the surface of the semiconductor layer. The semiconductor device according to claim 3, wherein the end surface of the insulating film is connected to the side surface of the contact trench. Further including an interlayer film formed on the semiconductor layer and having an opening including a side surface connected to the end surface of the insulating film.
The semiconductor device according to claim 4, wherein the surface electrode enters the contact trench through the opening of the interlayer film. The semiconductor device according to any one of claims 1 to 5, wherein the contact region is formed so as to extend laterally from the width of the contact trench. A fourth region of the second conductive type arranged on the back surface side of the semiconductor layer with respect to the third region,
The invention according to any one of claims 1 to 6, wherein the first conductive type buffer layer formed between the third region and the fourth region and having a higher impurity concentration than the third region is included. The semiconductor device described. The semiconductor device according to any one of claims 1 to 7, wherein the surface electrode selectively has a recess in a portion on the contact trench. The invention according to any one of claims 1 to 8, wherein a recess recessed in the trench in the upper surface of the embedded electrode is formed in the trench with respect to the surface of the semiconductor layer in the depth direction of the trench. Semiconductor device. The semiconductor device according to any one of claims 1 to 9, wherein the first conductive type is an n-type and the second conductive type is a p-type.

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