JP6726402B2 - Semiconductor device - Google Patents

Description

The present invention relates to a trench gate type semiconductor device.

Power MOSFETs, insulated gate bipolar transistors (IGBTs), and the like are used as switching elements (power semiconductor elements) that perform large-current switching operations. In these switching elements, a trench type gate electrode structure (trench gate type) in which a gate insulating film and a gate electrode are formed in a groove (trench) formed in a semiconductor substrate is adopted. However, in the trench gate type semiconductor device, the feedback capacitance such as the capacitance between the gate electrode and the drain region (gate-drain capacitance) and the capacitance between the gate electrode and the collector region (gate-collector capacitance) are large. As a result, the switching speed is reduced and problems occur in high frequency operation.

Various methods have been investigated to reduce the feedback capacitance. For example, a structure in which a gate electrode is arranged on the side surface of the groove and an electrode connected to the emitter electrode is arranged on the bottom surface of the groove is disclosed (for example, refer to Patent Document 1).

JP, 2015-201615, A

However, the reduction of the feedback capacitance is not sufficient in the above structure. Therefore, an object of the present invention is to provide a trench gate type semiconductor device in which the feedback capacitance generated at the bottom surface of the groove is reduced.

According to one aspect of the present invention, a first semiconductor region of the first conductivity type, a second semiconductor region of the second conductivity type disposed on the first semiconductor region, and a second semiconductor region disposed on the second semiconductor region. A third semiconductor region of the first conductivity type, an inner wall insulating film disposed on an inner wall of a groove extending from an upper surface of the third semiconductor region and penetrating the third semiconductor region and the second semiconductor region, and a second semiconductor region A control electrode disposed on the inner wall insulating film on the side surface of the groove facing the side surface of the groove, a bottom electrode disposed on the inner wall insulating film on the bottom surface of the groove and insulated from the control electrode, and a control electrode. An interlayer insulating film provided between the bottom electrode and the bottom electrode of the control electrode is provided so that the distance from the corner end of the groove on the bottom surface of the control electrode to the bottom surface of the trench is from the top surface of the bottom electrode on the side facing the control electrode. A semiconductor device is provided which is shorter than the distance to the bottom surface of the control electrode, and at least the position of the lower surface of the control electrode facing the bottom electrode is higher than the position of the upper surface of the bottom electrode on the control electrode side .

According to the present invention, it is possible to provide a trench gate type semiconductor device in which the feedback capacitance generated at the bottom surface of the groove is reduced.

It is a typical sectional view showing the structure of the semiconductor device concerning the embodiment of the present invention. It is a schematic diagram which shows the internal structure of the groove|channel of the semiconductor device which concerns on embodiment of this invention. FIG. 6 is a schematic process cross-sectional view for explaining the manufacturing method of the semiconductor device according to the embodiment of the present invention (No. 1). FIG. 6 is a schematic process cross-sectional view for explaining the manufacturing method of the semiconductor device according to the embodiment of the present invention (No. 2). FIG. 4 is a schematic process cross-sectional view for explaining the manufacturing method of the semiconductor device according to the embodiment of the present invention (No. 3). FIG. 6 is a schematic process cross-sectional view for explaining the manufacturing method of the semiconductor device according to the embodiment of the present invention (No. 4). FIG. 6 is a schematic process cross-sectional view for explaining the manufacturing method of the semiconductor device according to the embodiment of the present invention (No. 5). FIG. 6 is a schematic process cross-sectional view for explaining the method for manufacturing the semiconductor device according to the embodiment of the present invention (No. 6). FIG. 7 is a schematic process cross-sectional view for explaining the manufacturing method of the semiconductor device according to the embodiment of the present invention (No. 7). It is a typical process sectional view for explaining the manufacturing method of the semiconductor device concerning the embodiment of the present invention (the 8). It is a schematic diagram which shows the other structure inside the groove|channel of the semiconductor device which concerns on embodiment of this invention. It is a schematic diagram which shows the other structure of the interlayer insulation film of the semiconductor device which concerns on embodiment of this invention. It is a typical sectional view showing the structure of the semiconductor device concerning the modification of the embodiment of the present invention. It is a typical sectional view showing the structure of the semiconductor device concerning other embodiments of the present invention. It is a typical sectional view showing the structure of the semiconductor device concerning other embodiments of the present invention. It is a typical sectional view showing the structure of the semiconductor device concerning other embodiments of the present invention. It is a schematic diagram which shows the other structure inside the groove|channel of the semiconductor device which concerns on embodiment of this invention. It is a schematic diagram which shows the other structure inside the groove|channel of the semiconductor device which concerns on embodiment of this invention.

Next, an embodiment of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar reference numerals are given to the same or similar parts. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the plane dimension, the ratio of the length of each portion, and the like are different from the actual ones. Therefore, specific dimensions should be determined in consideration of the following description. Further, it is needless to say that the drawings include portions in which dimensional relationships and ratios are different from each other.

Further, the embodiments described below exemplify devices and methods for embodying the technical idea of the present invention, and the technical idea of the present invention is that the shape, the structure, the arrangement, etc. of the components are Not specific to: The embodiments of the present invention can be modified in various ways within the scope of the claims.

As shown in FIG. 1, the semiconductor device according to the embodiment of the present invention includes a first conductive type first semiconductor region (drift region 10) and a second conductive type first semiconductor region disposed on the first semiconductor region. Two semiconductor regions (base region 20) and a third semiconductor region (emitter region 30) of the first conductivity type disposed on the second semiconductor region are provided. A groove is formed extending from the upper surface of the third semiconductor region, penetrating the third semiconductor region and the second semiconductor region to reach the first semiconductor region, and the inner wall insulating film 40 is arranged on the inner wall of the groove.

The groove extends along the main surface of the stacked body of the semiconductor region, and the length of the groove in the extending direction is longer than the width W of the groove. FIG. 1 shows a cross section perpendicular to the extending direction of the groove.

The semiconductor device shown in FIG. 1 is a trench gate type IGBT having a control electrode (gate electrode 50) arranged on the inner wall insulating film 40 on the side surface of the groove facing the side surface of the base region 20. .. As shown in FIG. 1, the bottom electrode 150 side of the lower surface of the gate electrode 50 is not in contact with the inner wall insulating film 40 on the bottom surface of the groove. Further, the semiconductor device includes a bottom electrode 150 that is insulated from the gate electrode 50 and is disposed on the inner wall insulating film 40 on the bottom surface of the groove. The bottom electrode 150 is electrically connected to the emitter region 30.

The first conductivity type and the second conductivity type are opposite conductivity types. That is, if the first conductivity type is n-type, the second conductivity type is p-type, and if the first conductivity type is p-type, the second conductivity type is n-type. Hereinafter, a case where the first conductivity type is n-type and the second conductivity type is p-type will be described as an example.

As shown in FIG. 1, provided on the bottom electrode 150 between the gate electrode 50 and the bottom electrode 150 and between the bottom surface of the gate electrode 50 and the inner wall insulating film 40, and the interlayer insulation is provided in the gap inside the groove. Membrane 70 is embedded. The interlayer insulating film 70 insulates and separates the gate electrode 50 and the bottom electrode 150. In the semiconductor device, the distance from the lower surface of the gate electrode 50 to the bottom surface of the groove (hereinafter, referred to as “first distance d1”) is the distance from the lower surface of the bottom electrode 150 to the bottom surface of the groove (hereinafter, “first distance d1”). 2 distance d2") or the first distance d1 and the second distance d2 are equal. That is, the thickness of the insulating film between the gate electrode 50 and the drift region 10 below the gate electrode 50 (the total thickness of the inner wall insulating film 40 and the interlayer insulating film 70 in FIG. 1) is the bottom surface below the bottom electrode 150. It is thicker than or equal to the thickness of the insulating film between the electrode 150 and the drift region 10 (the thickness of the inner wall insulating film 40 in FIG. 1).

Drift region 10 is arranged on one main surface of p type collector region 60. An n-type field stop region 65 having an impurity concentration higher than that of the drift region 10 is arranged between the drift region 10 and the collector region 60. The field stop region 65 limits the amount of holes that reach the drift region 10 from the collector region 60 when the semiconductor device is on. Further, the depletion layer extending from the upper surface of the drift region 10 in the off state of the semiconductor device is suppressed from reaching the collector region 60. A collector electrode 80 electrically connected to collector region 60 is arranged on the other main surface of collector region 60.

A gate electrode 50 is arranged with an inner wall insulating film 40 facing the base region 20 interposed therebetween. An emitter region 30 is selectively arranged above the base region 20. The emitter electrode 90 is arranged on the interlayer insulating film 70, and the emitter electrode 90 connects to the base region 20 and the emitter region 30. The interlayer insulating film 70 electrically insulates the gate electrode 50 and the emitter electrode 90.

In the semiconductor device shown in FIG. 1, the surface of the base region 20 facing the gate electrode 50 via the inner wall insulating film 40 is a channel region in which a channel is formed. That is, the region of the inner wall insulating film 40 between the gate electrode 50 and the base region 20 functions as a gate insulating film. The gate electrode 50 is arranged at least opposite to the base region 20 so that a channel is formed in the base region 20 along the groove from the emitter region 30 to the drift region 10. Furthermore, the end of the gate electrode 50 on the corner side of the groove (the end on the side surface of the groove) extends to a position lower than the position where the interface between the base region 20 and the drift region 10 intersects the side surface of the groove, that is, extends to above the drift region 10. It is desirable to be doing. As a result, a channel is reliably formed in the base region 20 along the groove from the emitter region 30 to the drift region 10, and the semiconductor device can be reliably turned on.

As shown in FIG. 1, the gate electrode 50 is arranged on each of the opposite side surfaces of the inner wall of the groove. Then, in the cross section perpendicular to the extending direction of the groove, the gate electrode 50 is not continuously arranged along the inner wall of the groove, and the gate electrode 50 is not arranged on the bottom surface of the groove.

Here, the operation of the semiconductor device shown in FIG. 1 will be described. A predetermined collector voltage is applied between the emitter electrode 90 and the collector electrode 80, and a predetermined gate voltage is applied between the emitter electrode 90 and the gate electrode 50. For example, the collector voltage is about 300V to 1600V, and the gate voltage is about 10V to 20V. When the semiconductor device is turned on in this way, the channel region is inverted from p-type to n-type to form a channel. Electrons are injected from the emitter electrode 90 into the drift region 10 through the formed channel. Forward bias is applied between the collector region 60 and the drift region 10, and holes move from the collector electrode 80 through the collector region 60 to the drift region 10 and the base region 20 in this order. When the current is further increased, holes from the collector region 60 increase and holes are accumulated below the base region 20. As a result, the ON voltage decreases due to conductivity modulation.

When the semiconductor device is turned off, the gate voltage is controlled to be lower than the threshold voltage. For example, the gate voltage is set to the same potential as the emitter voltage or a negative potential. As a result, the channel of the base region 20 disappears, and the injection of electrons from the emitter electrode 90 into the drift region 10 is stopped. Since the potential of the collector electrode 80 is higher than that of the emitter electrode 90, the depletion layer spreads from the interface between the base region 20 and the drift region 10, and the holes accumulated in the drift region 10 escape to the emitter electrode 90. .. At this time, the holes move through the semiconductor region between the grooves. That is, the region between the grooves is the hole outlet.

Conventionally, in a trench gate type semiconductor device, there has been a problem that a discharge occurs between an end of a gate electrode and an end of a bottom electrode to cause a malfunction. However, in the semiconductor device shown in FIG. 1, the width of the groove is larger than the depth of the groove, and the bottom surface of the groove is relatively flat throughout. The position of at least the lower surface of the gate electrode 50 facing the bottom electrode 150 is above the position of the upper surface of the bottom electrode 150 on the gate electrode 50 side. The distance from at least the bottom surface of the gate electrode 50 facing the bottom surface electrode 150 to the bottom surface of the groove is longer than the distance from the bottom surface of the bottom surface electrode 150 facing the gate electrode 50 to the bottom surface of the groove. As a result, it is possible to reduce the occurrence of a discharge between the end of the gate electrode and the end of the bottom electrode and malfunction.

Further, in the semiconductor device shown in FIG. 1, the gate electrode 50 is not arranged on the bottom surface of the groove, and the distance between the lower surface of the gate electrode 50 and the groove is the distance between the side surface of the gate electrode 50 and the groove. It is desirable to be larger than. Therefore, the feedback capacitance (gate-collector capacitance) between the gate electrode 50 and the collector region 60 can be reduced.

Further, by disposing the bottom electrode 150 having the same potential as the emitter region 30 on the bottom surface of the groove, the semiconductor device functions as a field plate in the off state, and the depletion layer is satisfactorily spread from the bottom of the groove to the drift region 10. be able to. Further, by arranging the bottom surface electrode 150 on the bottom surface of the groove, the feedback capacitance between the gate and the collector is further reduced as compared with the case where the gate electrode 50 is provided in the entire groove. In order to electrically connect the bottom electrode 150 to the emitter region 30, for example, a through hole is provided in the interlayer insulating film 70 buried in the groove, and the through hole is filled with a conductor film to form the bottom electrode 150 and the emitter. The electrode 90 is electrically connected. The through hole may be provided in at least a part of the active region, or may be provided in the end portion of the bottom electrode 150 (outer peripheral side of the semiconductor device).

Further, in the semiconductor device shown in FIG. 1, it is desirable that the first distance d1 below the gate electrode 50 be longer than the second distance d2 below the bottom electrode 150. That is, the distance between the gate electrode 50 and the collector region 60 is wide, which allows the feedback capacitance between the gate and the collector to be further reduced.

As described above, in the semiconductor device shown in FIG. 1, the feedback capacitance generated at the bottom surface of the groove is reduced. As a result, the switching time of the semiconductor device can be shortened.

Further, by making the first distance d1 longer than the second distance d2, as shown in FIG. 2, the distance between the end 51 of the gate electrode 50 and the end 151 of the bottom electrode 150, and the gate electrode 50. The distance between the end 51 and the corner 101 of the groove (the boundary between the bottom surface and the side surface of the groove) increases. As a result, discharge is generated between the end 51 of the gate electrode 50 and the end 151 of the bottom electrode 150, and discharge is generated between the end 51 of the gate electrode 50 and the groove corner 101. Can be suppressed. Therefore, the electrical characteristics of the semiconductor device shown in FIG. 1 can be stabilized.

Since the gate electrode 50 and the bottom surface electrode 150 are arranged apart from each other, the breakdown voltage of the corner portion 101 of the groove is lowered due to the position separated from these electrodes. In order to suppress the decrease in breakdown voltage, it is preferable that the gate electrode 50 is arranged near the corner portion 101 of the groove. Therefore, as shown in FIG. 2, the position of the lower surface of the gate electrode 50 is preferably lower than the position of the upper surface of the bottom electrode 150.

In addition, as shown in FIG. 2, the inner wall insulating film is formed such that the film thickness of the region arranged on the bottom surface of the groove is larger than the film thickness of the region arranged on the side surface of the groove and facing the base region 20. It is preferable to form 40. When the width of the gate electrode 50 is widened, the parasitic capacitance generated between the gate electrode 50 and the semiconductor region on the bottom surface of the groove tends to increase. However, this parasitic capacitance can be reduced by increasing the film thickness of the inner wall insulating film 40 on the bottom surface of the groove.

However, since the region of the inner wall insulating film 40 arranged on the side surface of the groove functions as a gate insulating film, there is a limit in increasing the thickness of the inner wall insulating film 40 on the side surface of the groove. Therefore, the film thickness of the region of the inner wall insulating film 40 arranged on the bottom surface of the groove is made thicker than the film thickness of the region of the inner wall insulating film 40 arranged on the side surface of the groove. For example, the film thickness of the inner wall insulating film 40 on the bottom surface of the groove is about 300 nm, and the film thickness on the side surface of the groove is about 150 nm.

By the way, as the width W of the groove in which the gate electrode 50 is arranged is wider to a certain extent, the ON voltage of the semiconductor device is lowered and the breakdown voltage is improved, as described below. The width W of the groove in this case is, for example, about 3 μm to 20 μm.

First, the reason why the on-voltage decreases will be described. When the semiconductor device is turned on, electrons that have moved mainly from the emitter electrode 90 along the side surface of the groove through the channel formed in the channel region are injected into the drift region 10. The thickness of the drift region 10 below the bottom surface of the groove is, for example, 30 μm to 180 μm, which is sufficiently wider than the width W of the groove. Therefore, even if the width W of the groove is increased, the electrons moved along the groove are diffused in the drift region 10 in a region deeper than the groove. As a result, not only the interface between the collector region 60 and the drift region 10 immediately below the region between the trenches, but also the interface between the collector region 60 and the drift region 10 becomes a forward bias in a wider range than that, and holes from the collector region 60 become Move to the drift region 10.

The holes that have moved from the collector region 60 are prevented from moving by the bottom surface of the groove, the holes are accumulated in the drift region 10 near the bottom surface of the groove, and conductivity modulation occurs. The wider the width W of the groove, the more easily holes are accumulated in the drift region 10 near the bottom surface of the groove. As a result, the number of holes that move to the emitter electrode 90 decreases, and the on-voltage decreases.

If the distance S between the grooves is wide, the amount of holes that do not accumulate below the base region 20 and move to the base region 20 increases, or the chip area increases. Therefore, it is preferable that the width W of the groove is wider than the interval S in order to reduce the on-voltage.

Next, the reason why the breakdown voltage of the semiconductor device is improved by increasing the width W of the groove will be described. When the semiconductor device is switched from the ON state to the OFF state, the depletion layer spreads in the drift region 10 not only from the PN junction with the base region 20 but also from the periphery of the bottom surface of the groove. At this time, it is preferable that the depletion layer spreads uniformly and spreads over a wider range. When the depletion layer spreads unevenly or narrowly, the breakdown voltage decreases. When the width W of the groove is narrow, since the corner portions 101 of the groove, which are electric field concentration points, are close to each other, the depletion layer does not spread well and evenly over a wide area immediately below the bottom surface of the groove. However, when the width W of the groove is wide, since the corner portions 101 of the groove are distant from each other, the depletion layer immediately below the bottom surface of the groove between the corner portions 101 spreads more uniformly or in a wider area. Therefore, the breakdown voltage is improved in a semiconductor device having a wide groove width W.

Further, the breakdown voltage of the semiconductor device is improved by making the interval S between the grooves relatively narrow. This is for the following reason. That is, the depth of the depletion layer in the region between the trenches is shallower than the depth of the depletion layer immediately below the trench. When the distance S is wide, the depletion layer extending from the PN junction with the base region 20 in the region between the trenches is further flattened. Therefore, the portion where the depletion layer on the bottom surface of the groove is continuous with the depletion layer extending from the side surface of the groove has a more distorted shape. As a result, the electric field concentrates near the corner portion 101 of the groove, which is the distorted portion of the depletion layer, and the breakdown voltage decreases. Therefore, it is preferable that the space S is narrow to some extent, and for example, the space S is narrower than the width W of the groove.

As described above, in the semiconductor device shown in FIG. 1, it is preferable that the width W of the groove is wide and the interval S is narrow. For example, the groove is formed such that the length of the groove in the longitudinal direction in which the groove extends is longer than the width W of the groove in a plan view, and the width W of the groove is wider than the interval S between adjacent grooves.

When the width W of the groove is wide, the feedback capacitance between the gate and the collector tends to increase. However, in the semiconductor device shown in FIG. 1, the feedback capacitance between the gate and the collector can be reduced by disposing the capacitance portion using the bottom electrode 150 on the bottom surface of the groove.
Here, the width of the bottom electrode 150 is preferably larger than the thickness of the bottom electrode 150. This makes it possible to bring the gate electrode 50 closer to the corner portion 101 of the groove while suppressing the portion where the gate electrode 50 faces the bottom electrode 150. As a result, the breakdown voltage can be secured while suppressing the capacitance between the gate and the emitter.

By the way, since the chip area is limited, if the width W of the groove is increased when the chip size is fixed, the number of channels decreases. At this time, when the ratio of the channel region to the chip size of the semiconductor device decreases to a certain extent, the saturation voltage between the collector and the emitter increases. Therefore, if the effect of increasing the on-voltage due to the decrease in the number of channels is larger than the effect of accumulating holes and decreasing the on-voltage by increasing the width W of the groove, the on-voltage of the semiconductor device increases.

As a result of the studies made by the present inventors from the above viewpoint, the width W of the groove is preferably about 3 μm to 20 μm. Furthermore, it is more preferable that the width W of the groove is about 5 μm to 13 μm. According to the studies by the present inventors, the ON voltage is most effectively reduced when the width W of the groove is about 7 μm. Since the depth of the groove is generally about 5 μm, as a result of widening the width W of the groove, the width W of the groove may be larger than the depth of the groove.

As described above, in the semiconductor device according to the embodiment of the present invention, the first distance d1 from the lower surface of the gate electrode 50 to the bottom surface of the groove is the second distance from the lower surface of the bottom electrode 150 to the bottom surface of the groove. It is longer than the distance d2. Thereby, the feedback capacitance between the gate and the collector can be further reduced. As a result, the switching speed of the semiconductor device is improved. Further, it is possible to suppress the occurrence of discharge inside the semiconductor device. This stabilizes the electrical characteristics. Further, by increasing the width W of the groove, a semiconductor device having a high breakdown voltage and a low on-voltage can be realized.

A method of manufacturing a semiconductor device according to the embodiment of the present invention will be described with reference to FIGS. 3 to 10 illustrate a region including one groove. The manufacturing method described below is an example, and it goes without saying that it can be realized by various manufacturing methods including this modified example.

As shown in FIG. 3, p ⁻ is formed on the n ⁻ type drift region 10 formed on the stacked body of the p ⁺ type collector region 60 and the n ⁺ type field stop region 65 by the impurity diffusion method or the epitaxial growth method. ^- -type base region 20. For example, according to the impurity diffusion method, after the p-type impurity is injected into the drift region 10 from the upper surface of the drift region 10, diffusion is performed by an annealing process to form the base region 20 with a substantially uniform thickness. The p-type impurity in the base region 20 is, for example, boron (B). Next, as shown in FIG. 4, an n ⁺ -type emitter region 30 is selectively formed on a part of the upper surface of the base region 20 by using, for example, ion implantation and diffusion.

After that, as shown in FIG. 5, a groove 100 is formed which extends from the upper surface of the emitter region 30 and penetrates the emitter region 30 and the base region 20 and reaches the drift region 10 at the tip thereof. The groove 100 is formed by using, for example, a photolithography technique and an etching technique.

Next, as shown in FIG. 6, an inner wall insulating film 40 is formed on the inner wall surface of the groove 100. For example, as the inner wall insulating film 40, a silicon oxide (SiO ₂ ) film is formed by a thermal oxidation method. The film thickness of the inner wall insulating film 40 is, for example, about 100 nm to 300 nm.

After forming the inner wall insulating film 40, an impurity-added polysilicon film 500 is formed on the entire surface. As a result, as shown in FIG. 7, the polysilicon film 500 is arranged on the inner wall insulating film 40 inside the groove 100. At this time, as shown in FIG. 7, the inside of the groove 100 is not filled with the polysilicon film 500, and the polysilicon film 500 is formed along the wall surface of the groove 100.

Next, as shown in FIG. 8, a mask 510 is formed on the surface of the polysilicon film 500 on the side surface of the groove where the gate electrode 50 is formed and on the bottom surface of the groove where the bottom electrode 150 is formed by using a photolithography technique or an etching technique. Form. As shown in FIG. 8, a gap is provided between the mask 510a arranged on the side surface of the groove and the mask 510b formed on the bottom surface of the groove. For example, an oxide film or the like is used for the mask 510a and the mask 510b.

Using the mask 510 shown in FIG. 8 as an etching mask, the polysilicon film 500 is etched by isotropic etching. At this time, the polysilicon film 500 arranged at the corner portion of the groove 100 is etched by the etching species that enter through the gap between the mask 510a and the mask 510b. As a result, as shown in FIG. 9, a gap is formed between the lower surface of the polysilicon film 500 and the inner wall insulating film 40. As described above, the gate electrode 50 made of the polysilicon film is formed. At this time, when a complete gap is not formed between the lower surface of the gate electrode 50 and the inner wall insulating film 40 and the lower surface of the gate electrode 50 and the inner wall insulating film 40 are partially in contact with each other, the first distance d1 The second distances d2 are equal. In addition, when a complete gap is formed between the lower surface of the gate electrode 50 and the inner wall insulating film 40, the gap is filled with the interlayer insulating film 70 in the subsequent step of FIG. 2 is longer than the distance d2.
The region of the polysilicon film 500 masked by the mask 510b remains on the bottom surface of the groove 100 as the bottom electrode 150. In this manufacturing method, the gate electrode 50 and the bottom electrode 150 are formed in the same step, and the material of the gate electrode 50 and the material of the bottom electrode 150 are the same.

After removing the mask 510, as shown in FIG. 10, an interlayer insulating film 70 is formed on the entire surface so as to fill the groove 100. After that, an emitter electrode 90 connected to the emitter region 30 and the base region 20 is formed on the interlayer insulating film 70. For example, an opening is provided in a part of the interlayer insulating film 70 to expose the surfaces of the emitter region 30 and the base region 20, and the emitter electrode 90 is formed so as to fill the opening. Further, a collector electrode 80 is formed on the back surface of the collector region 60.
Are formed to complete the semiconductor device shown in FIG.

According to the method for manufacturing a semiconductor device according to the embodiment of the present invention described above, the first distance d1 from the lower surface of the gate electrode 50 to the bottom surface of the groove 100 is set to be the same as the first distance d1 from the lower surface of the bottom electrode 150 to the bottom surface of the groove 100. Can be greater than or the same as the second distance d2. it can. As a result, the gate-collector capacitance is reduced. Furthermore, it is possible to suppress the discharge between the end 51 of the gate electrode 50 and the end 151 of the bottom electrode 150, and the discharge between the end 51 of the gate electrode 50 and the groove corner 101.

In order to form the inner wall insulating film 40 so that the film thickness on the bottom surface of the groove is thicker than the film thickness on the side surface of the groove, the following method can be adopted. That is, after the oxide film is formed on the entire inner wall of the groove 100, the oxide film on the side surface is removed by etching. After that, an oxide film is formed again on the side surface and the bottom surface of the groove.

Further, in the above, the case where the gate electrode 50 and the bottom electrode 150 are formed in the same step and the material of the gate electrode 50 and the material of the bottom electrode 150 are the same has been described as an example. However, the gate electrode 50 and the bottom electrode 150 may be formed in different steps. In this case, the material of the gate electrode 50 and the material of the bottom electrode 150 may be different.

In the formation of the interlayer insulating film 70 described with reference to FIG. 10, it is necessary to arrange the interlayer insulating film 70 below the gate electrode 50 without a gap. In order to fill the inter-layer insulating film 70 in the corner portion surrounded by the gate electrode 50 and the bottom electrode 150 with no space, it is preferable to use a flexible material when forming the inter-layer insulating film 70 with high reflow property.

For example, the interlayer insulating film 70 is preferably a BPSG film containing phosphorus (P) at a high concentration. However, when a polysilicon film is used for the gate electrode 50, when the BPSG film and the gate electrode 50 come into contact with each other, phosphorus diffuses into the gate electrode 50. As a result, the conductivity of the gate electrode 50 changes, and the characteristics of the semiconductor device deteriorate.

Therefore, in order not to change the conductivity of the gate electrode 50, as shown in FIG. 11, between the gate electrode 50 and the first interlayer insulating film 71 made of a BPSG film, a protective film for preventing the diffusion of phosphorus. It is preferable to dispose the second interlayer insulating film 72. A material that does not affect the conductivity of the gate electrode 50 is used for the second interlayer insulating film 72. For example, an NSG film made of TEOS or the like is suitable for the second interlayer insulating film 72. The second interlayer insulating film 72 may be formed thinner than the first interlayer insulating film 71. By forming the interlayer insulating film 71 thick, the interlayer insulating film 70 can be embedded in the groove without any gap.

As described above, the first interlayer insulating film 71 made of a material that has a high reflow property but changes the conductivity of the gate electrode 50 and the second interlayer insulating film 72 that does not affect the conductivity of the gate electrode 50 are laminated. It is preferable to use the interlayer insulating film 70. As a result, the interlayer insulating film 70 can fill the inside of the groove up to the corner portion without leaving a gap and prevent deterioration of the characteristics of the semiconductor device.

Alternatively, a thermal oxide film 73 may be disposed between the gate electrode 50 and the second interlayer insulating film 72 by thermally oxidizing the surface of the gate electrode 50, as shown in FIG. The dense and uniform thermal oxide film 73 can more reliably prevent the diffusion of phosphorus from the first interlayer insulating film 71 made of the BPSG film to the gate electrode 50.

In order to make it easier for the interlayer insulating film 70 to enter the corner portion, as shown in FIG. 11, the gate is connected so that the end of the gate electrode 50 on the corner side of the groove and the end of the gate electrode 50 on the bottom surface electrode 150 side are connected. The lower surface of the electrode 50 is formed, and at least a part of the lower surface of the gate electrode 50 may be missing. Further, the lower surface of the gate electrode 50 may be tapered so as to connect the end of the gate electrode 50 on the corner side of the groove and the end of the gate electrode 50 on the bottom electrode 150 side. That is, by making the distance between the lower surface of the gate electrode 50 and the bottom surface of the groove 100 shorter toward the side surface of the groove 100, the interlayer insulating film 70 can easily enter the corner portion.

Here, in the semiconductor device of FIG. 11, the distance (d3) from the end of the lower surface of the gate electrode 50 on the corner side of the groove (the end of the gate electrode 50 on the corner side of the groove) to the bottom surface of the groove is the gate electrode. It is longer than the distance (d5) from the lower surface of the bottom electrode 150 on the 50 side to the lower surface of the groove. Then, the end of the bottom surface of the gate electrode 50 on the bottom electrode 150 side (the end of the gate electrode 50 on the bottom electrode 150 side) is located higher than the top surface of the bottom electrode 150 on the gate electrode 50 side, and The end of the lower surface of the gate electrode 50 is located above the upper surface of the bottom electrode 150 on the gate electrode 50 side. The distance (d4) from the end of the gate electrode 50 on the bottom electrode 150 side to the bottom surface of the groove is longer than the distance (d6) from the top surface of the bottom electrode 150 on the gate electrode 50 side to the bottom surface of the groove. Then, the lower surface of the gate electrode 50 is formed so as to cross the edge of the lower surface of the gate electrode 50 on the corner side of the groove and the edge of the gate electrode 50 on the side of the bottom electrode 150. At least a part of the lower surface of the gate electrode 50 is lacking, and for example, the lower surface of the gate electrode 50 is provided with a taper. In the semiconductor device of FIG. 11, discharge between the bottom electrode 150 and the end of the gate electrode 50 on the bottom electrode 150 side can be suppressed, and malfunction of the semiconductor device can be reduced.
Here, as shown in the semiconductor device of FIG. 17, the distance (d3) from the end of the lower surface of the gate electrode 50 on the corner side of the groove to the bottom surface of the groove is the bottom electrode 150 on the side facing the gate electrode 50. The distance (d5) from the lower surface to the upper surface of the groove may be the same. Incidentally, also in the semiconductor device of FIG. 17, the end portion of the lower surface of the gate electrode 50 on the bottom electrode 150 side is located higher than the upper surface of the bottom electrode 150 on the gate electrode 50 side, and the gate electrode on the bottom electrode 150 side. The lower surface of the gate electrode 50 is tapered so that the distance (d4) from the lower surface of 50 to the bottom surface of the groove is longer than the distance (d6) to the upper surface of the bottom electrode 150. Therefore, also in the semiconductor device of FIG. 17, it is possible to reduce the occurrence of malfunction between the end portion of the gate electrode and the end portion of the bottom electrode and malfunction. Although the feedback capacitance is increased as compared with the semiconductor device of FIG. 11, the semiconductor device of FIG. 17 has a gate electrode 50 disposed near the corner portion 101 of the groove, so that the gate electrode 50 is disposed near the corner portion 101 of the groove. It is preferable because the withstand voltage is improved.
In addition, as shown in FIG. 18, the distance (d3) from the end of the gate electrode 50 on the corner side of the groove to the bottom surface of the groove is from the bottom surface of the bottom electrode 150 on the side facing the gate electrode 50 to the bottom surface of the groove. May be smaller than the distance (d5). Incidentally, also in the semiconductor device of FIG. 18, the end of the gate electrode 50 on the bottom electrode 150 side is located above the top surface of the bottom electrode 150, and the bottom of the groove extends from the end of the gate electrode 50 on the bottom electrode 150 side. The taper is provided on the lower surface of the gate electrode 50 so that the distance (d4) to the distance is longer than the distance (d6) from the upper surface of the bottom electrode 150 to the bottom surface of the groove. Also in the semiconductor device of FIG. 18, it is possible to suppress the occurrence of discharge between the end portion of the gate electrode and the end portion of the bottom electrode and reduce malfunction. Although the feedback capacitance is increased as compared with the semiconductor device of FIG. 11, in the semiconductor device of FIG. 18, since the gate electrode 50 is arranged near the corner portion 101 of the groove, the semiconductor device of FIG. It is more preferable because the withstand voltage is further improved.

In addition, as shown in FIG. 11, the bottom electrode 150 has a trapezoidal shape so that the bottom electrode 150 has a lower surface that is wider than the top surface of the bottom electrode 150 and that the thickness of the bottom electrode 150 becomes smaller toward the side surface of the groove 100. May be. This also makes it easier for the interlayer insulating film 70 to enter the corners.
Further, as shown in FIG. 11, the distance between the lower surface of the bottom surface electrode 150 and the end of the gate electrode 50 on the corner side of the groove is equal to the upper surface of the bottom surface electrode 150 and the end of the gate electrode 50 on the bottom surface electrode 150 side. Longer than the distance between. This makes it possible to smooth the distortion of the electric field generated in the gap between the gate electrode 50 and the bottom electrode 150.

By the way, when the width W of the groove 100 is widened, a recess is formed on the upper surface of the interlayer insulating film 70 above the groove 100, the gap between the emitter electrode 90 and the upper portion of the gate electrode 50 becomes narrow, and the breakdown voltage decreases. There is a risk. Therefore, the upper surface of the gate electrode 50 may be tapered as shown in FIG. By lowering the upper surface of the gate electrode 50 toward the central portion of the groove 100, it is possible to suppress a decrease in breakdown voltage of the semiconductor device due to the proximity of the gate electrode 50 and the emitter electrode 90.

<Modification>
FIG. 13 shows a modification of the semiconductor device according to the embodiment of the present invention. In the semiconductor device shown in FIG. 13, the film thickness of the inner wall insulating film 40 is thicker in the central region distant from the side surface of the groove than in the peripheral region near the side surface of the groove. That is, the distance from the bottom surface of the bottom electrode 150 to the bottom surface of the groove is longer in the central region than in the peripheral region of the bottom electrode 150. As a result, the capacitance between the emitter and collector of the semiconductor device can be reduced.

(Other embodiments)
As described above, the present invention has been described by the embodiments, but it should not be understood that the descriptions and drawings forming a part of this disclosure limit the present invention. From this disclosure, various alternative embodiments, examples, and operation techniques will be apparent to those skilled in the art.

In the above, the example in which the semiconductor device is an IGBT has been shown. However, the semiconductor device may be a switching element having another structure adopting the trench gate type. FIG. 14 shows an example in which the semiconductor device is a trench gate type MOSFET. The semiconductor device shown in FIG. 14 is a MOSFET having a structure in which an n-type drain region 160 is arranged on the lower surface of the drift region 10. A drain electrode 180 electrically connected to the drain region 160 is arranged on the lower surface of the drain region 160.

Also in the case of the MOSFET semiconductor device shown in FIG. 14, the first distance d1 from the lower surface of the gate electrode 50 to the bottom surface of the groove is smaller than the second distance d2 from the lower surface of the bottom electrode 150 to the bottom surface of the groove. By increasing the length, the feedback capacitance between the gate and the drain can be reduced. As a result, the switching speed of the semiconductor device is improved. Further, also in the trench gate type MOSFET, the interlayer insulating film 70 may have a structure in which the first interlayer insulating film 71 and the second interlayer insulating film 72 shown in FIG. 11 are laminated. As a result, it is possible to fill the inside of the groove with the interlayer insulating film 70 without any gap up to the corner portion and prevent deterioration of the characteristics of the semiconductor device.

Further, in the semiconductor device of FIG. 1, the case where the distance from the lower surface of the gate electrode 50 to the bottom surface of the groove over the entire lower surface of the gate electrode 50 is longer than the distance from the lower surface of the bottom electrode 150 to the bottom surface of the groove is shown. It was However, in a part of the lower surface of the gate electrode 50, the distance from the lower surface of the gate electrode 50 on the bottom electrode 150 side to the bottom surface of the groove is set to be the distance from the lower surface of the bottom electrode 150 on the side surface facing the gate electrode 50 to the bottom surface of the groove. Longer than the distance. Further, the position of the gate electrode 50 on the side surface side of the groove is extended below the position of the upper surface on the side surface side of the bottom electrode 150, and is made substantially the same as the position of the lower surface on the side surface side of the bottom electrode 150. Also in this case, the feedback capacitance between the gate and the drain can be reduced. As in the semiconductor device shown in FIGS. 16 to 18, the second interlayer insulating film 72/ and the heat insulating film 72/ are formed between the gate electrode 50 and the first interlayer insulating film 71 made of a BPSG film as a protective film for preventing diffusion of phosphorus. The oxide film 73 may not be provided.
For example, in the semiconductor device shown in FIG. 15, the second interlayer insulating film 72/ and the thermal oxide film 73 are not provided, and the interlayer insulating film 70 is formed of the first interlayer insulating film 71. Here, the bottom electrode side end of the gate electrode 50 is above the top surface of the bottom electrode 150 on the gate electrode 50 side, and from a part of the bottom surface of the gate electrode 50 (end of the gate electrode 50 on the bottom electrode 150 side). The distance (d4) to the bottom surface of the groove is longer than the distance (d6) from the upper surface of the bottom electrode 150 to the bottom surface of the groove. The distance (d3) from the other part of the lower surface of the gate electrode 50 (the end of the gate electrode 50 on the corner side of the groove) to the bottom surface of the groove is equal to the distance (d5) from the lower surface of the bottom electrode 150 to the bottom surface of the groove. ) Is the same. Also in the semiconductor device shown in FIG. 15, the feedback capacitance between the gate and the drain can be reduced. Further, the breakdown voltage at the corner portion of the groove can be improved. Further, it is possible to reduce the occurrence of malfunction between the end portion of the gate electrode 50 and the end portion of the bottom surface electrode 150 and malfunction.
In the semiconductor device shown in FIG. 15, the distance (d3) from the other part of the lower surface of the gate electrode 50 (the end of the gate electrode 50 on the corner side of the groove) to the bottom surface of the groove is the lower surface of the bottom electrode 150. It may be longer than the distance (d5) from the to the bottom of the groove. Also in this semiconductor device, the feedback capacitance between the gate and the drain can be reduced. Further, it is possible to reduce the occurrence of malfunction between the end portion of the gate electrode 50 and the end portion of the bottom surface electrode 150 and malfunction.
In the semiconductor device shown in FIG. 15, the distance (d3) from the other part of the lower surface of the gate electrode 50 (the end of the gate electrode 50 on the corner side of the groove) to the bottom surface of the groove is the lower surface of the bottom electrode 150. May be shorter than the distance from to the bottom surface (d5) of the groove. Also in this semiconductor device, it is possible to reduce the occurrence of malfunction between the end portion of the gate electrode 50 and the end portion of the bottom surface electrode 150 and malfunction. Moreover, the breakdown voltage at the corner portion of the groove can be further improved. Further, since the gate electrode 50 is provided near the corner of the groove, the electric field near the corner of the groove can be more relaxed.
Further, in the semiconductor device of FIGS. 16 to 18, although the lower surface of the gate electrode 50 is tapered, the lower surface of the gate electrode 50 is not tapered, and the height of the lower surface of the gate electrode 50 on the bottom electrode 150 side is a groove. The height may be the same as the height of the bottom surface of the gate electrode 50 on the corner side. 16 to 18, the height of the edge of the gate electrode 50 on the bottom electrode 150 side may be lower than the height of the top surface of the bottom electrode 150. Also in the above semiconductor device, the diffusion of phosphorus from the first interlayer insulating film 71 made of the BPSG film to the gate electrode 50 can be prevented more reliably.
Further, in the semiconductor device of FIGS. 16 to 18, the bottom electrode 150 may not be provided, and it may be applied to a switching element having another structure adopting the well-known trench gate type. In the above semiconductor device, the diffusion of phosphorus from the first interlayer insulating film 71 made of the BPSG film to the gate electrode 50 can be prevented more reliably.

Further, in FIG. 11, the bottom electrode 150 is formed so that the film thickness of the bottom electrode 150 becomes smaller as it approaches the side surface of the groove 100, that is, the width of the top surface of the bottom electrode 150 becomes smaller than that of the bottom surface of the bottom electrode 150. Has a trapezoidal shape. However, as shown in FIG. 16, the bottom electrode 150 may have a trapezoidal shape so that the film thickness of the bottom electrode 150 increases as it approaches the side surface of the groove 100. As a result, the adhesion between the bottom electrode 150, the gate electrode 50, and the inner wall insulating film 40 at the portion of the interlayer insulating film 70 that is sandwiched between the bottom electrode 150 and the gate electrode 50 becomes good, and the interlayer insulating film 70 is formed. It is possible to prevent the interlayer insulating film 70 from being displaced when it is bonded to the emitter electrode 90.
Note that the semiconductor device of FIG. 16 is the case where the bottom electrode 150 is changed as compared with the semiconductor device of FIG. 11, but conversely, in the semiconductor device of FIG. 17 or 18, the bottom electrode 150 of the semiconductor device of FIG. As described above, the width of the upper surface of the bottom electrode 150 may be replaced with the trapezoidal bottom electrode 150 whose width is smaller than that of the lower surface of the bottom electrode 150. In this case, since the distance between the bottom surface of the gate electrode 50 and the bottom surface electrode 150 can be sufficiently secured in the thickness direction, the discharge between the gate electrode 50 and the bottom surface electrode 150 can be favorably suppressed.

Although the case where the semiconductor device is the n-channel type has been described as an example, it is clear that the effect of the present invention can be obtained even if the semiconductor device is the p-channel type.

As described above, it goes without saying that the present invention includes various embodiments and the like not described here. Therefore, the technical scope of the present invention is defined only by the matters specifying the invention according to the scope of claims reasonable from the above description.

10... Drift region 20... Base region 30... Emitter region 40... Inner wall insulating film 50... Gate electrode 60... Collector region 65... Field stop region 70... Interlayer insulating film 71... First interlayer insulating film 72... Second interlayer insulating Film 73... Thermal oxide film 80... Collector electrode 90... Emitter electrode 100... Groove 150... Bottom electrode

Claims (6)

A first semiconductor region of a first conductivity type;
A second semiconductor region of a second conductivity type disposed on the first semiconductor region,
A third semiconductor region of the first conductivity type disposed on the second semiconductor region,
An inner wall insulating film extending from an upper surface of the third semiconductor region and disposed on an inner wall of a groove penetrating the third semiconductor region and the second semiconductor region;
A control electrode disposed on the inner wall insulating film on the side surface of the groove, facing the side surface of the second semiconductor region;
A bottom electrode that is insulated from the control electrode and disposed on the inner wall insulating film on the bottom surface of the groove;
An interlayer insulating film for insulating between the control electrode and the bottom electrode,
The distance from the corner-side end of the groove on the lower surface of the control electrode to the bottom surface of the groove is shorter than the distance from the upper surface of the bottom electrode on the side facing the control electrode to the bottom surface of the groove. ,
At least the position of the lower surface of the control electrode on the side facing the bottom electrode is above the position of the upper surface of the bottom electrode on the control electrode side . Claim 1 the distance between the bottom surface of the lower surface and the groove of the control electrode to be shorter as it approaches the side surface of said groove, characterized in that it tapered to said lower surface of said control electrode The semiconductor device according to 1. As the thickness of the bottom electrode closer to the side surface of the groove becomes thinner, the semiconductor device according to any one of claims 1 to 2, wherein the bottom electrode is a trapezoidal shape. Distance from the lower surface of the bottom electrode to the bottom surface of the groove, according to any one of claims 1 to 3, characterized in that long in the central region than the peripheral region in the lower surface of the bottom electrode Semiconductor device. Stretching direction of a length of the groove in plan view is larger than the width of the groove, and any one of claims 1 to 4, wherein the width of the groove than the spacing of the grooves adjacent wide The semiconductor device according to item 1. Thickness of the inner wall insulating film in the region that is disposed on a bottom surface of the groove, in any one of claims 1 to 5, characterized in that thicker than region that is disposed on a side of said groove The semiconductor device described.

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