JP2018018850A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having a high breakdown voltage and a low ON-state voltage.SOLUTION: A semiconductor device comprises: an n-type drift region 10; an n-type high-concentration region 15 arranged on the drift region 10 and that has a dopant concentration higher than that of the drift region 10; a p-type base region 20 arranged on the high-concentration region 15; an n-type emitter region 30 arranged on the base region 20; an inner wall insulating film 40 arranged on an inner wall of a groove that extends from an upper surface of the emitter region 30, penetrates through the emitter region 30 and the base region 20 and reaches at least an upper part of the high-concentration region 15; and a gate electrode 50 arranged on the inner wall insulating film 40 on a lateral face of the groove so as to be opposed to a lateral face of the base region 20.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a trench gate type semiconductor device.

  An insulating gate bipolar transistor (IGBT) having a high input impedance and a low on-state voltage is used as a switching element (power semiconductor element) that performs a switching operation with a large current. In the IGBT, the breakdown voltage and the on-voltage are in a trade-off relationship.

  For this reason, various methods have been studied to reduce the on-voltage while maintaining a high breakdown voltage. For example, in a trench gate type IGBT, a technique for realizing a high breakdown voltage and low on-voltage semiconductor device by widening the width of a groove in which a gate electrode is disposed is disclosed (see Patent Document 1).

Japanese Patent No. 5838176

  It is desired to further reduce the on-voltage of the IGBT. An object of the present invention is to provide a semiconductor device having a high breakdown voltage and a low on-voltage.

  According to one aspect of the present invention, a first conductive type first semiconductor region and a first conductive type second semiconductor region disposed on the first semiconductor region and having an impurity concentration higher than that of the first semiconductor region. A third semiconductor region of the second conductivity type disposed on the second semiconductor region, a fourth semiconductor region of the first conductivity type disposed on the third semiconductor region, and an upper surface of the fourth semiconductor region The inner wall insulating film disposed on the inner wall of the groove extending through the fourth semiconductor region and the third semiconductor region and reaching at least the upper part of the second semiconductor region, and the groove facing the side surface of the third semiconductor region A semiconductor device including a control electrode disposed on an inner wall insulating film on a side surface is provided.

  According to the present invention, a semiconductor device having a high breakdown voltage and a low on-voltage can be provided.

It is a typical sectional view showing the structure of the semiconductor device concerning the embodiment of the present invention. It is a typical top view showing the structure of the peripheral field of the semiconductor device concerning the embodiment of the present invention. It is typical sectional drawing along the II-II direction of FIG. It is a typical top view showing other structures of the peripheral field of the semiconductor device concerning the embodiment of the present invention. It is typical process sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention (the 1). It is typical process sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention (the 2). FIG. 9 is a schematic process cross-sectional view for explaining the manufacturing method of the semiconductor device according to the embodiment of the present invention (No. 3). FIG. 10 is a schematic process cross-sectional view for explaining the manufacturing method of the semiconductor device according to the embodiment of the present invention (No. 4). FIG. 10 is a schematic process cross-sectional view for explaining the manufacturing method of the semiconductor device according to the embodiment of the present invention (No. 5). FIG. 6 is a schematic process cross-sectional view for explaining the manufacturing method of the semiconductor device according to the embodiment of the present invention (No. 6). It is typical process sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention (the 7). It is typical process sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention (the 8). It is typical sectional drawing which shows the structure of the semiconductor device which concerns on the modification of embodiment of this invention.

  Next, an embodiment of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the lengths of the respective parts, and the like are different from the actual ones. Therefore, specific dimensions should be determined in consideration of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

  Further, the embodiments described below exemplify apparatuses and methods for embodying the technical idea of the present invention, and the technical idea of the present invention includes the shape, structure, arrangement, etc. of components. It is not specified to the following. The embodiment of the present invention can be variously modified within the scope of the claims.

  As shown in FIG. 1, the semiconductor device according to the embodiment of the present invention includes a first conductivity type first semiconductor region (drift region 10) and a first semiconductor region disposed on the first semiconductor region. A first conductivity type second semiconductor region (high concentration region 15) having a high impurity concentration, a second conductivity type third semiconductor region (base region 20) disposed on the second semiconductor region, and a third And a fourth semiconductor region (emitter region 30) of the first conductivity type disposed on the semiconductor region. A groove extending from the upper surface of the fourth semiconductor region and penetrating the fourth semiconductor region and the third semiconductor region is formed, and the inner wall insulating film 40 is disposed on the inner wall of the groove. In the embodiment shown in FIG. 1, the groove also penetrates the second semiconductor region, and the tip reaches the first semiconductor region.

  The groove extends along the main surface of the semiconductor region, and the length of the groove in the extending direction is longer than the width W of the groove. FIG. 1 shows a cross section perpendicular to the direction in which the grooves extend.

  The semiconductor device shown in FIG. 1 is a trench gate type IGBT, and a control electrode (gate electrode 50) is disposed on the inner wall insulating film 40 on the side surface of the groove so as to face the side surface of the base region 20. The semiconductor device further includes a bottom electrode 150 that is insulated from the gate electrode 50 and disposed on the inner wall insulating film 40 at the bottom of the trench. Bottom electrode 150 is electrically connected to emitter region 30.

  The first conductivity type and the second conductivity type are opposite to each other. That is, if the first conductivity type is n-type, the second conductivity type is p-type. If the first conductivity type is p-type, the second conductivity type is n-type. Hereinafter, a case where the first conductivity type is n-type and the second conductivity type is p-type will be described as an example.

  As shown in FIG. 1, an interlayer insulating film 70 is buried inside the trench so as to cover the gate electrode 50 and the bottom electrode 150. By the interlayer insulating film 70, the gate electrode 50 and the bottom electrode 150 are insulated and separated.

  Drift region 10 is arranged on one main surface of p-type collector region 60. An n-type field stop region 65 having an impurity concentration higher than that of the drift region 10 is arranged between the drift region 10 and the collector region 60. The field stop region 65 prevents the depletion layer extending from the lower surface of the base region 20 in the off state from reaching the collector region 60. A collector electrode 80 that is electrically connected to the collector region 60 is disposed on the other main surface of the collector region 60.

  Above the gate electrode 50, an emitter electrode 90 that is electrically connected to the base region 20 and the emitter region 30 that is selectively disposed above the base region 20 is disposed. The emitter electrode 90 is disposed on the interlayer insulating film 70, and the emitter electrode 90 is connected to the base region 20 and the emitter region 30 through an opening provided in the interlayer insulating film 70. The gate electrode 50 and the emitter electrode 90 are electrically insulated by the interlayer insulating film 70.

  In the semiconductor device shown in FIG. 1, the surface of the base region 20 facing the gate electrode 50 with the inner wall insulating film 40 interposed therebetween is a channel region where a channel is formed. That is, the region between the gate electrode 50 and the base region 20 of the inner wall insulating film 40 functions as a gate insulating film.

  As shown in FIG. 1, the gate electrode 50 is arrange | positioned at each of the opposing side surface of the inner wall of a groove | channel. In the cross section perpendicular to the extending direction of the groove, the gate electrode 50 is not continuously disposed along the inner wall of the groove, and the gate electrode 50 is not disposed on the bottom surface of the groove.

  Here, the operation of the semiconductor device illustrated in FIG. 1 will be described. A predetermined collector voltage is applied between the emitter electrode 90 and the collector electrode 80, and a predetermined gate voltage is applied between the emitter electrode 90 and the gate electrode 50. For example, the collector voltage is about 300V to 1600V, and the gate voltage is about 10V to 20V. When the semiconductor device is turned on in this manner, the channel region is inverted from the p-type to the n-type to form a channel. Electrons are injected from the emitter electrode 90 into the drift region 10 through the formed channel. Further, a forward bias is applied between the collector region 60 and the drift region 10, and holes move from the collector electrode 80 through the collector region 60 in the order of the drift region 10, the high concentration region 15, and the base region 20. . As the current is further increased, holes from the collector region 60 increase and holes are accumulated in the drift region 10. As a result, the ON voltage decreases due to conductivity modulation.

  When the semiconductor device is changed from the on state to the off state, the gate voltage is controlled to be lower than the threshold voltage. For example, the gate voltage is set to the same potential as the emitter voltage or a negative potential. As a result, the channel of the base region 20 disappears, and the injection of electrons from the emitter electrode 90 to the drift region 10 stops. Since the potential of the collector electrode 80 is higher than that of the emitter electrode 90, a depletion layer spreads from the interface between the base region 20 and the high concentration region 15, and holes accumulated in the drift region 10 escape to the emitter electrode 90. Go. At this time, the holes move through the semiconductor region between the grooves. That is, the region between the grooves is a hole outlet.

  In the semiconductor device shown in FIG. 1, the high concentration region 15 having an impurity concentration higher than that of the drift region 10 is disposed between the drift region 10 and the base region 20. An electric field heading toward is generated. Thereby, holes are accumulated in the drift region 10 in the vicinity of the interface between the drift region 10 and the high concentration region 15. For this reason, as compared with the case where the high concentration region 15 is not disposed, more holes are accumulated. As a result, the on-voltage of the semiconductor device can be further reduced.

  If the impurity concentration of the high concentration region 15 is too high, the spread of the depletion layer generated from the PN junction at the interface between the base region 20 and the high concentration region 15 in the off state is suppressed. As a result, the breakdown voltage of the semiconductor device is reduced. Therefore, the impurity concentration of the high concentration region 15 is preferably higher than the impurity concentration of the drift region 10 and lower than the impurity concentration of the base region 20.

  FIG. 2 is a plan view of a peripheral region of the semiconductor device including an end portion in the longitudinal direction of the groove 100 in which the gate electrode 50 is disposed. In FIG. 2, the emitter electrode 90 and the interlayer insulating film 70 are not shown. Then, the high concentration region 15 is displayed through the base region 20.

  As shown in FIG. 2, the outer edge of the high concentration region 15 is located outside the outer edge of the emitter region 30 disposed along the groove 100. The groove 100 extends to the outside of the outer edge of the high concentration region 15. In FIG. 2, the distance along the extending direction of the groove 100 from the outer edge of the high concentration region 15 to the end of the groove 100 is shown as “stretching distance D”.

  As shown in FIG. 2, the base region 20 extends beyond the edge of the groove 100 beyond the outer edge of the high concentration region 15. That is, the base region 20 is disposed so as to surround the periphery of the end portion of the groove 100.

  The emitter region 30 may be disposed in an element region surrounded by the peripheral region and in which an element for switching operation is formed. On the other hand, by arranging the outer edge of the high concentration region 15 outside the outer edge of the emitter region 30, the amount of accumulated holes immediately below the high concentration region 15 can be increased. However, according to the study by the present inventors, when the outer edge of the high concentration region 15 is extended to the end of the groove 100, the breakdown voltage in the peripheral region of the semiconductor device is lowered. For this reason, it is preferable that the outer edge of the high-concentration region 15 is located inside the end of the groove 100.

  As described above, by providing the extension distance D in the peripheral region of the semiconductor device, the breakdown voltage in the peripheral region is improved. In particular, the inventors have found that the withstand voltage of the peripheral region can be further improved when the stretching distance D is greater than the film thickness of the high concentration region 15. For this reason, it is preferable to set the stretching distance D larger than the film thickness of the high concentration region 15.

  Regarding the film thickness of the inner wall insulating film 40, it is preferable that the film thickness T4 outside the region where the emitter region 30 is disposed is equal to or greater than the film thickness T3 in the region where the emitter region 30 is disposed. For example, T3 <T4.

  Further, regarding the distance between the gate electrode 50 and the bottom electrode 150 along the direction perpendicular to the longitudinal direction of the groove 100, the distance T2 outside the region where the emitter region 30 is disposed is the emitter region 30 disposed. The distance in the region is preferably equal to or less than T1. For example, T1> T2.

  FIG. 3 shows an embodiment in which the high concentration region 15 is formed up to the lower side of the groove 100. That is, the groove 100 may be formed so as to extend from the upper surface of the emitter region 30 and pass through the emitter region 30 and the base region 20, and the tip reaches the upper portion of the high concentration region 15.

  However, the gap between the gate electrode 50 and the bottom electrode 150 has a low breakdown voltage. If the high concentration region 15 is disposed in that portion, the withstand voltage of the gap portion is further reduced. Therefore, as shown in FIG. 3, it is preferable that the high concentration region 15 does not extend to a position immediately below the gap portion between the gate electrode 50 and the bottom electrode 150. That is, it is preferable that the outer edge of the high concentration region 15 is disposed inside the gap portion between the gate electrode 50 and the bottom electrode 150 at the end portion in the longitudinal direction of the groove 100.

  Further, as shown in FIG. 4, the outer edge of the bottom electrode 150 may be positioned in the same manner as the outer edge of the emitter region 30, and the area of the gate electrode 50 may be widened inside the tip of the trench 100. This facilitates contact with the gate electrode 50 from above.

  By the way, in the semiconductor device in which the gate electrode 50 is disposed inside the groove, there is a problem that the switching speed is lowered because the feedback capacity generated at the bottom surface of the groove is large. However, in the semiconductor device shown in FIG. 1, the gate electrode 50 is not disposed on the bottom surface of the groove. For this reason, the feedback capacitance (gate-collector capacitance) between the gate electrode 50 and the collector region 60 can be reduced.

  Further, by arranging the bottom electrode 150 having the same potential as that of the emitter region 30 on the bottom surface of the groove, the feedback capacitance between the gate and the collector is further reduced. In order to electrically connect the bottom electrode 150 to the emitter region 30, for example, a through hole is provided in the interlayer insulating film 70 embedded in the groove, and the through hole is filled with a conductor film so as to connect the bottom electrode 150 and the emitter. The electrode 90 is electrically connected.

  As described above, in the semiconductor device shown in FIG. 1, the feedback capacitance generated at the bottom surface of the groove is reduced. As a result, the switching time of the semiconductor device can be shortened.

  In addition, since the gate electrode 50 and the bottom electrode 150 are spaced apart from each other, the withstand voltage at the corner portion of the groove (the connection portion between the side surface and the bottom surface) is lowered due to the position away from these electrodes. In order to suppress this decrease in breakdown voltage, it is preferable that the gate electrode 50 be disposed near the corner of the groove. Therefore, the position of the lower surface of the gate electrode 50 is preferably lower than the position of the upper surface of the bottom electrode 150.

  By the way, as described below, the on-voltage of the semiconductor device is reduced and the breakdown voltage is improved as the width W of the groove in which the gate electrode 50 is disposed is increased to a certain level. In this case, the width W of the groove is, for example, about 3 μm to 20 μm.

  First, the reason why the ON voltage decreases will be described. When the semiconductor device is turned on, electrons that have moved through the channel formed in the channel region and moved mainly along the side surface of the groove from the emitter electrode 90 are injected into the drift region 10. The thickness of the drift region 10 below the bottom surface of the groove is, for example, 30 μm to 180 μm, and is sufficiently wider than the width W of the groove. For this reason, even if the width W of the groove is increased, the electrons moved along the groove are diffused in the drift region 10 in a region deeper than the groove. As a result, not only the interface between the collector region 60 and the drift region 10 immediately below the region between the trenches, but also the interface between the collector region 60 and the drift region 10 is forward biased in a wider range, and holes are transferred from the collector region 60. Move to the drift region 10.

  The holes that have moved from the collector region 60 are prevented from moving by the bottom surface of the groove, the holes are accumulated in the drift region 10 near the bottom surface of the groove, and conductivity modulation occurs. As the groove width W increases, holes are more likely to accumulate in the drift region 10 near the bottom of the groove. For this reason, the number of holes that move to the emitter electrode 90 decreases, and the on-voltage decreases.

  In addition, if the space | interval S between a groove | channel is large, the quantity of the hole which will not be accumulate | stored under the base area | region 20, but will move to the base area | region 20, will increase, or a chip area will increase. Therefore, in order to reduce the on-voltage, it is preferable that the width W of the groove is wider than the interval S.

  Next, the reason why the breakdown voltage of the semiconductor device is improved by increasing the width W of the groove will be described. When the semiconductor device is turned from the on state to the off state, the depletion layer spreads in the drift region 10 not only from the PN junction between the high concentration region 15 and the base region 20 but also from the periphery of the bottom surface of the trench. At this time, it is preferable that the depletion layer spreads uniformly and spreads over a wider range. When the depletion layer spreads unevenly or narrowly, the breakdown voltage decreases. When the width W of the groove is narrow, the corner portions of the groove, which are the electric field concentration points, are close to each other, so that the depletion layer is well uniform and does not spread over a wide range immediately below the bottom surface of the groove. However, when the width W of the groove is wide, the corner portions of the groove are separated, so that the depletion layer immediately below the bottom surface of the groove between the corner portions spreads more uniformly or over a wider range. For this reason, in a semiconductor device having a wide groove width W, the breakdown voltage is improved.

  Further, the withstand voltage of the semiconductor device is improved by relatively narrowing the gap S between the grooves. This is due to the following reason. That is, the depth of the depletion layer in the region between the grooves is shallower than the depth of the depletion layer immediately below the groove. When the interval S is wide, the depletion layer extending from the PN junction with the base region 20 in the region between the trenches becomes more flat. For this reason, the portion where the depletion layer on the bottom surface of the groove continues to the depletion layer extending from the side surface of the groove has a more distorted shape. For this reason, the electric field concentrates near the corner of the groove, which is a distorted portion of the depletion layer, and the breakdown voltage decreases. Accordingly, the interval S is preferably narrow to some extent. For example, the interval S is made narrower than the width W of the groove.

  As described above, in the semiconductor device shown in FIG. 1, it is preferable that the width W of the groove is wide and the interval S is narrow. For example, the groove is formed so that the length in the longitudinal direction in which the groove extends is longer than the width W of the groove and the width W of the groove is wider than the interval S between adjacent grooves.

  When the width W of the groove is wide, the feedback capacity between the gate and the collector tends to increase. However, in the semiconductor device shown in FIG. 1, the feedback capacitance between the gate and the collector can be reduced by disposing the capacitor portion using the bottom electrode 150 on the bottom surface of the groove.

  By the way, since the chip area is limited, if the width W of the groove is increased when the chip size is constant, the number of channels decreases. At this time, when the ratio of the channel region to the chip size of the semiconductor device decreases to a certain level, the saturation voltage between the collector and the emitter increases. For this reason, when the effect of increasing the on-voltage due to the decrease in the number of channels is greater than the effect of reducing the on-voltage by accumulating holes by increasing the width W of the trench, the on-voltage of the semiconductor device increases.

  As a result of investigations by the present inventors from the above viewpoint, the width W of the groove is preferably about 3 μm to 20 μm. Furthermore, the width W of the groove is more preferably about 5 μm to 13 μm. According to the study by the present inventors, the ON voltage is most effectively reduced when the width W of the groove is about 7 μm. Since the depth of the groove is generally about 5 μm, as a result of increasing the width W of the groove, the width W of the groove may be larger than the depth of the groove.

  The inner wall insulating film 40 is preferably formed so that the film thickness of the region disposed on the bottom surface of the groove is thicker than the film thickness of the region disposed on the side surface of the groove facing the base region 20. . When the width W of the groove is increased, the parasitic capacitance generated between the gate electrode 50 and the semiconductor region on the bottom surface of the groove tends to increase. However, this parasitic capacitance can be reduced by increasing the thickness of the inner wall insulating film 40 at the bottom of the trench.

  However, since the region disposed on the side surface of the groove of the inner wall insulating film 40 functions as a gate insulating film, there is a limit to increasing the thickness of the inner wall insulating film 40 on the side surface of the groove. For this reason, the film thickness of the region disposed on the bottom surface of the groove of the inner wall insulating film 40 is made larger than the film thickness of the region disposed on the side surface of the groove of the inner wall insulating film 40. For example, the film thickness at the bottom of the groove of the inner wall insulating film 40 is about 300 nm, and the film thickness at the side of the groove is about 150 nm.

  As described above, according to the semiconductor device of the embodiment of the present invention, the on-voltage can be reduced by disposing the high concentration region 15 above the drift region 10 along the groove. Furthermore, by increasing the width W of the groove, the breakdown voltage can be improved and the on-voltage can be further reduced. Thus, according to the semiconductor device shown in FIG. 1, a semiconductor device having a high breakdown voltage and a low on-voltage can be provided.

  With reference to FIGS. 5 to 12, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described. 5 to 12 illustrate a region including one groove. In addition, the manufacturing method described below is an example, and it is needless to say that it can be realized by various other manufacturing methods including this modified example.

As shown in FIG. 5, n ^- type drift region 10 formed on a stacked body of p-type collector region 60 and n ⁺ -type field stop region 65 has n concentration higher than that of drift region 10. A high concentration region 15 of the mold is formed. Further, a p ⁻ -type base region 20 is formed on the high concentration region 15 by an impurity diffusion method or an epitaxial growth method. For example, according to the impurity diffusion method, a p-type impurity is ion-implanted from the upper surface of the high concentration region 15 into the high concentration region 15, and then diffusion is performed by annealing, thereby forming the base region 20 with a substantially uniform thickness. Is done. The p-type impurity in the base region 20 is, for example, boron (B). Note that the impurity concentration of the base region 20 is preferably higher than the impurity concentration of the high concentration region 15.

Next, as shown in FIG. 6, an n ⁺ -type emitter region 30 is selectively formed in a part of the upper surface of the base region 20 by using, for example, ion implantation and diffusion.

  Thereafter, as shown in FIG. 7, a groove 100 extending from the upper surface of the emitter region 30 and penetrating the emitter region 30, the base region 20, and the high concentration region 15 and reaching the drift region 10 is formed. The groove 100 is formed using, for example, a photolithography technique and an etching technique.

Next, as shown in FIG. 8, an inner wall insulating film 40 is formed on the inner wall of the groove 100. For example, a silicon oxide (SiO ₂ ) film is formed as the inner wall insulating film 40 by a thermal oxidation method. The film thickness of the inner wall insulating film 40 is, for example, about 100 nm to 300 nm.

  After forming the inner wall insulating film 40, a polysilicon film 500 doped with impurities is formed on the entire surface. As a result, as shown in FIG. 9, the polysilicon film 500 is disposed on the inner wall insulating film 40 inside the trench 100. At this time, as shown in FIG. 9, the inside of the trench 100 is not filled with the polysilicon film 500, and the polysilicon film 500 is formed along the inner wall of the trench 100.

  Next, as shown in FIG. 10, a mask 510 is formed on the surface of the polysilicon film 500 on the side surface where the gate electrode 50 of the trench 100 is formed and the bottom surface where the bottom electrode 150 is formed using a photolithography technique or an etching technique. Form. As shown in FIG. 10, a gap is provided between the mask 510a disposed on the side surface of the groove 100 and the mask 510b formed on the bottom surface. For example, an oxide film or the like is used for the mask 510a and the mask 510b.

  The polysilicon film 500 is etched by isotropic etching using the mask 510 shown in FIG. 10 as an etching mask. At this time, the polysilicon film 500 disposed in the corner portion of the groove 100 is etched by the etching species entering from the gap between the mask 510a and the mask 510b. As a result, a gap is formed between the lower surface of the polysilicon film 500 and the inner wall insulating film 40 as shown in FIG. Thus, the gate electrode 50 made of a polysilicon film is formed. At this time, the region masked by the mask 510 b of the polysilicon film 500 remains on the bottom surface of the groove 100 as the bottom electrode 150. In this manufacturing method, the gate electrode 50 and the bottom electrode 150 are formed in the same process, and the material of the gate electrode 50 and the material of the bottom electrode 150 are the same.

  After removing the mask 510, as shown in FIG. 12, an interlayer insulating film 70 is formed on the entire surface so as to fill the trench 100. Thereafter, an emitter electrode 90 connected to the emitter region 30 and the base region 20 is formed on the interlayer insulating film 70. For example, an opening is provided in a part of the interlayer insulating film 70 to expose the surfaces of the emitter region 30 and the base region 20, and the emitter electrode 90 is formed so as to fill the opening. Further, the collector electrode 80 is formed on the back surface of the collector region 60, and the semiconductor device shown in FIG. 1 is completed.

  According to the method for manufacturing a semiconductor device according to the embodiment of the present invention described above, the high concentration region 15 is disposed between the drift region 10 and the base region 20, and the on-voltage of the semiconductor device can be lowered.

  In order to form the inner wall insulating film 40 so that the film thickness at the bottom surface of the groove is larger than the film thickness at the side surface of the groove, the following method or the like can be employed. That is, after the oxide film is formed on the entire inner wall of the groove 100, the side oxide film is removed by etching. Thereafter, an oxide film is formed again on the side and bottom surfaces of the groove.

  Further, the case where the gate electrode 50 and the bottom electrode 150 are formed in the same process and the material of the gate electrode 50 and the material of the bottom electrode 150 are the same has been described above as an example. However, the gate electrode 50 and the bottom electrode 150 may be formed in different steps. In this case, the material of the gate electrode 50 and the material of the bottom electrode 150 may be different.

<Modification>
FIG. 1 shows an example in which the bottom electrode 150 is disposed on the inner wall insulating film 40 on the bottom surface of the groove. However, for example, when it is not necessary to reduce the feedback capacitance between the gate and the collector by arranging the bottom electrode 150 on the bottom surface of the groove, the bottom electrode 150 may not be formed. FIG. 13 shows an example of a semiconductor device according to a modification of the embodiment of the present invention in which the bottom electrode 150 is not arranged. By not forming the bottom electrode 150, the semiconductor device can be manufactured more easily. For example, the structure shown in FIG. 13 can be employed when the width W of the groove is so narrow that the feedback capacitance generated on the bottom surface of the groove does not affect the characteristics of the semiconductor device.

(Other embodiments)
As mentioned above, although this invention was described by embodiment, it should not be understood that the description and drawing which form a part of this indication limit this invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

  For example, the case where the semiconductor device is an n-channel type has been described above as an example. However, the semiconductor device may be a p-channel type.

  As described above, the present invention naturally includes various embodiments that are not described herein. Therefore, the technical scope of the present invention is defined only by the invention specifying matters according to the scope of claims reasonable from the above description.

DESCRIPTION OF SYMBOLS 10 ... Drift region 15 ... High concentration region 20 ... Base region 30 ... Emitter region 40 ... Inner wall insulating film 50 ... Gate electrode 60 ... Collector region 65 ... Field stop region 70 ... Interlayer insulating film 80 ... Collector electrode 90 ... Emitter electrode 100 ... Groove 150 ... Bottom electrode

Claims (9)

A first semiconductor region of a first conductivity type;
A second semiconductor region of a first conductivity type disposed on the first semiconductor region and having an impurity concentration higher than that of the first semiconductor region;
A third semiconductor region of a second conductivity type disposed on the second semiconductor region;
A fourth semiconductor region of a first conductivity type disposed on the third semiconductor region;
An inner wall insulating film disposed on the inner wall of the groove extending from the upper surface of the fourth semiconductor region and penetrating the fourth semiconductor region and the third semiconductor region and reaching at least the upper portion of the second semiconductor region;
And a control electrode disposed on the inner wall insulating film on the side surface of the groove so as to face the side surface of the third semiconductor region. In a plan view of the peripheral area including the end of the groove in the longitudinal direction,
The outer edge of the second semiconductor region is located outside the outer edge of the fourth semiconductor region disposed along the groove,
The semiconductor device according to claim 1, wherein the groove extends to the outside of the outer edge of the second semiconductor region.   3. The semiconductor device according to claim 2, wherein a distance along the groove from the outer edge of the second semiconductor region to the end of the groove is larger than a film thickness of the second semiconductor region.   The film thickness of the said inner wall insulating film is thicker on the outer side than the area | region where the said 4th semiconductor region is arrange | positioned rather than the area | region where the said 4th semiconductor region is arrange | positioned. Semiconductor device. A bottom electrode that is insulated from the control electrode and disposed on the inner wall insulating film at the bottom of the groove;
The distance between the control electrode and the bottom electrode along the direction perpendicular to the longitudinal direction of the groove is larger than the region where the fourth semiconductor region is disposed than the region where the fourth semiconductor region is disposed. The semiconductor device according to claim 2, wherein the semiconductor device is narrow outside. A bottom electrode that is insulated from the control electrode and disposed on the inner wall insulating film at the bottom of the groove;
4. The outer edge of the second semiconductor region is located on an inner side in a plan view than a gap portion between the control electrode and the bottom electrode at an end portion in the longitudinal direction of the groove. 5. 2. The semiconductor device according to claim 1.   7. The semiconductor device according to claim 1, wherein an impurity concentration of the second semiconductor region is lower than an impurity concentration of the third semiconductor region.   The length in the extending direction of the groove in plan view is longer than the width of the groove, and the width of the groove is wider than the interval between the adjacent grooves. 2. A semiconductor device according to item 1. A collector region of a second conductivity type;
A first conductivity type field stop region having an impurity concentration higher than that of the first semiconductor region, disposed on the upper surface of the collector region;
9. The semiconductor device according to claim 1, wherein the first semiconductor region is disposed on an upper surface of the field stop region.

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