JP3218573U - Semiconductor device - Google Patents

Abstract

A trench type semiconductor device in which a decrease in breakdown voltage is suppressed is provided. A first conductive type first semiconductor region, a second conductive type second semiconductor region disposed on the first semiconductor region, and a second semiconductor extending from an upper surface of the second semiconductor region. An insulating film 40 disposed on the bottom and inner wall of the groove that reaches the first semiconductor region through the region, and is disposed inside the groove so as to face the second semiconductor region through the insulating film, and the upper surface of the groove The control electrode 50 is inclined so as to be lowered toward the center portion, and has a portion facing the upper portion of the control electrode through the insulating film, and is in contact with the periphery of the side surface of the groove on the upper surface of the second semiconductor region. The first conductive type third semiconductor region 30 is disposed, the interlayer insulating film 70 disposed on the control electrode, and the main electrode disposed on the interlayer insulating film, and the width W1 of the groove is 3 μm to 20 μm. An electrode is formed at the center of the bottom of the groove sandwiched between the control electrodes. Not. [Selection] Figure 1

Description

  The present invention relates to a semiconductor device having a trench type gate electrode structure.

  An insulated gate bipolar transistor (IGBT) has a high input impedance and a low on-voltage. For this reason, an IGBT having a trench-type gate electrode structure is used in a motor drive circuit or the like. However, in the IGBT, the breakdown voltage and the on-voltage are in a trade-off relationship.

  For this reason, various methods have been proposed to reduce the on-voltage while maintaining a high breakdown voltage. For example, a method has been proposed in which a low on-resistance is realized by using an emitter layer whose injection efficiency is optimally set low and an insulated gate portion whose depth, width and interval are optimally set (see, for example, Patent Document 1). ).

JP-A-5-243561

  In a semiconductor device having a trench-type gate electrode structure in which a gate electrode is formed inside a trench, when the gate electrode is not completely buried in the trench, an interlayer insulating film on the gate electrode or a part of the upper electrode Falls into the groove. In that case, when heat is applied to the interlayer insulating film by heat treatment, a part of the interlayer insulating film separating the gate electrode and the source electrode on the groove enters the groove, and the thickness of the interlayer insulating film is reduced by heat treatment. Is a problem. As a result, the gate-source breakdown voltage decreases.

  In view of the above problems, an object of the present invention is to provide a semiconductor device having a trench type gate electrode structure in which a decrease in breakdown voltage is suppressed.

  According to one aspect of the present invention, (a) a first conductive type first semiconductor region, (b) a second conductive type second semiconductor region disposed on the first semiconductor region, and (c) a first (2) an insulating film disposed on the bottom and inner walls of the groove extending from the upper surface of the semiconductor region and extending through the second semiconductor region to reach the first semiconductor region; (d) the second semiconductor region via the insulating film; A control electrode that is disposed inside the groove and is inclined so that the upper surface is lowered toward the center of the groove; and (e) a portion that opposes the upper part of the control electrode through an insulating film. A third semiconductor region of the first conductivity type disposed on the upper surface of the second semiconductor region in contact with the periphery of the side surface of the groove; (f) an interlayer insulating film disposed on the control electrode; and (g) an interlayer insulation. A main electrode disposed on the membrane, and (h) the width of the groove is 3 μm to 20 μm, and (b) sandwiched between the control electrodes A semiconductor device in which no electrode is formed is provided at the center of the bottom of the groove.

  According to the present invention, it is possible to provide a semiconductor device having a trench type gate electrode structure in which a decrease in breakdown voltage is suppressed.

1 is a schematic cross-sectional view showing a structure of a semiconductor device according to an embodiment of the present invention. It is typical sectional drawing for demonstrating the shape of the control electrode of the semiconductor device which concerns on embodiment of this invention. It is typical sectional drawing for demonstrating the control electrode of a comparative example. It is typical process sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention (the 1). It is typical process sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention (the 2). It is typical process sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention (the 3). It is typical process sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention (the 4). It is typical process sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention (the 5). It is typical process sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention (the 6). It is typical process sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention (the 7). It is typical sectional drawing which shows the structure of the semiconductor device which concerns on the modification of embodiment of this invention. It is typical sectional drawing which shows the structure of the semiconductor device which concerns on the other modification of embodiment of this invention.

  Next, an embodiment of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the lengths of the respective parts, and the like are different from the actual ones. Therefore, specific dimensions should be determined in consideration of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

  Further, the embodiment described below exemplifies an apparatus and a method for embodying the technical idea of the present invention. The technical idea of the present invention is based on the shape, structure, arrangement, etc. of components. It is not specified to the following. The embodiment of the present invention can be variously modified within the scope of the claims.

  A semiconductor device 1 according to the embodiment of the present invention shown in FIG. 1 includes a first conductive type first semiconductor region 10, a second conductive type second semiconductor region 20 disposed on the first semiconductor region 10, and An insulating film 40 extending from the upper surface of the second semiconductor region 20 and penetrating through the second semiconductor region 20 to reach the first semiconductor region 10 and disposed on the bottom and inner walls of the plurality of grooves, A control electrode 50 disposed inside the groove so as to face the second semiconductor region 20, and a third semiconductor region 30 of the first conductivity type disposed on the upper surface of the second semiconductor region 20 in contact with the periphery of the side surface of the groove. With.

  The first conductivity type and the second conductivity type are opposite to each other. That is, if the first conductivity type is n-type, the second conductivity type is p-type, and if the first conductivity type is p-type, the second conductivity type is n-type. Hereinafter, a case where the first conductivity type is n-type and the second conductivity type is p-type will be described as an example.

  The semiconductor device 1 according to the embodiment shown in FIG. 1 is an insulated gate bipolar transistor (IGBT). Hereinafter, for easy understanding, the first semiconductor region 10 is an n-type drift region 10, the second semiconductor region 20 is a p-type base region 20, the third semiconductor region 30 is an n-type source region 30, and control. The electrode 50 will be described as the gate electrode 50. A plurality of source regions 30 are selectively embedded in a part of the upper surface of the base region 20.

  As shown in FIG. 1, the cross-sectional structure of the gate electrode 50 cut in the film thickness direction is U-shaped, and the upper surface of the control electrode 50 near the side wall of the trench is higher than the lower surface of the source region 30. However, it is located at a lower level than the opening of the groove. The upper surface of the gate electrode 50 is inclined so as to become lower from the portion near the side wall of the groove toward the center of the groove. For example, as shown in FIG. 2, the upper surface near the sidewall of the groove of the gate electrode 50 and the semiconductor device and the horizontal plane X form an acute angle θ.

  In the semiconductor device 1, the surface of the base region 20 facing the gate electrode 50 is the channel region 100. That is, the region of the insulating film 40 formed on the side surface of the trench functions as a gate insulating film.

  In order to form a channel in the base region 20, the source region 30 needs to have a portion facing the upper portion of the gate electrode 50 with the insulating film 40 interposed therebetween. Since the upper surface of the gate electrode 50 is located below the opening of the groove, the source region 30 has a vertical portion extending in the film thickness direction while contacting the side surface of the groove from the opening of the groove. The source region 30 has a horizontal portion that extends along the upper surface of the base region 20 in connection with the vertical portion. For this reason, the cross section of the source region 30 cut in the film thickness direction of the base region 20 is L-shaped.

  It is also conceivable that the source region 30 is formed to be lower than the height of the upper surface of the gate electrode 50 by a thermal diffusion method. However, in that case, there arises a problem that the time required for forming the source region 30 increases. For this reason, it is preferable to form the source region 30 in an L shape. A method for forming the source region 30 will be described later.

  Drift region 10 is arranged on one main surface of p-type collector region 60. A collector electrode 80 electrically connected to the collector region 60 is disposed on the other main surface of the collector region 60. An n-type field stop region 65 having an impurity concentration higher than that of the drift region 10 is arranged between the drift region 10 and the collector region 60. The field stop region 65 suppresses the depletion layer from reaching the collector region 60 when turned off.

  An interlayer insulating film 70 is disposed on the upper surface of the gate electrode 50. A source electrode 90 electrically connected to the base region 20 and the source region 30 is disposed above the gate electrode 50 with the interlayer insulating film 70 interposed therebetween. The gate electrode 50 and the source electrode 90 are electrically insulated by the interlayer insulating film 70.

  In the example shown in FIG. 1, the entire interlayer insulating film 70 is embedded in a groove formed in the base region 20. Therefore, the upper surface of the source electrode 90 is flattened as compared with the case where the upper surface of the interlayer insulating film 70 is higher than the upper surface of the base region 20. As a result, it is possible to eliminate problems in the process of wire bonding on the source electrode 90 and the like.

  When the width of the groove is wide, the upper surface of the interlayer insulating film 70 is lower than the opening of the groove, and at least a part of the source electrode 90 enters the inside of the groove. The interlayer insulating film 70 falls into the trench by the heat treatment process, and the interlayer insulating film 70 becomes thin on the upper surface of the gate electrode 50 (on the opening side of the trench). For this reason, the breakdown voltage between the gate and the source of the semiconductor device 1 is lowered.

  However, in the example shown in FIG. 1, since the upper surface of the gate electrode 50 is inclined toward the central portion of the groove, the interlayer insulating film 70 can be prevented from being thinned at the opening of the groove due to heat treatment or the like. Therefore, a pressure | voltage resistant fall is suppressed.

  Here, the operation of the semiconductor device 1 will be described. A predetermined collector voltage is applied between the source electrode 90 and the collector electrode 80, and a predetermined gate voltage is applied between the source electrode 90 and the gate electrode 50. For example, the collector voltage is about 300V to 1600V, and the gate voltage is about 10V to 20V. When the semiconductor device 1 is turned on in this way, the channel region 100 is inverted from the p-type to the n-type to form a channel. Electrons are injected from the source electrode 90 into the drift region 10 through the formed channel. The injected electrons cause a forward bias between the collector region 60 and the drift region 10, and holes move from the collector electrode 80 through the collector region 60 in the order of the drift region 10 and the base region 20. . As the current is further increased, holes from the collector region 60 increase and holes are accumulated below the base region 20. As a result, the ON voltage decreases due to conductivity modulation.

  When the semiconductor device 1 is changed from the on state to the off state, the gate voltage is controlled to be lower than the threshold voltage, for example, so that the gate voltage becomes the same potential as the source voltage or a negative potential. Thereby, the channel region 100 disappears, and the injection of electrons from the source electrode 90 to the drift region 10 stops. Since the potential of the collector electrode 80 is higher than that of the source electrode 90, the depletion layer spreads from the interface between the base region 20 and the drift region 10 and holes accumulated in the drift region 10 escape to the source electrode 90. . The above is the operation of the semiconductor device 1.

  By the way, the ON voltage decreases as the groove width W1 increases. This is due to the following reason.

  When the semiconductor device 1 is turned on, electrons that have passed through the channel formed in the channel region 100 and moved mainly along the side surface of the groove from the source electrode 90 are injected into the drift region 10. The injected electrons cause forward bias between the collector region 60 and the drift region 10, and holes move from the collector region 60 to the drift region 10. The width W1 of the groove is, for example, about 3 μm to 20 μm. On the other hand, the thickness of the drift region 10 below the bottom of the groove is, for example, 30 μm to 180 μm, which is sufficiently wider than the width W1 of the groove. For this reason, even if the width W1 of the groove is increased, the electrons moved along the groove are diffused in the drift region 10 in a region deeper than the groove. As a result, not only the interface between the collector region 60 and the drift region 10 immediately below the inter-groove region, but also the interface between the collector region 60 and the drift region 10 is forward-biased in a wider range, and holes are transferred from the collector region 60 to the drift region. Move to 10.

  The holes that have moved from the collector region 60 are prevented from moving by the bottom of the groove, and the holes are accumulated in the drift region 10 near the bottom of the groove, resulting in conductivity modulation. As the width W1 of the groove is wider, holes are more easily accumulated in the drift region 10 near the bottom of the groove. Therefore, in order to reduce the number of holes moving to the source electrode 90, the on-voltage can be reduced by forming the groove width W1 wider than the width W2 of the base region 20 in contact with the source electrode 90.

  Further, when the semiconductor device 1 is turned from the on state to the off state, a depletion layer spreads in the drift region 10 not only from the PN junction interface side with the base region 20 but also from the periphery of the bottom of the groove where the gate electrode 50 is formed. To go. At this time, it is preferable that the depletion layer spreads uniformly and spreads over a wider range. When the depletion layer spreads unevenly or narrowly, the breakdown voltage decreases. When the width W1 of the groove is narrow, both end portions of the bottom portion of the groove, which is the electric field concentration point, are close to each other, so that the depletion layer is not uniformly spread over the wide area directly below the bottom portion of the groove. However, when the width W1 of the groove is wide, since the end portions of the bottom portion of the groove are separated from each other, the depletion layer immediately below the bottom portion of the groove between the end portions spreads more uniformly or over a wider range. For this reason, the breakdown voltage is improved in the semiconductor device 1 having the wide groove width W1. Considering the on-voltage, W1 / W2 is preferably about 1.5-2.

  Furthermore, since the width W1 of the groove is wide, the gate resistance is reduced. For this reason, the semiconductor device 1 can be operated at high speed. Even when a large number of elements are arranged in the same chip, the element operation in the semiconductor device 1 can be made uniform.

  On the other hand, the wider the groove width W1, the more easily the lower surface of the source electrode 90 enters the groove. When the position of the upper surface of the gate electrode 50 and the opening of the groove is the same, the wider the groove width W1, the more the gate electrode 50 and the interlayer insulating film 70 are recessed at the center of the groove 200 as shown in FIG. It is easy to become. As described above, the film thickness d at the opening of the groove 200 of the interlayer insulating film 70 is reduced, and the breakdown voltage of the semiconductor device is reduced.

  However, in the semiconductor device 1, since the upper surface of the gate electrode 50 is inclined so as to become lower toward the center of the groove, the film thickness of the interlayer insulating film 70 is not reduced at the opening of the groove. For this reason, in the semiconductor device 1, a pressure | voltage resistant fall is suppressed. Further, the width of the interlayer insulating film 70 is formed thicker on the bottom side of the groove than on the opening side of the groove. As shown in FIGS. 1 and 2, the width of the bottom surface where the gate electrode 50 is not formed in the groove is a, the maximum value of the width of the interlayer insulating film 70 formed on the side surface of the gate electrode 50 is b1, and the gate electrode When the minimum value of the film thickness of the interlayer insulating film 70 formed on 50 is b2, if a> 2 × b1> 2 × b2> 0, the interlayer insulating film 70 is not formed thick. Can withstand pressure.

  In the semiconductor device 1 shown in FIG. 1, insulation is performed so that the thickness t1 of the region disposed at the bottom of the groove is thicker than the thickness t2 of the region disposed on the side surface of the groove and facing the base region 20. A film 40 is formed. In the semiconductor device 1, since the width W1 of the groove in which the gate electrode 50 is formed is wide, the parasitic capacitance (Cgd) generated between the gate electrode 50 disposed at the bottom of the groove and the semiconductor region tends to increase. However, the parasitic capacitance (Cgd) can be reduced by increasing the thickness of the insulating film 40 on the bottom side of the trench. Thereby, the operation speed (switching operation) of the semiconductor device 1 is improved.

  Since the side surface side of the insulating film 40 functions as a gate insulating film, there is a limit to increasing the film thickness on the side surface side of the insulating film 40. For this reason, it is preferable to make the film thickness on the bottom side of the insulating film 40 thicker than the film thickness on the side surface side of the insulating film 40. The thickness t1 at the bottom of the groove of the insulating film 40 is, for example, about 300 nm, and the thickness t2 at the side surface of the groove is, for example, about 100 nm.

  As described above, in the semiconductor device 1 according to the embodiment of the present invention, the upper surface is inclined so as to become lower from the portion in contact with the side wall of the groove toward the center of the groove. For this reason, the film thickness of the interlayer insulating film 70 is not thinned at the opening of the groove, and the breakdown voltage of the semiconductor device 1 is suppressed.

  A method for manufacturing the semiconductor device 1 according to the embodiment of the present invention will be described with reference to FIGS. In addition, the manufacturing method described below is an example, and it is needless to say that it can be realized by various other manufacturing methods including this modified example.

  As shown in FIG. 4, on the n − type drift region 10 formed on the stacked body of the p − type collector region 60 and the n + type field stop region 65, p − is applied by an impurity diffusion method or an epitaxial growth method. A mold base region 20 is formed. For example, according to the impurity diffusion method, a p-type impurity is injected into the drift region 10 from the upper surface of the drift region 10 by ion implantation, and then diffusion is performed by annealing, so that the base region 20 has a substantially uniform thickness. It is formed. The p-type impurity in the base region 20 is, for example, boron (B).

  Next, as shown in FIG. 5, a groove 200 extending from the upper surface of the base region 20 and penetrating through the base region 20 to reach the drift region 10 is formed by a photolithography technique and an etching technique.

  Thereafter, as shown in FIG. 6, an insulating film 40 is formed on the inner wall and the bottom of the groove 200. For example, a silicon oxide (SiO2) film is formed by a thermal oxidation method. At this time, the insulating film 40 is formed so that the thickness t1 of the region disposed at the bottom of the groove 200 is larger than the thickness t2 of the region disposed on the side surface of the groove 200.

  Next, the gate electrode 50 is formed. For example, a polysilicon film to which impurities are added is formed inside the trench 200. At this time, since the width W1 of the groove 200 is wide, the gate electrode 50 is not completely filled as shown in FIG. 7, but is formed to have a U shape along the bottom and side surfaces of the groove.

  As shown in FIG. 8, a resist film 500 is disposed so that the upper surface of the gate electrode 50 along the base region 20 and along the trench 200 is exposed. At this time, the upper surface of the resist film 500 is made lower than the upper surface of the gate electrode 50 to expose the side surface on the upper surface side of the gate electrode 50. Then, the gate electrode 50 is selectively removed by etching using the resist film 500 as a mask. As a result, as shown in FIG. 9, the gate electrode 50 whose upper surface is located below the opening of the groove 200 is formed. At this time, etching is also performed from the side surface on the upper surface side of the gate electrode 50, and the upper surface of the gate electrode 50 can be inclined so as to become lower from the portion in contact with the side wall of the groove 200 toward the center portion of the groove 200. Although it is possible to arbitrarily set how much the position of the upper surface of the gate electrode 50 is lowered from the opening of the trench 200, the upper surface of the gate electrode 50 is etched to such an extent that the interlayer insulating film 70 does not rise so much in the opening. For example, the etching amount of the upper surface of the gate electrode 50 is about 1 μm.

  Next, as shown in FIG. 10, a part of the upper surface of the base region 20 around the opening of the groove 200 and the side wall of the groove 200 are formed by an oblique ion implantation method in which impurities are implanted obliquely from above toward the opening of the groove 200. A part is doped with n-type impurities. By diffusing this n-type impurity, an L-shaped source region 30 is formed. FIG. 9 shows an example in which impurities are doped obliquely from above as shown by an arrow toward one wall surface A of the groove 200. However, impurities are similarly doped toward the other wall surface of the groove 200. Is done. For example, impurities are doped into the base region 20 around the opening of the trench 200 from four directions. By adopting the oblique ion implantation method in this way, the source region 30 can be formed more easily than when the entire source region 30 is formed deeply along the film thickness direction.

  Further, after forming the interlayer insulating film 70 on the gate electrode 50, the source electrode 90 connected to the source region 30 and the base region 20 is formed on the interlayer insulating film 70. Further, by forming the collector electrode 80 on the back surface of the collector region 60, the semiconductor device 1 shown in FIG. 1 is completed.

  As described above, according to the method for manufacturing the semiconductor device 1 according to the embodiment of the present invention, the upper surface of the gate electrode 50 is located below the opening of the groove, and the upper surface is in contact with the sidewall of the groove. The semiconductor device 1 inclined so as to become lower from the portion toward the center of the groove can be manufactured. According to this semiconductor device 1, the film thickness of the interlayer insulating film 70 is not reduced at the opening of the groove, and the breakdown voltage of the semiconductor device 1 is suppressed.

<Modification>
In order to form a channel, the gate electrode 50 only needs to face the base region 20 on the side surface of the groove. For this reason, as shown in FIG. 11, the gate electrode 50 may not be disposed on the center of the groove bottom. That is, the cross-sectional shape of the gate electrode 50 cut in the film thickness direction is L-shaped.

  In the semiconductor device 1 shown in FIG. 11, the parasitic capacitance between the gate electrode 50 and the drift region 10 at the bottom of the trench can be reduced. Therefore, the operation speed of the semiconductor device 1 can be further improved.

  In addition, when the width W1 of the groove is not so wide, as shown in FIG. 12, the concave portion of the gate electrode 50 in the central portion of the groove becomes small. Also in this case, the upper surface of the gate electrode 50 is located below the opening of the groove, and the upper surface is inclined so as to become lower from the portion in contact with the side wall of the groove toward the central portion of the groove. A decrease in pressure resistance of the device 1 can be suppressed.

(Other embodiments)
As mentioned above, although this invention was described by embodiment, it should not be understood that the statement and drawing which form a part of this indication limit this invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

  In the above description, only the example in which the interlayer insulating film 70 is buried in the trench is shown, but it is obvious that the effect of the present invention can be obtained even if the interlayer insulating film 70 protrudes over the opening of the trench. Further, it is apparent that the effect of the present invention can be obtained even when the interlayer insulating film 70 has a shape that protrudes from the upper surface of the base region 20.

  In the above description, the semiconductor device 1 is an IGBT. However, the present invention can also be applied to a MOSFET other than an IGBT, for example, a MOSFET having a trench type gate electrode structure, and a decrease in breakdown voltage can be suppressed.

  As described above, the present invention naturally includes various embodiments not described herein. Therefore, the technical scope of the present invention is defined only by the device-specific matters according to the scope of claims reasonable from the above description.

DESCRIPTION OF SYMBOLS 1 ... Semiconductor device 10 ... Drift region, 1st semiconductor region 20 ... Base region, 2nd semiconductor region 30 ... Source region, 3rd semiconductor region 40 ... Insulating film 50 ... Gate electrode, control electrode 60 ... Collector region 65 ... Field stop Region 70 ... Interlayer insulating film 80 ... Collector electrode 90 ... Source electrode 100 ... Channel region 200 ... Groove

Claims (5)

A first semiconductor region of a first conductivity type;
A second semiconductor region of a second conductivity type disposed on the first semiconductor region;
An insulating film disposed on a bottom and an inner wall of a groove extending from the upper surface of the second semiconductor region and penetrating through the second semiconductor region to reach the first semiconductor region;
A control electrode disposed inside the groove so as to face the second semiconductor region through the insulating film, and inclined so that the upper surface is lowered toward the center of the groove;
A third semiconductor region of a first conductivity type having a portion facing the upper portion of the control electrode through the insulating film and disposed on the upper surface of the second semiconductor region in contact with the periphery of the side surface of the groove;
An interlayer insulating film disposed on the control electrode;
A main electrode disposed on the interlayer insulating film,
The width of the groove is 3 μm to 20 μm,
2. A semiconductor device according to claim 1, wherein no electrode is formed at the central portion of the bottom portion of the groove sandwiched between the control electrodes.   The width of the bottom surface of the interlayer insulating film on the central side surface of the control electrode in the trench is a, and the maximum value of the width of the interlayer insulating film between the central side surface of the control electrode and the main electrode is b1, 2. The device according to claim 1, wherein a> 2 × b1> 2 × b2> 0 when the minimum value of the film thickness of the interlayer insulating film formed on the control electrode is b2. Semiconductor device. The third semiconductor region is
A vertical portion extending in the film thickness direction while contacting the side surface of the groove from the upper surface of the second semiconductor region;
A horizontal portion connected to the vertical portion and extending along the upper surface of the second semiconductor region; and a cross section along the film thickness direction of the second semiconductor region is L-shaped. The semiconductor device according to claim 1.   4. The semiconductor device according to claim 1, wherein an upper surface of the control electrode is positioned below an opening of the groove. 5.   5. The semiconductor device according to claim 1, wherein at least a part of a bottom surface of the main electrode is located in the groove lower than a position of the opening of the groove.

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