JP6241640B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device having an IGBT structure.

  Insulated gate bipolar transistors (IGBTs) are mainly used as switching elements in motor drive circuits and the like. As such an IGBT structure, a structure having a trench in which a gate electrode is embedded on a substrate surface is widely known.

  As shown in FIG. 1, a conventional IGBT having a trench gate structure includes a semiconductor substrate 1, an emitter electrode 2, a collector electrode 3, a gate electrode 4, and a gate provided on the wall surface of a trench 5 formed of a recess or a groove. An insulating film 6 and an interlayer insulating film 7 are included.

  Semiconductor substrate 1 has a P + -type collector region 8, an N + -type buffer region 9, an N − -type drift region 10, a P-type base region 11, and an N-type emitter region 12. The N − type drift region 10 or a combination of the N − type drift region 10 and the N + type buffer region 9 can also be called an N type base region.

The trench 5 extends from one main surface 13 of the semiconductor substrate 1 toward the other main surface 14 and P
It is formed deeper than the mold base region 11. The gate electrode 4 made of conductive polycrystalline silicon or the like is opposed to the wall surface of the trench 5 through the gate insulating film 6. Since the P-type base region 11 is exposed in the trench 5, a portion along the trench 5 of the P-type base region 11 becomes a channel portion.

  A recess 15 for exposing the side surface of the emitter region 12 and the P-type base region 11 is formed between the trenches 5 on one main surface 13 of the semiconductor substrate 1. The emitter electrode 2 is disposed so as to fill the recess 15 and is connected to the emitter region 12 and the P-type base region 11. The collector electrode 3 is disposed on the other main surface 14 of the semiconductor substrate 1 and connected to the P-type collector region 8.

  When a voltage higher than that of the emitter electrode 2 is applied to the gate electrode 4 of the IGBT, an N channel is formed in a portion along the trench 5 of the P-type base region 11, and a current flows between the collector electrode 3 and the emitter electrode 2. . The IGBT as described above is known, for example, in the following Patent Document 1.

2009-152364

  However, as the characteristics of such an IGBT, it is desired to improve the breakdown resistance with a low on-voltage, but it has been difficult to achieve both. In view of such problems, it is an object of the present invention to provide a semiconductor device capable of further improving the breakdown resistance while maintaining a low on-voltage.

According to one aspect of the present invention, a semiconductor substrate having one main surface and the other main surface, a p-type collector region formed in the semiconductor substrate, and disposed on the collector region in the semiconductor substrate An n-type drift region formed in the semiconductor substrate, a p-type base region disposed on the drift region in the semiconductor substrate, and a base region that forms a pn junction with the base region in the semiconductor substrate. A partially disposed n-type emitter region, a plurality of grooves penetrating the emitter region and the base region from one main surface of the semiconductor substrate, and gates disposed on the bottom and side surfaces of the groove An oxide film, and a gate electrode embedded in the groove so as to face the base region through the gate oxide film, and both the base region and the emitter region The main surface of one side of the semiconductor substrate is alternately in contact with the side wall surface extending the groove, and extends in parallel with the direction in which the groove extends away from the groove between the groove and the groove, A hole having a depth penetrating the emitter region from one main surface of the semiconductor substrate is formed, and a plurality of the holes are formed in the extending direction of the groove , and the holes are parallel to the extending direction of the groove. And a pair of second side walls provided between the first side walls as viewed from above, the first side walls being An emitter region is formed, and the second sidewall is formed by the base region;
An emitter electrode formed on one main surface of the semiconductor substrate is in contact with the base region at a bottom portion and a second side wall portion of the hole.

  ADVANTAGE OF THE INVENTION According to this invention, the semiconductor device which can aim at the further improvement of a destruction tolerance can be provided, maintaining a low on-voltage.

It is sectional drawing of the conventional IGBT. 1 is a schematic cross-sectional view showing a structure of a semiconductor device according to a first embodiment of the present invention. 1 is a schematic perspective view showing a structure of a semiconductor device according to a first embodiment of the present invention. 1 is a schematic top view showing a structure of a semiconductor device according to a first embodiment of the present invention. FIG. 5 is a schematic cross-sectional view along the AA direction of the semiconductor device shown in FIG. 4. It is a typical perspective view which shows the structure of the semiconductor device which concerns on the 2nd Embodiment of this invention.

  Next, an embodiment of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic and ratios of thicknesses of the respective regions are different from actual ones. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

This semiconductor device (IGBT) is a trench gate type element having a configuration in which a gate is formed in a groove (trench) formed in a semiconductor substrate. 2, in the semiconductor substrate 50 is on the ^{p +} region (fourth semiconductor region) 21 serving as a collector region, ^{n +} region 40 serving as a buffer region, a drift region n ^- region (first A semiconductor region) 22 and a p ⁻ region (second semiconductor region) 23 serving as a base region are sequentially formed. On one main surface of the semiconductor substrate 50, a groove (trench) 30 is formed which penetrates the p ⁻ region 23 (second semiconductor region) from the main surface and reaches the n ⁻ region (first semiconductor region) 22. Has been. A plurality of grooves 30 are formed in parallel to extend in a direction perpendicular to the paper surface in FIG. A gate oxide film 26 is uniformly formed on the inner surface (side surface) of the groove 30, and a gate electrode 27 is formed so as to fill the groove 30.

On one main surface of the semiconductor substrate 50, n ⁺ regions (third semiconductor regions) 24 serving as emitter regions are formed on both sides of the groove 30. A collector electrode (back surface electrode) 29 is formed on the other main surface of the semiconductor substrate 50 so as to be electrically connected to the collector region 21. On one main surface of the semiconductor substrate 50, an emitter electrode (common electrode) 28 is formed. However, since the interlayer insulating film 25 is formed so as to cover the gate electrode 27 (groove 30) above the trench 30, the emitter electrode (common electrode) 28 is formed in the emitter region 24 through the opening of the interlayer insulating film 25. Are electrically connected to both the base region 23 and insulated from the gate electrode 27.

In this semiconductor device, for each groove 30, a channel is generated in the base region 23 on the side surface of the groove 30 by the voltage applied to the gate electrode 27, and current can flow through this channel. Therefore, it operates as an n-channel MOSFET between the drift region 22 and the emitter region 24. When this MOSFET is turned on, in addition to the operation as a normal MOSFET, holes are injected from the collector region 21 to the drift region side, so that conductivity modulation occurs in the drift region, and the on-resistance of the IGBT is particularly small. Become. For this reason, a particularly large current can flow. In other words, the current applied between the emitter electrode (common electrode) 28 and the collector electrode (back electrode) 29 can be controlled by the voltage applied to the gate electrode 27.

Between adjacent grooves 30, a hole 31 is shown as an emitter connection opening. The emitter electrode 28 and the semiconductor substrate 50 are in direct contact with each other through this hole 31. The hole 31 is deeper from one main surface of the semiconductor substrate 50 than the lower surface of the emitter region 24, and its bottom is dug down to a depth at which a part of the base region 23 is exposed.

The configuration in the cross-sectional view shown in FIG. 2 is the same as that of the conventional IGBT shown in FIG. 1, but the characteristic portion of the present invention is disclosed in FIG. 3, which is a perspective view from a top perspective view. In FIG. 3, the emitter electrode 28 is seen through. In FIG. 3, the holes 31 are formed in the direction in which the grooves 30 extend. In the direction in which the grooves 30 extend, the emitter regions 24 and the base regions 23 are alternately arranged so as to be in contact with the side surfaces of the grooves 30. It is formed on one main surface of the substrate 50. Thus, in the direction in which the groove 30 extends, the emitter region 24 is thinned to form the base region 23a exposed on the side wall of the hole 31, thereby increasing the contact area between the emitter electrode 28 and the base region, Since the number of holes extracted when the IGBT is turned off increases, the amount of remaining holes when the IGBT is turned off decreases. Therefore, it contributes to the improvement of the breakdown tolerance due to the remaining holes when the IGBT is turned off.

Although it is possible to increase the area of the base region 23 in contact with the emitter electrode 28 by digging the hole 31 deeply without thinning the emitter region 24 along the direction of the groove 30, the hole 31 is formed in the semiconductor substrate 50. It is not desirable to dig too deep from the surface. First, the emitter electrode 28 is embedded in the hole 31. However, if the hole 31 is formed deeply, the emitter electrode 28 does not reach the bottom of the hole 31, and the contact with the base region 23 is sufficiently low. This is because it is considered that the remaining holes cannot be extracted well when the IGBT is turned off. Second, when the base region 23 is formed by impurity diffusion, the concentration on one main surface side of the semiconductor substrate 50 is high and gradually decreases toward the inside of the semiconductor substrate 50. Since the hole 31 is formed by etching after the base region 23 is formed, the deeper the hole 31 is, the lower the impurity concentration is exposed at the bottom of the hole 31. This is because a sufficiently low contact with the emitter electrode 28 cannot be obtained, and the remaining holes when the IGBT is turned off cannot be extracted well. Therefore, it is sufficient that the hole 31 is deeper than the lower surface of the emitter region 24 from one main surface of the semiconductor substrate 50 and the bottom thereof is dug down to a depth at which a part of the base region 23 is exposed.

Next, an interval for thinning the emitter region 24 in the extending direction of the groove 30 will be described. FIG. 4 is a perspective view of the IGBT according to the present invention seen through the emitter electrode 28 and the interlayer insulating film 25 from the upper surface direction. On one main surface of the semiconductor substrate 50, the emitter regions 24 and the base regions 23 a are alternately arranged so as to be in contact with the side surfaces of the grooves 30. The emitter region 24 extends in the vertical direction with respect to the groove 30 as viewed from above, with the groove 30 and the hole 31 interposed therebetween.
Here, when the width in the direction of the groove 30 in the emitter region 24 is W1, and the width in the direction of the groove 30 in the base region 23a sandwiched between the emitter regions is W2, the ratio between W1 and W2 is as follows. , W2 is preferably 0.8 to 9.0, and more preferably 0.8 to 6.0. This is because if W2 is made smaller than 0.8 with respect to W1, the base region 23a sandwiched between the emitter regions 24 becomes smaller, so that the contact area with the emitter electrode 28 also becomes smaller, and holes are pulled out when the IGBT is off. This is because the frontage is narrowed, leading to a reduction in fracture resistance.
On the other hand, if W2 is set to be larger than 9.0 with respect to W1, the current path in the channel region formed on the side surface of the groove 30 is reduced when the IGBT is turned on, and the on-voltage is increased. . The mechanism is described in a little more detail below.

  FIG. 5 is a cross-sectional view along the direction AA in FIG. When a voltage higher than that of the emitter electrode 28 is applied to the gate electrode 27 of the IGBT, an N channel region 60 is formed in a portion along the groove 30 of the P-type base region 23, and a current flows between the collector electrode 29 and the emitter electrode 28. Flows. Here, as is well known, electrons are supplied from the emitter region 24, but as shown in FIG. 5, the electrons move so as to spread in an obliquely downward direction of the emitter region 24. Therefore, even in the lower part of the base region 23 a sandwiched between the emitter regions 24, a current path is formed by supplying electrons from the adjacent emitter regions 24. As a result, the current path can be secured and the on-voltage can be kept low, while the base region 23a formed by thinning the emitter region widens the hole extraction hole when the IGBT is off, thereby improving the breakdown resistance. be able to.

  However, if the width (W2) of the base region 23a sandwiched between the plurality of emitter regions 24 is made too wide, a region where no current path is formed is formed below the base region 23a sandwiched between the emitter regions. If the base region 23a has a large width (W2) even if electrons move so as to spread obliquely downward from the adjacent emitter regions 24, the channel region 60 formed below the base region 23a This is because electrons are not spread all over and a current path is not secured in that portion. For this reason, there arises a disadvantage that the on-voltage increases. Therefore, when the width of W1 is 1, the width of W2 is preferably 0.8 to 9.0, and more preferably the width of W2 is 0.8 to 6.0. Thereby, it is possible to realize an IGBT having an improved breakdown resistance while maintaining the on-voltage low.

  FIG. 6 shows a second embodiment of the present invention. The IGBT according to the second embodiment is different from that according to the first embodiment only in the shape of the hole 31. In the IGBT according to the first embodiment, one hole 31 is formed between the groove 30 and the groove 30 so as to be separated from the groove 30, and the emitter region 24 and the base region 23 a are the same on the side wall of the hole 31. Alternatingly arranged on the surface. On the other hand, in the IGBT according to the second embodiment shown in FIG. 6, a plurality of holes 31 are formed between the groove 30 and the groove 30 so as to be separated from the groove 30 in the extending direction of the groove 30. Is constituted by a pair of first side wall portions 70 opposed to each other and a pair of second side wall portions 80 provided between the first side wall portions 70 as viewed from above. The first side wall portion 70 is an emitter. The region 24 has a part of the base region 23 a on both sides thereof, and the second side wall 80 is formed by the base region 23. However, the first side wall portion 70 only needs to include the emitter region 24, and does not necessarily have to have part of the base region 23 a on both sides thereof.

In other words, in the second embodiment, the hole 31 is formed by being thinned out in the extending direction of the groove 30, similarly to the emitter region 24. Compared with the IGBT of the first embodiment, the region where the holes 31 are formed is reduced, and the area of the base region 23 on one main surface of the semiconductor substrate 50 is increased. Thereby, since the impurity concentration is higher on the one main surface of the semiconductor substrate 50 than the bottom of the hole 31 as described above, sufficient ohmic property with the emitter electrode 28 is ensured when connecting to the emitter electrode 28. Can make good contact,
. Therefore, the emitter region 24 is exposed on the side wall of the emitter. More reliability can be improved.
Further, since the base region is exposed at the second side wall portion of the hole 31, a sufficient base region in contact with the emitter electrode 28 can be secured, and the breakdown resistance is higher than that of the IGBT according to the first embodiment. There is no decline.
That is, the IGBT according to the second embodiment can improve the breakdown withstand while maintaining the low on-voltage, similarly to the IGBT according to the first embodiment, and is further improved than the IGBT according to the first embodiment. Reliability is improved.

As described above, the present invention naturally includes various embodiments not described herein. Therefore, the technical scope of the present invention is defined only by the invention specifying matters according to the scope of claims reasonable from the above description.

21 ... Collector region 22 ... Drift region 23, 23a ... Base region 24 ... Emitter region 25 ... Interlayer insulating film 26 ... Gate oxide film 27 ... Gate electrode 28 ... Emitter electrode 29 ... Collector electrode 30 ... Groove 31 ... Hole 40 ... Buffer region 50 ... Semiconductor substrate 60 ... Channel region 70 ... First side wall 80 ... First Second side wall

Claims (2)

A semiconductor substrate having one main surface and the other main surface;
A p-type collector region formed in the semiconductor substrate;
An n-type drift region disposed on the collector region in the semiconductor substrate;
A p-type base region disposed on the drift region in the semiconductor substrate;
N-type emitter regions that are partially spaced apart from each other on the base region constituting the pn junction with the base region in the semiconductor substrate;
A plurality of grooves penetrating the emitter region and the base region from one main surface of the semiconductor substrate;
A gate oxide film disposed on the bottom and side surfaces of the trench;
A gate electrode embedded in the trench facing the base region through the gate oxide film;
With
Both the base region and the emitter region are alternately in contact with the side wall surface extending the groove on one main surface of the semiconductor substrate, and are spaced from the groove between the groove and the groove. Extending in parallel with the extending direction, and having a hole having a depth penetrating the emitter region from one main surface of the semiconductor substrate,
A plurality of the holes are formed in the extending direction of the groove,
The hole is
A pair of opposed first side walls formed in parallel with the extending direction of the groove ;
It is constituted by a pair of second side walls provided between the first side walls when viewed from above,
The first sidewall is formed including the emitter region;
The second side wall is formed by the base region;
A semiconductor device, wherein an emitter electrode formed on one main surface of the semiconductor substrate is in contact with the base region at a bottom of the hole and the second side wall. 2. The semiconductor device according to claim 1, wherein a ratio of the width of the base region to the width of the emitter region in the extending direction of the groove is 0.8 to 9.0.

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