JP2015142073A - semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a trench gate semiconductor device which has reduced capacitance between a gate and a collector and which does not cause a snapback phenomenon occurring in output characteristics.SOLUTION: A semiconductor device comprises: a collector region; a drift region arranged on the collector region; a base region arranged on a top face of the base region; a wall surface insulation film arranged on a bottom face and lateral faces of a trench which extends from a top face of the source region and pierces the source region and the base region to reach the drift region and has a trench width of 3-20 μm; a bottom electrode arranged on the wall surface insulation film at the bottom face of the trench; a bottom insulation film which is arranged on the bottom electrode inside the trench and has a film thickness thicker than a film thickness of the wall surface insulation film arranged at the bottom surface of the trench; and a gate electrode which is opposite to the base region across the wall surface insulation film arranged on the lateral face of the trench and arranged on the bottom insulation film inside the trench.

Description

  The present invention relates to a trench gate type semiconductor device.

  As a switching element (power semiconductor element) through which a large current flows, a power MOSFET, an insulated gate bipolar transistor (IGBT), or the like is used. In these switching elements, a trench type gate electrode structure (trench gate type) in which a gate insulating film and a gate electrode are formed in a groove (trench) formed in a semiconductor substrate is employed. However, in the trench gate type semiconductor device, the capacitance between the gate and the drain which is the capacitance at the bottom of the trench and the capacitance between the gate and the collector are large, so that the switching speed is lowered, causing a problem in high frequency operation.

  For this reason, for example, a semiconductor device in which a semiconductor layer is formed below the gate electrode inside the trench to reduce the gate-drain capacitance has been proposed (see, for example, Patent Document 1).

JP 2006-93506 A

  In the IGBT, when the hole injection amount from the collector region on the back surface is controlled, the negative resistance in the low current region of the Vce-Ic characteristic (output characteristic) indicating the relationship between the collector voltage Vce and the collector current Ic. There was a problem that “snapback phenomenon” appears. An object of the present invention is to provide a trench gate type semiconductor device in which the capacitance between the gate and the collector is reduced and the snapback phenomenon does not occur in the output characteristics.

  According to one aspect of the present invention, a first conductivity type collector region, a second conductivity type drift region disposed on the collector region, a first conductivity type base region disposed on the drift region, A source region of the second conductivity type disposed on the upper surface of the base region, and a groove extending from the upper surface of the source region and penetrating the source region and the base region to the drift region and having a groove width of 3 to 20 μm, On the bottom surface of the wall insulating film disposed on the bottom electrode on the bottom surface and the side surface, on the bottom electrode disposed on the wall insulating film on the bottom surface of the groove, and on the bottom electrode inside the groove Arranged on the bottom insulating film inside the groove, facing the base region through the bottom insulating film having a thickness greater than the thickness of the disposed portion and the wall surface insulating film disposed on the side surface of the groove A semiconductor device including a gate electrode is provided.

  According to the present invention, it is possible to provide a trench gate type semiconductor device in which a gate-collector capacitance is reduced and a snapback phenomenon does not occur in output characteristics.

It is a typical sectional view showing the structure of the semiconductor device concerning the embodiment of the present invention. It is a graph for demonstrating the relationship between an output characteristic and groove width. It is typical process sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention (the 1). It is typical process sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention (the 2). FIG. 9 is a schematic process cross-sectional view for explaining the manufacturing method of the semiconductor device according to the embodiment of the present invention (No. 3). FIG. 10 is a schematic process cross-sectional view for explaining the manufacturing method of the semiconductor device according to the embodiment of the present invention (No. 4). FIG. 10 is a schematic process cross-sectional view for explaining the manufacturing method of the semiconductor device according to the embodiment of the present invention (No. 5). FIG. 6 is a schematic process cross-sectional view for explaining the manufacturing method of the semiconductor device according to the embodiment of the present invention (No. 6). It is typical process sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention (the 7).

  Next, an embodiment of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the lengths of the respective parts, and the like are different from the actual ones. Therefore, specific dimensions should be determined in consideration of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

  The following embodiments exemplify apparatuses and methods for embodying the technical idea of the present invention, and the technical idea of the present invention includes the shape, structure, arrangement, etc. of components. It is not specified to the following. The embodiment of the present invention can be variously modified within the scope of the claims.

  As shown in FIG. 1, a semiconductor device 1 according to an embodiment of the present invention includes a first conductivity type collector region 10 having a first main surface 101 and a second main surface 102 facing each other, and a collector region. The second conductivity type drift region 20 disposed above the first main surface 101 of the tenth, the first conductivity type base region 30 disposed on the drift region 20, and the upper surface of the base region 30 And a source region 40 of the second conductivity type.

  The first conductivity type and the second conductivity type are opposite to each other. That is, if the first conductivity type is p-type, the second conductivity type is n-type. If the first conductivity type is n-type, the second conductivity type is p-type. Hereinafter, a case where the first conductivity type is p-type and the second conductivity type is n-type will be described as an example.

  The semiconductor device 1 shown in FIG. 1 is an insulated gate bipolar transistor (IGBT). That is, a groove extending from the upper surface of the source region 40 and penetrating the source region 40 and the base region 30 to reach the drift region 20 is formed, and the wall insulating film 50 is disposed on the bottom surface and the side surface of the groove. ing. Inside the trench, the bottom electrode 160 is disposed on the wall insulating film 50 at the bottom of the trench, the bottom insulating film 170 is disposed on the bottom electrode 160, and the gate electrode 60 is disposed on the bottom insulating film 170. Yes. For the gate electrode 60 and the bottom electrode 160, for example, a polysilicon film or a metal film such as an aluminum film is used. For example, a silicon oxide film or the like can be used for the wall surface insulating film 50 and the bottom insulating film 170.

  The gate electrode 60 is opposed to the base region 30 and the source region 40 through a wall insulating film 50 disposed on the side surface of the trench. Although details will be described later, the thickness t2 of the bottom insulating film 170 is thicker than the thickness t1 of the portion disposed on the bottom surface of the groove of the wall surface insulating film 50.

  In the semiconductor device 1, the surface portion of the base region 30 facing the gate electrode 60 is a channel region 100 where a channel is formed. The gate electrode 60 is arranged to face the base region 30 so that a channel is formed in the base region 30 along the groove from the source region 40 to the drift region 20. That is, the region sandwiched between the gate electrode 60 and the base region 30 of the wall surface insulating film 50 functions as a gate insulating film.

  The semiconductor device 1 includes a collector electrode 80 disposed on the second main surface 102 of the collector region 10 and a source electrode 90 disposed above the gate electrode 60 and electrically connected to the base region 30 and the source region 40. And further comprising. The source electrode 90 is electrically connected to the base region 30 and the source region 40 through an opening provided in the interlayer insulating film 70 disposed on the upper surface of the gate electrode 60. The gate electrode 60 and the source electrode 90 are electrically insulated by the interlayer insulating film 70.

  As shown in FIG. 1, a second conductivity type (n-type) field stop region 15 having an impurity concentration higher than that of the drift region 20 may be disposed between the drift region 20 and the collector region 10. The field stop region 15 suppresses the depletion layer extending downward from the upper surface of the drift region 20 from reaching the collector region 10 when turned off.

  Here, the operation of the semiconductor device 1 will be described. A predetermined collector voltage is applied between the source electrode 90 and the collector electrode 80, and a predetermined gate voltage is applied between the source electrode 90 and the gate electrode 60. For example, the collector voltage is about 300V to 1600V, and the gate voltage is about 10V to 20V. When the semiconductor device 1 is turned on in this way, the channel region 100 is inverted from the p-type to the n-type to form a channel. Electrons are injected from the source electrode 90 into the drift region 20 through the formed channel. A forward bias is applied between the collector region 10 and the drift region 20, and holes move from the collector electrode 80 through the collector region 10 to the drift region 20 and the base region 30 in this order. As the current is further increased, holes from the collector region 10 increase and holes are accumulated below the base region 30. As a result, the ON voltage decreases due to conductivity modulation.

  When switching the semiconductor device 1 from the on state to the off state, the gate voltage is controlled to be lower than the threshold voltage. For example, the gate voltage is set to the same potential as the source voltage or a negative potential. Thereby, the channel of the base region 30 disappears, and the injection of electrons from the source electrode 90 to the drift region 20 is stopped. Since the potential of the collector electrode 80 is higher than that of the source electrode 90, the depletion layer spreads from the interface between the base region 30 and the drift region 20, and holes accumulated in the drift region 20 escape to the source electrode 90. . The above is the operation of the semiconductor device 1.

  In the conventional trench gate type IGBT, the gate-collector capacitance Cgc, which is the capacitance at the bottom of the groove in which the gate electrode 60 is disposed, is large, and there is a problem in that the switching speed decreases. In contrast, in the semiconductor device 1, a capacitor layer having a structure in which the bottom electrode 160 is covered with the wall surface insulating film 50 and the bottom insulating film 170 is formed at the bottom of the groove. For this reason, the capacitance Cgc between the gate and the collector of the semiconductor device 1 is reduced. As a result, a decrease in switching speed of the semiconductor device 1 can be suppressed.

  Moreover, the gate-collector capacitance Cgc can be further reduced by adopting a structure in which the gate electrode 60 and the drift region 20 are not opposed to each other on the side surface of the groove. That is, it is preferable that the gate electrode 60 is disposed in the remaining region of the region facing the drift region 20 of the wall surface insulating film 50 on the side surface of the trench. For this reason, in the semiconductor device 1 shown in FIG. 1, the gate electrode 60 is disposed inside the trench so as to face the source region 40 and the base region 30 except for the region facing the drift region 20. That is, the boundary between the gate electrode 60 and the bottom insulating film 170 coincides with the boundary between the base region 30 and the drift region 20. Thereby, the switching time of the semiconductor device 1 can be shortened.

  However, even if the boundary between the gate electrode 60 and the bottom insulating film 170 does not completely coincide with the boundary between the base region 30 and the drift region 20, the semiconductor device 1 can operate and the capacitance Cgc. Is reduced. For example, even when the end of the gate electrode 60 slightly faces the drift region 20 due to a manufacturing error or the like, the gate-collector capacitance Cgc can be sufficiently reduced. In addition, there is no problem even if a region that does not overlap with the base region 30 is generated at the end of the gate electrode 60 in a range where the semiconductor device 1 operates. Thus, in the semiconductor device 1 according to the embodiment of the present invention, the gate electrode 60 is opposed to the base region 30 except for the region opposed to the drift region 20. This is a concept including not only the case where the boundary between and the base region 30 and the drift region 20 completely coincide with each other, but also the case where they substantially coincide.

  The bottom electrode 160 is preferably set to the same potential as the source region 40. Thereby, the gate-collector capacitance Cgc can be further reduced. For example, a through hole is provided in the interlayer insulating film 70, and the through hole is filled with a conductor film to electrically connect the bottom electrode 160 and the source electrode 90.

  In that case, the gate-source capacitance can be reduced as the thickness t2 of the bottom insulating film 170 is increased. However, in order to form a channel in the base region 30, it is preferable that the position of the upper surface of the bottom insulating film 170 not be higher than the position of the lower surface of the base region 30. For this reason, in order to increase the film thickness t2 of the bottom insulating film 170, the groove is formed deeply. However, when the grooves are formed deeply, problems such as an increase in the difficulty of the process and an increase in manufacturing time occur. Therefore, the thickness t2 of the bottom insulating film 170 cannot be increased without limit. As a result of investigations by the present inventors regarding manufacturing problems and gate-source capacitance reduction, it was found that the thickness t2 of the bottom insulating film 170 is preferably about 0.5 μm to 1.5 μm.

  On the other hand, if the gate insulating film is too thin or too thick, the breakdown voltage of the semiconductor device is lowered. According to the study by the present inventors, the thickness of the gate insulating film is preferably 100 nm to 300 nm. The film thickness of the wall surface insulating film 50 may be constant between the portion disposed on the side surface of the groove functioning as the gate insulating film and the portion disposed on the bottom surface of the groove, or the bottom surface side may be thick. The film thickness t2 of the bottom insulating film 170 is thicker than the film thickness t1 of the portion disposed on the bottom surface of the groove of the film 50, and t1 <t2.

  Incidentally, in the trench gate type IGBT, when the width W of the groove in which the gate electrode 60 is disposed is narrow, as shown in the characteristic A of FIG. 2, the Vce-Ic characteristic indicating the relationship between the collector voltage Vce and the collector current Ic. Snapback phenomenon often occurs in (output characteristics). This is because holes injected from the back surface are not accumulated well.

  On the other hand, according to the study by the present inventors, when the groove width W is set to 3 μm or more, the output characteristics are linear (monotonically increasing) as shown in the characteristic B of FIG. ). This is because the movement of holes is hindered in the drift region near the bottom of the groove, and holes are more easily accumulated from the low current region.

  For this reason, in the semiconductor device 1, a groove having a width W of 3 μm or more is formed. On the other hand, if the width W of the groove in which the gate electrode 60 is embedded is too wide, there arises a problem that the on-resistance increases. This is because when the width W of the groove is wide, the density of the channel decreases and the injection of electrons decreases. Further, increasing the width W of the groove hinders miniaturization of the semiconductor device 1. Accordingly, the width W of the groove needs to be a certain level or less. As a result of repeated studies by the present inventors, the width W of the groove is preferably 20 μm or less.

  Therefore, it is preferable that the width W of the groove is about 3 μm to 20 μm. More preferably, the width W of the groove is 5 μm to 15 μm so as not to cause a snapback phenomenon in the output characteristics and to reduce the on-resistance.

  Note that if the width W of the groove is less than a certain level, the on-voltage is lowered and the breakdown voltage is improved. This is due to the following reason.

  When the semiconductor device 1 is turned on, electrons that have passed through the channel formed in the base region 30 and moved mainly along the side surface of the groove from the source electrode 90 are injected into the drift region 20. The injected electrons cause forward bias between the collector region 10 and the drift region 20, and holes move from the collector region 10 to the drift region 20. As already described, the width W of the groove is, for example, about 3 μm to 20 μm. On the other hand, the thickness of the drift region 20 below the bottom surface of the groove is, for example, 30 μm to 180 μm, which is sufficiently wider than the width W of the groove. For this reason, even if the width W of the groove is increased, the electrons moved along the groove are diffused in the drift region 20 in a region deeper than the groove. As a result, not only the interface between the collector region 10 and the drift region 20 immediately below the inter-groove region, but also the interface between the collector region 10 and the drift region 20 is forward-biased in a wider range, and holes are transferred from the collector region 10 to the drift region. Move to 20.

  The holes that have moved from the collector region 10 are prevented from moving by the bottom surface of the groove, the holes are accumulated in the drift region 20 near the bottom surface of the groove, and conductivity modulation occurs. As the groove width W increases, holes are more likely to accumulate in the drift region 20 near the bottom of the groove. For this reason, the on-voltage can be lowered by forming the width W of the groove wide.

  Further, when the semiconductor device 1 is turned from the on state to the off state, a depletion layer spreads in the drift region 20 not only from the PN junction interface side with the base region 30 but also from the periphery of the bottom surface of the groove where the gate electrode 60 is formed. To go. At this time, it is preferable that the depletion layer spreads uniformly and spreads over a wider range. When the depletion layer spreads unevenly or narrowly, the breakdown voltage decreases. When the width W of the groove is narrow, both end portions of the bottom surface of the groove, which is an electric field concentration point, are close to each other, so that the depletion layer is not uniformly spread over a wide area directly below the bottom surface of the groove. However, when the width W of the groove is wide, since the end portions of the bottom surface of the groove are separated from each other, the depletion layer immediately below the bottom surface of the groove between the end portions spreads more uniformly or over a wider range. For this reason, in the semiconductor device 1 having a wide groove width W, the breakdown voltage is improved. According to the study by the present inventors, when the width W of the groove is 3 μm to 20 μm, the semiconductor device 1 can be reduced in ON voltage and improved in breakdown voltage.

  By the way, when the width W of the groove in which the gate electrode 60 is formed is large, the gate-collector capacitance Cgc tends to increase. However, in the semiconductor device 1, the capacitance Cgc can be reduced by disposing the capacitance portion using the bottom electrode 160 below the gate electrode 60. Thereby, the fall of the switching speed of the semiconductor device 1 is suppressed.

  As described above, in the semiconductor device 1 according to the embodiment of the present invention, the capacitor portion using the bottom electrode 160 is formed below the gate electrode 60. As a result, the gate-collector capacitance Cgc is reduced, and the switching speed of the semiconductor device 1 is improved. At this time, the film thickness t2 of the bottom insulating film 170 is formed thicker than the film thickness t1 of the portion disposed on the bottom surface of the groove of the wall surface insulating film 50.

  Furthermore, in the semiconductor device 1, the width W of the groove in which the gate electrode 60 is embedded is formed wide, for example, to about 3 μm to 20 μm. For this reason, the snapback phenomenon does not occur in the output characteristics of the semiconductor device 1.

  As described above, according to the semiconductor device 1, a trench gate type semiconductor device in which the gate-collector capacitance Cgc is reduced and the snapback phenomenon does not occur in the output characteristics is provided.

  A method for manufacturing the semiconductor device 1 according to the embodiment of the present invention will be described with reference to FIGS. In addition, the manufacturing method described below is an example, and it is needless to say that it can be realized by various other manufacturing methods including this modified example.

As shown in FIG. 3, p ^- type collector region 10 and the n ⁺ -type n formed in the field stop region 15 stack on the ^- type on the drift region 20 of, p by impurity diffusion or epitaxial growth method ^- A mold base region 30 is formed. For example, according to the impurity diffusion method, a p-type impurity is implanted into the drift region 20 from the upper surface of the drift region 20 by ion implantation, and then diffusion is performed by annealing, so that the base region 30 has a substantially uniform thickness. It is formed. The p-type impurity in the base region 30 is, for example, boron (B). Next, as shown in FIG. 4, an n ⁺ -type source region 40 is formed on a part of the upper surface of the base region 30 by using, for example, an ion implantation method and diffusion.

  Thereafter, as shown in FIG. 5, a trench 200 is formed by extending from the upper surface of the source region 40 through the source region 40 and the base region 30 by the photolithography technique and the etching technique, and reaching the drift region 20 at the tip. . The bottom surface of the groove 200 is substantially flat. At this time, the groove 200 is formed so that the width W is 3 μm to 20 μm, more preferably 5 μm to 15 μm.

Thereafter, as shown in FIG. 6, a wall insulating film 50 is formed on the inner wall surface of the groove 200. Thereby, the gate insulating film is disposed on the side surface and the bottom surface of the trench 200. For example, a silicon oxide (SiO ₂ ) film is formed by a thermal oxidation method. The film thickness t1 of the wall surface insulating film 50 is, for example, about 100 nm to 300 nm.

  After the wall surface insulating film 50 is formed, a bottom electrode 160 is formed on the wall surface insulating film 50 on the bottom surface of the groove 200 as shown in FIG. The bottom electrode 160 is made of, for example, polysilicon. Next, as shown in FIG. 8, a bottom insulating film 170 is formed on the bottom electrode 160 inside the trench 200. The bottom insulating film 170 is made of, for example, silicon oxide. At this time, the bottom insulating film 170 is formed so that the film thickness t2 is thicker than the film thickness t1 of the portion formed on the bottom surface of the groove 200 of the wall surface insulating film 50. For example, the film thickness t1 of the wall insulating film 50 is about 100 nm to 300 nm, whereas the film thickness t2 of the bottom insulating film 170 is about 0.5 μm to 1.5 μm. The position of the upper surface of the bottom insulating film 170 is set not to be higher than the position of the lower surface of the base region 30 so that the channel region 100 is formed at a position facing the gate electrode 60 of the base region 30.

  Thereafter, the gate electrode 60 is formed on the bottom insulating film 170 inside the trench 200. For example, a polysilicon film doped with impurities is buried in the trench, and the surface of the base region 30 is flattened to form the gate electrode 60 by a polishing process such as chemical mechanical polishing (CMP), as shown in FIG. .

  Further, after forming the interlayer insulating film 70 on the gate electrode 60, the source electrode 90 connected to the source region 40 and the base region 30 is formed on the interlayer insulating film 70. For example, an opening is provided in a part of the interlayer insulating film 70 to expose the surfaces of the source region 40 and the base region 30, and the source electrode 90 is formed so as to fill the opening. Further, the collector electrode 80 is formed on the second main surface 102 of the collector region 10, whereby the semiconductor device 1 shown in FIG. 1 is completed.

  By the manufacturing method described above, the capacitor portion including the bottom electrode 160 is formed below the gate electrode 60 of the semiconductor device 1. As a result, the gate-collector capacitance Cgc is reduced and the switching speed of the semiconductor device 1 is improved. At this time, the film thickness t2 of the bottom insulating film 170 is formed thicker than the film thickness t1 of the portion formed on the bottom surface of the groove of the wall surface insulating film 50. Furthermore, since the width W of the groove 200 is formed to be as wide as about 3 μm to 20 μm, for example, the snapback phenomenon does not occur in the output characteristics of the semiconductor device 1.

  Therefore, according to the manufacturing method of the semiconductor device 1 described above, it is possible to obtain a trench gate type semiconductor device in which the gate-collector capacitance Cgc is reduced and the snapback phenomenon does not occur in the output characteristics.

(Other embodiments)
As mentioned above, although this invention was described by embodiment, it should not be understood that the description and drawing which form a part of this indication limit this invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

  For example, the case where the semiconductor device 1 is an n-channel type has been described above as an example, but it is apparent that the effects of the present invention can be obtained even if the semiconductor device 1 is a p-channel type.

  As described above, the present invention naturally includes various embodiments not described herein. Therefore, the technical scope of the present invention is defined only by the invention specifying matters according to the scope of claims reasonable from the above description.

DESCRIPTION OF SYMBOLS 1 ... Semiconductor device 10 ... Collector region 15 ... Field stop region 20 ... Drift region 30 ... Base region 40 ... Source region 50 ... Wall surface insulating film 60 ... Gate electrode 70 ... Interlayer insulating film 80 ... Collector electrode 90 ... Source electrode 100 ... Channel Region 101 ... first main surface 102 ... second main surface 160 ... bottom electrode 170 ... bottom insulating film 200 ... groove

Claims (3)

A collector region of a first conductivity type;
A drift region of a second conductivity type disposed on the collector region;
A base region of a first conductivity type disposed on the drift region;
A source region of a second conductivity type disposed on the upper surface of the base region;
A wall insulating film disposed on a bottom surface and a side surface of a groove extending from an upper surface of the source region and penetrating the source region and the base region to the drift region and having a groove width of 3 to 20 μm; ,
A bottom electrode disposed on the wall insulating film at the bottom of the groove;
A bottom insulating film disposed on the bottom electrode inside the groove and having a thickness greater than that of a portion of the wall surface insulating film disposed on the bottom surface of the groove;
A semiconductor device comprising: a gate electrode disposed on the bottom insulating film inside the groove and facing the base region through the wall insulating film disposed on a side surface of the groove.   The semiconductor device according to claim 1, wherein the source region and the bottom electrode are electrically connected.   2. The gate electrode is disposed in a remaining region of a region facing the drift region of the wall insulating film disposed on a side surface of the trench and is opposed to the base region. Or the semiconductor device of 2.

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