JP2019024133A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device having an IGBT capable of curbing the rise of ON-state voltage while improving withstand voltage.SOLUTION: A semiconductor device 1 which includes: a plurality of gate trenches 8 formed in a semiconductor substrate 2; gate electrodes 20 each embedded in the gate trench 8 via a gate insulation film 22; an ntype emitter region 13, a p type base region 10, an ntype drift region 6 and a ptype collector region 4 which are formed adjacent to each other on the semiconductor substrate 2; emitter trenches 14 formed between every two pairs of gate trenches 8 lying adjacent to each other; and embedded electrodes 21 each embedded in the emitter trench 14 via an insulation film 19. The semiconductor device 1 further includes a p type floating region 15 including an overlapping part 17 having ends 18 each of which wraps around a bottom of the emitter trench 14 and is located closer to the gate trench 8 with respect to the center of the emitter trench 14 in a width direction.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device including an IGBT (Insulated Gate Bipolar Transistor).

Conventionally, a trench type IGBT having a collector-emitter saturation voltage V _CE (sat) and a high short-circuit tolerance has a p-type floating layer. The p-type floating layer is generally formed in the same process as the p-type base layer. Thereby, the p-type floating layer has the same depth as the p-type base layer.

Satoru Machida, Takahide Sugiyama, Masayasu Ishiko, Satoshi Yasuda, Jun Saito, Kimimori Hirota, “Analysis of IGBT Switching Loss and Device Capacitance”, IEEJ Electronic Materials Study Group (EFM-09, 16-26, 28-) 29), p. 55-59 Watanabe, Hiroshi Mori, Atsuka Arai, Keisuke Ishibashi, Satoshi Toyoda, Tetsuo Oda, Taku Harada, Katsuaki Saito, “Low loss, low noise, high reliability 1.7kV trench IGBT with floating p-layer separated from gate” , Electrotechnical Society Electronic Device Research Material (EDD-11, 66-83), p. 67-71 Japanese Patent No. 4785334

However, in the conventional structure, when the p-type floating layer is deeply diffused to maintain the breakdown voltage of the device, the breakdown voltage is maintained, but the p-type base layer becomes thick accordingly and the on-voltage increases. is there. On the other hand, if the p-type base layer is thinned to reduce the on-voltage, it is difficult to maintain a sufficient breakdown voltage.
Therefore, an object of the present invention is to provide a semiconductor device including an IGBT that can suppress an increase in on-voltage while improving a withstand voltage.

In order to achieve the above object, a semiconductor device of the present invention includes a semiconductor layer and a plurality of semiconductor layers formed in the semiconductor layer so as to extend in a first direction and aligned in a second direction perpendicular to the first direction. A repeating structure of a trench, a plurality of gate electrodes embedded in the plurality of trenches via an insulating film and adjacent to each other in the second direction, and a plurality of emitter electrodes adjacent to each other along the second direction, and the gate An n ⁺ -type emitter region, a p-type base region, and an n ⁻ that are arranged in this order from the surface side of the semiconductor layer in the depth direction of the trench in a region between the adjacent gate electrodes on the side of the electrode. A drift region and a region between the emitter electrodes adjacent to each other, deeper than the p-type base region, and wraps under the emitter electrode A p-type floating region including an overlapping portion, and a p ⁺ -type collector region disposed on the back side of the semiconductor layer with respect to the n ⁻ -type drift region, the p-type base region and the n ⁻ -type The interface with the drift region is set at the center or top of the trench.

FIG. 1 is a schematic cross-sectional view of a semiconductor device according to the first embodiment of the present invention. FIG. 2 is a perspective view for explaining the internal structure of the semiconductor device of FIG. FIG. 3A is a diagram for explaining a manufacturing process of the semiconductor device of FIG. 1. FIG. 3B is a diagram showing a step subsequent to FIG. 3A. FIG. 3C is a diagram showing a step subsequent to FIG. 3B. FIG. 3D is a diagram showing a step subsequent to FIG. 3C. FIG. 3E is a diagram showing a step subsequent to that in FIG. 3D. FIG. 3F is a diagram showing a step subsequent to that in FIG. 3E. FIG. 3G is a diagram showing a step subsequent to FIG. 3F. FIG. 3H is a diagram showing a step subsequent to FIG. 3F. FIG. 3I is a diagram showing a step subsequent to that in FIG. 3F. FIG. 4 is a schematic cross-sectional view of a semiconductor device according to the second embodiment of the present invention. FIGS. 5A and 5B are diagrams for explaining the internal structure of the semiconductor device of FIG. 4. FIG. 5A is a perspective view and FIG. 5B is a plan view. FIG. 6 is a schematic cross-sectional view of a semiconductor device according to the third embodiment of the present invention. FIG. 7 is an enlarged view of a portion surrounded by a broken line in FIG. FIG. 8A is a diagram for explaining a manufacturing process of the semiconductor device of FIG. FIG. 8B is a diagram showing a step subsequent to FIG. 8A. FIG. 8C is a diagram showing a step subsequent to FIG. 8B. FIG. 8D is a diagram showing a step subsequent to FIG. 8C. FIG. 8E is a diagram showing a step subsequent to that in FIG. 8D. FIG. 8F is a diagram showing a step subsequent to that in FIG. 8E. FIG. 8G is a diagram showing a step subsequent to FIG. 8F. FIG. 8H is a diagram showing a step subsequent to FIG. 8G. FIG. 8I is a diagram showing a step subsequent to that in FIG. 8H. FIG. 8J is a diagram showing a step subsequent to that in FIG. 8I. FIG. 8K is a diagram showing a step subsequent to that in FIG. 8J. FIG. 9 is a schematic cross-sectional view of a semiconductor device according to the fourth embodiment of the present invention. FIG. 10 is an enlarged view of a portion surrounded by a broken line in FIG. FIG. 11 is a graph showing the V _CE -I _Cf characteristics of the device.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a schematic cross-sectional view of a semiconductor device 1 according to the first embodiment of the present invention. FIG. 2 is a perspective view for explaining the internal structure of the semiconductor device of FIG.
The semiconductor device 1 is a device including an IGBT, and includes a semiconductor substrate 2 as an example of a semiconductor layer of the present invention. The semiconductor substrate 2 may be, for example, an n ⁻ type silicon substrate having a thickness of 50 μm to 200 μm.

The semiconductor substrate 2 has a structure in which a p ⁺ -type collector region 4, an n-type buffer region 5 and an n ⁻ -type drift region 6 are stacked in order from the back surface 3 side. The p ⁺ type collector region 4 is exposed on the entire back surface 3 of the semiconductor substrate 2, and the n ⁻ type drift region 6 is selectively exposed on a part of the front surface 7 of the semiconductor substrate 2.
As the p-type dopant of the p ⁺ -type collector region 4, for example, B (boron), Al (aluminum), or the like can be used (hereinafter the same). On the other hand, as the n-type dopant of the n-type buffer region 5 and the n ⁻ -type drift region 6, for example, N (nitrogen), P (phosphorus), As (arsenic), or the like can be used (hereinafter the same).

Moreover, the dopant concentration of the p ⁺ -type collector region 4 is, for example, 1 × 10 ¹⁵ cm ⁻³ to 2 × 10 ¹⁹ cm ⁻³ . On the other hand, the dopant concentration of the n-type buffer region 5 is, for example, 1 × 10 ¹⁵ cm ^{−3 to} 5 × 10 ¹⁷ cm ⁻³ , and the dopant concentration of the n ⁻ -type drift region 6 is 1 × 10 ¹³ cm ^−3. It is -5 * 10 < ¹⁴ > cm < ^-3 >.
A plurality of gate trenches 8 are formed on the surface 7 side of the semiconductor substrate 2. In this embodiment, the plurality of gate trenches 8 are formed, for example, in a stripe shape, and are arranged as a pair of trench units 9 in the lateral direction along the surface 7 of the semiconductor substrate 2. Pitch _{P 1} of the trench unit 9 adjacent to each other, for example, a 4Myuemu～20myuemu. Further, in the pair of gate trenches 8, the pitch P ₂ (the distance between the center points of the gate trenches 8) between one gate trench 8 and the other gate trench 8 is, for example, 2 μm to 7 μm, and the interval L ₁ ( The distance between the side surfaces of the gate trench 8 is, for example, 1 μm to 6 μm.

A p-type base region 10 is formed between the pair of gate trenches 8. The p-type base region 10 is shared by one gate trench 8 and the other gate trench 8. In this embodiment, the interface between the p-type base region 10 and the n ⁻ -type drift region 6 is set at the center or upper portion of the gate trench 8, and the p-type base region 10 is relatively It is shallowly diffused.

A contact trench 11 dug from the surface 7 of the semiconductor substrate 2 is formed in the p-type base region 10. The contact trench 11 is formed with a certain width along the longitudinal direction of the gate trench 8. A p ⁺ -type base contact region 12 is formed on the bottom surface of the contact trench 11.
An n ⁺ -type emitter region 13 is formed on the surface portion of the p-type base region 10 between the contact trench 11 and one and the other gate trenches 8. One n ⁺ -type emitter region 13 is provided on each side of the contact trench 11, and each n ⁺ -type emitter region 13 is exposed on the side surface of the contact trench 11.

Moreover, the dopant concentration of the p-type base region 10 is, for example, 1 × 10 ¹⁶ cm ⁻³ to 1 × 10 ¹⁸ cm ⁻³ . The dopant concentration of the p ⁺ type base contact region 12 is, for example, 5 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²⁰ cm ⁻³ . The dopant concentration of the n ⁺ -type emitter region 13 is 1 × 10 ¹⁹ cm ^{−3 to} 5 × 10 ²⁰ cm ⁻³ .
A plurality (two in FIG. 1) of emitter trenches 14 are formed between the pair of gate trenches 8 on the surface 7 side of the semiconductor substrate 2. In this embodiment, the plurality of emitter trenches 14 are formed, for example, in a stripe shape (parallel to the gate trench 8), and are arranged at equal intervals in the lateral direction along the surface 7 of the semiconductor substrate 2. The distance L ₂ between adjacent emitter trenches 14 (distance between the side surfaces of the emitter trench 14) is, for example, 3 μm or less, preferably 0.8 μm to 3 μm. The plurality of emitter trenches 14 are formed at the same depth as the gate trench 8. Thereby, since the emitter trench 14 can be formed in the same process as the gate trench 8, the manufacturing process can be simplified.

Among the plurality of emitter trenches 14, a trench adjacent to the gate trench 8 (a trench facing the gate trench 8 without a trench) is interposed between the gate trench 8 and the n ⁻ type drift region 6. The distance L ₃ (distance between the side surface of the emitter trench 14 and the side surface of the gate trench 8) is 2 μm or less. That is, the n ⁻ type drift region 6 is interposed between the emitter trench 14 and the gate trench 8 over the entire depth direction.

  A p-type floating region 15 is formed between each of the plurality of emitter trenches 14. The p-type floating region 15 is a semiconductor region in which an electrically floating state is maintained, and is separated from the gate trench 8 by an emitter trench 14 adjacent to the gate trench 8. In this embodiment, the p-type floating region 15 is formed deeper than the p-type base region 10.

  The p-type floating region 15 has a bottom portion 16 that bulges toward the back surface 3 side of the semiconductor substrate 2 with respect to the bottom portion of the emitter trench 14, and an overlap portion 17 that wraps below the emitter trench 14 adjacent to the gate trench 8. doing. The overlap portion 17 has an end portion 18 located on the side closer to the gate trench 8 with respect to the center in the width direction of the emitter trench 14. It is preferable that the end portion 18 does not protrude from the emitter trench 14 to the gate trench 8 side.

Moreover, the dopant concentration of the p-type floating region 15 is, for example, 5 × 10 ¹⁵ cm ⁻³ to 1 × 10 ¹⁸ cm ⁻³ .
A gate electrode 20 and a buried electrode 21 are buried in the gate trench 8 and the emitter trench 14 via an insulating film 19 (for example, silicon oxide (SiO ₂ )). The gate electrode 20 and the buried electrode 21 are made of a conductive material such as polysilicon, for example. The insulating film 19 is integrally formed along the inner surface of the gate trench 8, the surface 7 of the semiconductor substrate 2, and the inner surface of the emitter trench 14. A portion of the insulating film 19 in the gate trench 8 functions as the gate insulating film 22. The plurality of buried electrodes 21 in the emitter trench 14 are electrically connected to an emitter electrode 25 described later.

An interlayer film 23 made of an insulating material such as boron phosphorus silicate glass (BPSG) or silicon oxide (SiO ₂ ) is laminated on the surface 7 of the semiconductor substrate 2. A contact hole 24 for selectively exposing the n ⁺ -type emitter region 13 and the p ⁺ -type base contact region 12 through the contact trench 11 is formed in the interlayer film 23.
An emitter electrode 25 is stacked on the interlayer film 23. The emitter electrode 25 enters the contact trench 11 and is connected to the n ⁺ -type emitter region 13 on the side surface of the contact trench 11. In addition, the bottom surface of the contact trench 11 is connected to the p-type base region 10 via the p ⁺ -type base contact region 12.

Next, a method for manufacturing the semiconductor device 1 will be described. 3A to 3I are views for explaining the manufacturing process of the semiconductor device 1 of FIG. 1 in the order of steps.
To manufacture the semiconductor device 1, as shown in FIG. 3A, a mask 28 is formed on the surface 7 of the n ⁻ type semiconductor substrate 2 (n ⁻ type drift region 6). The mask 28 has an opening for selectively exposing a region to be formed in the p-type floating region 15 on the surface 7. Then, a p-type dopant is ion-implanted (implanted) into the surface 7 of the semiconductor substrate 2 through the mask 28. Thereby, the ion implantation region 26 is formed.

Next, as shown in FIG. 3B, the semiconductor substrate 2 is selectively etched, so that the gate trench 8 and the emitter trench 14 are formed simultaneously.
Next, as shown in FIG. 3C, a sacrificial oxide film 27 is formed on the entire surface including the inner surfaces of the gate trench 8 and the emitter trench 14 by thermally oxidizing the semiconductor substrate 2. Then, by annealing the semiconductor substrate 2 covered with the sacrificial oxide film 27, the p-type dopant in the ion implantation region 26 is diffused (drive-in). This annealing process is performed under the condition that the p-type dopant goes around below the emitter trench 14. Thereby, the p-type floating region 15 is formed. At this time, since the semiconductor substrate 2 is covered with the sacrificial oxide film 27, it is possible to prevent the escape of ions from the surface of the substrate, so that the p-type dopant can be diffused efficiently.

Next, as shown in FIG. 3D, the sacrificial oxide film 27 is peeled off.
Next, as shown in FIG. 3E, the semiconductor substrate 2 is thermally oxidized to form an insulating film 19 (gate insulating film 22) over the entire surface including the inner surfaces of the gate trench 8 and the emitter trench.
Next, as shown in FIG. 3F, an electrode material such as polysilicon is embedded in the gate trench 8 and the emitter trench 14. Thereby, the gate electrode 20 and the buried electrode 21 are formed simultaneously.

Next, as shown in FIG. 3G, n-type and p-type dopants are selectively ion-implanted and diffused into the surface 7 of the semiconductor substrate 2, thereby causing the p-type base region 10 and the n ⁺ -type emitter region 13. Are formed in order.
Next, as shown in FIG. 3H, an interlayer film 23 is formed on the surface 7 of the semiconductor substrate 2 by depositing an insulating material such as boron phosphorus silicate glass (BPSG) or silicon oxide (SiO ₂ ). . Next, after the interlayer film 23 is selectively etched to form the contact hole 24, the semiconductor substrate 2 exposed from the contact hole 24 is selectively etched. Thereby, the contact trench 11 is formed.

Next, as shown in FIG. 3I, p ⁺ -type base contact region 12 is formed by ion implantation and diffusion of p-type dopant selectively into the bottom of contact trench 11 through contact hole 24. The
Thereafter, after the emitter electrode 24 and the like are formed on the front surface 7 side of the semiconductor substrate 2, n-type and p-type dopants are selectively ion-implanted and diffused into the back surface 3 of the semiconductor substrate 2. A buffer region 5 and a p ⁺ -type collector region 4 are formed in order.

Through the steps as described above, the semiconductor device 1 shown in FIG. 1 is obtained. 3A to 3I represent only a part of the manufacturing process of the semiconductor device 1, and the manufacturing process may include a process that is not shown in FIGS. 3A to 3I.
According to this semiconductor device 1, the p-type floating region 15 (overlap portion 17) is formed up to the bottom of the emitter trench 14 (hereinafter referred to as “emitter junction trench”) in which the buried electrode 21 is buried. The collector-emitter voltage loaded on the emitter junction trench during the off operation can be relaxed. Therefore, it is possible to prevent the device from being destroyed with respect to a steep voltage change (dv / dt).

Further, the breakdown voltage can be improved by the p-type floating region 15 deeper than the p-type base region 10, while the p-type base region 10 may be shallow, so that the channel can be obtained by appropriately designing the depth of the p-type base region 10. It is also possible to suppress an increase in on-voltage by shortening the length (the length of the gate trench 8 in the depth direction).
A gate trench 8 in which the gate electrode 20 is embedded (hereinafter referred to as “gate junction trench”) is separated from the p-type floating region 15 by an emitter junction trench. Thereby, the junction between the p-type floating region 15 and the gate junction trench can be prevented. Therefore, stray capacitance between the gate junction trench and the p-type floating region 15 can be eliminated.

On the other hand, the n ⁻ type drift region 6 where the gate junction trench is joined over the entire depth direction is grounded together with the p ⁺ type collector region 4. For this reason, the capacitance change between the gate junction trench and the n ⁻ -type drift region 6 is stabilized during the switching operation, so that noise is hardly generated. As a result, it is possible to reduce noise generation and switching loss during the switching operation.

In addition, since the distance L between the emitter junction trench and the gate junction trench is 2 μm or less, the breakdown voltage can be maintained well.
Further, since the side surface of the contact trench 11 can be effectively utilized as an area for contact with the n ⁺ -type emitter region 13, the junction area of the emitter electrode 25 for the n ⁺ -type emitter region 13 can be sufficiently ensured . As a result, the planar area of the n ⁺ -type emitter region 13 can be sacrificed, so that the distance L ₁ between the one and the other gate trenches 8 in the pair of gate trenches 8 is made finer, and the p is smaller than in the conventional case. The mold base region 10 can be formed. As a result of miniaturization of the gate trench 8, the trade-off relationship between the short-circuit withstand voltage and the on-voltage of the device can be improved, so that the charge promotion effect can be improved. Therefore, V _CE (sat) in the low current region can be improved.

FIG. 4 is a schematic cross-sectional view of a semiconductor device 31 according to the second embodiment of the present invention. FIGS. 5A and 5B are diagrams for explaining the internal structure of the semiconductor device of FIG. 4. FIG. 5A is a perspective view and FIG. 5B is a plan view. 4 and 5, parts corresponding to those shown in FIG. 1 are given the same reference numerals.
In the first embodiment described above, the gate trench 8 is formed as a pair of trench units 9, and a common p-type base region 10 is formed between one and the other gate trench 8. On the other hand, the semiconductor device 31 of the second embodiment includes a plurality of gate trenches 33 formed as one trench unit 32 in the lateral direction along the surface 7 of the semiconductor substrate 2 and both sides of each gate trench 33 ( A p-type base region 34 formed in a region between the emitter trenches 14) and an n ⁺ -type emitter region 35 formed in a surface portion of each p-type base region 34. The n ⁺ -type emitter regions 35 are formed one by one along both side surfaces of the gate trench 33 and are exposed on the surface 7 of the semiconductor substrate 2.

A p ⁺ -type base contact region 37 is formed on the surface of the p-type base region 34 on the side of the n ⁺ -type emitter region 35 (opposite the gate trench 33). The dopant concentration of the p ⁺ type base contact region 37 is, for example, 5 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²⁰ cm ⁻³ .
As shown in FIGS. 5A and 5B, the n ⁺ -type emitter region 35 selectively has a lead-out portion 38 that is led out in the lateral direction along the surface 7 of the semiconductor substrate 2 from the side surface of the gate trench 33. ing. The lead portions 38 are arranged, for example, at regular intervals along the longitudinal direction of the gate trench 33. When a pair of n ⁺ -type emitter regions 35 are provided for the gate trench 33 as in this embodiment, the lead-out portion 38 of each n ⁺ -type emitter region 35 has one side, as shown in FIG. The other end may be arranged to face each other across the gate trench 33, and the end of one lead-out portion 38 and the end of the other lead-out portion 38 are arranged in the longitudinal direction of the gate trench 33. You may arrange | position alternately along (not shown). As a result, the portion adjacent to the lead portion 38 in the p ⁺ -type base contact region 37 is a narrow portion 39 that is selectively narrower than the other portions.

Further, a contact hole 36 for selectively exposing the p ⁺ type base contact region 37 and the n ⁺ type emitter region 35 is formed in the interlayer film 23. In the n ⁺ -type emitter region 35, the lead portion 38 is selectively exposed from the contact hole 36. The emitter electrode 25 is connected to the p ⁺ type base contact region 37 and the n ⁺ type emitter region 35 through a contact hole 36.

This semiconductor device 31 can also achieve the same effect as the semiconductor device 1 of the first embodiment.
FIG. 6 is a schematic cross-sectional view of a semiconductor device according to the third embodiment of the present invention. FIG. 7 is an enlarged view of a portion surrounded by a broken line in FIG.
The semiconductor device 101 is a device including an IGBT and includes a semiconductor substrate 102 as an example of a semiconductor layer of the present invention. The semiconductor substrate 102 may be, for example, an n ⁻ type silicon substrate having a thickness of 50 μm to 200 μm.

The semiconductor substrate 102 has a structure in which a p ⁺ -type collector region 104, an n-type buffer region 105, and an n ⁻ -type drift region 106 are stacked in this order from the back surface 103 side. The p ⁺ type collector region 104 is exposed on the entire back surface 103 of the semiconductor substrate 102, and the n ⁻ type drift region 106 is selectively exposed on a part of the front surface 107 of the semiconductor substrate 102.
As the p-type dopant in the p ⁺ -type collector region 104, for example, B (boron), Al (aluminum), or the like can be used (hereinafter the same). On the other hand, for example, N (nitrogen), P (phosphorus), As (arsenic), or the like can be used as the n-type dopant of the n-type buffer region 105 and the n ⁻ -type drift region 106 (hereinafter the same).

The dopant concentration of the p ⁺ -type collector region 104 is, for example, 1 × 10 ¹⁵ cm ⁻³ to 2 × 10 ¹⁹ cm ⁻³ . On the other hand, the dopant concentration of the n-type buffer region 105 is, for example, ^{1 × 10 15 cm -3 ~5 ×} 10 17 cm -3, n - dopant concentration type drift region 106, 1 × ¹⁰ 13 ^{cm -3} It is -5 * 10 < ¹⁴ > cm < ^-3 >.
A plurality of gate trenches 108 and a plurality of dummy trenches 109 are formed adjacent to each other on the surface 107 side of the semiconductor substrate 102. In this embodiment, a plurality of trench units 110 including a pair of dummy trenches 109 and a gate trench 108 sandwiched between the pair of dummy trenches 109 are spaced apart in the lateral direction along the surface 107 of the semiconductor substrate 102. Is arranged. Thereby, the gate trench 108 and the dummy trench 109 are formed in a stripe shape as a whole.

Pitch _{P 1} of the trench units 110 adjacent to each other, for example, a 2Myuemu～7myuemu. In each trench unit 110, the distance L ₁ between the gate trench 108 and the dummy trenches 109 on both sides thereof (the distance between the side surface of the gate trench 108 and the side surface of the dummy trench 109) is preferably 2 μm or less.
In each trench unit 110, a p-type base region 111 is formed on both sides of the gate trench 108 (regions between the dummy trenches 109), and an n ⁺ -type emitter region 112 is formed on the surface of the p-type base region 111. In addition, a p ⁺ -type base contact region 113 is formed (see FIG. 7). In this embodiment, the interface between the p-type base region 111 and the n ⁻ -type drift region 106 is set at the center or upper portion of the gate trench 108, and the p-type base region 111 is relatively shallow in the semiconductor substrate 102. Diffusion is formed.

The n ⁺ -type emitter region 112 and the p ⁺ -type base contact region 113 are arranged adjacent to each other in a region between the gate trench 108 and the dummy trench 109. Specifically, n ⁺ -type emitter regions 112 are formed one by one along both side surfaces 114 of the gate trench 108, and p ⁺ -type base contact regions 113 are formed one by one along the side surface 115 of each dummy trench 109. Has been. As a result, the n ⁺ -type emitter region 112 is exposed on the surface 107 of the semiconductor substrate 102 and the side surface 114 of the gate trench 108. On the other hand, the p ⁺ -type base contact region 113 is exposed on the surface 107 of the semiconductor substrate 102 and the side surface 115 of the dummy trench 109.

Moreover, the dopant concentration of the p-type base region 111 is, for example, 1 × 10 ¹⁶ cm ⁻³ to 1 × 10 ¹⁸ cm ⁻³ . The dopant concentration of the n ⁺ -type emitter region 112 is 1 × 10 ¹⁹ cm ^{−3 to} 5 × 10 ²⁰ cm ⁻³ . The dopant concentration of the p ⁺ type base contact region 113 is, for example, 5 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²⁰ cm ⁻³ .
A plurality (three in FIG. 6) of emitter trenches 116 are formed between adjacent trench units 110 on the surface 107 side of the semiconductor substrate 102. In this embodiment, the plurality of emitter trenches 116 are formed, for example, in a stripe shape (parallel to the gate trench 108 and the dummy trench 109), and are arranged at equal intervals in the lateral direction along the surface 107 of the semiconductor substrate 102. Yes. An interval L ₂ (distance between the side surfaces of the emitter trench 116) between the emitter trenches 116 adjacent to each other is, for example, 3 μm or less, preferably 0.8 μm to 3 μm. The plurality of emitter trenches 116 are formed at the same depth as the gate trench 108 and the dummy trench 109. Thereby, the emitter trench 116 can be formed in the same process as the gate trench 108 and the dummy trench 109, so that the manufacturing process can be simplified.

Among the plurality of emitter trenches 116, a trench adjacent to the dummy trench 109 (a trench facing the dummy trench 109 without a trench) is spaced from the dummy trench 109 by an interval L ₃ of 0.5 μm to 20 μm. (Distance between the side surface of the emitter trench 116 and the side surface of the dummy trench 109).
A p-type floating region 117 is formed in the semiconductor substrate 102. The p-type floating region 117 extends to a region sandwiched between the dummy trenches 109 of the adjacent trench units 110 facing each other with the emitter trench 116 therebetween. The p-type floating region 117 is a semiconductor region that is kept in an electrically floating state, and is separated from the gate trench 108 by a dummy trench 109 adjacent to the gate trench 108. In this embodiment, the p-type floating region 117 is formed deeper than the p-type base region 111.

  The p-type floating region 117 has a bottom portion 118 that bulges toward the back surface 103 of the semiconductor substrate 102 with respect to the bottom portion of the emitter trench 116, and an overlap portion 119 that goes around the dummy trench 109. The overlap portion 119 has an end portion 120 located on the side closer to the gate trench 108 with respect to the center in the width direction of the dummy trench 109. It is preferable that the end portion 120 does not protrude from the emitter trench 116 to the gate trench 108 side.

Moreover, the dopant concentration of the p-type floating region 117 is, for example, 5 × 10 ¹⁵ cm ⁻³ to 1 × 10 ¹⁸ cm ⁻³ .
In the gate trench 108, the dummy trench 109, and the emitter trench 116, the gate electrode 122, the first embedded electrode 123, and the second embedded electrode 124 are embedded through an insulating film 121 (for example, silicon oxide (SiO ₂ )). Yes. The gate electrode 122, the first embedded electrode 123, and the second embedded electrode 124 are made of a conductive material such as polysilicon, for example. The insulating film 121 is integrally formed along the inner surface of the gate trench 108, the inner surface of the dummy trench 109, the surface 107 of the semiconductor substrate 102, and the inner surfaces of the emitter trench 116. A portion of the insulating film 121 in the gate trench 108 functions as the gate insulating film 125. The first embedded electrode 123 and the second embedded electrode 124 are electrically connected to an emitter electrode 132 described later.

  In this embodiment, the gate electrode 122 and the second buried electrode 124 backfill the trenches 108 and 116 to the opening end, whereas the first buried electrode 123 is in the depth direction of the dummy trench 109. It is backfilled halfway. Thus, a space without an electrode is formed in the upper region of the first buried electrode 123 in the dummy trench 109. Then, a buried insulating film 126 is buried in the dummy trench 109 so as to fill this space back to the opening end.

The buried insulating film 126 is made of an insulating material such as boron phosphorus silicate glass (BPSG) or silicon oxide (SiO ₂ ), and has a thickness of 0.5 μm or more. In the buried insulating film 126 and the insulating film 121 therebelow, a removal portion 127 that exposes the p ⁺ type base contact region 113 on the side surface 115 of the dummy trench 109 is selectively formed. That is, the buried insulating film 126 selectively has an upper surface 128 at a position lower than the surface 107 of the semiconductor substrate 102 so as to be continuous with the side surface 115 of the dummy trench 109, and between the upper surface 128 and the surface 107. The p ⁺ type base contact region 113 is exposed in the region of the side surface 115 of the dummy trench 109.

An interlayer film 129 made of an insulating material such as boron phosphorus silicate glass (BPSG) or silicon oxide (SiO ₂ ) is laminated on the surface 107 of the semiconductor substrate 102. The interlayer film 129 is formed integrally with the buried insulating film 126. A contact hole 130 is formed in the interlayer film 129 so as to straddle the surface 107 of the semiconductor substrate 102 and the opening end of the dummy trench 109. The contact hole 130 exposes the ^{n +} -type emitter region 112 and ^{p +} -type base contact region 113 at the surface 107 of the semiconductor substrate 102, the side surface 115 of the dummy trench 109 (removed portion 127) in ^{the p +} -type base contact region 113 To expose. That is, the p ⁺ type base contact region 113 is exposed at the corner 131 of the dummy trench 109 formed by the intersection of the surface 107 and the side surface 115. Note that the n ⁺ -type emitter region 112 selectively has a lead-out portion that is led out from the side surface 114 of the gate trench 108 in the lateral direction along the surface 107 of the semiconductor substrate 102, and only this lead-out portion is the contact hole 130. May be selectively exposed.

On the interlayer film 129, an emitter electrode 132 as an example of the contact electrode of the present invention is laminated. The emitter electrode 132 enters the contact hole 130, is connected to the n ⁺ -type emitter region 112 on the surface 107 of the semiconductor substrate 102, and is connected to the p ⁺ -type base contact region 113 at the corner 131 of the dummy trench 109.
Next, a method for manufacturing the semiconductor device 101 will be described. 8A to 8K are views for explaining the manufacturing process of the semiconductor device 101 of FIGS. 6 and 7 in the order of steps. 8A to 8F show cross sections corresponding to FIG. 6, and FIGS. 8G to 8K show cross sections corresponding to FIG.

In order to manufacture the semiconductor device 101, as shown in FIG. 8A, a mask 160 is formed on the surface 107 of the n ⁻ type semiconductor substrate 102 (n ⁻ type drift region 106). The mask 160 has an opening for selectively exposing a region to be formed in the p-type floating region 117 on the surface 107. Then, a p-type dopant is ion-implanted (implanted) into the surface 107 of the semiconductor substrate 102 through the mask 160. Thereby, an ion implantation region 161 is formed.

Next, as shown in FIG. 8B, the semiconductor substrate 102 is selectively etched, so that the gate trench 108, the dummy trench 109, and the emitter trench 116 are simultaneously formed.
Next, as shown in FIG. 8C, a sacrificial oxide film 162 is formed over the entire surface including the inner surfaces of the gate trench 108, the dummy trench 109, and the emitter trench 116 by thermally oxidizing the semiconductor substrate 102. Then, by annealing the semiconductor substrate 102 covered with the sacrificial oxide film 162, the p-type dopant in the ion implantation region 161 is diffused (drive-in). This annealing process is performed under the condition that the p-type dopant wraps around the dummy trench 109. Thereby, the p-type floating region 117 is formed. At this time, since the semiconductor substrate 102 is covered with the sacrificial oxide film 162, it is possible to prevent ions from escaping from the substrate surface, so that the p-type dopant can be efficiently diffused.

Next, as shown in FIG. 8D, the sacrificial oxide film 162 is peeled off.
Next, as shown in FIG. 8E, the semiconductor substrate 102 is thermally oxidized to form an insulating film 121 (gate insulating film 125) over the entire surface including the inner surfaces of the gate trench 108, the dummy trench 109, and the emitter trench 116. Is done.
Next, as shown in FIG. 8F, an electrode material such as polysilicon is embedded in the gate trench 108, the dummy trench 109, and the emitter trench 116. As a result, the gate electrode 122, the first embedded electrode 123, and the second embedded electrode 124 are formed simultaneously.

Next, as shown in FIG. 8G, n-type and p-type dopants are selectively ion-implanted and diffused into the surface 107 of the semiconductor substrate 102, so that the p-type base region 111 and the n ⁺ -type emitter region 112. Are formed in order.
Next, as shown in FIG. 8H, by etching the first embedded electrode 123 from the upper surface, only the first embedded electrode 123 is selectively retained while maintaining the embedded state of the gate electrode 122 and the second embedded electrode 124. Digging down.

Next, as shown in FIG. 8I, an insulating material such as boron phosphorus silicate glass (BPSG) or silicon oxide (SiO ₂ ) is deposited on the surface 107 of the semiconductor substrate 102, so that The space is backfilled with the insulating material, and the surface 107 is covered with the insulating material. Thereby, the buried insulating film 126 and the interlayer film 129 are formed simultaneously.

Next, as shown in FIG. 8J, the contact hole 130 and the removal portion 127 are simultaneously formed by selectively etching the interlayer film 129 and the buried insulating film 126.
Next, as shown in FIG. 8K, the p-type dopant is selectively ion-implanted and diffused into the surface 107 of the semiconductor substrate 102 exposed in the contact hole 130. Thereby, the p ⁺ type base contact region 113 is formed.

Thereafter, after the emitter electrode 132 and the like are formed on the front surface 107 side of the semiconductor substrate 102, n-type and p-type dopants are selectively implanted and diffused into the back surface 103 of the semiconductor substrate 102, whereby the n-type A buffer region 105 and a p ⁺ -type collector region 104 are formed in order.
Through the steps described above, the semiconductor device 101 shown in FIGS. 6 and 7 is obtained. 8A to 8K only show a part of the manufacturing process of the semiconductor device 101, and the manufacturing process may include a process that is not shown in FIGS. 8A to 8K.

According to this semiconductor device 101, the side surface 115 of the dummy trench 109 can be effectively used as the p ⁺ -type base contact region 113, so that the junction area of the emitter electrode 132 with respect to the p-type base region 111 is set to the surface of the semiconductor substrate 102. Sufficiently securing both the upper surface 107 and the side surface 115 of the dummy trench 109 is possible. Thus, it is possible to sacrifice planar area of the p-type base region 111, the distance L ₁ between the gate trench 108 and the dummy trench 109 is miniaturized, form fine p-type base region 111 as compared with the conventional can do. In addition, since the dummy trench 109 can be formed using the same mask as the gate trench 108, there is no positional shift with respect to the gate trench 108. The alignment of the emitter electrode 132 can be easily performed because it is sufficient to match the area including the planar area of the dummy trench 109.

Specifically, first, the semiconductor substrate 102 is etched using the same mask to simultaneously form the gate trench 108, the dummy trench 109, and the emitter trench 116 (FIG. 8B). Next, polysilicon is embedded in these trenches 108, 109, and 116 to form the gate electrode 122, the first embedded electrode 123, and the second embedded electrode 124 (FIG. 8F). Next, a mask for selectively exposing the dummy trench 109 is formed on the semiconductor substrate 102, and the upper portion of the polysilicon in the dummy trench 109 is selectively removed by etching through this mask. As a result, a space is formed in a region above the first buried electrode 123 of the dummy trench 109 (FIG. 8H). Next, an interlayer film 129 is formed by depositing an insulating material such as BPSG on the semiconductor substrate 102 by, eg, CVD (FIG. 8I). Part of the insulating material enters the dummy trench 109 as a buried insulating film 126. Next, a mask for forming the contact hole 130 is aligned with the semiconductor substrate 102. At this time, since the end portion of the contact hole 130 may cover the dummy trench 109, alignment can be performed in a wide area including the surface 107 of the semiconductor substrate 102 and the planar area of the dummy trench 109. Then, the interlayer film 129 and the buried insulating film 126 are continuously etched through the mask. Thereby, the contact hole 130 and the removal part 127 are formed simultaneously (FIG. 8J). After that, if the p ⁺ type base contact region 113 is formed in a self-aligned manner by ion implantation of p type dopant using the interlayer film 129 as a mask, the p ⁺ type base contact region 113 is surely formed at the corner 131 of the dummy trench 109. (FIG. 8K). In addition, since the contact hole 130 can be formed relatively wide, a part of the emitter electrode 132 using aluminum (Al) or the like can be used as a plug without using a plug with good filling properties such as tungsten (W). Can do.

As a result of the miniaturization of the trench structure as described above, the trade-off relationship between the short-circuit withstand voltage and the on-voltage of the device can be improved, so that the charge promotion effect can be improved. Therefore, V _CE (sat) in the low current region can be improved.
Further, according to the semiconductor device 101, the gate trench 108 in which the gate electrode 122 is embedded (hereinafter referred to as “gate junction trench”) is embedded in the first embedded electrode 123 connected to the n ⁺ -type emitter region 112. The p-type floating region 117 is separated by a dummy trench 109 (hereinafter referred to as “emitter junction trench”). Thereby, the junction between the p-type floating region 117 and the gate junction trench can be prevented. Therefore, stray capacitance between the gate junction trench and the p-type floating region 117 can be eliminated.

On the other hand, the n ⁻ type drift region 106 where the gate junction trench is joined in the depth direction is grounded together with the p ⁺ type collector region 104. For this reason, the capacitance change between the gate junction trench and the n ⁻ -type drift region 106 is stabilized during the switching operation, so that noise is hardly generated. As a result, it is possible to reduce noise generation and switching loss during the switching operation.

Further, the emitter junction trench, the spacing L ₁ between the gate junction trench is 2μm or less, may be satisfactorily hold the breakdown voltage.
Furthermore, according to this semiconductor device 101, since the p-type floating region 117 (overlap portion 119) is formed up to the bottom of the emitter junction trench, the collector-emitter voltage applied to the emitter junction trench during the switching-off operation is reduced. can do. Therefore, it is possible to prevent the device from being destroyed with respect to a steep voltage change (dv / dt).

Further, the breakdown voltage can be improved by the p-type floating region 117 deeper than the p-type base region 111, while the p-type base region 111 may be shallow, so that the channel can be obtained by appropriately designing the depth of the p-type base region 111. An increase in on-voltage can be suppressed by shortening the length (the length of the gate trench 108 in the depth direction).
FIG. 9 is a schematic cross-sectional view of a semiconductor device 141 according to the fourth embodiment of the present invention. FIG. 10 is an enlarged view of a portion surrounded by a broken line in FIG. 9 and 10, the same reference numerals are given to portions corresponding to the respective portions shown in FIGS. 6 and 7 described above.

In the third embodiment described above, the trench unit 110 includes a pair of dummy trenches 109 and a gate trench 108 sandwiched between the pair of dummy trenches 109. On the other hand, the semiconductor device 141 according to the fourth embodiment has a trench unit 144 including a pair of gate trenches 142 and a dummy trench 143 sandwiched between the pair of gate trenches 142. In this case, the distance L ₃ between the gate trench 142 and the emitter trench 116 (distance between the side surface of the gate trench 142 and the side surface of the emitter trench 116) is preferably 2 μm or less.

In each trench unit 144, a p-type base region 145 is formed on both sides of the dummy trench 143 (regions between the gate trenches 142), and an n ⁺ -type emitter region 146 is formed on the surface of the p-type base region 145. And a p ⁺ -type base contact region 147 is formed (see FIG. 10). In this embodiment, the interface between the p-type base region 145 and the n ⁻ -type drift region 106 is set at the center or upper part of the gate trench 142, and the p-type base region 145 is relatively shallow in the semiconductor substrate 102. Diffusion is formed.

The n ⁺ -type emitter region 146 and the p ⁺ -type base contact region 147 are arranged adjacent to each other in a region between the gate trench 142 and the dummy trench 143.
Specifically, n ⁺ -type emitter regions 146 are formed one by one along the side surface 148 of each gate trench 142, and p ⁺ -type base contact regions 147 are formed one by one along the side surfaces 149 of the dummy trench 143. Has been. As a result, the n ⁺ -type emitter region 146 is exposed on the surface 107 of the semiconductor substrate 102 and the side surface 148 of the gate trench 142. On the other hand, the p ⁺ -type base contact region 147 is exposed on the surface 107 of the semiconductor substrate 102 and the side surface 149 of the dummy trench 143.

  A p-type floating region 150 is formed in the semiconductor substrate 102. The p-type floating region 150 extends between each of the plurality of emitter trenches 116. The p-type floating region 150 is a semiconductor region that is kept in an electrically floating state, and is separated from the gate trench 142 by an emitter trench 116 adjacent to the gate trench 142. In this embodiment, the p-type floating region 150 is formed deeper than the p-type base region 145.

  The p-type floating region 150 has a bottom portion 151 that bulges toward the back surface 103 of the semiconductor substrate 102 with respect to the bottom portion of the emitter trench 116, and an overlap portion 152 that wraps around the emitter trench 116 adjacent to the gate trench 142. doing. The overlap portion 152 has an end portion 153 located on the side closer to the gate trench 142 with respect to the center in the width direction of the emitter trench 116. It is preferable that the end portion 153 does not protrude from the emitter trench 116 to the gate trench 142 side.

Such a p-type floating region 150 can be formed, for example, in the same manner as the p-type floating region 117 described above.
A first embedded electrode 154 is embedded in the dummy trench 143 through the insulating film 121. The first embedded electrode 154 is made of, for example, a conductive material such as polysilicon, and is electrically connected to the gate electrode 122. Further, the first buried electrode 154 is buried back to the middle of the dummy trench 143 in the depth direction. Thereby, in the dummy trench 143, a space without an electrode is formed above the first embedded electrode 154. Then, a buried insulating film 155 is buried in the dummy trench 143 so as to fill the space up to the opening end.

The buried insulating film 155 is made of an insulating material such as boron phosphorus silicate glass (BPSG) or silicon oxide (SiO ₂ ), and has a thickness of 0.5 μm or more. In the buried insulating film 155 and the insulating film 121 therebelow, a removal portion 156 that exposes the p ⁺ -type base contact region 147 on both side surfaces 149 of the dummy trench 143 is selectively formed. That is, the buried insulating film 155 selectively has an upper surface 157 at a position lower than the surface 107 of the semiconductor substrate 102 so as to continue to both side surfaces 149 of the dummy trench 143. A p ⁺ -type base contact region 147 is exposed in the region of both side surfaces 149 of the dummy trench 143 therebetween.

A contact hole 158 is formed in the interlayer film 129 so as to straddle the p-type base region 145 facing each other with the dummy trench 143 interposed therebetween. The contact hole 158, the surface 107 of the semiconductor substrate 102 to expose the ^{n +} -type emitter region 146 and ^{p +} -type base contact region 147, ^{p +} -type base contact region on both sides 149 (removed portion 156) of the dummy trenches 143 147 is exposed. That is, the p ⁺ -type base contact region 147 is exposed at both corners 159 of the dummy trench 143 formed by the intersection of the surface 107 and the side surface 149. Note that the n ⁺ -type emitter region 146 selectively has a lead-out portion that is led out from the side surface 148 of the gate trench 142 in the lateral direction along the surface 107 of the semiconductor substrate 102, and only this lead-out portion is the contact hole 158. May be selectively exposed.

Emitter electrode 132 enters contact hole 158, is connected to n ⁺ -type emitter region 146 at surface 107 of semiconductor substrate 102, and is connected to p ⁺ -type base contact region 147 at both corners 159 of dummy trench 143. .
This semiconductor device 141 can also achieve the same effect as the semiconductor device 101 of the third embodiment.

As mentioned above, although embodiment of this invention was described, this invention can also be implemented with another form.
For example, the above-described features grasped from the disclosure of the above-described embodiments can be combined with each other even in different embodiments.
In the above-described embodiment, only the configuration of the IGBT included in the semiconductor devices 1, 31, 101, and 141 is illustrated. However, in the semiconductor device of the present invention, an element other than the IGBT (for example, MOSFET, diode, etc.) You may prepare in the area | region different from a formation area.

In addition, various design changes can be made within the scope of matters described in the claims.
In addition to the invention described in the claims, the following features can be extracted from the description of the specification and the drawings.
(Claim 1) A semiconductor layer, a gate trench formed in the semiconductor layer, a gate electrode embedded in the gate trench through a gate insulating film, and a side of the gate trench with a predetermined interval. And an n ⁺ -type emitter region, a p-type base region, and a n-type emitter region disposed in order from the surface side of the semiconductor layer in the depth direction of the gate trench in a region between the gate trench and the dummy trench an n ⁻ -type drift region, a p ⁺ -type collector region disposed on the back side of the semiconductor layer with respect to the n ⁻ -type drift region, and embedded in the dummy trench, with respect to the surface of the semiconductor layer A buried insulating film having an upper surface on the bottom side of the dummy trench, and is disposed in front of a portion from the surface to the upper surface on the side surface of the dummy trench. A buried insulating film that selectively exposes a part of the p-type base region as a contact region, and is buried in a region above the buried insulating film of the dummy trench and connected to the contact region on the side surface of the dummy trench. A semiconductor device including a contact electrode.

  According to this configuration, since the side surface of the dummy trench can be effectively used as a contact region, a sufficient contact area of the contact electrode with respect to the p-type base region can be ensured. As a result, the planar area of the p-type base region can be sacrificed, so that the distance between the gate trench and the dummy trench can be made finer, and a finer p-type base region can be formed compared to the conventional case. Moreover, since the dummy trench can be formed using the same mask as the gate trench, there is no positional shift with respect to the gate trench. The alignment of the contact electrode can be easily performed because it is sufficient to match the area including the planar area of the dummy trench.

Further, as a result of the miniaturization of the trench structure, the trade-off relationship between the short-circuit withstand voltage and the on-voltage of the device can be improved, so that the charge promoting effect can be improved. Therefore, V _CE (sat) in the low current region can be improved.
(Item 2) The semiconductor device according to Item 1, further including a first embedded electrode embedded in an area below the embedded insulating film of the dummy trench through an insulating film.

(Item 3) The semiconductor device according to Item 2, wherein the semiconductor device has a trench unit including a pair of the dummy trenches and a gate trench sandwiched between the pair of dummy trenches.
(Item 4) The semiconductor device according to Item 3, wherein the first buried electrode is electrically connected to the n ⁺ -type emitter region.
(Item 5) A plurality of the trench units are formed in a lateral direction along the surface of the semiconductor layer, and the semiconductor device includes a plurality of emitter trenches formed between the trench units adjacent to each other, A second buried electrode buried in an emitter trench through an insulating film and electrically connected to the n ⁺ -type emitter region; the dummy unit in the trench unit; and the dummy trench in the trench unit adjacent thereto; Item 5. The semiconductor device according to Item 4, further comprising a p-type floating region formed therebetween.

(Item 6) The semiconductor device according to Item 5, wherein the p-type floating region includes an overlap portion that is formed deeper than the p-type base region and extends below the dummy trench.
According to this configuration, the p-type floating region (overlap portion) is formed up to the bottom of the dummy trench (hereinafter referred to as “emitter junction trench”) in which the first buried electrode connected to the n ⁺ -type emitter region is buried. Therefore, the collector-emitter voltage applied to the emitter junction trench during the switching-off operation can be relaxed. Therefore, it is possible to prevent the device from being destroyed with respect to a steep voltage change (dv / dt).

In addition, the breakdown voltage can be improved by the p-type floating region deeper than the p-type base region, while the p-type base region may be shallow, so that the ON voltage can be increased by appropriately designing the depth of the p-type base region. It can also be suppressed.
(Item 7) The semiconductor device according to Item 6, wherein the overlap portion has an end located on a side closer to the gate trench with respect to the center in the width direction of the dummy trench.

With this configuration, the collector-emitter voltage applied to the emitter junction trench can be more favorably reduced.
(Item 8) The semiconductor device according to Item 2, wherein the semiconductor device has a trench unit including a pair of gate trenches and a dummy trench sandwiched between the pair of gate trenches.

(Item 9) The semiconductor device according to Item 8, wherein the first embedded electrode is electrically connected to the gate electrode.
(Item 10) A plurality of the trench units are formed in a lateral direction along the surface of the semiconductor layer, and the semiconductor device includes a plurality of emitter trenches formed between the adjacent trench units, A second buried electrode embedded in the emitter trench through an insulating film and electrically connected to the n ⁺ -type emitter region; and a p-type floating region formed between the plurality of emitter trenches; Item 10. The semiconductor device according to Item 9.

(Item 11) The semiconductor device according to Item 10, wherein the p-type floating region includes an overlap portion that is formed deeper than the p-type base region and extends below the emitter trench.
According to this configuration, the p-type floating region (overlap portion) is formed up to the bottom of the emitter trench (hereinafter referred to as “emitter junction trench”) in which the second buried electrode connected to the n ⁺ -type emitter region is buried. Therefore, the collector-emitter voltage applied to the emitter junction trench during the switching-off operation can be relaxed. Therefore, it is possible to prevent the device from being destroyed with respect to a steep voltage change (dv / dt).

In addition, the breakdown voltage can be improved by the p-type floating region deeper than the p-type base region, while the p-type base region may be shallow, so that the ON voltage can be increased by appropriately designing the depth of the p-type base region. It can also be suppressed.
(Item 12) The semiconductor device according to item 11, wherein the overlap portion has an end located on a side closer to the gate trench with respect to a center in a width direction of the emitter trench.

With this configuration, the collector-emitter voltage applied to the emitter junction trench can be more favorably reduced.
(Item 13) The semiconductor device according to any one of Items 1 to 12, wherein the buried insulating film has a thickness of 0.5 μm or more.
(Item 14) The semiconductor device according to any one of Items 1 to 13, wherein the dummy trench is disposed with an interval of 2 μm or less between the dummy trench and the gate trench.

(Item 15) The n ⁺ type emitter region according to any one of Items 1 to 14, wherein the n ⁺ type emitter region has an n-type dopant concentration of 1 × 10 ¹⁹ cm ^{−3 to} 5 × 10 ²⁰ cm ⁻³ . Semiconductor device.
(Item 16) The semiconductor according to any one of Items 1 to 15, wherein the p-type base region has a p-type dopant concentration of 1 × 10 ¹⁶ cm ⁻³ to 1 × 10 ¹⁸ cm ^−3. apparatus.
(Item 17) The n ⁻ type drift region according to any one of Items 1 to 16, wherein the n ⁻ type drift region has an n-type dopant concentration of 1 × 10 ¹³ cm ^{−3 to} 5 × 10 ¹⁴ cm ⁻³ . Semiconductor device.

(Item 18) The p ⁺ type collector region according to any one of items 1 to 17, wherein the p ⁺ type collector region has a p-type dopant concentration of 1 × 10 ¹⁵ cm ⁻³ to 2 × 10 ¹⁹ cm ⁻³ . Semiconductor device.
(Item 19) A semiconductor layer, a plurality of gate trenches formed in the semiconductor layer, a gate electrode embedded in the plurality of gate trenches via a gate insulating film, and a side of each of the gate trenches, An n ⁺ -type emitter region, a p-type base region and an n ⁻ -type drift region disposed in order from the front surface side of the semiconductor layer in the depth direction of the gate trench, and the back surface of the semiconductor layer with respect to the n ⁻ -type drift region P ⁺ -type collector region disposed on the side, a plurality of emitter trenches formed between the plurality of adjacent gate trenches, and a surface portion of the p-type base region with respect to the n ⁺ -type emitter region A p ⁺ type base contact region formed on the opposite side of the gate trench, and the n ⁺ type embedded in the plurality of emitter trenches via an insulating film An embedded electrode electrically connected to the emitter region; a p-type floating region formed between the plurality of emitter trenches; and an interlayer film formed on the semiconductor layer, wherein the p-type floating region is , Formed deeper than the p-type base region, wraps around below the emitter trench closest to the gate trench among the plurality of emitter trenches, and is located on the side closer to the gate trench with respect to the center in the width direction of the emitter trench. The p-type base region is exposed on the surface of the semiconductor layer between the p ⁺ -type base contact region and the emitter trench, and the interlayer film includes: It is formed so as to cover a part of the whole of the n ⁺ -type emitter region and the p ⁺ -type base contact region Semiconductor device.

  According to this configuration, the p-type floating region (overlap portion) is formed up to the bottom of the emitter trench in which the buried electrode is buried (hereinafter referred to as “emitter junction trench”). Thereby, the collector-emitter voltage loaded on the emitter junction trench during the switching-off operation can be relaxed. Therefore, it is possible to prevent the device from being destroyed with respect to a steep voltage change (dv / dt).

Further, the breakdown voltage can be improved by the p-type floating region deeper than the p-type base region, while the p-type base region may be shallow, so that the channel length can be shortened by appropriately designing the depth of the p-type base region. Thus, an increase in on-voltage can be suppressed.
(Item 20) The p-type floating region may have a bottom that bulges toward the back surface of the semiconductor layer with respect to the bottom of the emitter trench.

(Item 21) It is preferable that the emitter trench is formed at the same depth as the gate trench.
In this case, since the emitter trench can be formed in the same process as the gate trench, the manufacturing process can be simplified.
(Item 22) The n ⁺ -type emitter region may have an n-type dopant concentration of 1 × 10 ¹⁹ cm ^{−3 to} 5 × 10 ²⁰ cm ⁻³ .

(Section 23) The p-type base region may have a p-type dopant concentration of 1 × 10 ¹⁶ cm ⁻³ to 1 × 10 ¹⁸ cm ⁻³ .
(Section 24) The n ⁻ type drift region may have an n type dopant concentration of 1 × 10 ¹³ cm ^{−3 to} 5 × 10 ¹⁴ cm ⁻³ .
(Section 25) The p ⁺ -type collector region may have a p-type dopant concentration of 1 × 10 ¹⁵ cm ⁻³ to 2 × 10 ¹⁹ cm ⁻³ .

(Item 26) It is preferable that the n ⁺ -type emitter region selectively has a lead-out portion that is led out in a lateral direction along the surface of the semiconductor layer from a side surface of the gate trench.
(Item 27) A semiconductor layer, a plurality of gate trenches formed in the semiconductor layer, a gate electrode embedded in the plurality of gate trenches via a gate insulating film, and a side of each of the gate trenches, An n ⁺ -type emitter region, a p-type base region and an n ⁻ -type drift region disposed in order from the front surface side of the semiconductor layer in the depth direction of the gate trench, and the back surface of the semiconductor layer with respect to the n ⁻ -type drift region A p ⁺ type collector region disposed on the side, a plurality of emitter trenches formed between the plurality of adjacent gate trenches, and an n ⁺ type embedded in the plurality of emitter trenches via an insulating film A buried electrode electrically connected to the emitter region, a p-type floating region formed between the plurality of emitter trenches, and the gate The n ⁺ -type emitter region between the wrench, the p-type base region and the n ^- As -type drift region is formed, and the dummy trench formed at a predetermined interval laterally of said gate trench A buried insulating film embedded in the dummy trench and having an upper surface on the bottom side of the dummy trench with respect to the surface of the semiconductor layer, the portion on the side surface of the dummy trench extending from the surface to the upper surface A buried insulating film that selectively exposes a part of the p-type base region as a contact region, and is buried in a region above the buried insulating film of the dummy trench and connected to the contact region on the side surface of the dummy trench And the p-type floating region is formed deeper than the p-type base region. A semiconductor including an overlap portion that wraps around below the emitter trench closest to the gate trench among the plurality of emitter trenches and has an end located on the side closer to the gate trench with respect to the widthwise center of the emitter trench apparatus.

  According to this configuration, since the side surface of the dummy trench can be effectively used as a contact region, a sufficient contact area of the contact electrode with respect to the p-type base region can be ensured. As a result, the planar area of the p-type base region can be sacrificed, so that the distance between the gate trench and the dummy trench can be made finer, and a finer p-type base region can be formed compared to the conventional case. Moreover, since the dummy trench can be formed using the same mask as the gate trench, there is no positional shift with respect to the gate trench. The alignment of the contact electrode can be easily performed because it is sufficient to match the area including the planar area of the dummy trench.

Further, as a result of the miniaturization of the trench structure, the trade-off relationship between the short-circuit withstand voltage and the on-voltage of the device can be improved, so that the charge promoting effect can be improved. Therefore, V _CE (sat) in the low current region can be improved.
(Item 28) The semiconductor device may further include a first buried electrode buried in an area below the buried insulating film of the dummy trench through an insulating film.

(Item 29) The semiconductor device may include a trench unit including a pair of the dummy trenches and a gate trench sandwiched between the pair of dummy trenches.
(Item 30) It is preferable that the dummy trench also serves as the emitter trench when the first buried electrode is electrically connected to the n ⁺ -type emitter region.
(Item 31) The semiconductor device may include a trench unit including a pair of the gate trenches and a dummy trench sandwiched between the pair of the gate trenches.

In this case, (Item 32) The first embedded electrode is preferably electrically connected to the gate electrode.
(Item 33) The buried insulating film preferably has a thickness of 0.5 μm or more.

EXAMPLES Next, although this invention is demonstrated based on an Example, this invention is not limited by the following Example.
With respect to the structure of the semiconductor device 101 shown in FIG. 6, how the improvement effect of the trade-off relationship between the short-circuit withstand voltage and the on-voltage (V _CE ) changes depending on the distance L ₁ between the gate trench 108 and the dummy trench 109. In order to confirm the above, the V _CE -I _Cf characteristics of four types of devices having different intervals L ₁ were examined. The results are shown in FIG. In FIG. 11, device A (trench interval L ₁ = 2 μm dot-dash line) and device C (trench interval L ₁ = 3.5 μm dashed line) were used.

According to FIG. 11, the narrower the trench distance _{L 1,} the rise of the _V CE (sat) is low, it steady loss is low can be confirmed (see the lower right enlarged view of FIG. 11). Moreover, in the high current region of _ICf , it was confirmed that the saturation current density was lowered by the miniaturization of the trench (volume reduction of the p-type base region 111), and the short-circuit withstand capability was improved.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Semiconductor substrate 3 Back surface 4 p ⁺ type collector region 5 n type buffer region 6 n ⁻ type drift region 7 Surface 8 Gate trench 10 p type base region 13 n ⁺ type emitter region 14 Emitter trench 15 p type floating region 16 Bottom portion 17 Overlap portion 18 End portion 19 Insulating film 20 Gate electrode 21 Embedded electrode 22 Gate insulating film 31 Semiconductor device 33 Gate trench 34 p-type base region 35 n ⁺ -type emitter region 38 Lead-out portion 101 Semiconductor device 102 Semiconductor substrate 103 Back surface 104 p ⁺ -type collector region 106 n ^- -type drift region 107 surface 108 gate trenches 109 dummy trench 110 trench unit 111 p-type base region 112 n ⁺ -type emitter region 113 p ⁺ -type base contact region 11 Side surface 115 Side surface 116 Emitter trench 117 P-type floating region 118 Bottom portion 119 Overlap portion 120 End portion 121 Insulating film 122 Gate electrode 123 First embedded electrode 124 Second embedded electrode 125 Gate insulating film 126 Embedded insulating film 127 Removing portion 128 Upper surface 132 Emitter electrode 141 Semiconductor device 142 Gate trench 143 Dummy trench 144 Trench unit 145 p-type base region 146 n ⁺ -type emitter region 147 p ⁺ -type base contact region 148 Side surface 149 Side surface 150 p-type floating region 151 Bottom portion 152 Overlapping portion 153 End portion 154 First embedded electrode 155 Embedded insulating film 156 Removal portion 157 Upper surface 159 Corner portion

Claims (11)

A semiconductor layer;
A plurality of trenches formed in the semiconductor layer so as to extend in a first direction and aligned in a second direction perpendicular to the first direction;
A plurality of gate electrodes embedded in the plurality of trenches via an insulating film and adjacent to each other in the second direction and a plurality of emitter electrodes adjacent to each other along the second direction;
An n ⁺ -type emitter region, a p-type base region, and a n-type emitter region disposed in this order from the surface side of the semiconductor layer in the depth direction of the trench in a region between the gate electrodes adjacent to each other on the side of the gate electrode an n ⁻ type drift region;
A p-type floating region formed in a region between the emitter electrodes adjacent to each other, formed deeper than the p-type base region, and including an overlap portion that goes around below the emitter electrode;
A p ⁺ type collector region disposed on the back side of the semiconductor layer with respect to the n ⁻ type drift region,
The semiconductor device, wherein an interface between the p-type base region and the n ⁻ -type drift region is set at a central portion or an upper portion of the trench.   The semiconductor device according to claim 1, wherein the p-type floating region has a bottom portion that bulges toward a back surface side of the semiconductor layer with respect to a bottom portion of the trench.   3. The semiconductor device according to claim 1, wherein the overlap portion of the p-type floating region has an end portion located on a gate electrode side with respect to a center in a width direction of the emitter electrode. The bottom of the trench is formed in a curved shape so that the center in the width direction is the most convex,
The semiconductor device according to claim 3, wherein an end portion of the overlap portion is located beyond the center in the width direction. The semiconductor device according to claim 1, wherein an n-type buffer layer is formed between the n ⁻ -type drift region and the p ⁺ -type collector region. The semiconductor device according to claim 1, wherein the n ⁺ -type emitter region has an n-type dopant concentration of 1 × 10 ¹⁹ cm ^{−3 to} 5 × 10 ²⁰ cm ⁻³ . The semiconductor device according to claim 1, wherein the p-type base region has a p-type dopant concentration of 1 × 10 ¹⁶ cm ⁻³ to 1 × 10 ¹⁸ cm ⁻³ . The semiconductor device according to claim 1, wherein the n ⁻ -type drift region has an n-type dopant concentration of 1 × 10 ¹³ cm ^{−3 to} 5 × 10 ¹⁴ cm ⁻³ . The semiconductor device according to claim 1, wherein the p ⁺ -type collector region has a p-type dopant concentration of 1 × 10 ¹⁵ cm ⁻³ to 2 × 10 ¹⁹ cm ⁻³ . In the p-type base region, a contact portion dug from the surface of the semiconductor substrate is formed,
The semiconductor device according to claim 1, wherein a p ⁺ -type base contact region is formed on a bottom surface of the contact portion.   The semiconductor device according to claim 1, wherein the p-type floating region and the gate electrode are separated and formed so as not to overlap.

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