JP2006314112A - Method for controlling semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enhance reliability by stabilizing gate voltage, even at high voltage, high current, preventing current nonuniformity and oscillation, and the like, thereby protecting the device against breakdowns. <P>SOLUTION: In the method for controlling the semiconductor device, having two main electrodes and a control electrode part which controls current between the main electrodes, in a detection process, an amount of charge accumulated at the control electrode part is detected, based on voltage of the control electrode part. In a control process, voltage applied to the control electrode part and/or current flow to the control electrode part is controlled, based on the amount of charge detected by the detecting process. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device for power control and a control method thereof, and more particularly to a control method of a semiconductor device capable of improving stability by optimizing the capacity of a control terminal.

    Generally, semiconductor devices for power control include IGBTs (Insulated Gate Bipolar Transistors) or IEGTs (Injection Enhanced Gate Bipolar Transistors) that can control a large amount of power with a control terminal (hereinafter referred to as a gate) having a MOS structure. It is used.

  FIG. 64 is a cross-sectional view showing the configuration of this type of IGBT. In this IGBT, a collector electrode 2 is formed on a p-type emitter layer 1, and an n-type base layer 3 is formed on the surface of the p-type emitter layer 1 opposite to the collector electrode 2. A p-type base layer 4 is selectively diffused on the surface of the n-type base layer 3. An n-type source layer 5 is selectively formed on the surface of each p-type base layer 4.

  On the region from one n-type source layer 5 through the p-type base layer 4 and the n-type base layer 3 to the other p-type base layer 4 and the n-type source layer 5, a gate insulating film 6 is interposed. A gate electrode 7 is provided. A common emitter electrode 8 is provided on each p-type base layer 4 and n-type source layer 5.

  In order to turn on the IGBT, a voltage that is positive with respect to the emitter electrode 8 is applied to the gate electrode 7 in a state where a voltage (main voltage) that is positive with respect to the emitter electrode 8 is applied to the collector electrode 2 side. Apply. As a result, an n-type channel is formed on the surface of the p-type base layer 4 sandwiched between the n-type base layer 3 and the n-type source layer 5, and an electron current flows into the n-type base layer 3. On the other hand, a hole current flows from the p-type emitter layer 1 into the n-type base layer 3, thereby conducting conductivity modulation in the n-type base layer 3 and turning on the IGBT.

  On the other hand, to turn off, a voltage that is 0 or negative with respect to the emitter electrode 8 is applied to the gate electrode 7. As a result, the n-type channel disappears and electron injection into the n-type base layer 3 disappears, and the IGBT is eventually turned off. Even in this state, the main voltage is applied.

  Note that an IGBT that is actually commercialized is manufactured by integrating such individual fine IGBTs in a chip. That is, the IGBT described in FIG. 64 is a unit region called a cell composed of two IGBTs at both ends of one gate electrode 7 among all IGBTs in the chip. The IGBTs of these cells are integrated and formed in parallel to each other to form a chip-like IGBT.

However as described above IGBT such semiconductor device, such as by instability of nonuniformity and the gate voltage V _G of the on-current (collector current) in the chip or in the cell, may become impossible to current control, In this case, there is a possibility that the IGBT itself is destroyed.

Incidentally, instability of such gate voltage V _G is caused by disrupting factors made of the noise, or slight non-uniformity of the variation and the IGBT of the gate resistance properties mixed into the gate circuit.

For example, as shown in FIG. 65, when noise of 1V is mixed into the gate resistance 300Ω of one IGBT 1 for a moment (about 10 nsec) in the two IGBTs 1 and 2 in the on state, as shown in FIG. _G is biased toward the other IGBT 2, and as shown in FIG. 67, a phenomenon occurs in which an on-current flows only through the other IGBT 2.

Furthermore, this phenomenon is only an example, this addition, there is a possibility that phenomena such as current concentration in vibration and the cells of the gate voltage V _G occurs. In any case, if the IGBT is generated in a high voltage and high current state, there is a possibility that the IGBT will be destroyed, so that the reliability of the semiconductor device is lowered.

  On the other hand, for this type of semiconductor device, a short-circuit protection method for improving reliability is known. FIG. 68 is a circuit diagram for explaining the short-circuit protection method, and FIG. 69 is a plan view showing the appearance of the semiconductor device.

  This semiconductor device has a structure in which a main IGBT element M1 as a main element and a sense IGBT element S1 for current detection are electrically connected in parallel and formed in the same chip. However, the ratio of the device regions in the chip is such that the main IGBT element M1 is in the range of “100 to 1000” when the sense IGBT element S1 is “1”.

  Here, the current flowing through the main IGBT element M1 is detected by a voltage drop across the resistor Rs connected to the emitter of the sense IGBT element S1. That is, when a large current flows through the sense IGBT element S1 due to a short circuit or the like, a voltage drop occurs in the resistor Rs. As shown in FIG. 68, this voltage causes a current to flow through the base of the transistor Tr1 whose collector is connected to the gate circuit. Thereby, the transistor Tr1 is turned on, and the gate voltages of the main IGBT element M1 and the sense IGBT element S1 are lowered.

  However, this short circuit protection method has the following problems. When the operation mode changes instantaneously such as turn-on and turn-off, the detected current may not correspond to the current of the entire IGBT chip. For this reason, there are many cases in which a protective operation does not occur during a short circuit. In addition, there is a problem that the manufacturing variation is large.

  Furthermore, since the sense IGBT element S1 is provided in the same chip as the main IGBT element M1, there is a problem of narrowing the effective area of the main IGBT element M1. In addition, since the feedback loop from the detection of a large current to the reduction of the gate voltage is long, protection delay and unstable oscillation are likely to occur. Further, once the sense IGBT TS1 is formed, there is a problem that it is extremely difficult to adjust the protection level. Further, there is a problem that the semiconductor device has a four-terminal structure having the emitter of the sense IGBT element S1 in addition to the three terminals of the collector, gate and emitter of the main IGBT element M1. That is, there is a problem that the semiconductor device has a complicated structure and increases costs.

Next, protection of the semiconductor device at turn-off will be described. FIG. 70A is a time chart showing a time change of the voltage V _CE applied to the main IGBT element M1 and the current I _CE flowing through the main IGBT element M1 when the main IGBT element M1 is turned off. FIG. 70 (b) is a time chart obtained by differentiating the voltage waveform shown in FIG. 70 (a). In both figures, a solid line indicates when the gate resistance Rg connected in series to the MOS gate circuit is small, and a broken line indicates when Rg is large.

  In order to increase the turn-off speed, the power element is not limited to the main IGBT element M1, and it is necessary to reduce the loss at turn-off (the product of voltage and current integrated over time) when driven by a high-frequency signal. It is necessary to reduce the gate resistance Rg. However, the waveform having a small Rg has a large peak value of dV / dt because the turn-off time is short, as shown in FIG. Since the target voltage VCE is constant, the two differential waveforms shown in FIG. 70B have the same time axis and area.

  Now, in this way, when the gate Rg is reduced and the rate of increase dV / dt of the voltage VCE applied to the main IGBT element M1 is increased, if the peak value of dV / dt exceeds a certain value, it is proportional to dV / dt. Therefore, there is a problem that the main IGBT element M1 fails to be turned off and is destroyed due to the displacement current flowing therethrough.

  On the other hand, when the gate resistance Rg is increased and the main IGBT element M1 is protected from the breakdown due to dV / dt, there is a problem that the turn-off speed becomes slow, the turn-off loss increases, and the switching speed becomes difficult.

Above-described manner conventional semiconductor device, such as by instability of V _G of the gate voltage, there is a possibility that the device itself is destroyed becomes impossible to current control.

  In addition, with regard to short circuit protection, since the feedback loop from detection of a large current to reduction of the gate voltage is long, there is a problem that protection delay or unstable oscillation is likely to occur.

  Further, regarding the turn-off, when the gate resistance Rg is made small, there is a problem that the main element fails to be turned off and is destroyed due to a displacement current flowing in proportion to dV / dt. On the other hand, when the gate resistance Rg is increased, there is a problem that the turn-off speed is lowered.

In addition, there exists a thing shown in the nonpatent literature 1, for example as a related literature of IEGT.
1993, IEEE, 679-IEDM, 28. 3. 1, A 4500 V Injection Enhanced Insulated Gate Bipolar Transistor (IEGT) Operated in a Mode Similar to a Thyristor

  The present invention provides a method for controlling a semiconductor device, which can stabilize gate voltage even at high voltage and large current, prevent current non-uniformity and oscillation, etc., and thereby protect the device from destruction and improve reliability. It is what.

  According to the present invention, in a method for controlling a semiconductor device having two main electrodes and a control electrode unit that controls a current between the main electrodes, the voltage is stored in the control electrode unit based on the voltage of the control electrode unit. And a control step for controlling the voltage applied to the control electrode unit and / or the inflow current to the control electrode based on the charge amount detected by the detection step. It is characterized by being.

  Further, the present invention provides a method for controlling a semiconductor device having two main electrodes and a control electrode unit that controls a current between the main electrodes, and a current passing through the control electrode unit before and after the passing. And a control step of controlling an applied voltage to the control electrode unit and / or an inflow current to the control electrode based on a difference between the current before passing and the current after passing, respectively. It is characterized by including.

  According to the present invention, there is provided a semiconductor device control method capable of stabilizing gate voltage even at high voltage and large current, preventing current non-uniformity and oscillation, etc., thereby protecting the device from destruction and improving reliability. it can.

In the present invention, one of the main causes of IGBT breakdown is that the gate has a negative differential capacitance (C _G = dQ _G / dV _G , where Q _G is a charge stored in the gate) at a high collector voltage. This is based on the knowledge found by the present inventors. That is, the gist of the present invention is to improve the stability of the device by eliminating the negative differential capacity of the gate at all times, thereby protecting the device from destruction.

  Next, the knowledge on which the present invention is based will be described.

44. As shown in FIG. 44, the present inventors made a 1200V high voltage IGBT (trade name GT25Q101 manufactured by Toshiba, length of n-type base layer 3 = about 100 μm or more, impurity concentration = 5 × 10 ¹³ cm ^−3. relates less), the gate voltage V _G dependence of gate charge Qc (slope = gate capacitance) were examined by experiments for different collector voltage V _CE. In the gate voltage V _G , a single pulse sine wave having an amplitude of about 15 V is superimposed on a DC bias indicated by the horizontal axis. In other words, in the measurement, a well-known CV measurement method cannot be used from the viewpoint of avoiding the temperature rise of the element being measured. Therefore, a sine wave of one pulse is applied to the gate, and the charge flowing into the gate is measured simultaneously. The result of FIG. 44 is obtained by inputting the gate voltage on the horizontal axis and the charge amount on the vertical axis of the oscilloscope. At this time, the frequency of the sine wave is 10 to 20 kHz.

As shown in the figure, when the collector voltage V _CE is 881 V, the gate charge Q _G decreases as the gate voltage V _G increases, and a negative differential capacity of the gate appears.

45 and 46 show the results of simulating the experimental contents of FIG. 44, and similar results are obtained. That is, in the gate capacitance calculated from the simulation results, as shown in FIG. 46, at high collector voltage V _CE, negative capacitance has appeared above the gate threshold Vth.

  This negative capacity appears to be caused by the following mechanisms (M1) to (M3) and cause the effect (M4).

(M1) At the time of a high collector voltage, holes injected from the p-type emitter layer 1 are accelerated by a high electric field in the n-type base layer 3 and reach the interface between the n-type base layer 3 and the gate insulating film 6. . (M2) at high collector voltage, the potential of the n-type base layer 3 is higher than the gate voltage V _G, a hole channel at an interface of the n-type base layer 3 (storage layer) is formed. (M3) The positive charge of the hole channel induces a negative charge in the gate electrode 7 and causes a negative capacity of the gate.

(M4) negative capacitance of such a gate is, when connecting the gate resistor to the gate electrode 7, the negative C · R time constant, causing the instability of the gate voltage V _G, such as shown in FIG. 66 The gate voltage V _G may increase or decrease, and the gate voltage V _G may be oscillated to make the gate circuit uncontrollable.

  Such negative capacitance can also be expressed using mathematical formulas as described below. FIG. 47 shows the phenomenon (M1) to (M3) described above in more detail. 47 can be replaced with the equivalent circuit shown in FIG. However, the relationship between the capacitance and the voltage of each part is the equivalent circuit shown in FIG.

From the equivalent circuit shown in FIG. 48, the electron current _Ie injected into the n-type base layer 3 through the n-channel at the interface of the p-type base layer 4 is expressed by the following equation (1).

^{_{I e = g m n-ch}} (V GE -V th n-ch) ... (1)
Here, g _m ^n-ch represents a mutual conductance, and V _th ^n-ch represents an n-channel threshold voltage.

On the other hand, hole current _{I h} injected from the p-type emitter layer 1, using the current amplification factor of the pnp transistor portion of the IGBT (IEGT) beta, shown as the following equation (2).

I _h = βI _e (2)
Considering that all the hole current Ih flows through the p-channel at the interface of the n-type base layer 3 to the p-type base layer 4, it can be expressed by the following equation (3).

^{_{I h = g m pch (V}} pch -V GE -V th pch) ... (3)
At this time, by substituting the equations (1) and (3) into the equations (2), the relational expressions of the respective voltages are obtained as shown in the following equation (4).

^{_{g m pch (V pch -V GE}} -V th pch) = βg m n-ch (V GE -V th n -ch) ... (4)
On the other hand, from the equivalent circuit shown in FIG. 49, the charge ΔQG stored in the gate is expressed by the following equation. ΔQ _G = C _G−S ΔV _GE + C _G−p−ch Δ (V _GE −V _pch )
From the equation (4), Δ (V _GE −V _pch ) = − β (g _m ^n−ch / g _m ^p−ch ) ΔV _GE , so that the gate capacitance CG is expressed by the following equation (5). Can show.

C _G = ΔQ _G / ΔV _GE = C _G-S -C _G-p-ch · β · g _m ^n-ch / g _m ^p-ch
... (5)
Here, the second term on the right side is a negative value, which causes a negative capacitance.

  The above knowledge about the negative (differential) capacity has been obtained for the first time by the inventors' research.

  Subsequently, the gist of the present invention based on this finding will be described in detail.

50 and 51 schematically show the negative capacitance shown in FIG. The gate capacitance _CG includes a capacitance C2 composed of n-type base layer 3 / gate insulating film 6 / gate electrode 7, and (n-type source layer 5 / p-type base layer 4) / gate insulating film 6 / gate electrode 7. This is considered to be a parallel combined capacity with a capacity C1 composed of

Here, capacitor C1, as shown in FIG. 52, irrespective takes an almost constant value to the gate voltage V _G. Capacitor C2, as shown in FIG. 53, decreases stepwise with respect to the gate voltage V _G. In the capacity C2, as it can be inferred from FIG. 46, the positive capacitor C2 ⁺ and negative capacitance C2 ^- ratio of about 2: 1.

In the present invention, by increasing the actively C1, as shown in FIG. 54, and raised the capacity C2, C2 ^- counteracts the negative capacitance due. Specifically, C1 ≧ C2 ⁻ = (1/2) C2 ⁺ . That is, when the following expression (6) is satisfied, the gate capacitance _CG is always zero or a positive value and does not have a negative value.

  For example, the expression (6) represents the area of the MOS structure including the n-type base layer 3 (corresponding to the capacitor C2) and the area of the MOS structure including the n-type source layer 5 and the p-type base layer 4 (corresponding to the capacitor C1). ) Can be used to design the mask pattern. In addition, the method of realizing the expression (6) is not limited to the area of the MOS structure, and the thickness and material (dielectric constant ε) of the gate insulating film in the MOS structure may be designed corresponding to the capacitors C1 and C2. Further, if the expression (6) is an essentially equivalent substitution, another expression such as “the area of the MOS structure” or another expression such as “the area of the capacitor C2 / the total area of the gate = 2/3 or less”. You may show using the relational expression.

  The above findings have been confirmed experimentally as described below, and the relevance to parameters in device design such as the length of the n-type base layer 3 has also been confirmed. Here, the length of the n-type base layer 3 (hereinafter also referred to as N-base length) corresponds to the distance of the n-type base layer 3 between the p-type emitter layer 1 and the bottom of the p-type base layer 4. To do.

  FIG. 55 is a graph confirming the relationship between the length of the n-type base layer 3 and C1 / (C2 ++ C1) by actually using four IGBTs. When the length of the n-type base layer 3 is 100 μm, the value of C1 / (C2 ++ C1) is reduced from 0.33 to 0.2 (1/3 to 1/5).

This is in accordance with N base length increases, it is necessary to increase the carrier accumulation amount of n-type base layer 3 is due to the traditional idea of extending the gate length L _G. That is, by increasing the gate length L _G, promotes injection of electrons from MOS channel comes from a conventional design method of achieving a lower on-voltage. Therefore, the value of C2 + is increased and the value of C1 / (C2 ++ C1) is decreased. As a result, C2− also becomes large, and it is easy to cause negative gate capacitance.

  Therefore, as shown in FIG. 55, an IGBT with C1 / (C2 ++ C1) = 0.33 (N base length = about 63 μm; hereinafter referred to as IGBT element A) and C1 / (C2 ++ C1) = 0.2. The instability of the gate of the IGBT (N base length = 100 μm; hereinafter referred to as IGBT element B) was examined by noise pulses as described above.

  Specifically, as shown in FIG. 56, an experiment was conducted in which two IGBT elements A1 and A2 were connected in parallel, a noise pulse was applied to the gate of one IGBT element A2, and the behavior of the gate voltage was observed. A similar experiment was also performed for the two IGBT elements B1 and B2.

  As a result, when the IGBT elements A1 and A2 are connected in parallel, although there is a temporary gate voltage fluctuation due to the noise pulse, it immediately converges stably to the gate bias voltage (voltage given by the gate signal).

On the other hand, in the IGBT elements B1 and B2, as shown in FIG. 57, after applying the noise pulse, the oscillations of the gate voltages V _G1 and V _G2 do not converge and increase. In addition, since a noise pulse is applied to the IGBT element B2, the gate voltage V _G1 of the other IGBT element B1 also vibrates greatly, and oscillation due to instability due to negative capacitance occurs between the parallel elements B1 and B2.

  From this experimental result, instability does not surely occur when C1 / (C2 ++ C1) ≧ 0.33, and instability such as oscillation and current non-uniformity occurs when C1 / (C2 ++ C1) ≦ 0.2. Therefore, considering instability, the value of C1 / (C2 ++ C1) needs to be at least larger than 0.2 (= 1/5), and should be 0.33 (= 1/3) or more. desirable.

  In addition, in an element having an N base length of 100 μm or more, according to the conventional design method, C1 / (C2 ++ C1) is reduced to about 0.2. Therefore, the present invention is particularly effective for an element having an N base length of 100 μm or more. It is.

  In an element having an N base length of 300 μm or more, the value of C1 / (C2 ++ C1) is about (1/10) = 0.1, which is less than 0.2. It is effective to improve the instability to raise 1/5 to 0.2.

  The above description is about the planar type device, but it has been confirmed by the inventors' research that the same negative gate capacitance is produced in the case of the trench type device. However, in the trench type element, the ratio of C2 +: C2 + is slightly different from that of the planar type element.

  58 is a diagram showing a configuration of a trench type IEGT device without gate skipping, FIG. 59 is a diagram showing a configuration of a trench type IEGT device with gate skipping, and FIG. 60 shows these two types of IEGT devices. 5 is a diagram showing a calculation result of gate voltage dependency in gate capacitance. In the present specification, the term “jump” means omission of the n-type source layer 5.

  That is, in the IEGT element TA without skipping, an n-type source layer 5 is formed on the surface of the n-type source layer 5 via the p-type base layer 4 instead of the planar gate insulating film 6 and the gate electrode 7 as shown in FIG. Grooves (trench) are dug up to a depth reaching the base layer 3. An embedded gate electrode 7t is disposed in the trench surrounded by a gate insulating film 6t provided on the side surface of the p-type base layer 4 sandwiched between the n-type base layer 3 and the n-type source layer 5. The gate electrode 7t is connected to a gate terminal (not shown).

  On the other hand, as shown in FIG. 59, the skipped IEGT element TB differs from the configuration shown in FIG. 58 in that the p-type base layer 4 having the n-type source layer 5 and the p-type base layer 5 in which the n-type source layer 5 is omitted. The mold base layers 4 are alternately arranged between the grooves.

Here, as shown in FIG. 60, the IEGT element TA without skip has a portion where the gate capacitance becomes a negative value. Further, in the IEGT device TB of there skipping, a large negative gate capacitance _{C G} occurs.

In this type of trench type device, although the change in the gate capacitance _{C G} is complicated, C2 +: ratio of C2- is generally in the configuration without skipping, C2 +: C2- = 5: 1, skipping In the existing configuration, C2 +: C2 +-= 4: 1.

  For this reason, in the structure without skipping, it is preferable that the value of C1 / (C2 ++ C1) is 1/6 or more. Similarly, in a configuration with skipping, it is preferable that the value of C1 / (C2 ++ C1) is 1/5 or more.

  In FIG. 60, a negative peak occurs in the vicinity of a gate voltage of 4.5 V. This negative peak is not considered because it is generated in a small current region where the collector current is small and is less affected by breakdown.

  Next, a method for controlling a semiconductor device according to the study by the present inventors will be described. This control method is mainly concerned with protection in the event of a short circuit.

  As shown in FIG. 61 and FIGS. 62 (a) to (b), the inventors have found that when the IGBT is short-circuited, the charge accumulated in the gate is reduced as compared with the normal operation. It was. That is, a state in which the charge accumulated in the gate is reduced as compared with the normal operation is detected as a short circuit state. Moreover, when the short circuit state is detected, the IGBT can be protected from the short circuit by reducing the gate voltage.

  FIG. 63 is a block diagram of a protection circuit prototyped based on this finding. A charge counter circuit (charge counter) CC is connected in series with the gate circuit of the main IGBT element M1.

  On the other hand, a transistor Tr1 is connected between the gate circuit and the ground.

  Here, the differential amplifier AM1 determines whether or not the gate charge amount detected by the charge detection circuit CC is equal to or less than a predetermined value (prohibited area shown in FIG. 61) while referring to the gate voltage. When the charge amount is equal to or less than a predetermined value, the differential amplifier AM1 applies a base current to the transistor Tr1 to control the Tr1 to be in an on state, thereby reducing the gate voltage.

  As a method for detecting the charge amount of the gate, voltage or current detection by an arbitrary circuit can be used as appropriate.

  Further, a method for controlling the semiconductor device related to detection of dV / dt will be described. This semiconductor device has a dV / dt detection element electrically in parallel with the main switching element, and controls the resistance value of the gate resistance based on the detection result of the detection element.

  As a result, the turn-off can be accelerated within a range in which the main switching element is not destroyed, so that the off loss can be reduced and the element characteristics can be improved.

  Based on the above-described knowledge and outline of the present invention, specifically, the following means for solving are realized.

  According to a first aspect of the method for controlling a semiconductor device of the present invention, a semiconductor device having two main electrodes and a control electrode unit that controls a current between the main electrodes is controlled. Based on the detection step of detecting the amount of charge accumulated in the control electrode unit, and the voltage applied to the control electrode unit and / or the inflow current to the control electrode based on the amount of charge detected by the detection step And a control process.

  As the control step, when the charge amount has a negative value, the applied voltage and / or the inflow current are reduced.

  According to a second aspect of the method for controlling a semiconductor device of the present invention, a semiconductor device having two main electrodes and a control electrode unit that controls a current between the main electrodes is controlled, and passes across the control electrode unit. And a control process for controlling the applied voltage to the control electrode section and / or the inflow current to the control electrode based on the difference between the current before the passage and the current after the passage. Process.

  As the control step, when the result of integrating the difference has a negative value, the applied voltage and / or the inflow current is reduced.

  According to the first aspect, when the charge amount of the control electrode portion is detected and the charge amount has a negative value, the applied voltage and / or the inflow current to the control electrode portion is reduced as a short-circuit state. The semiconductor device can be protected from a short circuit state.

  Further, according to the second aspect, the current passing through the control electrode portion is detected before and after passing, and the result of integrating the difference between the current before passing and the current after passing has a negative value. In some cases, the voltage applied to the control electrode portion and / or the inflow current is reduced as a short circuit state, so that the semiconductor device can be protected from the short circuit state.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First reference example)
1 is a plan view showing a configuration of an IGBT according to a first reference example, and FIG. 2 is a cross-sectional view taken along lines IIA-IIA and IIB-IIB in FIG. Are denoted by the same reference numerals, and detailed description thereof will be omitted. Only different parts will be described here. In addition, the same description will be omitted for each of the following reference examples.

  In other words, the semiconductor device according to this reference example stabilizes the gate voltage by eliminating the negative capacitance of the gate. As shown in FIG. 1 and FIG. A portion of the gate insulating film 6 is partially formed on the n-type base layer 3 over the entire width. For this reason, the area of the interface portion where the n-type base layer 3 and the gate insulating film 6 are in contact with each other is made smaller than in the prior art.

Specifically, the area S _G (so-called area of the gate electrode 7) at the interface between the gate electrode 7 and the gate insulating film 6 and the portion where the gate electrode 7 and the n-type base layer 3 overlap with each other through the gate insulating film 6. The ratio with the area _SNB is defined by the following equation (7).

The equation (7) shows an equivalent relationship to the above-described equation (6). That is, the expression (7) describes from the reverse direction that the capacity C1 in the expression (6) is 1/3 or more of the total gate capacity, and the area _SNB corresponding to the capacity C2 is defined as the total gate capacity. It is defined as 2/3 or less of the corresponding area.

Further, when the thickness t _ox of the gate insulating film 6 is partially different, such as a terrace gate, the IGBT is designed so as to satisfy the following equation (8).

  Next, the operation of such an IGBT will be described.

  As described above, when the IGBT is turned on, when the collector voltage is high, holes injected from the p-type emitter layer 1 are accelerated by a high electric field in the n-type base layer 3, and the n-type base layer 3 and the gate insulating film 6 is reached.

  When the collector voltage is high, the potential of the n-type base layer 3 is higher than the gate voltage, so that a hole channel (storage layer) is formed at the interface of the n-type base layer 3.

  Due to the positive charge of the hole channel, a negative charge is induced in the gate electrode 7 along the IIA-IIA cross section.

  However, unlike the conventional IGBT, an n channel is generated at the interface with the gate insulating film 6 in the p-type base layer 4 in the portion shown in the IIB-IIB cross section, and this n channel causes the gate electrode 7 to have an n channel. The negative charge is canceled and a positive charge is induced in the gate electrode 7, so that no negative capacitance is generated. Further, since holes are discharged to the emitter electrode 8 at the time of a high collector voltage, it is further difficult to generate a negative capacity. Therefore, it is possible to ensure the stability of the gate voltage.

  As described above, according to the first reference example, when a voltage is applied between the collector electrode 1 and the emitter electrode 8, the capacitance viewed from the gate electrode 7 is always a positive value or a zero value. By eliminating the negative differential capacity of the gate at the time of voltage, the gate voltage can be stabilized even at high voltage and high current, and current non-uniformity and oscillation can be prevented, thereby protecting the device from destruction and improving reliability. Can be improved.

Further, when the current between the collector electrode 1 and the emitter electrode 8 is cut off, the minimum value of the capacitance viewed from the gate electrode 7 is set to 1/3 or more of the maximum value of the capacitance. since the area S _NB of the portion in contact with the n-type base layer 3 is limited to 2/3 or less of the total area S _G of the gate electrode 7, it can be easily, reliably effects described above.

  In addition, since the length of the n-type base layer 3 is set to 100 μm or more, the above-described effects can be realized in a high breakdown voltage IGBT of 1200 V or more.

(Second reference example)
Next, an IGBT according to a second reference example will be described.

  FIG. 3 is a plan view showing the configuration of the IGBT. This reference example is a modified configuration of the first reference example, in which the planar shape of the p-type base layer 4 is modified. Specifically, as shown in FIG. The p-type base layer 4 formed on the n-type base layer 3 over the entire width 6 has a ladder-like planar shape.

  Even with the configuration as described above, the same effect as the first reference example can be obtained, and the pattern of the p-type base layer 4 is formed more uniformly than the configuration shown in FIG. An improvement in the stability of the gate voltage can be expected.

(Third reference example)
Next, an IGBT according to a third reference example will be described.

  FIG. 4 is a cross-sectional view showing the configuration of the IGBT. This reference example is a modified configuration of the first reference example, which is a modified configuration of the p-type base layer 4, specifically, as shown in FIG. 4, an n-type base just below the center of the gate electrode 7. A p-type layer 10 is selectively formed on the surface of the layer 3.

  Here, although not shown, the p-type layer 10 is connected to each p-type base layer 4 immediately below the emitter electrode 8.

  With such a configuration, the potential of the p-type layer 10 is fixed to the emitter potential. For this reason, the surface of the p-type layer 10 is kept at a low voltage even at a high collector voltage.

  Here, if the gate voltage is positive, an inversion layer is formed on the surface of the p-type layer 10, so that the gate voltage can be held positive as in the first reference example.

  This structure is particularly effective for high breakdown voltage IGBTs of 2 kV or higher. For example, in the case of a high breakdown voltage IGBT, it is preferable to set the gate width L to, for example, 60 μm or more in order to achieve carrier accumulation and low on resistance in the on state. In this case, the p-type layer may be 1/3 or more of the gate width L (for example, 20 μm width).

  According to this structure, since the gate width L is wide, the p-type layer 10 and the p-type base layer 4 can be integrated, and a low on-resistance can also be realized.

(Fourth reference example)
Next, a semiconductor device according to a fourth reference example will be described.

  5 is a perspective sectional view showing the structure of the semiconductor device, FIG. 6 is a plan view showing the structure of the semiconductor device, and FIG. 7 is a line VII A-VII A and a line VII B-VII B in FIG. It is arrow sectional drawing.

  This reference example is a modified configuration of the first reference example, in which holes at the interface with the gate insulating film 6 in the n-type base layer 3 are positively discharged. Specifically, FIG. 7 to 7, an IGBT region in which a p-type layer 11 is selectively formed on the surface of an n-type base layer 3 and a p-channel MOSFET region using the p-type layer 11 as a source are provided in one chip. Yes.

  Here, in the p-channel MOSFET, the p-type source layer 11s in which the p-type layer 11 in the IGBT region is extended in the longitudinal direction on the surface of the n-type base layer 3, and the p-type base layer 4 of the IGBT is the n-type base layer 3 A p-type drain layer 4d extending in the longitudinal direction on the surface, and an IGBT emitter electrode 8 extending in the longitudinal direction on the p-type base layer 4 and the n-type source layer 5 are selected on the p-type drain layer 4d. And an emitter electrode 8e formed in a conventional manner.

  The p-channel MOSFET is gated on the p-type drain layer 4d, on the p-type source layer 11s and on the n-type base layer 3 between the layers 4d and 11s via the gate insulating film 6. An electrode 12 is formed. The gate electrode 12 is electrically connected to the emitter electrode 8e and is electrically insulated from the gate electrode 7 of the IGBT.

  A floating electrode 13 is formed on the p-type source layer 11s along the longitudinal direction thereof. The floating electrode 13 is for equalizing the potentials of the p-type layers 11s and 11 from the p-channel MOSFET region to the IGBT region, and is insulated from the electrodes 7, 8, 8e, and 12 in the IGBT and p-channel MOSFET. It is in a floating state in terms of potential.

  Next, the operation of such a semiconductor device will be described.

  As described above, when the IGBT is turned on, when the collector voltage is applied, the holes injected from the p-type emitter layer 1 are accelerated by the high electric field in the n-type base layer 3 and are insulated from the n-type base layer 3 and the gate insulation. It reaches the interface with the film 6. At this time, the p-type layer 11 of the IGBT is floating in potential, and does not prevent carrier accumulation at the interface between the n-type base layer 3 and the gate insulating film 6. Therefore, in this reference example, the ON voltage does not increase.

  Here, when a high collector voltage is applied, since the potential of the n-type base layer 3 is higher than the gate voltage, a hole channel (p-channel) is formed at the interface of the n-type base layer 3.

  That is, at the time of a high collector voltage, the p-type source layer 11s and the p-type drain layer 4d of the p-channel MOSFET are short-circuited by this p-channel, while the potentials of the p-type layer 11 and the p-type source layer 11s rise by several volts. To do.

  Thereby, in the p-channel MOSFET, the hole current from the p-type layer 11 of the IGBT flows to the p-type drain layer 4d through the p-type source layer 11s and the p-channel, and the potential of the p-type source layer 11s becomes the p-channel. It is fixed to Vth (for example, about 4V) of the MOSFET.

  Therefore, since holes on the surface of the n-type base layer 3 of the IGBT can also be discharged from the p-type layer 11, negative gate capacitance is not generated, and the stability of the gate voltage can be improved. At this time, the capacity of C follows the formula (11) described later.

(Fifth reference example)
Next, an IGBT according to a fifth reference example will be described.

  FIG. 8 is a cross-sectional view showing the structure of the IGBT, and only the parts different from FIG. 64 will be described. Unlike the method of formula (6) in which the capacitance C1 is increased, this reference example has a configuration in which the negative potential of the gate is blocked by using the emitter potential. Specifically, as shown in FIG. The thickness of the insulating film 14 u on the gate electrode 7 facing the n-type base layer 3 through the gate insulating film 6 and the gate electrode 7 is made thinner than other portions of the insulating film 14 on the gate electrode 7. It has a structure. Note that the emitter electrode 8 of each IGBT is connected to each other through the insulating films 14 and 14 u on the gate electrode 7.

  With such a structure, the negative potential of the emitter electrode 8 can induce a positive charge in the gate electrode 7 through the thin layer of the insulating film 14u, and as a result, the negative capacitance of the gate can be blocked. In addition, the same effect as that of the second reference example can be realized without reducing the effective operation region.

(Sixth reference example)
Next, an IGBT package according to a sixth reference example will be described. FIG. 9 is a circuit diagram showing a configuration of the IGBT package. This IGBT package 21 has a configuration realized by the capacity design when the IGBT according to the present invention is packaged, and a capacitor C is connected between the gate G and the emitter E in the package of the IGBT.

  As a result, the capacitance C1 can be increased and the generation of a negative capacitance of the gate can be prevented.

  As shown in FIG. 10, in addition to the configuration shown in FIG. 9, a resistor R may be connected in series with the capacitor C between the gate G and the emitter E in the IGBT package 22. Even in such a configuration, in addition to the above-described effect due to the increase in the capacitance C1, the resistance R prevents vibration due to the wiring inductance, so that the stability can be further improved.

(Seventh reference example)
Next, an IGBT package according to a seventh reference example will be described. FIG. 11 is a circuit diagram showing the configuration of the IGBT package. The IGBT package 23 has a configuration in which a capacitor C and a resistor R are connected in series between both gate electrodes of two IGBTs (regions or chips). Each gate electrode G of the IGBT package 23 can be individually connected to a gate bias circuit (not shown) via gate resistors RG1 and RG2.

Here, the capacitance C inserted between the gates G is a value that satisfies the following equation (9) with respect to the original C2 + and C1 of the IGBT.

Equation (9) indicates that the capacitance C inserted between the gates G is ½ times that of the sixth reference example. When this is, as shown in FIG. 66, the gate voltage V _G of the two IGBT moves vertically symmetrical, the influence of the gate voltage V _G according to the inserted capacitance C, inserting the capacitance between the gate and emitter This is because the effect is twice as large.

  With such a configuration, current unevenness when IGBTs are connected in parallel can be prevented.

  Similarly, as shown in FIG. 12, the IGBT package 24 may have a configuration in which three IGBTs are connected in parallel, and the gate electrodes G are individually connected to each other by a series circuit of a capacitor C and a resistor R.

In the case of the three parallels, the capacity C is expressed by the following equation (10).

  Similarly, in an IGBT package in which four or more IGBTs are arranged in parallel, each capacitor has a capacitance C (and a resistance R) having a value (1 / IGBT number) times as large as the capacitance C of the sixth reference example. Connect between them.

However, when the capacitor C is inserted between the IGBTs in a star shape, the capacitor C is a value that satisfies the following equation (11) regardless of the number of IGBTs.

(Eighth reference example)
Next, IEGT according to an eighth reference example will be described.

  13 is a plan view showing the configuration of the IEGT, and FIG. 14 is a cross-sectional view taken along line XIV A-XIV A and a cross-sectional view taken along line XIV B-XIV B in FIG. This reference example is a modification in which the first and second reference examples are applied to a trench type element. Specifically, as shown in FIGS. 13 and 14, the planar type gate insulating film 6 and the gate electrode 7 are formed. Instead, a groove (trench) is dug in the surface of the n-type source layer 5 through the p-type base layer 4 to a depth reaching the n-type base layer 3.

  An embedded gate electrode 7t is disposed in the trench surrounded by a gate insulating film 6t provided on the side surface of the p-type base layer 4 sandwiched between the n-type base layer 3 and the n-type source layer 5. The gate electrode 7t is connected to a gate terminal (not shown).

  In addition, the p-type base layer 4 formed so that the two n-type source layers 5 are individually in contact with the surface of each groove between the grooves is selectively formed on the surface of the n-type base layer 3. That is, between each groove, each IEGT region having each n-type source layer 5 and p-type base layer 4 as shown between XIV B and XIV B in FIG. 14 and each XIV A-XIVA as shown in FIG. The element invalid regions not having the n-type source layer 5 and the p-type base layer 4 are alternately formed.

  Here, in the element invalid region, the p-type emitter layer 1 is formed deeper than the depth of the p-type emitter layer 1 in the IEGT region.

  As described above, the structure in which the p-type emitter layer 1 is partially formed deeply accelerates the holes injected from the p-type emitter layer 1 by partially canceling the high electric field in the n-type base layer 3. Since the degree is reduced and the amount of holes reaching the interface between the n-type base layer 3 and the gate insulating film 6t is reduced and the inversion layer is not generated, the negative capacity can be canceled.

  The configuration in which the p-type emitter layer 1 is partially deepened is applied to an invalid gate electrode 7t that is connected to the gate terminal but is not in contact with the n-type source layer 5 and the p-type base layer 4. Negative capacity can be negated.

(Ninth Reference Example)
Next, IEGT according to a ninth reference example will be described.

  FIG. 15 is a cross-sectional view showing the configuration of the IEGT, and only parts different from FIG. 58 will be described. In this reference example, the influence of the high electric field of the n-type base layer 3 is reduced to prevent negative capacitance. Specifically, as shown in FIG. 15, there are usually two n-type source layers. The number of 5 is one for each gate, and the distance WG between the gates is reduced. Although the ninth to twelfth reference examples are not individually described, unlike FIG. 13, the n-type source layer 5 and the p-type base layer 4 have a constant configuration along the surface stripe direction. It has become.

  The distance WG between the gates is designed to be about 3 to 4 μm, for example.

  With the configuration in which the distance WG between the gates is reduced to about 3 to 4 μm as described above, the amount of injected electrons can be increased, so that the influence of the high electric field in the n-type base layer 3 can be reduced, and thus negative. The gate capacitance can be prevented.

  In addition, with the configuration in which one n-type source layer 5 is provided between the gates, the distance WG between the gates can be easily and reliably reduced to about 3 to 4 μm.

(10th reference example)
Next, IEGT according to a tenth reference example of the present invention will be described.

  FIG. 16 is a cross-sectional view showing the configuration of this IEGT, and only parts different from FIG. 59 will be described. In this reference example, negative charges are discharged from the gate electrode in the skip region. Specifically, as shown in FIG. 16, it is arranged between the p-type base layers 4 having no n-type source layer 5. The invalid gate electrode 7t is connected to the emitter terminal instead of the connection to the gate terminal.

  With the configuration as described above, the gate electrode 7t is fixed at a constant potential with respect to the emitter, so that the negative charge generated in the gate electrode 7t in the skip region is discharged, thereby preventing the influence of the negative charge on the gate electrode 7t. Can do.

(Eleventh reference example)
Next, IEGT according to an eleventh reference example of the present invention will be described.

  FIG. 17 is a cross-sectional view showing the configuration of this IEGT, and only parts different from FIG. 59 will be described. In this reference example, in order to reduce the negative gate capacitance, the skip region and the IEGT region are grouped. Specifically, as shown in FIG. 17, two skips (n-type source layer) 5) and two IEGT regions are alternately arranged. Note that the ratio of the number of skip regions to the IEGT regions is 2: 2 (= 1: 1).

  The embedded gate electrode 7t in the skip region is connected to the emitter terminal. On the other hand, the gate electrode 7t indicated by G in the drawing is connected to a gate terminal (not shown) as usual, and so on.

  59 is different from the configuration shown in FIG. 59 in spite of the same skip number ratio (1: 1) as that of the configuration shown in FIG. 59, the gate electrode 7t in the skip region is different from the configuration shown in FIG. Since it is fixed at a constant potential with respect to the emitter, negative gate capacitance can be suppressed as described above.

  In addition, the invalid gate is separated from the gate electrode to be used in potential and connected to the ground or a fixed potential, so that the characteristics are improved as compared with the case of connecting to the gate potential. That is, since the gate capacitance is reduced, the switching speed when dropping to zero potential is improved. In addition, since there is no extra capacitance, the device operation is stabilized, so that reliability can be improved. Specifically, the SOA (safety operating area) can be expanded.

  As a modification, as shown in FIG. 18, when the skip region and the IEGT region are grouped by m, (n-1) invalid gates may be fixed at a constant potential with respect to the emitter. it can.

  In this reference example, only the case where the number of skip regions and IEGT regions is the same number has been described. However, the present invention is not limited to this, and the same applies to the number ratio when the skip region and IEGT region are different from each other. Can be implemented. Further, the number ratio of the IEGT regions to one skip region is preferably in the range of 1 to 4 in view of element characteristics such as high breakdown voltage and large current. Further, since this is a number ratio, it indicates that m skip regions and m to 4 m IEGT regions can be arranged alternately.

(Twelfth reference example)
Next, IEGT according to a twelfth reference example of the present invention will be described.

  FIG. 19 is a cross-sectional view showing the configuration of the IEGT. This reference example is a modified configuration of the eleventh reference example, in which the number of carriers annihilated by interface recombination at the trench oxide film interface is reduced, and the amount of accumulated carriers in the n-type base layer 3 is increased. Specifically, as shown in FIG. 19, for example, between the two gate electrodes and the emitter terminal in the three skip regions, the emitter terminal is set to the positive potential side, and the gate electrode is set to the negative potential side. The power supply 30 is inserted.

With the above configuration, an inversion layer or an interface accumulation layer is formed at the trench oxide film interface between the gate insulating film 6t and the n-type base layer 3 in the gate electrode 7t in the skip region. is, having an electron concentration ns at the interface, the relation either to each other and the hole concentration ps at the interface becomes very large number compared to the other (n _s «p _s or n _s »p _s).

Here, generally at a high injection state, the carriers disappear oxide film interface, expressed by ^{(1 cm} 2, per _{second) Us = s 0 (p s} n s) / (p s + n s). However, s ₀ is the interface recombination velocity.

At this time, the number of carriers that recombine at the interface becomes maximum when p ₀ = n ₀ as shown in FIG. This is, for example, p ₀ = about n ₀ when the gate electrode 7 t and the emitter terminal are at the same potential.

However, IEGT of this reference example, a voltage to the gate electrode 7t in skipping region applied, the interface between the gate insulating film 6t and the n-type base layer 3 is _n s << P _s, or _{n s »p} s state Therefore, the amount of recombination at the trench oxide film interface can be reduced, the number of accumulated carriers in the n-type base layer 3 can be increased, and the negative gate capacitance can be reduced.

  The voltage applied to the gate electrode 7t in the skip region is effective even if the voltage is lower than about 0.5V. For this reason, even when a built-in voltage is generated in the gate by using a heavily doped polysilicon gate instead of applying a voltage, an equivalent effect can be obtained without applying a voltage from the outside.

(First embodiment)
The first to seventh embodiments relate to protection of an element from a short circuit state.

  21 and 22 are circuit diagrams showing a short circuit protection system for a semiconductor device according to the first embodiment of the present invention. This short-circuit protection system is intended to protect the semiconductor device at the time of a short circuit as in the configuration shown in FIG.

  Schematically, this short-circuit protection system includes C12, between the gate of a main IGBT element (model number: GT25Q101) M1 having a gate capacitance CG (10 nF in normal operation) and its gate driver Gd1. A voltage bridge circuit having R4 and R5, a differential amplifier (model number: LF356) AM1 connected to the voltage bridge circuit, and a transistor Tr1 that receives the output from the differential amplifier AM1 and makes the gate and ground conductive. A short-circuit protection circuit SCP having a model number: MPSA56) is inserted.

  Here, the voltage bridge circuit supplies a voltage corresponding to the gate charge of the main IGBT element M1 to the inverting input terminal of the differential amplifier AM1, and the gate charge is applied to the non-inverting input terminal as shown in FIG. It has a function of supplying a reference voltage for determining whether or not it is within. This voltage bridge circuit can dynamically change the gate charge inhibition region as shown in FIG. 23 by adjusting R4 (RRef) or the power supply Vref connected to R4.

  The differential amplifier AM1 detects the gate charge accumulated in the gate of the main IGBT element M1 from the voltage across the C12, and determines whether or not the detection result enters the prohibited region, a voltage bridge composed of CG, C12, R4 and R5. When it is detected by the circuit and the gate charge is in the prohibited region, it has a function of giving an output to the base of the transistor Tr1.

  The resistor R1 between the gate and the gate drive circuit has a function of removing unnecessary vibration between the gate capacitance CG and the capacitor C12, and can be changed or omitted to a smaller value when the wiring length is short. Is possible.

  Next, the operation of such a semiconductor device short-circuit protection system will be described. At normal times, the main IGBT element M1 is turned on / off within its operating range. At this time, the differential amplifier AM1 detects the gate charge of the main IGBT element M1 from the voltage across the C12, and detects that the detection result is outside the prohibited region by the voltage bridge circuit.

  On the other hand, at the time of a short circuit, a large current flows through main IGBT element M1, and gate charge enters the prohibited region in FIG.

  The differential amplifier AM1 detects that the gate charge has entered the prohibited region, and provides an output to the base of the transistor Tr1. The transistor Tr1 is turned on by the base input, and conducts the gate and the ground through the resistor R8, the diode D, and the like, and reduces the gate voltage.

  Due to the decrease in the gate voltage, the main IGBT element M1 is turned off, and the gate charge escapes from the prohibited area and enters the normal operation area, thereby protecting the main IGBT element M1.

  Here, for example, as shown in FIG. 24, when the short circuit protection circuit SCP of the present embodiment is not provided, a current of about 200 A flows to the main IGBT element M1 during a short circuit. On the other hand, when the short circuit protection circuit SCP is inserted as in the present embodiment, the value of the current flowing through the main IGBT element M1 is suppressed. Further, the current value at which the protection operation is started can be arbitrarily set by changing Vref.

  As described above, according to the present embodiment, the gate charge is detected by the voltage bridge circuit, and the differential amplifier AM1 detects whether the gate charge is in the prohibited region. The main IGBT element M1 can be protected from destruction by reducing the voltage and putting the gate charge into the normal operation region.

  Further, as shown in FIG. 22, the short circuit protection circuit SCP of the present embodiment adds a short circuit protection function to the main IGBT element M1 only by being inserted between the gate drive circuit Gd1 and the gate of the main IGBT element M1. can do. For this reason, it can be easily applied to an existing IGBT or a device using an IGBT. That is, a short-circuit protection function can be added even to an IGBT chip that does not incorporate the sense IGBT element S1. Further, since the short circuit protection circuit can be built in the gate drive circuit by making it into an IC or the like, it can be realized with almost no increase in cost.

  The short-circuit protection circuit can be realized in a small area, and the feedback loop from the detection of the gate charge to the reduction of the gate voltage can be shortened. Therefore, unlike conventional methods, protection delay and unstable oscillation can be eliminated. .

  The protection level can be electrically controlled by adjusting Vref and the like. For this reason, it is possible to program the short circuit protection method according to the situation such as the temperature and the operation mode of the main IGBT.

(Second Embodiment)
FIG. 25 is a circuit diagram showing a gate charge detection method in the short-circuit protection system for a semiconductor device according to the second embodiment of the present invention.

  This embodiment is a modification obtained by improving the first embodiment. That is, in the first embodiment, the gate charge is detected by the voltage across the capacitor C12 inserted in series in the gate circuit. However, in the first embodiment, since the gate voltage changes due to the voltage sharing of the capacitor C12, when the main IGBT element M1 is in the ON state (when a positive voltage is applied to the gate), the gate drive circuit Gd1 gives A voltage slightly lower than the applied voltage is applied to the gate of the main IGBT element M1.

  On the other hand, in the present embodiment, the charge accumulated in the gate is detected based on the current flowing through the power supply wiring of the gate drive circuit Gd1.

  As shown in the figure, since the input resistance of the gate drive circuit Gd1 is very high, the charge flowing into the gate integrates the difference between the current I1 flowing into the gate drive circuit Gd1 and the current I2 flowing out as shown in the following equation. Is obtained.

  QG = ∫ (I1−I2) dt or less. Similarly, the differential amplifier (not shown) detects whether or not the gate charge enters the prohibited region, and when the gate charge enters the prohibited region, the gate voltage is lowered. The main IGBT element M1 is protected from a short circuit.

  As described above, according to the present embodiment, in addition to the effects of the first embodiment, the short circuit protection operation is realized by detecting the gate charge without reducing the voltage applied to the gate from the gate drive circuit. Can do.

(Third embodiment)
FIG. 26 is a circuit diagram showing a gate charge detection method in the semiconductor device short-circuit protection system according to the third embodiment of the present invention.

  This embodiment is a modification of the second embodiment. Specifically, in the present embodiment, as shown in FIG. 26 and the following equation, the inflow current I1 and the outflow current I2 in the gate drive circuit Gd1 are detected based on the voltage drop at the resistor Rcc, and the both currents I1 and I2 are detected. Is integrated to detect the charge QG flowing into the gate.

QG = ∫− (V1−V2) / Rcc dt
However, I1 = V1 / Rcc, I2 = V2 / Rcc
Even with such a configuration, the same effects as those of the second embodiment can be obtained.

  The present embodiment can be modified as shown in FIG. That is, as shown in FIG. 27, the difference between the two currents I1 and I2 may be taken out by the resistor Ra, and the charge QC accumulated in the gate may be detected by an integrating circuit as shown in the following equation.

QG = 2 ・ R1 ・ C ・ V3 / Rcc
The same effect can be obtained even when deformed in this way.

(Fourth embodiment)
FIG. 28 is a circuit diagram showing a gate charge detection method in the short circuit protection system for a semiconductor device according to the fourth embodiment.

  This embodiment is a modification of the second or third embodiment. Specifically, in the present embodiment, as shown in FIG. 28, a current is detected through a current mirror circuit, and this current flows into the capacitor C, so that the charge QG flowing into the gate becomes the capacitor C as shown in the following equation. It detects based on the voltage difference V4 of both ends.

QG = C ・ V4 ・ r
However, r: mirror current factor Even with such a configuration, the same effect as in the third or fourth embodiment can be obtained. In this embodiment, if the effective area of the mirror side transistors Tr13 and Tr14 on the chip of the current mirror circuit is smaller than that of the input side transistors Tr11 and Tr12, the power consumption of the circuit is reduced, which is advantageous. is there. It is desirable that the ratio of the effective area be within the range of 5 to 1000 for the input side transistors Tr11 and Tr12, where the mirror side transistors Tr13 and Tr14 are set to 1.

(Fifth embodiment)
FIG. 29 is a circuit diagram showing a gate drive circuit and a gate charge detection method in the short circuit protection system for a semiconductor device according to the fifth embodiment of the present invention.

  In the present embodiment, the configuration shown in FIG. 28 in the fourth embodiment is embodied including the gate drive circuit Gd1 as shown in FIG.

  In FIG. 29, Tr11 to Tr14 interlocked with the potential of the input terminal IN correspond to the gate drive circuit Gd1, and Tr15 to Tr18 for taking out the current flowing through Tr13 and Tr14 of the gate drive circuit Gd1 correspond to the current mirror circuit. However, for convenience of explanation, these composite circuits are denoted by reference numeral Gd1 in the drawings.

  The gate drive circuit Gd1 outputs a current from the drive output terminal OUT. The current mirror circuit outputs a current from the extraction terminal OUTREF. The current flowing through the drive output terminal OUT and the current flowing through the extraction terminal OUTREF are proportional to the ratio of the effective area of the mirror transistor, and are independent of the voltage at the extraction terminal OUTREF.

  In the present embodiment, the same effects as those of the fourth embodiment can be obtained easily and reliably by the specific configuration as described above.

(Sixth embodiment)
FIG. 30 is a circuit diagram showing a short-circuit protection system for a semiconductor device according to the sixth embodiment of the present invention. The circuit shown in FIG. 29 is inserted into the broken line.

  This embodiment has a configuration in which the fifth embodiment is applied to a circuit using a voltage bridge circuit similar to FIG. Even with such a configuration, the same effects as those of the first and fifth embodiments can be obtained.

  Further, the present embodiment can be modified as shown in FIG. 31 or FIG. The modification shown in FIG. 31 or FIG. 32 is a circuit in which a transistor Tr1 for short-circuit protection is arranged on the input side of the gate drive circuit Gd1, and gives the output of the differential amplifier AM1 to this transistor Tr1.

  In these modified examples, since the transistor Tr1 (for example, MPSA56) performs conduction with the ground at the high resistance input portion of the gate drive circuit Gd1, a large current does not flow through the gate drive circuit Gd1 even during short-circuit protection. The drive circuit Gd1 has an advantage that there is little possibility of causing electrical loss and heat generation.

  Further, the transistor Tr1 only needs to be able to conduct the signal of the high resistance input portion of the gate drive circuit Gd1 to the ground, and therefore can be reduced in size compared to the case where it is provided on the output side of the gate drive circuit Gd1. Note that the modified example shown in FIG. 32 can stabilize the operation because the emitter potential is more stable than the configuration shown in FIG.

(Seventh embodiment)
FIG. 33 is a block diagram showing a configuration of a short-circuit protection system for a semiconductor device according to the seventh embodiment of the present invention.

  This embodiment is a modification of the first to sixth embodiments. Specifically, as shown in FIG. 33, a PWM (pulse width modulation) controller 31, a digital logic circuit 32, an analog gate drive circuit 33, and The main IGBT element M1 is sequentially connected.

  Here, the PWM controller 31 supplies a gate signal and IGBT control data to the digital logic circuit 32 based on the operation state received from the digital logic circuit 32.

  The digital logic circuit 32 gives the gate signal received from the PWM controller 31 to the analog gate drive circuit 33 through the gate waveform control unit 32a, and starts short circuit protection based on the detection result received from the analog gate drive circuit 33. And has a function of giving a determination result to a supervisory circuit 33a of the analog gate driving circuit 33.

  In addition, the digital logic circuit 32 can be omitted, but has a function 32b for communicating an operation state with another short-circuit protection system.

  The analog gate drive circuit 33 provides a drive signal to the gate of the main IGBT element M1 based on the gate signal received from the digital logic circuit 32, and the gate charge, gate voltage, and collector voltage Vc of the main IGBT element M1. In addition, a supervisory circuit 33a is provided that gives detection results such as the collector current Ic and temperature Tj to the digital logic circuit 32 and controls the drive signal based on the determination result received from the digital logic circuit 32.

  Even if it is the above structures, the effect similar to 1st-6th embodiment can be acquired. In addition, the short-circuit protection method can be programmed easily and reliably according to the temperature, operation mode, and other conditions of the main IGBT element M1.

(13th reference example)
The thirteenth to seventeenth reference examples relate to protection of the device from an increase in dV / dt during turn-off.

  FIG. 34 is a cross-sectional view showing a configuration of a semiconductor device according to a thirteenth reference example of the present invention. As shown in the figure, a collector electrode 42 is formed on one surface of the p + -type emitter layer 41. On the other surface of the p + -type emitter layer 41, an n-type buffer layer 43 and an n − -type base layer 44 are sequentially formed.

  A p-type base layer 45 is selectively formed on the surface of the n − -type base layer 44. An n + -type source layer 46 is selectively formed on the surface of the p-type base layer 45. A trench 47 is selectively formed on the surface of the n + -type source layer 46 so as to penetrate the p-type base layer 45 to a depth in the middle of the n − -type base layer 44.

  A gate electrode 49 is embedded in the trench 47 via a gate insulating film 48. An emitter electrode 50 is formed on a part of the n + -type source layer 46 and the p-type base layer 45.

  Note that a broken line portion from the emitter electrode 50 to the collector electrode 42 including the gate electrode 49 functions as the main IGBT element M1, and therefore is referred to as an element portion M1a in this specification.

  On the other hand, a sense electrode 52 is selectively formed on the n − -type base layer 44 away from the element portion M1a via an insulating film 51. The sense electrode 52 is connected to the emitter electrode 50 through the resistor 53 and is also connected to the gate control unit 60. Note that a broken line portion including the insulating film 51 and the sense electrode 52 from the collector electrode 42 to the resistor 53 has a function of detecting dV / dt, and is referred to as a dV / dt detector Dt1 in this specification.

  The gate controller 60 corresponds to the function of controlling the value of the gate resistance Rg between the gate electrode 49 and the gate drive circuit (not shown) corresponding to the potential of the sense electrode 52 and the potential of the emitter electrode 50. And a substrate potential fixing function.

  Here, a normally-on type p-channel MOSFET as shown in FIGS. 35 and 36 is applied to the gate controller 60. This p-channel MOSFET is normally in an on state and has a fixed channel resistance. When the potential of the control terminal 69 rises according to dV / dt and becomes close to the threshold voltage at the time of turn-off, the channel resistance increases. Has characteristics.

  Specifically, the gate control unit 60 includes an n-type well layer 62 selectively formed on the surface of the p-type substrate 61, p + -type drain layers 63 and p + selectively formed in the n-type well layer 62. A p-type layer 65 formed between the p-type source layer 64 and the p + -type layers 63 and 64 is provided as a semiconductor layer.

  In the p + -type drain layer 63, an input terminal 66 connected to a gate drive circuit (not shown) is formed. In the p + type source layer 64, an output terminal 67 connected to the gate electrode 49 of the element portion M1a is formed. A control terminal 69 is formed on the p− type layer 65 via an insulating film 68, and this control terminal 69 is connected to the sense electrode 52 of the dV / dt detector Dt1. A potential fixing terminal 70 is formed on the n-type well layer 62 and the p-type substrate 61, and this potential fixing terminal 70 is connected to the emitter electrode 50 of the element portion M1a.

  Next, the operation of such a semiconductor device will be described. When the element portion M1a is turned off, a flowing displacement current (a product of a depletion layer in the substrate, a capacitive component composed of the insulating film 51 and the sense electrode 52 on the substrate, and dV / dt) passes through the resistor 53 and the emitter electrode 50 Flowing into. At the same time, the potential of the sense electrode 52 rises and gives a control signal to the control terminal 69 of the gate controller 60.

  FIGS. 37A and 37B are the same as FIGS. 70A and 70B described above.

  FIG. 37 (c) shows a waveform in which the potential Vs of the sense electrode 52 changes following the change in dV / dt (when Rg is small). When the value of Vs exceeds the threshold voltage Va of the gate control unit 60, the gate control unit 60 operates and a resistance component between the input terminal 66 and the output terminal 67, as shown in FIG. Increase Rg.

  As a result, as indicated by the solid line in FIG. 37 (e), the peak value of dV / dt is suppressed, and the element portion M1a is protected from destruction. In this reference example, since the turn-off is faster than in the conventional case where Rg is increased from the beginning and the peak value of dV / dt is suppressed, the off loss can be reduced.

  As described above, according to the present reference example, the gate resistance Rg is small in the normal on state, and the gate resistance Rg is large in the turn-off state. Therefore, the element portion M1a (main IGBT) is broken by high dV / dt at the turn-off time. The turn-off speed can be increased and the off-loss can be reduced.

  Moreover, although this reference example demonstrated the case where dV / dt detection part Dt1 and element part M1a were formed in the same board | substrate, this invention is implemented similarly even if both are provided as a different body. The same effect can be obtained.

(14th reference example)
FIG. 38 is a cross-sectional view showing a configuration of an element portion applied to a semiconductor device according to a fourteenth reference example of the present invention. In this reference example, a planar IGBT is applied in place of the trench gate shown in FIG. That is, the trench 47 is omitted, the insulating film 71 is formed on the n− type base layer 44, the p type base layer 45 and the n + type source layer 46, and the gate electrode 72 is formed on the insulating layer 71.

  Even with the configuration as described above, the same effects as those of the thirteenth reference example can be obtained. 34 and 38, the case where the IGBT is used as the element portion M1a has been described. However, the present invention is not limited to this, and the present invention can be applied to all vertical MOS gate drive power semiconductor elements. .

  As this type of vertical MOS gate drive power semiconductor element, for example, there is a trench type MOSFET or a planar type MOSFET.

  In the trench type MOSFET, as shown in FIG. 39, an n + type drain layer 73 is formed instead of the p + type emitter layer 41 and the n type buffer layer 43 shown in FIG.

  Similarly, in the planar type MOSFET, as shown in FIG. 40, an n + type drain layer 73 is formed in place of the p + type emitter layer 41 and the n type buffer layer 43 shown in FIG.

  As described above, the IGBT and the MOSFET have different structures on the collector (drain in the MOSFET) side, but the present invention can be made in the same manner as described above by making the collector side of the dV / dt detector Dt1 with the same structure as the element M1a. Can be implemented.

(15th reference example)
FIG. 41 is a cross-sectional view showing a configuration of a dV / dt detector applied to a semiconductor device according to a fifteenth reference example of the present invention. In this reference example, instead of the insulating film 51 and the sense electrode 52 on the n − -type base layer 44 shown in FIG. 34, as shown in FIG. 41, the insulating film 75 and the p-type RESURF layer 74 at the junction termination portion are formed. A sense electrode 76 is formed.

  With the configuration as described above, in addition to the effect of the thirteenth reference example, the effective area of the element portion M1a can be increased.

(16th reference example)
FIG. 42 is a cross-sectional view showing a configuration of a dV / dt detector applied to a semiconductor device according to a sixteenth reference example of the present invention. In this reference example, the trench structure of the element portion M1a shown in FIG. 34 is applied to the dV / dt detection portion Dt1. That is, instead of the insulating layer 51 and the sense electrode 52 on the n− type base layer 44, the sense electrode is interposed in the trench 47a formed in the n− type base layer 44 via the insulating layer 48a as shown in FIG. 49a is embedded.

  With the configuration as described above, since the trench structures of both the element portion M1a and the dV / dt detection portion Dt1 can be formed simultaneously, in addition to the effect of the thirteenth reference example, the number of manufacturing steps of the semiconductor device can be reduced.

(17th reference example)
FIG. 43 is a cross-sectional view showing a configuration of a dV / dt detector applied to a semiconductor device according to a seventeenth reference example of the present invention. In this reference example, the configurations shown in FIGS. 41 and 42 are combined with each other. That is, instead of the insulating layer 51 and the sense electrode 52 on the n − -type base layer 44 shown in FIG. 34, a trench 47a is formed in the p-type RESURF layer 74 at the junction termination, as shown in FIG. A sense electrode 49a is embedded in the trench 47a via an insulating layer 48a.

  With the configuration as described above, in addition to the effects of the thirteenth reference example, the effects of the fifteenth and sixteenth reference examples can be obtained simultaneously.

  The configurations of the element unit M1a and the dv / dt detection unit Dt1 shown in the thirteenth to seventeenth reference examples can be implemented in any combination.

  In the present invention, the case where the main switching element is an IGBT or a MOSFET has been described as an example. However, the present invention is not limited to this, and the present invention can be implemented in various modifications to devices such as an MCT (CMOS Controlled Thyristor) and an IGBT.

  In addition, the present invention can be variously modified and implemented without departing from the scope of the invention.

The top view which shows the structure of IGBT which concerns on a 1st reference example IIA-IIA line and IIB-IIB line sectional view of FIG. The top view which shows the structure of IGBT which concerns on a 2nd reference example. The top view which shows the structure of IGBT which concerns on a 3rd reference example A perspective sectional view showing a configuration of a semiconductor device according to a fourth reference example. A plan view showing a configuration of a semiconductor device in the reference example VII A-VII A line and VII B-VII B line sectional view of FIG. Sectional drawing which shows the structure of the semiconductor device which concerns on a 5th reference example Circuit diagram showing a configuration of an IGBT package according to a sixth reference example The circuit diagram which shows the deformation | transformation structure of the IGBT package in the reference example The circuit diagram which shows the structure of the IGBT package which concerns on a 7th reference example The circuit diagram which shows the deformation | transformation structure of the IGBT package in the reference example The top view which shows the structure of IEGT which concerns on an 8th reference example XIV A-XIV A arrow sectional view and XIV B-XIV B arrow sectional view of FIG. Sectional drawing which shows the structure of IEGT which concerns on a 9th reference example Sectional drawing which shows the structure of IEGT which concerns on the 10th reference example of this invention Sectional drawing which shows the structure of IEGT which concerns on the 11th reference example of this invention Sectional drawing which shows the deformation | transformation structure of IEGT in the reference example Sectional drawing which shows the structure of IEGT which concerns on the 12th reference example of this invention The figure which shows the carrier ratio dependence of the recombination carrier number for demonstrating the operation | movement in the same reference example 1 is a circuit diagram showing a short circuit protection system for a semiconductor device according to a first embodiment of the present invention; The circuit diagram which shows the short circuit protection system of the semiconductor device in the embodiment The figure for demonstrating the setting adjustment and prohibition area | region in the embodiment The figure which shows the suppression effect of the electric current in the same embodiment The circuit diagram which shows the detection method of the gate charge in the short circuit protection system of the semiconductor device which concerns on the 2nd Embodiment of this invention. The circuit diagram which shows the detection method of the gate charge in the short circuit protection system of the semiconductor device which concerns on the 3rd Embodiment of this invention. Circuit diagram showing a modified configuration of the same embodiment The circuit diagram which shows the detection method of the gate charge in the short circuit protection system of the semiconductor device concerning the 4th Embodiment of this invention The circuit diagram which shows the gate drive circuit in the short circuit protection system of the semiconductor device concerning the 5th Embodiment of this invention, and the detection method of a gate charge A circuit diagram showing a short circuit protection system of a semiconductor device concerning a 6th embodiment of the present invention. Circuit diagram showing a modified configuration of the same embodiment Circuit diagram showing a modified configuration of the same embodiment The block diagram which shows the structure of the short circuit protection system of the semiconductor device which concerns on the 7th Embodiment of this invention. Sectional drawing which shows the structure of the semiconductor device based on the 13th reference example of this invention Circuit symbol diagram showing the configuration of the gate controller in the reference example Sectional drawing which shows the structure of the gate control part in the reference example Time chart for explaining the operation of the reference example Sectional drawing which shows the structure of the element part applied to the semiconductor device based on the 14th reference example of this invention Sectional drawing which shows the deformation | transformation structure of the element part in the reference example Sectional drawing which shows the deformation | transformation structure of the element part in the reference example Sectional drawing which shows the structure of the dV / dt detection part applied to the semiconductor device based on the 15th reference example of this invention. Sectional drawing which shows the structure of the dV / dt detection part applied to the semiconductor device based on the 16th reference example of this invention. Sectional drawing which shows the structure of the dV / dt detection part applied to the semiconductor device based on the 17th reference example of this invention. The figure which shows the experimental result for demonstrating the knowledge used as the basis of this invention Figure showing simulation results to explain the findings Figure showing simulation results to explain the findings Schematic diagram for explaining the findings Equivalent circuit diagram for explaining the findings Equivalent circuit diagram for explaining the findings Sectional drawing of IGBT for demonstrating the main point of this invention The figure which shows the conventional gate capacity-gate voltage characteristic for demonstrating the same skeleton The figure which shows the capacity | capacitance C1-gate voltage characteristic for demonstrating the same skeleton The figure which shows the capacity | capacitance C2-gate voltage characteristic for demonstrating the same skeleton The figure which shows the gate capacity-gate voltage characteristic based on this invention for demonstrating the same skeleton The figure which shows the experimental result which confirmed the knowledge used as the basis of this invention Circuit diagram showing the circuit applied to the experiment Diagram showing behavior of gate voltage after noise pulse mixing in the same experiment The figure which shows the structure of the trench type | mold IEGT element without the skip of the gate by which the knowledge used as the basis of this invention was confirmed. The figure which shows the structure of the trench type | mold IEGT element with the skip of the gate by which the knowledge used as the basis of this invention was confirmed. The figure which shows the gate voltage dependence of the gate capacitance in two types of IEGT elements with which the same knowledge was confirmed The figure for demonstrating the knowledge regarding the short circuit protection which concerns on this invention Illustration for explaining the findings Block diagram of protection circuit based on the findings Sectional drawing which shows the structure of conventional IGBT Schematic diagram of IGBT for explaining conventional problems The figure which shows the behavior of the gate voltage at the time of the conventional noise mixture A diagram showing the behavior of collector voltage and collector current when conventional noise is mixed Circuit diagram for explaining a conventional semiconductor device short-circuit protection system Plan view showing the appearance of a conventional semiconductor device Time chart for explaining conventional protection at turn-off

Explanation of symbols

1, 41 ... p-type emitter layer, 2,42 ... collector electrode, 3,44 ... n-type base layer, 4,45 ... p-type base layer, 4d ... p-type drain layer, 5,46 ... n-type source layer, 6, 6t, 48 ... gate insulating film, 7, 7t, 12, 49 ... gate electrode, 8, 8e, 50 ... emitter electrode, 10, 11 ... p-type layer, 11s ... p-type source layer, 13 ... floating electrode, 14, 14u ... insulating film, 21-24 ... IGBT package, 30 ... DC power supply, 31 ... PWM controller, 32 ... digital logic circuit, 32a ... gate waveform control unit, communication function ... 32b, 33 ... analog gate drive circuit, 33a ... Supervision circuit, 43 ... n-type buffer circuit, 47a ... trench, 48a ... insulating layer, 49a, 52, 76 ... sense electrode, 51 ... insulating film, 60 ... gate controller, 61 ... p-type substrate, 62 ... n Well layer 63 ... p + type drain layer 64 ... p + type source layer 65 ... p-type layer 66 ... input terminal 67 ... output terminal 51,68,71,75 ... insulating film 69 ... control terminal, 70 ... potential fixing terminal, 73 ... n + -type drain layer, 74 ... p-type RESURF layer, S _{NB ...} area, S G _... area, R, RG1, RG2, RG , Rg, R1~R9, Rcc, Ra , 53 ... resistors, C, C1, C2, CG, C11 to C13 ... capacity, Q G _... charge, Gd1 ... gate driver circuit, AM1 ... differential amplifier, Tr1, Tr11～Tr18 ... transistors, SCP ... short-circuit protection circuit, M1 ... main IGBT element, S1 ... sense IGBT element, I1, I2 ... current, M1a ... element part, Dt1 ... dV / dt detection part.

Claims (4)

In a control method of a semiconductor device having two main electrodes and a control electrode unit that controls a current between the main electrodes,
A detection step of detecting a charge amount accumulated in the control electrode unit based on a voltage of the control electrode unit;
A control step of controlling a voltage applied to the control electrode section and / or an inflow current to the control electrode based on the amount of charge detected by the detection step. Method. The method for controlling a semiconductor device according to claim 1,
The method of controlling a semiconductor device, wherein the control step reduces the applied voltage and / or the inflow current when the charge amount has a negative value. In a control method of a semiconductor device having two main electrodes and a control electrode unit that controls a current between the main electrodes,
A detection step of detecting the current passing through the control electrode part before and after the passage, respectively;
And a control step of controlling an applied voltage to the control electrode unit and / or an inflow current to the control electrode based on a difference between the current before passing and the current after passing. For controlling a semiconductor device. The method for controlling a semiconductor device according to claim 3,
The method of controlling a semiconductor device, wherein the control step reduces the applied voltage and / or the inflow current when a result of integrating the difference has a negative value.

Images