JP2009043782A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the reliability of an element by suppressing negative capacitance. <P>SOLUTION: An insulating gate type semiconductor device 10 is provided with: a first-conductivity-type semiconductor layer 13; a plurality of trenches 14A, 14B, 14C and 14D prepared on the face of the semiconductor layer 13 with a predetermined pitch; a second-conductivity-type base layer 17 formed between the trenches 14A and 14B; second-conductivity-type dummy base layers 34, 35 formed between the trenches 14B, 14C and 14D and having a diffusion depth larger than that of the base layer 17; gate electrodes 16A, 16B, 16C and 16D each formed by embedding a conductor into each of the trenches 14A, 14B, 14C and 14D via an insulating film 15; emitter layers 19A and 19B formed on the surface of the base layer 17; and a second-conductivity-type collector layer 11 formed on the other surface of the semiconductor layer 13. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a structure of a semiconductor device having a trench gate and a manufacturing method thereof.

  Conventionally, IEGT (Injection Enhanced Gate Bipolar Transistor) is well known as a switching element in the field of power electronics.

  In the trench gate type IEGT element, a P-type base layer is formed on one surface of an N-type semiconductor layer, and a plurality of trenches extending from the P-type base layer to the N-type semiconductor layer are provided. Inside the trench, a conductive layer is embedded via an insulating film to form a gate electrode. An N + type emitter layer is formed on the surface of the P type base layer sandwiched between the two trench gate electrodes. An emitter electrode is formed on the N + type emitter layer. The cell region of the P-type base layer where the N + type emitter layer is not formed constitutes a dummy cell. A P-type collector layer is formed on the other surface of the N-type semiconductor layer, and a collector electrode is formed on the P-type collector layer (for example, Patent Document 1, Patent Document 2, and Patent Document 3).

  When a voltage is applied to the collector electrode to turn on the IEGT, holes from the P-type collector layer reach between the N-type semiconductor layer and the trench gate insulating film in the dummy cell region, and enter the interface of the N-type semiconductor layer. Hole channels are formed. Negative holes are excited in the gate electrode by the hole channel, and negative differential capacity (hereinafter referred to as negative capacity) is generated in the gate electrode.

Due to the action of the negative capacitance, when the IEGT element is turned on, the gate voltage oscillates and rises (bounces up), the switching speed (dV / dt) becomes abnormally large, and the collector current suddenly flows to destroy the element. There is a risk of causing it.
JP 2006-245477 A

  An object of the present invention is to improve the reliability of an element by suppressing negative capacitance and at the same time improving the load short-circuit withstand capability.

  In one embodiment of the present invention, a semiconductor device includes a first conductivity type semiconductor substrate, a plurality of gate trenches provided at a predetermined interval on the first surface of the semiconductor substrate, and a first surface of the semiconductor substrate. A second conductivity type base layer formed in the first region and a second conductivity type formed between the gate trenches in the second region of the first surface of the semiconductor substrate and having a larger diffusion depth than the base layer. Dummy base layer, a gate electrode formed by burying a conductor through an insulating film inside the gate trench, and a first conductivity type emitter selectively formed on the surface of the base layer so as to be in contact with the gate trench A layer, an emitter electrode formed to connect to the emitter layer and the base layer, a collector layer of a second conductivity type formed on the second surface of the semiconductor substrate, and formed to connect to the collector layer Characterized in that a collector electrode.

  In another aspect of the present invention, a method for manufacturing a semiconductor device includes: a second conductivity type base layer on one surface of a first conductivity type semiconductor substrate; and a second conductivity type having a larger diffusion depth than the base layer. Forming a plurality of dummy base layers by ion implantation at a predetermined pitch, and a plurality of depths that are deeper than the base layer from the surface of the semiconductor substrate between the base layer and the dummy base layer and reach substantially the same depth as the dummy base layer Forming a gate trench, forming a gate insulating film inside the gate trench, forming a gate electrode by burying a conductor inside the gate trench through the gate insulating film, and a surface of the first diffusion layer And a step of selectively forming a first conductivity type emitter layer by ion implantation so as to be in contact with the gate trench.

  According to the present invention, negative capacitance can be suppressed and abnormal oscillation of the gate voltage at turn-on can be prevented. In addition, the load short-circuit resistance can be improved. As a result, the reliability of the element is improved.

  Embodiments of an insulated gate semiconductor device according to the present invention will be described below in detail with reference to the drawings.

  FIG. 1 is a schematic sectional view of a part of an insulated gate semiconductor device according to an embodiment of the present invention. FIG. 2 is a plan view schematically showing a part of the element pattern layout corresponding to FIG. In FIG. 2, for convenience of explanation, an oxide film covering the surface of the element, an emitter electrode, and the like are omitted. FIG. 1 shows a cross-sectional view taken along the line A-A ′ of FIG. 2.

  The insulated gate semiconductor device 10 according to the present embodiment is configured by alternately forming drive cells 20 functioning as transistors and dummy cells 30 arranged adjacent to the drive cells 20. The drive cell 20 and the dummy cell 30 are formed in an N− / N + / P + type substrate 37. In the N− / N + / P + type substrate 37, a high impurity concentration P + type collector layer 11 is formed on the back surface of the N− type semiconductor layer 13 via a high impurity concentration N + type buffer layer 12. It is configured. The N− / N + / P + type substrate 37 forms an N + type buffer layer 12 on the P + type substrate 11 by epitaxial growth, and further has an impurity concentration lower than that of the N + type buffer layer 12 by epitaxial growth thereon. It can be obtained by forming the N − type semiconductor layer 13. In addition, in the N− / N + / P + type substrate 37, the N− type semiconductor layer 13 is formed on the N + type buffer layer 12, and the P + type collector layer 11 is formed on the back surface of the N + type buffer layer 12. It can also be obtained by forming.

  In the N − type semiconductor layer 13, trenches 14A, 14B, 14C, and 14D extending in the vertical direction (depth direction), for example, at regular intervals are formed. Gate oxide films 15A, 15B, 15C, and 15D are formed on the inner wall surfaces of the trenches 14A, 14B, 14C, and 14D, respectively. Inside the trenches 14A, 14B, 14C, and 14D, a conductive film such as polysilicon is embedded to constitute trench gate electrodes 16A, 16B, 16C, and 16D. Among these, the trench gate electrodes 16A, 16B, and 16D are drive gate electrodes, and the trench gate electrode 16C sandwiched between the trench gate electrodes 16B and 16D is a dummy gate electrode. An interlayer insulating film 31 is formed in common above the gate electrodes 16B, 16C, and 16D, and the dummy gate electrode 16C is electrically insulated from the trench gate electrodes 16B and 16D.

  The drive cell 20 is selectively formed in a P-type base diffusion layer 17 having a desired depth formed in a region between the trench gate electrodes 16A and 16B in the N − type semiconductor layer 13 and an upper portion thereof. A P + -type contact layer 18 doped with impurities at a higher concentration than the P-type base diffusion layer 17 is provided. On the surface of the P-type base diffusion layer 17, N + -type emitter diffusion layers 19A and 19B are formed. The N + -type emitter diffusion layers 19A and 19B extend in the lateral direction and are in contact with the side surfaces of the trench gate electrodes 16A and 16B via the gate oxide films 15A and 15B, respectively. The exposed surfaces of the N + -type emitter diffusion layers 19A and 19B and the exposed surface of the P + -type base diffusion layer 18 constitute a contact region as described in detail below. The drive cells 20 are provided at equal intervals with the dummy cell 30 in between. In addition, it may be provided intermittently at different intervals.

  The dummy cell 30 includes P-type dummy base diffusion layers 34 and 35 having a desired depth and formed in a region between the trench gate electrodes 16B, 16C and 16D inside the N − type semiconductor layer 13. The dummy trenches 14C are provided so that the intervals between the trenches 14A, 14B, 14C, and 14D are constant. Polysilicon is buried inside the dummy trench 14C to constitute a dummy gate electrode 16C. Here, the dummy gate electrode 16C is irrelevant to the operation of the element 10, and can be omitted. The P-type dummy base diffusion layers 34 and 35 are formed by being diffused to a position deeper than the P-type base diffusion layer 17 described above. Specifically, the P-type dummy base diffusion layer 34 is formed to have substantially the same depth as the trenches 14B, 14C, and 14D. Here, “substantially the same” means that the negative capacitance is negligible as long as the side surfaces of the trenches 14B, 14C, and 14D are covered with the P-type dummy base diffusion layer 34. Specifically, May be about 1 μm or less. N + type emitter diffusion layer is not formed in the dummy cell 30.

  Next, the pattern layout of the insulated gate semiconductor device 10 according to the present embodiment will be described in detail. FIG. 2 is a plan view of the insulated gate semiconductor element 10 according to the present embodiment. 1 is a cross-sectional view taken along line A-A ′ of FIG. 2. As shown in FIG. 2, the trenches 14A, 14B, 14C, and 14D are provided in stripes and at the same pitch.

  Emitter diffusion layers 19A and 19B are formed between the trench 14A and the trench 14B. The emitter diffusion layers 19 </ b> A and 19 </ b> B are covered with the interlayer insulating film 31 and have stripe regions 41 </ b> A and 41 </ b> B, and have stripe regions 42 </ b> A and 42 </ b> B located in the contact region 40 connected to the emitter electrode 33. Furthermore, the emitter diffusion layers 19A and 19B include a connecting portion 44 extending in the X direction so as to connect the stripe regions 42A and 42B.

  In the contact region 40, an exposed surface 43 of the P + -type contact layer 18 formed at an equal pitch in the longitudinal direction (Y direction) is exposed in the region between the stripe regions 42A and 42B. Then, the aforementioned connecting portion 44 is formed between each of the exposed surfaces 43. Thus, the emitter diffusion layers 19A and 19B are configured as ladder-like emitter layers as a whole. In addition, the emitter diffusion layers 19 </ b> A and 19 </ b> B may not be connected by the connecting portion 44, but may be composed of only stripe portions, 41 </ b> A, 41 </ b> B, 42 </ b> A, 42 </ b> B.

  Returning to FIG. 1, the description will be continued. An interlayer insulating film 31 is formed on the element surface. A contact hole 32 is opened in the portion of the interlayer insulating film 31 corresponding to the contact region 40. A conductor film made of, for example, aluminum is commonly formed on the interlayer insulating film 31 and in the contact hole 32. This conductor film is patterned into a desired pattern to constitute the emitter electrode 33 and the wiring. Further, a collector electrode 38 is formed on the back surface of the P + -type collector layer 11.

  Next, impurity concentration profiles in the depth direction of the base diffusion layer 17 of the drive cell 20 and the dummy base diffusion layer 34 of the dummy cell 30 of the semiconductor device according to the present embodiment will be described with reference to the drawings. FIG. 3 is a graph showing impurity concentration profiles in the depth direction in the base regions 17 and 34 for the drive cell 20 and the dummy cell 30, respectively. A curve 51 shows a boron (B) concentration profile of the P-type base diffusion layer 17 of the drive cell 20. In the drive cell 20 of the semiconductor device according to the present embodiment, the impurity concentration curve 51 of the P-type base diffusion layer 17 is deeper than the junction depth between the emitter diffusion layers 19A and 19B and the base diffusion layer 17 (for example, It has an impurity concentration peak at a depth of about 2 μm. Thereby, the load short circuit tolerance can be improved.

  On the other hand, in the dummy cell 30, the impurity concentration curve 52 of the P-type dummy base diffusion layer 34 has an impurity concentration at two locations inside the base diffusion layer (depth of about 2 μm) and deeper than that (depth of about 4.2 μm). Has a peak. In this way, by creating another impurity concentration peak at a deeper position, the P-type dummy base diffusion layer 34 is uniformly diffused to a deeper position than the P-type base diffusion layer 17 of the driving cell. Is possible.

  As will be described in detail below, the depth of the P-type dummy base diffusion layers 34 and 35 can be formed to the same extent as the depth of the trenches 14B and 14C by appropriately adjusting the impurity concentration profile. By doing so, the side surfaces of the trench gate electrodes 16B and 16C are completely covered with the P-type dummy base diffusion layers 34 and 35, so that the side surfaces near the bottom of the trench gate electrodes 16B and 16C and the bottom surface of the dummy base diffusion layer 34 are directly below. It is possible to suppress the generation of negative capacitance with the holes injected from the accumulated collector layer 11. As a result, the occurrence of abnormal oscillation of the gate potential at turn-on is suppressed, and the reliability of the element is improved.

  Subsequently, the operation principle of the insulated gate semiconductor device 10 according to the present embodiment will be described.

  When a positive voltage is applied to the collector electrode 38 with respect to the emitter electrode 33 and a positive voltage exceeding the threshold is applied to the trench gate electrodes 16A and 16B, the device is turned on. An electron channel is formed in the P-type base diffusion layer 17, and electrons flow from the emitter layers 19 A and 19 B to the P-type base layer 17. On the other hand, holes are injected from the collector layer 11 into the N− type semiconductor layer 13 through the N + type buffer layer 12.

  In IEGT, the electron injection efficiency of the emitter is promoted compared to IGBT. In the case of a conventional IGBT, holes injected from the P collector layer monotonously decrease toward the P base layer because the P base layer does not serve as a barrier against holes. Therefore, the on-voltage is high. On the other hand, in IEGT, a barrier against holes is formed by a combination of a thinning structure of an emitter contact with a trench structure and a dummy base structure. Therefore, the flow of holes into the P base layer is reduced, and the amount of injected electrons is relatively increased.

  Of the plurality of P-type base diffusion layers sandwiched between adjacent trenches, holes are accumulated directly below the dummy base diffusion layers 34 and 35 where the N + -type emitter layer is not formed, and therefore conductivity modulation is performed. The effect is enhanced, the on-resistance is reduced, and the maximum breaking current density can be increased.

  Conventionally, at the time of turn-on, a negative capacitance is generated between the holes accumulated immediately below the dummy base 34 and the side surface near the bottom of the trench gate electrode, and the gate voltage oscillates and rises due to the action of the capacitance. (DV / dt) became abnormally large, and there was a risk of element destruction.

  According to the present embodiment, since the dummy base layer 34 is formed to be uniformly diffused deeply, a negative capacitance between the side surface of the trench gate and the holes accumulated immediately below the dummy base layer 34 is obtained. Occurrence is greatly suppressed. As a result, an abnormal increase in switching speed due to the oscillation of the gate voltage at turn-on is suppressed, and the reliability of the element is improved.

  Next, a method for manufacturing the trench gate semiconductor device 10 according to the present embodiment will be described with reference to the drawings. 4A to 4G schematically show a part of the manufacturing process of the insulated gate semiconductor device 10 according to the present embodiment. 4A to 4D are shown at the same scale. 4E and 4F show the dotted line region of FIG. 4D in an enlarged manner. FIG. 4G schematically shows a completed sectional view. The scale of each component between these drawings is not necessarily the same for convenience of explanation.

  First, as step 1, as shown in FIG. 4A, an N− / N + / P + type silicon substrate 37 is prepared. Here, instead of the N− / N + / P + type silicon substrate 37, an N type silicon substrate may be used.

Next, as step 2, as shown in FIG. 4B, an insulating film 60 such as a silicon oxide film (SiO ₂ ) is formed on the N − type semiconductor layer 13 by thermal oxidation. Next, a photoresist is applied to the entire surface, and a mask having an opening at the outermost peripheral portion of the element 10 is formed by a photolithography technique. Next, using the mask, for example, boron (B) is ion-implanted at a predetermined concentration to form a P + -type termination guard ring (GR) diffusion layer 61.

  Next, as step 3, as shown in FIG. 4C, the oxide film 60 is patterned by a photolithography technique, and the oxide film 60 in a portion where the P-type base layer 17 and the P-type dummy base diffusion layer 34 are to be formed is removed. .

Next, as step 4, as shown in FIG. 4D, a buffer oxide film (not shown) is formed, a photoresist is applied thereon, and then only in the region where the dummy cells 30 are to be formed by photolithography. A photoresist layer 64 having an opening is selectively formed. Next, boron (B) accelerated by high energy that passes through the photoresist layer 64 and does not pass through the oxide film 62 is ion-implanted at a dose of about 3 × 10 ¹⁹ cm ⁻² , for example. Thus, by one ion implantation, a peak of the impurity doping concentration profile is formed at a position of about 2 μm from the surface in the base region and at a position of about 4 μm from the surface in the dummy base region. Next, by removing the photoresist layer 64 and performing thermal diffusion, the P-type base layer 17 and the P-type dummy base diffusion layer 34 that is uniformly diffused to a deeper position than the P-type base layer 17 are formed simultaneously. At this time, due to side diffusion from the P-type base layer 17, a peak of impurity concentration appears in the regions of the dummy base layers 34 and 35 at substantially the same depth as the P-type base layer 17. Here, when the widths of the dummy base layers 34 and 35 are wide, there are cases where two peaks do not appear because the width of the side diffusion is exceeded.

  Next, as step 5, as shown in FIG. 4E, a photoresist is applied, and a mask having openings with a predetermined pitch P is formed by photolithography. Using the mask, trenches 14A, 14B, 14C, 14D, and 14E reaching the N − type semiconductor layer 13 from the surface of the P type base diffusion layer 17 are formed by dry etching. Next, an insulating film 66 such as a silicon oxide film is formed on the entire surface including the inside of the trench by thermal oxidation or the like. This insulating film 66 later becomes gate oxide films 15A, 15B, 15C, 15D, and 15E. Next, polysilicon is embedded in the trenches 14A, 14B, 14C, 14D, and 14E. Thereafter, gate electrodes 16A, 16B, 16C, 16D, and 16E are formed by photolithography and etching processes. If desired, a polysilicon layer (not shown) for the protective diode may be formed simultaneously.

  Next, as step 6, as shown in FIG. 4F, a resist is applied, a mask having an opening at a desired position is formed by using a photolithography technique, and a P + type is formed by ion implantation using the mask. A contact layer 18 is formed. Next, a resist is applied again, and a mask having a ladder-shaped opening only in the drive cell region is formed by using a photolithography technique. Next, using the mask, for example, phosphorus (P) is ion-implanted at a desired concentration to form N + -type emitter diffusion layers 19A and 19B. Next, an interlayer insulating film 31 having a desired thickness is deposited on the entire element region by, for example, thermal CVD or plasma CVD. Next, a photoresist is applied, a mask having an opening at a desired position is formed by a photolithography technique, and using this, dry etching such as RIE is performed to form a contact hole 32. Thereafter, for example, an aluminum thin film is deposited on the entire surface by sputtering. Next, a metal wiring layer having a desired pattern is formed by photolithography and etching processes. Thus, the emitter electrode 33 and the wiring are formed.

  Finally, as step 7, as shown in FIG. 4G, a polyimide film is deposited on the entire surface, and passivation films 69A and 69B are formed by a photolithography technique and a dry etching process. Next, a metal film such as aluminum or nickel is deposited on the back surface of the P + -type collector layer 11 by sputtering to form a collector electrode 38.

1 schematically shows a cross-sectional view of a part of an insulated gate semiconductor device according to an embodiment of the present invention. 1 is a plan view of a part of an insulated gate semiconductor device according to an embodiment of the present invention. 1 schematically shows a concentration profile of a base layer of an insulated gate semiconductor device according to an embodiment of the present invention. It is a figure explaining the manufacturing process of the insulated gate semiconductor device which concerns on embodiment of this invention. It is a figure explaining the manufacturing process of the insulated gate semiconductor device which concerns on embodiment of this invention. It is a figure explaining the manufacturing process of the insulated gate semiconductor device which concerns on embodiment of this invention. It is a figure explaining the manufacturing process of the insulated gate semiconductor device which concerns on embodiment of this invention. It is a figure explaining the manufacturing process of the insulated gate semiconductor device which concerns on embodiment of this invention. It is a figure explaining the manufacturing process of the insulated gate semiconductor device which concerns on embodiment of this invention. It is a figure explaining the manufacturing process of the insulated gate semiconductor device which concerns on embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Insulated gate type semiconductor device, 11 ... Collector layer, 12 ... Buffer layer, 13 ... N- type semiconductor layer, 14A-14D ... Trench, 15A-15D ... Gate oxidation Membrane, 16A to 16D ... trench gate electrode, 17 ... P-type base diffusion layer, 18 ... P + contact layer, 19A, 19B ... N + emitter diffusion layer, 20 ... drive Cell 30... Dummy cell 31. Interlayer insulating film 32. Contact hole 33. Emitter electrode 34. P-type dummy base diffusion layer 35. P-type dummy base diffusion Layer, 37... Silicon substrate, 38.

Claims (5)

A first conductivity type semiconductor substrate;
A plurality of gate trenches provided at predetermined intervals on the first surface of the semiconductor substrate;
A second conductivity type base layer formed in the first region of the first surface of the semiconductor substrate;
A dummy base layer of a second conductivity type formed between the gate trenches in the second region of the first surface of the semiconductor substrate and having a diffusion depth larger than the base layer;
A gate electrode formed by burying a conductor through an insulating film inside the gate trench;
An emitter layer of a first conductivity type selectively formed on the surface of the base layer so as to be in contact with the gate trench;
An emitter electrode formed to connect to the emitter layer and the base layer;
A collector layer of a second conductivity type formed on the second surface of the semiconductor substrate;
A collector electrode formed to connect to the collector layer;
A semiconductor device comprising:   The semiconductor device according to claim 1, wherein a depth of the dummy base layer is substantially the same as a depth of the gate trench.   The first peak of the second conductivity type impurity concentration distribution of the dummy base layer is deeper than the junction depth between the emitter layer and the base layer in the depth direction, and the second peak is the depth. The semiconductor device according to claim 2, wherein the semiconductor device has a depth greater than a junction depth between the base layer and the semiconductor substrate in a direction. A second conductivity type base layer and a second conductivity type dummy base layer having a diffusion depth larger than that of the base layer are formed by ion implantation at a predetermined pitch on one surface of the first conductivity type semiconductor substrate. Process,
Forming a plurality of gate trenches that are deeper than the base layer from the surface of the semiconductor substrate between the base layer and the dummy base layer and reach substantially the same depth as the dummy base layer;
Forming a gate insulating film inside the gate trench;
Forming a gate electrode by burying a conductor inside the gate trench through a gate insulating film;
Selectively forming an emitter layer of a first conductivity type by ion implantation on the surface of the first diffusion layer so as to be in contact with the gate trench;
A method for manufacturing a semiconductor device, comprising: The step of forming the base layer and the dummy base layer includes:
Forming an oxide film on the semiconductor substrate;
Removing the oxide film in regions where the base layer and the dummy base layer are to be formed;
Covering the oxide film and the region from which the oxide film has been removed with a photoresist, and forming a photoresist layer having an opening only in a portion where the dummy base layer is to be formed;
Using the oxide film and the photoresist layer as a mask, simultaneously performing high-acceleration ion implantation of impurity ions of the second conductivity type into regions where the base layer and the dummy base layer are to be formed;
The manufacturing method of the semiconductor device of Claim 4 containing this.

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