CN105938798A - Manufacturing method of trench IGBT device structure - Google Patents
Manufacturing method of trench IGBT device structure Download PDFInfo
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- CN105938798A CN105938798A CN201610215399.4A CN201610215399A CN105938798A CN 105938798 A CN105938798 A CN 105938798A CN 201610215399 A CN201610215399 A CN 201610215399A CN 105938798 A CN105938798 A CN 105938798A
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- well
- igbt device
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 26
- 238000000034 method Methods 0.000 claims abstract description 32
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 23
- 239000012535 impurity Substances 0.000 claims abstract description 20
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 19
- 239000010703 silicon Substances 0.000 claims abstract description 19
- 238000002161 passivation Methods 0.000 claims abstract description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000013461 design Methods 0.000 claims abstract description 9
- 238000001259 photo etching Methods 0.000 claims abstract description 8
- 239000002184 metal Substances 0.000 claims abstract description 7
- 238000004544 sputter deposition Methods 0.000 claims abstract description 7
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 5
- 239000000956 alloy Substances 0.000 claims abstract description 5
- 238000001312 dry etching Methods 0.000 claims abstract description 5
- 238000005530 etching Methods 0.000 claims abstract description 5
- 238000011065 in-situ storage Methods 0.000 claims abstract description 5
- 239000002210 silicon-based material Substances 0.000 claims abstract description 5
- 230000007704 transition Effects 0.000 claims description 26
- 238000000137 annealing Methods 0.000 claims description 8
- 239000000126 substance Substances 0.000 claims description 8
- 238000001039 wet etching Methods 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- 230000001413 cellular effect Effects 0.000 claims description 4
- 238000000280 densification Methods 0.000 claims description 4
- 238000005224 laser annealing Methods 0.000 claims description 4
- 238000001459 lithography Methods 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 238000001704 evaporation Methods 0.000 abstract description 2
- 238000000151 deposition Methods 0.000 abstract 3
- 238000002347 injection Methods 0.000 abstract 2
- 239000007924 injection Substances 0.000 abstract 2
- 238000009792 diffusion process Methods 0.000 abstract 1
- 238000004857 zone melting Methods 0.000 abstract 1
- 238000002955 isolation Methods 0.000 description 19
- 238000010276 construction Methods 0.000 description 16
- 238000010586 diagram Methods 0.000 description 16
- 238000005516 engineering process Methods 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000013507 mapping Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Bipolar Transistors (AREA)
Abstract
The invention provides a manufacturing method of a trench IGBT device structure. The manufacturing method comprises the following steps of: (a) firstly defining an active region on selected N-type epitaxial silicon substrate or zone-melting sheet and growing a field region oxide layer; (b) selectively defining a deep well or not according to a terminal structure and the design of unit cells of the active region; (c) photoetching a trench pattern and carrying out dry etching on the silicon substrate; (d) growing a gate oxide layer, depositing an in-situ doped polycrystalline silicon material for filling of a trench, then photoetching a gate pattern and etching polycrystalline silicon to form a gate with a top-layer structure; (e) injecting P-type impurities and forming a shallow P well as a trench region in a diffusion manner; (f) sputtering top-layer metal, photoetching the top-layer metal, depositing a passivation layer, photoetching the passivation layer and finally finishing manufacturing of the top-layer structure by an alloy; and (g) thinning the back surface of a silicon wafer to a specific thickness, carrying out back injection of the P-type impurities or injection of N-type impurities and the P-type impurities and finally depositing a back metal through a sputtering or evaporating method to finish the manufacturing process of the overall IGBT device.
Description
Technical field
The present invention relates to the manufacture method of a kind of trench IGBT device transition region structure, belong to the manufacture technology field of IGBT device.
Background technology
As the main representative of Novel power semiconductor device, IGBT is widely used in industry, information, new forms of energy, medical science, traffic, military affairs and aviation field.At present, the pressure up to 6500V of the IGBT device on market, single die electric current is up to 200A, and frequency reaches 300KHz.In high-frequency high-power field, there is presently no any one other device and can substitute for it.Along with semi-conducting material and the continuous progress of processing technique, the IGBT device of trench technique is used to become main product.Requirement to trench IGBT device electric property is more and more higher simultaneously.
In order to improve trench IGBT shorted devices ability to work, optimised devices structure is needed to reduce effective gully density to realize the control of saturation current.The method generally used has widens unit cell spacing, forms invalid active area (Dummy cell) etc..But, widen unit cell spacing and easily cause the increase of channel bottom electric field, thus reduce device electric breakdown strength.Meanwhile, in order to improve static properties and obtain controlled mapping, the electric isolation realizing invalid active area with effective channel region is needed.Especially in active area and the transition region of terminal structure, need to optimize design, to reach the compromise degree of best static state and dynamic property.
Summary of the invention
It is an object of the invention to the deficiency overcoming prior art to exist, and provide a kind of technology controlling and process simple, and general groove-shaped IGBT process compatible, and without increasing the manufacture method of the trench IGBT device transition region structure of technique cost of manufacture.
It is an object of the invention to complete by following technical solution, the manufacture method of a kind of trench IGBT device architecture, this manufacture method comprises the steps:
A) on selected N-type epitaxial silicon substrate or district's fuse piece, active area is first defined, growth place oxide layer；
B) according to terminal structure and the design of active area unit cell, optionally define deep p-well or do not do this step；
C) lithographic trenches figure, dry etching silicon substrate, this groove defines active region gate groove and for isolating the transition region groove of invalid active area simultaneously；
D) growth grid oxic horizon, the polycrystalline silicon material that deposit is mixed in situ fills groove；Then photoetched grid figure, etches polycrystalline silicon forms the grid of top level structure；
E) implanting p-type impurity diffuse to form shallow p-well as channel region；Before shallow p-well channel region also may be optionally formed on definition groove；Photoetching N-type source region injects N-type impurity；Then the insulant such as deposited oxide layer or silicon nitride densification of annealing, lithography contact hole, etching insulating layer exposes p-well region and the N-type source region silicon face of all cellulars formed before；Implanting p-type impurity also activates, it is ensured that p-well region and the Ohmic contact of top-level metallic.
F) sputtering top-level metallic, chemical wet etching top-level metallic, deposit passivation layer, chemical wet etching passivation layer, final alloy completes the making of top level structure；
G) then silicon chip back side is thinned to specific thickness, back side implanting p-type or inject N-type and p type impurity, form IGBT collecting zone by process annealing or laser annealing or terminate the FS-IGBT of level with field, completing the manufacturing process of whole IGBT device finally by the method deposit back metal sputtered or evaporate.
As preferably: described manufacture method is to utilize transition region groove and the design of deep p-well to isolate invalid active area and effective channel region.
It is simple that the present invention has technology controlling and process, and general groove-shaped IGBT process compatible, and without increasing the features such as technique cost of manufacture.
Accompanying drawing explanation
Fig. 1 is trench IGBT device transition region groove isolation construction schematic diagram of the present invention.
Fig. 2 is trench IGBT device transition region groove isolation construction another kind schematic diagram of the present invention.
Fig. 3 is trench IGBT device transition region groove isolation construction another kind schematic diagram of the present invention.
Fig. 4 is trench IGBT device transition region groove isolation construction another kind schematic diagram of the present invention.
Fig. 5 is trench IGBT device transition region groove isolation construction another kind schematic diagram of the present invention.
Fig. 6 is trench IGBT device transition region groove isolation construction another kind schematic diagram of the present invention.
Fig. 7 is trench IGBT device transition region groove isolation construction another kind schematic diagram of the present invention.
Fig. 8 is trench IGBT device transition region groove isolation construction another kind schematic diagram of the present invention.
Fig. 9 is trench IGBT device transition region groove isolation construction another kind schematic diagram of the present invention.
Figure 10 is trench IGBT device transition region groove isolation construction another kind schematic diagram of the present invention.
Figure 11 is trench IGBT device transition region groove isolation construction another kind schematic diagram of the present invention.
Figure 12 is trench IGBT device transition region groove isolation construction another kind schematic diagram of the present invention.
Figure 13 is trench IGBT device transition region groove isolation construction another kind schematic diagram of the present invention.
Figure 14 is trench IGBT device transition region groove isolation construction another kind schematic diagram of the present invention.
Figure 15 is trench IGBT device transition region groove isolation construction another kind schematic diagram of the present invention.
Figure 16 is trench IGBT device transition region groove isolation construction another kind schematic diagram of the present invention.
Detailed description of the invention
The present invention will be described in detail below in conjunction with the accompanying drawings and the specific embodiments: the manufacture method of a kind of trench IGBT device architecture of the present invention, this manufacture method comprises the steps:
A) on selected N-type epitaxial silicon substrate or district's fuse piece, active area is first defined, growth place oxide layer；
B) according to terminal structure and the design of active area unit cell, optionally define deep p-well or do not do this step；
C) lithographic trenches figure, dry etching silicon substrate, this groove defines active region gate groove and for isolating the transition region groove of invalid active area simultaneously；
D) growth grid oxic horizon, the polycrystalline silicon material that deposit is mixed in situ fills groove；Then photoetched grid figure, etches polycrystalline silicon forms the grid of top level structure；
E) implanting p-type impurity diffuse to form shallow p-well as channel region；Before shallow p-well channel region also may be optionally formed on definition groove；Photoetching N-type source region injects N-type impurity；Then the insulant such as deposited oxide layer or silicon nitride densification of annealing, lithography contact hole, etching insulating layer exposes p-well region and the N-type source region silicon face of all cellulars formed before；Implanting p-type impurity also activates, it is ensured that p-well region and the Ohmic contact of top-level metallic.
F) sputtering top-level metallic, chemical wet etching top-level metallic, deposit passivation layer, chemical wet etching passivation layer, final alloy completes the making of top level structure；
G) then silicon chip back side is thinned to specific thickness, back side implanting p-type or inject N-type and p type impurity, form IGBT collecting zone by process annealing or laser annealing or terminate the FS-IGBT of level with field, completing the manufacturing process of whole IGBT device finally by the method deposit back metal sputtered or evaporate.
This manufacture method is to utilize transition region groove and the design of deep p-well to isolate invalid active area and effective channel region.
Embodiment: the manufacture method of the present invention is completely compatible with common trench IGBT device technology, it is not necessary to increase technology difficulty；Specifically:
First on selected N-type epitaxial silicon substrate or district's fuse piece, define active area, growth place oxide layer；According to terminal structure and the design of active area unit cell, optionally define deep p-well or do not do this step；Lithographic trenches figure, dry etching silicon substrate, this groove defines active region gate groove and the transition region groove for isolation simultaneously, and the present invention lists the different figures designed for trench isolations and unit cell, specifically refers to shown in Fig. 1 to Figure 16.
Growth grid oxic horizon, the polycrystalline silicon material that deposit is mixed in situ fills groove；Then photoetched grid figure, etches polycrystalline silicon forms the grid of top level structure.Implanting p-type impurity also diffuses to form shallow p-well (P-base) as channel region；Before shallow p-well channel region (P-base) also may be optionally formed on definition groove.Photoetching N-type source region injects N-type impurity；Then the insulant such as deposited oxide layer or silicon nitride densification of annealing, lithography contact hole, etching insulating layer exposes p-well region and the N-type source region silicon face of all cellulars formed before；
Implanting p-type impurity also activates, it is ensured that p-well region and the Ohmic contact of top-level metallic.Sputtering top-level metallic, chemical wet etching top-level metallic, deposit passivation layer, chemical wet etching passivation layer, final alloy completes the making of top level structure；Then silicon chip back side is thinned to specific thickness, back side implanting p-type (or injecting N-type and p-type) impurity forms IGBT collecting zone (or terminating the FS-IGBT of level with field) by process annealing or laser annealing, and then the method deposit back metal by sputtering or evaporation completes the manufacturing process of whole IGBT device.
Claims (2)
1. the manufacture method of a trench IGBT device architecture, it is characterised in that this manufacture method comprises the steps:
A) on selected N-type epitaxial silicon substrate or district's fuse piece, active area is first defined, growth place oxide layer；
B) according to terminal structure and the design of active area unit cell, optionally define deep p-well or do not do this step；
C) lithographic trenches figure, dry etching silicon substrate, this groove defines active region gate groove and for isolating the transition region groove of invalid active area simultaneously；
D) growth grid oxic horizon, the polycrystalline silicon material that deposit is mixed in situ fills groove；Then photoetched grid figure, etches polycrystalline silicon forms the grid of top level structure；
E) implanting p-type impurity diffuse to form shallow p-well as channel region；Before shallow p-well channel region also may be optionally formed on definition groove；Photoetching N-type source region injects N-type impurity；Then the insulant such as deposited oxide layer or silicon nitride densification of annealing, lithography contact hole, etching insulating layer exposes p-well region and the N-type source region silicon face of all cellulars formed before；Implanting p-type impurity also activates, it is ensured that p-well region and the Ohmic contact of top-level metallic；
F) sputtering top-level metallic, chemical wet etching top-level metallic, deposit passivation layer, chemical wet etching passivation layer, final alloy completes the making of top level structure；
G) then silicon chip back side is thinned to specific thickness, back side implanting p-type or inject N-type and p type impurity, form IGBT collecting zone by process annealing or laser annealing or terminate the FS-IGBT of level with field, completing the manufacturing process of whole IGBT device finally by the method deposit back metal sputtered or evaporate.
The manufacture method of trench IGBT device architecture the most according to claim 1, it is characterised in that this manufacture method is to utilize transition region groove and the design of deep p-well to isolate invalid active area and effective channel region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610215399.4A CN105938798A (en) | 2016-04-08 | 2016-04-08 | Manufacturing method of trench IGBT device structure |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610215399.4A CN105938798A (en) | 2016-04-08 | 2016-04-08 | Manufacturing method of trench IGBT device structure |
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| CN105938798A true CN105938798A (en) | 2016-09-14 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110875309A (en) * | 2019-07-29 | 2020-03-10 | 上海道之科技有限公司 | Groove IGBT device structure with built-in current sensor and manufacturing method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009043782A (en) * | 2007-08-06 | 2009-02-26 | Toshiba Corp | Semiconductor device and manufacturing method thereof |
| CN203134807U (en) * | 2012-11-23 | 2013-08-14 | 中国科学院微电子研究所 | Insulated gate bipolar transistor |
| CN104332492A (en) * | 2013-07-22 | 2015-02-04 | 三星电子株式会社 | Semiconductor device and method for fabricating the same |
| CN104835735A (en) * | 2015-05-07 | 2015-08-12 | 嘉兴斯达微电子有限公司 | Trench IGBT device manufacturing method |
-
2016
- 2016-04-08 CN CN201610215399.4A patent/CN105938798A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009043782A (en) * | 2007-08-06 | 2009-02-26 | Toshiba Corp | Semiconductor device and manufacturing method thereof |
| CN203134807U (en) * | 2012-11-23 | 2013-08-14 | 中国科学院微电子研究所 | Insulated gate bipolar transistor |
| CN104332492A (en) * | 2013-07-22 | 2015-02-04 | 三星电子株式会社 | Semiconductor device and method for fabricating the same |
| CN104835735A (en) * | 2015-05-07 | 2015-08-12 | 嘉兴斯达微电子有限公司 | Trench IGBT device manufacturing method |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110875309A (en) * | 2019-07-29 | 2020-03-10 | 上海道之科技有限公司 | Groove IGBT device structure with built-in current sensor and manufacturing method |
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Application publication date: 20160914 |