DE102009008714B4 - Semiconductor device of the trench gate type - Google Patents

Abstract

A trench-gate type semiconductor device comprising: a first semiconductor layer (101) having a first conductivity type and formed on a semiconductor substrate; a second semiconductor layer (102, 103) having a second conductivity type and disposed adjacent to the first semiconductor layer (101); a third semiconductor layer (104) having the first conductivity type and disposed adjacent to the second semiconductor layer (103); a plurality of insulated gates (105) extending from a first main surface of the third semiconductor layer (104) into the second semiconductor layer (103), penetrating the third semiconductor layer (104); a first region and a second region (115) of the third semiconductor layer (104) each defined between the adjacent isolated gates (105); a fourth semiconductor layer (111) having the second conductivity type and in contact with the insulated gates (105) in the first region of the third semiconductor layer (104); a first main electrode (109) in electrical contact with the first region of the third semiconductor layer (104) and the fourth semiconductor layer (111); and a second main electrode (100) in electrical contact with the first semiconductor layer (101), wherein the third semiconductor layer in the second region (115) is a floating layer, and the floating layer is electrically connected to the first main electrode (109) via a capacitance ( 206) which is an insulating layer (121) of silicon oxide interposed between the second regions of the third semiconductor layer (104) and a polycrystalline silicon layer (122) in contact with the first main electrode (109), and wherein a short-circuit Resistor 207) is connected in parallel with the capacitance.

Description

The invention relates to the structure of a semiconductor device with trench gates.

An insulated gate bipolar transistor (hereinafter referred to as IGBT) is a switching element in which the current flowing between the collector and emitter electrodes is controlled by a voltage applied to a gate electrode.

This switching element can control power of several tens to several 100,000 watts and a switching frequency of several tenths of Hz to several 100 kHz. Being capable of a very cold control range, it finds a variety of applications from low power domestic appliances such as air conditioners and microwave ovens to high power facilities such as inverters for use in rail vehicles and steel mills.

The power loss is one of the most important operating factors of the IGBT. Recently, trench-gate type IGBTs have emerged because their power loss is relatively small. The feature of the IGBT structure is that the gate electrode is embedded in a silicon substrate.

In the basic configuration, a p-type collector layer, an n-type low resistivity buffer layer, and a high resistivity n-type drift layer are formed on the silicon substrate in the order named, and a p-type collector layer. Type-base layer is formed on the exposed surface of the drift layer.

A plurality of grooves having the same planar shape of a strip are buried in the p-type base layer. In the grooves, trench gate electrodes made of polycrystalline silicon are provided, the trench gate electrodes being isolated from the silicon substrate by means of insulating films. Consequently, the side walls of the trench gate electrodes serve as MOS channels.

The trench-gate type IGTB has more gate electrodes per unit area than a planar gate-type IGBT of which the gate electrodes are formed on the surface of the silicon substrate. Consequently, the trench gate type IGBT can be provided with more channels than the planar gate type IGBT, so that the channel resistance can be made low, resulting in a small power loss. He also has a lower ON-voltage, d. That is, a lower voltage generated between the collector and the emitter during the conduction state than the planar gate type IGBT.

The JP 2000-307116 A discloses a Trech-gate type IGBT in which the trench gate electrodes are arranged at two different intervals to lower the power loss during the conduction state. According to this conventional technique, no channel is formed between the two gates having the larger interval, and only one p-type layer (FP layer) is kept floating, ie, all of the gate electrodes, emitter electrodes, and collector Electrodes isolated while a channel is formed between the two gates, which have a narrower interval.

With this configuration, the breakdown of the switching element due to excessive current can be prevented, line losses can be reduced, and the ON voltage can be lowered.

With the configuration described above, the FP layer is kept in the floating state, and therefore, the collector-gate capacitance becomes large.

To solve this problem, the JP-2004-39838 A a configuration in which the FP layer is electrically connected to an emitter electrode through a resistor having an electrical resistance of at least 100 Ω.

This conventional technique enables the collector-gate capacitance to be reduced, and the hole current flowing into the emitter electrode to be limited by the resistor, so that the FP layer is kept in the quasi-floating state ,

According to the configuration described above, the FP layer is electrically connected to the emitter electrode through a resistor having an electrical resistance of at least 100 Ω. However, the present inventors have found that the ON voltage is higher in this case than in the case where the FP layer is isolated from the emitter electrode.

The JP 2005-032941 A is directed to providing an insulated gate semiconductor device in which the gate-collector capacitance is reduced without hindering an ON voltage, which is caused by an injection-enhancing effect. For this purpose, an insulating layer having a thickness equal to or larger than the one gate insulating layer and thinner than an interlayer insulating layer covering a gate electrode is formed on the surface of a floating p-type region. An emitter potential region at which a Emitter potential is applied is formed over it, so that a relatively large capacitance between the floating p-region and an emitter electrode is formed. The capacitance converts a majority of the gate-collector capacitance into a collector-emitter capacitance and a gate-emitter capacitance, thereby reducing the effective gate-collector capacitance.

The JP 2004-039838 A is directed to providing a trench-gate type semiconductor device having a small parasitic capacitance. For this purpose, the semiconductor device comprises a first semiconductor layer having a first conductivity type, a second semiconductor layer having a second conductivity type adjacent to the first semiconductor layer, a third semiconductor layer having the first conductivity type adjacent to the second semiconductor layer, a plurality of insulated gates, penetrating the third semiconductor layer to the second semiconductor layer, a fourth semiconductor layer of the second conductivity type adjacent to the insulated gates, a first main electrode electrically connected to the third and fourth semiconductor layers, and a second main electrode electrically connected to the first first main conductor layer is connected. A floating p-layer is electrically connected to the first main electrode via a resistor. The floating layer does not make direct contact with the electrodes and is connected to the emitter electrode via the short circuit resistor.

It is therefore an object of this invention to provide a trench-gate type semiconductor device having a low ON voltage and a small parasitic capacitance while preventing the IGBT from malfunctioning.

For this purpose, a trench-gate type semiconductor device having the features of claim 1 is provided. The claim 2 characterizes an advantageous embodiment of claim 1.

Brief description of the drawings

1 Fig. 12 is a cross-sectional view of the structure of a trench-gate type semiconductor device according to a first embodiment of this invention;

2A - 2D show equivalent circuits of trench-gate type semiconductor devices, in which Figs 2A . 2C and 2D conventional semiconductor devices and 2 B shows a semiconductor device according to a first embodiment of this invention;

3 Fig. 12 is a plan view showing the detailed structure of the trench gate type semiconductor device according to a second embodiment of this invention;

4 Fig. 10 is an enlarged cross-sectional view of the structure of the trench gate type semiconductor device according to the second embodiment of this invention;

5 FIG. 12 is a cross-sectional view of the structure of the trench gate type semiconductor device according to the second embodiment of this invention; FIG.

6 shows an equivalent circuit of a third embodiment of this invention and

7 shows a block diagram of a fourth embodiment of this invention.

Embodiment 1

1 FIG. 10 shows a cross section of the structure of a trench-gate type semiconductor device as a first embodiment of this invention. FIG. The trench-gate type semiconductor device includes a collector electrode 100 ; a p-type collector layer 101 ; an n-type buffer layer 102 ; an n-type drift layer 103 ; a p-type base layer 104 ; Gate electrodes 105 ; Gate insulating films 106 ; insulating films 107 ; an emitter electrode 109 ; p-type contact layers 110 ; n-type emitter layers 111 ; a gate connection 112 ; an emitter terminal 114 ; floating layers 115 (hereinafter referred to as FP layers); insulating films 121 that has an electrostatic capacity between the FP layers 115 and the emitter electrode 109 form; polycrystalline silicon layers 122 and a collector connection 116 ,

The collector electrode 100 is electrically connected to a first semiconductor layer of a first conductivity type, for example the p-type collector layer 101 , which is formed in an end surface of a semiconductor substrate. A second semiconductor layer of a second conductivity type, for example an n-type semiconductor layer, is on the collector layer 101 educated. In this embodiment, the second semiconductor layer is made of the n-type buffer layer 102 , and the n-type drift layer 103 is on the n-type buffer layer 102 and has a lower impurity or doping concentration than the n-type buffer layer 102 , A third semiconductor layer of the first conductivity type, for example the p-type base layer 104 is on the n-type drift layer 103 educated.

Each of the plurality of gate electrodes 105 extends from a major surface of the p-type base layer 104 into the n-type drift layer 103 where it is the p-type base layer 104 penetrate. The outer circumference of the gate electrode 105 is with the gate insulation film 106 covered.

The isolation film 107 is on the main surface of the base layer 104 arranged. The base layer 104 is through a variety of gate electrodes 105 divided into first and second areas. A fourth semiconductor layer of the second conductivity type, for example, the n-type emitter layer 111 , is in contact with the gate electrode 105 in a part of the base layer 104 formed belonging to the first area. The emitter electrode 109 is with the n-type emitter layer 111 and further with the base layer 104 via a p-type contact layer 110 connected. Accordingly, a conduction channel between the two gate electrodes 105 educated. On the other hand, part of the base layer 104 belonging to the second area, the floating layer 115 (hereinafter referred to as FP layer) which is not connected to any electrode at all but to the emitter electrode 109 connected via the capacitance coming out of the insulation film 121 and the polycrystalline silicon layer 122 is formed. The gate electrode 105 , the emitter electrode 104 and the collector electrode 100 have in gate connection 112 , the emitter connection 114 or the collector connection 116 ,

The gate insulation film 106 and the insulation film 121 which serve as electrostatic capacitance can be formed by a thermal oxidation method. Furthermore, the gate electrode 105 and the polycrystalline silicon layer 122 deposited according to the same film forming process and then partially etched, so that the structure can be prepared as shown in 1 is shown. When these oxidation, film formation and etching steps are carried out in the same procedure, an advantage in terms of cost can be obtained.

The isolation film 107 is usually prepared by a chemical vapor deposition (CVD = Chemical Vapor Deposition) process. An oxide film produced by CVD has a lower withstand voltage than a thermal oxidation film. Therefore, usually the CVD oxide film 107 have a thickness of at least 500 nm (5000 Å) to provide a sufficient gate-emitter withstand voltage. If the insulation film is thicker, the electrostatic capacity is smaller. Then, the use of the insulating film generates 107 as capacity between the FP layer 115 and the emitter electrode 104 an increase in impedance, so that the effect of the short circuit with the electrostatic capacity becomes small.

The thickness of the gate insulation film 106 That is, the oxide film is about 50-150 nm (500-1500 Å). The actual growth rate of a thermal oxidation film is in the range of 0.75 to 1.3 times a mean oil speed depending on the plane orientation. Thus, the thickness of the gate oxidation film 106 be different from that of the insulating film 121 because the plane orientation of the surface of the trench gate is usually different from that of the major surface. However, when the thickness of the gate oxidation film 106 and the plane orientation of the trench can be appropriately selected, the insulating film can 121 and the gate oxidation film 106 be simultaneously thermally oxidized, so that the thickness of the insulating film 121 not more than 150 nm (1500 Å).

The operation of this invention will now be described with reference to 1 described. First, a voltage of several tenths to several thousand volts between the collector terminal 116 and the emitter terminal 114 applied, and then a voltage of about 15 V between the gate terminal 112 and the emitter terminal 114 created. This voltage of 15 V, connected to the gate terminal 112 is applied to the the gate electrode 105 and then forms an inversion layer at the boundary regions between the base layer 104 and the gate insulation layer ( 106 ) and between the FP layer 115 and the gate insulation layer 106 , The Inverstionsschicht, in the base layer 104 is formed, connects the emitter layer 111 with the drift layer 103 to form a duct.

Electrons are from the emitter layer 111 in the drift layer 103 injected through the duct. The injected electrodes in turn assist in the injection of positive holes from the collector layer 101 , The of the collector layer 101 injected holes flow through the drift layer 103 and the base layer 104 into the emitter electrode 109 ,

Part of the hole current passes through the FP layer 115 through and is charged into the capacitance coming out of the insulation film 121 that is between the FP layer 115 and the emitter electrode 104 is arranged, formed.

However, in the steady state, that is, in the state where the capacitance is fully charged, the FP layer is 115 and the emitter layer 109 isolated from each other.

As described above, in the ON / OFF transient state of the IGBT, a low impedance between the FP layer becomes 115 and the emitter electrode 109 achieved by the capacity effect thereof. Accordingly, the FP layer 115 and the emitter electrode 104 electrically connected to each other to increase the collector-gate capacitance reduce, as in the structure of the conventional semiconductor device, in JP 2004-39838 A is disclosed.

On the other hand, in the stable state, where the capacitance between the FP layer 115 and the emitter electrode 104 is sufficiently charged, a high impedance between the FP layer 115 and the emitter electrode 109 receive. Accordingly, the FP layer becomes 115 held in the floating state as in the structure of the conventional semiconductor device used in JP 2000-307116 A is disclosed. As a result, positive holes are prevented from coming from the inside of the drift layer 103 to escape, and they are therefore in the drift layer 103 accumulated so that the ON voltage of the IGBT is lowered. This feature acts to have this embodiment a low ON voltage in the steady state, while this feature provides the effect of reducing the collector gate capacitance in the ON / OFF transient state.

The 2A . 2C and 2D show the equivalent circuits of conventional trench-gate type semiconductor devices and 2 B shows the equivalent circuit of a trench-gate type semiconductor device according to an embodiment of the invention. In the conventional trench-gate type semiconductor device used in JP 2000-307116 is disclosed, the FP layer 115 belonging to the second area, not electrically connected to the adjacent element, that is, it is electrically floating. Accordingly, the equivalent circuit is as in 2D is shown.

The equivalent circuit used in 2D shown includes an IGBT 200 , a collector-emitter capacitance Cce 201 , a collector gate capacitance Ccg 202 , a gate-emitter capacitance Cge 203 , a capacity Cfd 204 between the FP layer and the drift layer and a capacitance Cgf 205 between the gate and the FP layer.

In the equivalent circuit in 2D , the IGBT is shown symbolically for the sake of simplicity, and the parasitic capacitances are connected to the symbolic IGBT. Because in this structure, by the in 2D is shown holding the FP layer in the floating state, the collector gate capacitance becomes large. The reason for this is described below.

In addition, when an FP layer is present, the capacitance Cgf between the gate and the FP layer and the capacitance Cfd between the FP layer and the drift layer contribute to a feedback capacitance, so that the collector-gate capacitance increases. The rise in the collector-gate capacitance Ccg causes an increase in the parasitic current flowing through the collector-gate capacitance Ccg due to the sudden collector voltage change (dv / dt) occurring when the IGBT turns off. As a result, there occurs a possibility that the parasitic current flowing into the gate terminal causes the IGBT to be turned on in a malfunction.

In order to prevent this malfunction of the IGBT, the gate resistors connected to the gate terminals in the inverter using the IGBTs must have a low resistance value. However, a decrease in the resistance of the gate resistor causes an increase in the gate current. This requires the use of a gate driver circuit having a large current capacity, and hence the entire inverter becomes large in size and weight.

Further, when a large noise influence takes place between the collector and the emitter of the IGBT, a parasitic current flows into the gate through the collector-gate capacitance Ccg, causing the IGBT to malfunction. To prevent this malfunction, there is a need for additional components for noise reduction, such as noise filters. These additional components increase the size, weight, and cost of production of the inverter.

Further, an electric vehicle system using such a large-sized inverter can suffer not only from the size of the construction and the heavy weight, resulting in a short range of uninterrupted driving, but also by increasing the manufacturing cost of the entire system.

On the other hand, the conventional trench-gate type semiconductor device used in JP 2004-39838 A discloses a short circuit resistance 207 that is between the FP layer 115 and the emitter electrode 109 connected as in 2C is shown. Accordingly, when a high voltage is suddenly applied between the collector and the emitter of the transistor, the parasitic current that would otherwise cause a malfunction is caused by the short circuit resistance 207 diverted to the emitter without flowing into the gate, so that the malfunction can be prevented.

However, since the hole current through the short circuit resistance 207 flows into the emitter, this semiconductor device has a larger hole concentration in the drift layer 103 and therefore a higher ON-voltage than the semiconductor device used in the JP 2000-307116 A discloses where the FP layer 115 from the emitter electrode 109 is isolated.

The conventional component has, as in 2A shown is a capacity 206 that the insulating film 121 is that between the FP layer 115 and the emitter electrode 109 is provided. As a result, even if a high voltage is suddenly applied between the collector and the emitter of the transistor, the parasitic current that might otherwise cause a malfunction becomes in the capacitance 206 charged so that the parasitic current is prevented from flowing into the gate. This can prevent the malfunction.

Embodiment 2

3 shows a plan view of a semiconductor device according to a second embodiment of this invention. For easier understanding of the structure, the emitter electrode 109 in 3 omitted. The isolation film 107 is also omitted, and only the contact holes are indicated by broken lines. The cross sections along the dot-dash lines A-A ', BB' and CC 'in 3 correspond to the 1 . 4 respectively. 5 , In 3 to 5 are the same components by the same reference numbers as in the 1 and 2 designated.

In 3 are a first contact 300 , a second contact 301 , a p-type well layer 302 and a third contact 303 shown. This second embodiment is characterized in that the FP layer 115 electrically with the emitter electrode 109 about the capacity passing through the insulation film 121 is shown, and connected to a resistor which is connected in parallel with the capacitance.

Because the FP layer 115 is usually formed by diffusion of impurities, it has a specific resistance. In many cases, the resistivity becomes a sheet resistance value of tens to hundreds of ohms (Ω). This sheet resistance is called short-circuit resistance 207 used.

The equivalent circuit of this embodiment is shown in FIG 2 B shown. As in 2 B shown are the FP layer 115 and the emitter electrode 109 to each other by a parallel connection of the capacity 206 and in short-circuit resistance 207 electrically connected. Accordingly, in the ON / OFF transient state of the IGBT, even if the resistance value of the resistor 207 is made larger than that in the conventional component used in 2C shown is the resulting impedance resulting from the resistor 207 and the capacity 206 is comparable to the corresponding impedance in the conventional device disclosed in US Pat 2C is shown. Therefore, the voltage applied to the gate can be similarly stabilized.

On the other hand, in the stable state, since the short-circuit resistance 207 which has a large resistance value, to an increase in the impedance between the FP layer 115 and the emitter electrode 109 leads, the resulting impedance be higher than the corresponding impedance in the conventional component, which in 2C is shown. As a result, more holes are accumulated in the drift layer, so that the ON voltage becomes lower.

Embodiment 3

6 Fig. 10 is a circuit diagram of a semiconductor device according to a third embodiment of this invention. In 6 are shown gate driver circuits 1700 , a first input terminal 1701 , a second input port 1702 , IGBT's 1703 , Diodes 1704 and first to third output terminals 1705 to 1707 , This third embodiment of the invention is characterized in that such IGBTs as described in the first and second embodiments of this invention are applied to an inverter.

The IGBTs used in the third embodiment of this invention have a small collector-gate capacitance, so that conduction as a malfunction due to steep transition dv / dt rarely takes place. Accordingly, there is an advantage that the gate current can be reduced, and the gate drive circuits each having a small capacitance can be employed. Further, since each gate driver circuit can be made small in size, an additional advantage can be obtained in which the overall size, and hence the production cost of the inverter, can be reduced.

Embodiment 4

7 shows a block diagram of a fourth embodiment of this invention. In 7 are shown a battery 1000 , an inverter 1001 , an electric motor 1002 , a gearbox 1003 , Bikes 1004 a vehicle and waves 1005 ,

The operation of the system, which in 7 is shown below. An electric current coming from the battery 1000 is supplied by the inverter 1001 controlled, and the controlled current becomes an electric motor 1002 fed to the engine 1002 drive. A torque caused by the rotation of the engine 1002 is generated, is about the shaft 1005 to the gearbox 1003 transfer. The gear 1003 distributes the torque to the left and right wheels 1004 ; the speed of the motor is downshifted to turn the wheels at a suitable rotational speed; and the vehicle is moving. This fourth embodiment of the present invention is characterized in that trench-gate type semiconductor devices are connected to the inverter 1001 an electric car. The trench-gate type semiconductor device according to this invention has the advantages that (1) it is resistant to noises, so that the size of the noise filter to be used can be made small, and (2) the gate Current is small, so the size of the gate driver to be used can be made small. Accordingly, this embodiment contributes to the reduction in size and weight of the electric automobile.

There is another advantage that reducing the weight of the electric car increases range and also makes power consumption economical. There is the further advantage that, since the sizes of the noise filter and the gate driver can be made smaller, the production cost of the inverter and therefore that of the electric car can be made lower.

In this embodiment, the advantages will be described in the case where the trench gate type semiconductor device according to this invention is applied to an electric car. However, the invention can be applied not only to electric cars but also to any other devices including at least one inverter.

For example, when the trench gate type semiconductor device according to this invention is applied to a hybrid automobile in which an internal combustion engine and an engine / inverter system are combined, such advantages can be improved as fuel consumption and reduction of fuel consumption Production costs are achieved due to the reduction in size and weight as in the case of an electric automobile described above. Furthermore, similar advantages can be obtained when the invention is applied to railway vehicles.

Claims (2)

A semiconductor device of the trench gate type comprising: a first semiconductor layer ( 101 ) having a first conductivity type and formed on a semiconductor substrate; a second semiconductor layer ( 102 . 103 ), which has a second conductivity type and which is adjacent to the first semiconductor layer ( 101 ) is arranged; a third semiconductor layer ( 104 ) which has the first conductivity type and which is adjacent to the second semiconductor layer ( 103 ) is arranged; a variety of isolated gates ( 105 ) extending from a first major surface of the third semiconductor layer ( 104 ) in the second semiconductor layer ( 103 ), wherein the third semiconductor layer ( 104 penetrate); a first area and a second area ( 115 ) of the third semiconductor layer ( 104 ), each between the adjacent, isolated gates ( 105 ) are defined; a fourth semiconductor layer ( 111 ), which has the second conductivity type and which is in contact with the isolated gates ( 105 ) in the first region of the third semiconductor layer ( 104 ) stands; a first main electrode ( 109 ) in electrical contact with the first region of the third semiconductor layer ( 104 ) and the fourth semiconductor layer ( 111 ); and a second main electrode ( 100 ) in electrical contact with the first semiconductor layer ( 101 ), wherein the third semiconductor layer in the second region ( 115 ) is a floating layer, and the floating layer is electrically connected to the first main electrode ( 109 ) have a capacity ( 206 ), which is an insulation layer ( 121 ) is made of silicon oxide, which between the second regions of the third semiconductor layer ( 104 ) and a polycrystalline silicon layer ( 122 ) in contact with the first main electrode ( 109 ), and wherein a short circuit resistance 207 ) is connected in parallel with the capacity. A trench-gate type semiconductor device according to claim 1, wherein the resistance of the short-circuit resistance ( 207 ) is at least not less than 100 Ω.

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