JP5235443B2 - Trench gate type semiconductor device - Google Patents

Description

  The present invention relates to a structure of a semiconductor device having a trench gate.

  An insulated gate bipolar transistor (hereinafter abbreviated as IGBT) is a switching element that controls a current flowing between a collector electrode and an emitter electrode by a voltage applied to the gate electrode.

  The power that can be controlled is from several tens of watts to several hundred thousand watts, and the width of the switching frequency ranges from several tens of hertz to one hundred kilohertz. Taking advantage of this feature, it is widely used from small household appliances such as air conditioners and microwave ovens to large electric appliances such as inverters for railways and steelworks.

  One of the most important performances of an IGBT is loss. In recent years, trench gate type IGBTs have attracted attention for reducing loss. The trench gate type IGBT has a structure in which a gate electrode is embedded in a silicon substrate.

  The basic configuration is that a p-type collector layer, a low-resistance n-type buffer layer, and a high-resistance n-type drift layer are formed on a silicon substrate, and a p-type base layer is formed on the exposed surface side of the drift layer. It is a thing.

  In the p-type base layer, a plurality of grooves having the same shape, whose planar shape is a stripe shape, are dug. In this trench, a trench gate electrode made of polycrystalline silicon is provided in a state insulated from the silicon substrate by an insulating film. Therefore, the sidewall of the trench gate electrode has a structure serving as a MOS channel.

  The trench gate type IGBT can form a larger number of gate electrodes in the same area than the planar gate type IGBT in which the gate electrode is formed on the surface of the silicon substrate. For this reason, the number of channels can be increased, the channel resistance is low, and the loss is small. In addition, the on-voltage, that is, the voltage generated between the collector and the emitter during conduction is lower than that of the conventional planar IGBT.

  Japanese Patent Laid-Open No. 2000-307116 discloses a structure for reducing loss by changing the arrangement pitch of trench gate electrodes. In this prior art, a channel is not formed in a portion where the pitch between the gates is wide, and only the p layer [FP layer] is in a floating state, that is, it is electrically connected to any of the gate electrode, the emitter electrode, and the collector electrode. A structure in which a channel is formed only at a narrow pitch is disclosed.

  According to such a configuration, it is possible to prevent element destruction due to overcurrent and reduce conduction loss and on-voltage.

  Although the floating FP layer is provided in the above structure, the collector-gate capacitance increases.

  For this problem, Japanese Patent Application Laid-Open No. 2004-39838 discloses a structure in which the FP layer is electrically connected to the emitter electrode through a resistance of at least 100Ω or more.

  According to this prior art, the collector-gate capacitance can be reduced, and the hole current flowing through the emitter electrode is limited by the resistance, so that the FP layer becomes close to a floating state.

JP 2000-307116 A JP 2004-39838 A

  In the above-described structure, the FP layer and the emitter electrode are electrically connected via a resistance of at least 100Ω. However, as a result of investigation by the inventors, the FP layer is insulated from the emitter electrode. It turns out that the on-voltage increases.

  Accordingly, an object of the present invention is to provide a trench gate type semiconductor device having a low on-voltage and a low parasitic capacitance.

  A semiconductor device of the present invention includes a first conductive type first semiconductor layer formed on a semiconductor substrate, a second conductive type second semiconductor layer adjacent to the first semiconductor layer, and the second semiconductor layer. An adjacent first conductive type third semiconductor layer; a plurality of insulated gates that penetrate the third semiconductor layer from one main surface of the third semiconductor layer and reach the second semiconductor layer; and the adjacent insulated gates A first region and a second region adjacent to each other, and a second conductivity type fourth semiconductor layer in contact with the insulated gate in the third semiconductor layer in the first region; A first main electrode electrically connected to the third semiconductor layer and the fourth semiconductor layer in the first region; a second main electrode electrically connected to the first semiconductor layer; The third semiconductor layer in the region is electrically connected to the first main electrode through a capacitor. It is a trench gate type semiconductor device according to claim being connected.

  At this time, it is preferable that the capacitor is formed of an oxide film having a thickness of 1500 mm or less sandwiched between the third semiconductor layer and the polycrystalline silicon layer in contact with the first main electrode in the second region. Further, the third semiconductor layer in the above-described second region may be electrically connected to the first main electrode through the capacitor and a resistor connected in parallel with the capacitor.

  As described above, by connecting the floating p layer (FP layer) to the emitter electrode through a capacitor, a low on-voltage and a reduction in collector-gate capacitance can be realized at the same time, and erroneous firing of the IGBT can be prevented. The capacity of the gate driver can be reduced, noise countermeasures can be eliminated or reduced, and the inverter can be reduced in size, weight and cost.

Example 1
FIG. 1 shows a cross-sectional structure diagram of a trench gate type semiconductor device of this embodiment. The semiconductor device of this embodiment includes a collector electrode 100, a p-conducting collector layer 101, an n-conducting buffer layer 102, an n-conducting drift layer 103, a p-conducting base layer 104, a gate electrode 105, and gate insulation. Film 106, insulating film 107, emitter electrode 109, p-conducting contact layer 110, n-conducting emitter layer 111, gate terminal 112, short-circuit resistor 207, emitter terminal 114, floating layer 115 (hereinafter abbreviated as FP layer), An insulating film 121, a polycrystalline silicon 122, and a collector terminal 116 constituting a capacitance between the FP layer 115 and the emitter electrode are provided.

  The collector electrode 100 is electrically connected to a first conductivity type first semiconductor layer formed on one end of the semiconductor substrate, for example, a p conductivity type collector layer 101. A second conductivity type second semiconductor layer, for example, an n conductivity type semiconductor layer, is provided adjacent to the collector layer 101. In the embodiment, this semiconductor layer is composed of an n + conductivity type buffer layer 102 and an n− conductivity type drift layer 103 adjacent to the buffer layer 102 and having an impurity concentration lower than that of the buffer layer 102. A first conductivity type third semiconductor layer, for example, a p conductivity type base layer 104 is provided adjacent to the drift layer 103.

  A plurality of gate electrodes 105 are provided that penetrate the base layer 104 from one main surface of the p-conductivity type base layer 104 and reach the drift layer 103 that is an n-type semiconductor layer. The outer periphery of the gate electrode 105 is covered with a gate insulating film 106.

  An insulating film 107 is provided on the main surface of the base layer 104. The base layer 104 is divided into a first region and a second region by a plurality of gate electrodes 105. In the base layer 104 belonging to the first region, a second conductive type fourth semiconductor layer in contact with the gate electrode 105, for example, an n conductive type emitter layer 111 is formed. The emitter electrode 109 is connected to the n conductivity type emitter layer 111 and is also connected to the base layer 104 via the p conductivity type contact layer 110. As a result, a channel is formed between the two gate electrodes 105. On the other hand, the base layer 104 belonging to the second region is a floating layer 115 (hereinafter abbreviated as FP layer) that is not directly connected to any electrode, and the emitter electrode 109 is connected via the capacitor made of the insulating film 121 and the polycrystalline silicon 122. Connect to. The gate electrode 105, the emitter electrode 109, and the collector electrode 100 include a gate terminal 112, an emitter terminal 114, and a collector terminal 116, respectively.

  The gate insulating film 106 and the insulating film 121 constituting the capacitor may be formed by the same thermal oxidation process. Alternatively, the gate electrode 105 and the polycrystalline silicon 122 may be deposited in the same film formation process and partially etched to have the configuration shown in FIG. It is advantageous in cost to make these oxidation, film formation, and etching processes the same.

  The insulating film 107 is generally formed by CVD. Since the oxide film formed by CVD has a lower withstand voltage than the thermal oxide film, it is generally set to 5000 mm or more in order to ensure the withstand voltage between the gate and the emitter. Since the capacitance decreases when the thickness of the insulating film is large, when the insulating film 107 is used for the capacitance between the FP layer 115 and the emitter electrode 109, the impedance increases and the effect of short-circuiting the capacitance is reduced.

  The thickness of the gate oxide film 106 is about 500 to 1500 mm. Since the growth rate of the thermal oxide film has a plane orientation dependency of about 0.75 to 1.3 times, the thicknesses of the gate oxide film 106 and the insulating film 121 are not the same depending on the plane orientation of the trench gate and the main surface. However, the thickness of the insulating film 121 can be reduced to 1500 mm or less by thermally oxidizing the insulating film 121 simultaneously with the gate oxide film 106 by selecting the film thickness and the plane orientation of the gate oxide film 106.

  Next, the operation of this embodiment will be described with reference to FIG. First, a voltage of about several tens to several thousand volts is applied between the collector terminal 116 and the emitter terminal 114, and then a voltage of about 15 volts is applied between the gate terminal 112 and the emitter terminal 114. The 15 volts applied to the gate terminal 112 is transmitted to the gate electrode 105 and forms an inversion layer at the boundary between the base layer 104 and the FP layer 115 and the gate insulating film 106. The inversion layer formed in the base layer 104 electrically connects the emitter layer 111 and the drift layer 103 to form a channel.

  Through this channel, electrons are injected from the emitter layer 111 into the drift layer 103, and these electrons prompt the injection of holes from the collector layer 101. Holes injected from the collector layer 101 pass through the drift layer 103, pass through the base layer 104, and flow into the emitter electrode 109.

  A part of the hole current passes through the FP layer 115 and is charged into a capacitor composed of the insulating film 121 between the FP layer 115 and the emitter electrode 109.

  However, when the charging of the capacitor is completed, that is, in a steady state, the FP layer 115 and the emitter electrode 109 are insulated.

  As described above, due to the effect of the capacitance between the FP layer 115 and the emitter electrode 109, the impedance between the FP layer 115 and the emitter electrode 109 becomes low in the on / off transition state of the IGBT. Thus, the collector-gate capacitance can be reduced because the FP layer 115 and the emitter electrode 109 are electrically connected in the same manner as the structure of the semiconductor device of the prior art described in JP-A-2004-39838.

  On the other hand, in a steady state in which the capacitance between the FP layer 115 and the emitter electrode 109 is sufficiently charged, the FP layer 115 is described in Japanese Patent Application Laid-Open No. 2000-307116 because the impedance between the FP layer 115 and the emitter electrode 109 is high. As in the structure of the conventional semiconductor device, the semiconductor device is in a floating state, and the holes are accumulated in the drift layer so that the holes do not escape from the drift layer, and the on-voltage is lowered. As a result, this embodiment has a low ON voltage in the steady state. On the other hand, in the on / off transition state, there is an effect of reducing the collector-gate capacitance.

  FIGS. 2A and 2B are equivalent circuit diagrams of cross-sectional structures of the present embodiment and a conventional apparatus, respectively. The conventional device described in Japanese Patent Laid-Open No. 2000-307116 has a structure in which the FP layer 115 in the second region is not connected anywhere. Therefore, the equivalent circuit is represented as shown in FIG.

  FIG. 2 (d) is an equivalent circuit, and includes IGBT 200, collector-emitter capacitance Cce201, collector-gate capacitance Ccg202, gate-emitter capacitance Cge203, FP layer-drift interlayer capacitance Cfd204, and gate-FP interlayer capacitance Cgf205. It is configured.

  In FIG. 2 (d), an IGBT is represented using symbols for convenience, and an equivalent circuit is shown with a configuration in which parasitic capacitances are connected to the symbols. In this structure, the floating FP layer is provided, but the collector-gate capacitance increases. The reason will be described below.

  If the FP layer is present, the gate-FP interlayer capacitance Cgf and the FP layer-drift interlayer capacitance Cfd are added to the feedback capacitance, and the collector-gate capacitance increases. When the collector-gate capacitance Ccg increases, the parasitic current flowing through the collector-gate capacitance Ccg also increases due to a rapid voltage change (dv / dt) of the collector voltage when the IGBT is turned off, and this current flows into the gate terminal. There is a possibility that the IGBT may falsely fire.

  Therefore, in general, in an inverter using an IGBT, the value of the gate resistance connected to the gate terminal is reduced to prevent false firing. However, if the gate resistance is reduced, the gate current increases, a gate drive circuit having a large capacity must be used, and the inverter becomes large and heavy.

  When a large noise is input between the collector and emitter of the IGBT, a parasitic current flows into the gate through the collector-gate capacitance Ccg, and the IGBT malfunctions. For this reason, noise countermeasure parts such as a noise filter are required, the number of parts increases, the inverter becomes larger, the weight increases, or the manufacturing cost increases.

  Further, when the inverter becomes larger as described above, the electric vehicle system using the inverter becomes larger and heavier, the cruising distance becomes shorter, or the price of the electric vehicle increases.

  On the other hand, in the conventional apparatus described in Japanese Patent Application Laid-Open No. 2004-39838, a short-circuit resistor 206 is provided between the FP layer 115 and the emitter electrode 109 as shown in FIG. Therefore, when a high voltage is suddenly applied between the collector and the emitter, a parasitic current that causes a malfunction is bypassed to the emitter through the short-circuit resistor 207, so that it does not flow into the gate, thereby preventing malfunction.

  However, since the hole current flows to the emitter electrode 109 through the short-circuit resistor 206, the drift layer 103 in the drift layer 103 is compared with the conventional device described in Japanese Patent Laid-Open No. 2000-307116 in which the FP layer 115 is insulated from the emitter electrode 109. The hole concentration decreases and the on-voltage increases.

  On the other hand, in this embodiment, as shown in FIG. 2A, a capacitor made of the insulating film 121 is provided between the FP layer 115 and the emitter electrode 109. Therefore, when a high voltage is suddenly applied between the collector and the emitter, a parasitic current that causes a malfunction does not flow into the gate because the capacitor 206 is charged, and malfunction can be prevented.

(Example 2)
FIG. 3 shows a top view of the semiconductor device of this embodiment. The emitter electrode 109 is omitted for easy understanding of the structure. Further, the insulating film 107 is also omitted, and only the contact holes are indicated by broken lines. 3 corresponds to FIG. 1. FIG. 4 shows a BB ′ cross section in FIG. FIG. 5 shows a cross-section CC ′ in FIG. 3 to 5, the same components as those in FIGS. 1 and 2 are denoted by the same reference numerals.

  In FIG. 3, 300 is a contact, 301 is a contact, 302 is a p conductivity type well layer, and 303 is a contact. The feature of this embodiment is that the emitter electrode 109 of the FP layer 115 is electrically connected by a capacitor made of the insulating film 121 and a resistor connected in parallel thereto.

  The FP layer 115 generally has a specific resistance formed by impurity diffusion. In many cases, this resistor has a sheet resistance value of several tens Ω to several hundreds Ω, and this is used as the short-circuit resistor 207.

  An equivalent circuit of this embodiment is shown in FIG. The FP layer 115 and the emitter electrode 109 are electrically connected by a capacitor 206 and a short-circuit resistor 207 connected in parallel. As a result, in the on / off transition state of the IGBT, the same impedance can be obtained even if the resistance value of the short-circuit resistor 207 is increased as compared with the conventional invention shown in FIG. To stabilize. On the other hand, in a steady state, since the short-circuit resistance 207 is large, the impedance between the FP layer 115 and the emitter electrode 109 is larger than that in the conventional invention shown in FIG. Therefore, the on-voltage becomes smaller.

(Example 3)
FIG. 6 is a circuit diagram of this embodiment. In FIG. 6, the same components as those in FIGS. 1 to 5 are denoted by the same reference numerals. In FIG. 6, 1700 is a gate drive circuit, 1701 is an input terminal, 1702 is an input terminal, 1703 is an IGBT, 1704 is a diode, and 1705 to 1707 are output terminals. The feature of this embodiment is that the IGBT described in Embodiments 1 and 2 is applied to the inverter.

  Since the IGBT used in this embodiment has the smallest collector-gate capacity, dv / dt false firing is unlikely to occur. Therefore, there is an effect that the gate current can be reduced and a gate drive circuit having a small capacity can be used. Further, since the gate drive circuit can be reduced in size, there is an effect that the size of the inverter can be reduced and the price can be reduced.

Example 4
FIG. 7 shows this embodiment. In FIG. 7, 1000 is a battery, 1001 is an inverter, 1002 is a motor, 1003 is a transmission, 1004 is a wheel, and 1005 is a shaft.

  The operation of FIG. 7 will be described. Electric power supplied from the battery 1000 is controlled by the inverter 1001, and the motor 1002 is rotated. The driving force generated by the rotation of the motor 1002 is transmitted to the transmission 1003 via the shaft 1005. The driving force is distributed and shifted between the left and right wheels by the transmission 1003, the vehicle is rotated, and the vehicle body moves.

  A feature of this embodiment is that the trench gate type semiconductor device of the present invention is applied to an inverter 1001 of an electric vehicle. The trench gate type semiconductor device of the present invention is characterized in that (1) it is strong against noise and the noise filter can be reduced, and (2) the gate current is small and the gate driver can be reduced, which is effective in reducing the size and weight of an electric vehicle. .

  Moreover, if it can be lightened, the mileage can be extended and the electricity bill can be saved. Furthermore, the manufacturing cost can be reduced by reducing the noise filter and the gate driver, and the electric vehicle can be provided at low cost.

  In this embodiment, the effect when the trench gate type semiconductor device according to the present invention is applied has been described using an electric vehicle as an example. However, the present invention is not limited to the electric vehicle, and the same effect can be obtained if an inverter is mounted. can get.

  For example, even in a combination system of an internal combustion engine and a motor / inverter such as a hybrid vehicle, when the trench gate type semiconductor device according to the present invention is applied as in the above-described example of the electric vehicle, the fuel consumption is improved by reducing the size and weight and the cost is reduced. The effects such as can be obtained. Similarly, the effect can be obtained even when applied to a railway vehicle.

It is a sectional structure figure of the 1st example. It is an equivalent circuit diagram of a 1st, 2nd Example and the conventional apparatus. It is a plane structure figure of the 2nd example. It is sectional structure drawing of a 2nd Example. It is sectional structure drawing of a 2nd Example. It is the equivalent circuit schematic of a 3rd Example. It is a block diagram of a 4th example.

Explanation of symbols

100 collector electrode 101 collector layer 102 buffer layer 103 drift layer 104 base layer 105 gate electrode 106 gate oxide film 107 insulating film 109 emitter electrode 110 contact layer 111 emitter layer 112 gate terminal 114 emitter terminal 115 floating layer 116 collector terminal 121 insulating film 122 Polycrystalline silicon 200, 1703 IGBT
201 Collector-emitter capacitance Cce
202 Collector-gate capacitance Ccg
203 Gate-emitter capacitance Cge
204 FP layer-drift interlayer capacitance Cfd
205 Gate-FP interlayer capacitance Cgf
206 Capacitance 207 Short-circuit resistance 300, 301, 303 Contact 302 p conductive type well layer 1000 Battery 1001 Inverter 1002 Motor 1003 Transmission 1004 Wheel 1005 Shaft 1100 Polycrystalline silicon gate wiring 1101 Gate wiring 1102 Field oxide film 1103 Polycrystalline silicon diode High-concentration p-type impurity layer (anode layer)
1104 Low concentration n-type impurity layer (cathode layer) of polycrystalline silicon diode
1105 High concentration n-type impurity layer (cathode contact layer) of polycrystalline silicon diode
1106 Contact layer 1700 Gate drive circuit 1701, 1702 Input terminal 1704 Diode 1705, 1707 Output terminal

Claims (2)

A first conductivity type first semiconductor layer formed on a semiconductor substrate, a second conductivity type second semiconductor layer adjacent to the first semiconductor layer, and a first conductivity type adjacent to the second semiconductor layer. A region formed between a third semiconductor layer, a plurality of insulated gates that penetrate the third semiconductor layer from one main surface of the third semiconductor layer and reach the second semiconductor layer, and the adjacent insulated gates; A first region and a second region adjacent to each other; a second semiconductor layer of a second conductivity type in contact with the insulated gate in the third semiconductor layer in the first region; and the first region in the first region. A third main layer electrically connected to the third semiconductor layer and the fourth semiconductor layer; and a second main electrode electrically connected to the first semiconductor layer, the third semiconductor layer in the second region. Is electrically connected to the first main electrode through a capacitor ,
The capacitor is an insulating layer made of a silicon oxide film having a thickness of 1500 μm or less sandwiched between the third semiconductor layer and the polycrystalline silicon layer in contact with the first main electrode in the second region;
The third semiconductor layer in the second region is electrically connected to the first main electrode via the capacitor and a resistor connected in parallel to the capacitor;
The polycrystalline silicon layer and the insulating layer are each divided into a plurality of
The resistor is formed of the third semiconductor layer in the second region, and is in contact with the first main electrode between adjacent polycrystalline silicon layers among the divided polycrystalline silicon layers. Trench gate type semiconductor device. The trench gate type semiconductor device according to claim 1, wherein the resistance is at least 100Ω or more.

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