JP5686507B2 - Trench gate type semiconductor device - Google Patents

Description

  The present invention relates to a trench gate type semiconductor device, and more particularly to a trench gate type semiconductor device suitable for use in an inverter such as an air conditioner or an electric vehicle.

  An insulated gate bipolar transistor (hereinafter abbreviated as IGBT) is a switching element that controls a current flowing between a collector electrode and an emitter electrode by a voltage applied to the gate electrode. The power that can be controlled by the IGBT is several tens of watts to several hundred thousand watts, and the width of the switching frequency ranges from several tens of hertz to one hundred kilohertz.

  IGBTs that make use of this feature are widely used from small household appliances such as air conditioners and microwave ovens to large electric appliances such as inverters for railways and steelworks.

  In recent years, a trench gate type IGBT has attracted attention as a structure for reducing the on-voltage and conduction loss of the IGBT.

  The trench gate type IGBT has a structure in which a gate electrode is embedded in a semiconductor. The basic structure of the trench gate type IGBT is that a p-type collector layer is formed on one surface of a high-resistance n-type drift layer with a low-resistance n-type buffer layer interposed therebetween. A p-type base layer is formed on the other surface of the n-type drift layer. In this p-type base layer, a plurality of trenches (grooves) having the same shape and having a stripe shape are dug. In this trench, a gate electrode formed of polycrystalline silicon is provided in a state of being insulated from the n-type drift layer and the p-type base layer by an insulating film. Therefore, the sidewall of the trench gate electrode has a structure serving as a MOS channel.

  Therefore, more gate electrodes can be formed in the same area than the planar gate type IGBT in which the gate electrode is formed on the silicon substrate surface, and the number of channels can be increased, resulting in low channel resistance and loss. Is small. In addition, the on-voltage, that is, the voltage generated between the collector and the emitter during conduction is lower than that of a conventional planar IGBT.

  With respect to the arrangement of the trench gate electrodes, a structure in which the arrangement pitch of the trench gate electrodes is arranged at equal intervals has been shown in the past. was there.

  In response to this problem, Japanese Patent Application Laid-Open No. 2000-307116 discloses a structure for changing the arrangement pitch of the trench gate electrodes. In this prior art, a channel is not formed at a portion where the pitch between the gates is wide, and only the p layer is in a floating state, that is, in a state where it is not in electrical contact with any of the gate electrode, emitter electrode, and collector electrode. A structure in which a channel is formed only at a narrow pitch is disclosed.

  According to such a configuration, it is possible to prevent element destruction due to overcurrent and reduce conduction loss and on-voltage.

JP 2000-307116 A JP 2004-39838 A

  In the above-described conventional structure, a floating p layer (hereinafter abbreviated as FP layer) in a floating state is provided, but the capacitance between the collector and the gate increases, and noise easily enters the gate.

  For this problem, Japanese Patent Application Laid-Open No. 2004-39838 discloses a structure in which the FP layer is electrically connected to the emitter electrode through a resistance of at least 100Ω or more. According to this prior art, the collector-gate capacitance can be reduced, and the hole current flowing through the emitter electrode is limited by the resistance. Therefore, the FP layer becomes close to a floating state. The on-voltage is increased as compared with the case where the FP layer is insulated from the emitter electrode.

  SUMMARY OF THE INVENTION The present invention has been made in view of the above-described points. The object of the present invention is to provide a trench gate type in which an on-voltage is reduced and gate noise is reduced by providing an insulator having a large capacity for the FP layer and the emitter electrode. A semiconductor device is provided.

  To achieve the above object, a trench gate type semiconductor device according to the present invention includes a first conductivity type first semiconductor layer formed on a semiconductor substrate, and a second conductivity type second semiconductor layer adjacent to the first semiconductor layer. A plurality of semiconductor layers, a third semiconductor layer of the first conductivity type adjacent to the second semiconductor layer, and a plurality of semiconductor layers that penetrate the third semiconductor layer from one main surface of the third semiconductor layer and reach the second semiconductor layer The first and second regions adjacent to each other and in the third semiconductor layer in the first region, the region formed between the adjacent insulating gates and the adjacent insulating gates. A fourth semiconductor layer of a second conductivity type in contact; a first main electrode electrically connected to the third semiconductor layer and the fourth semiconductor layer in the first region; and electrically connected to the first semiconductor layer. And a second main electrode to be connected In that trench semiconductor device, the third semiconductor layer in said second region, characterized in that it is electrically connected to the first main electrode through an insulator having a large electrical capacitance.

  In the present invention, it is possible to provide a trench gate type semiconductor device in which the ON voltage is small and the gate noise is reduced by electrically connecting the FP layer and the emitter electrode with an insulator having a large electric capacity.

It is a top view of Example 1 of a trench gate type semiconductor device concerning the present invention. FIG. 2 is a cross-sectional structural view taken along the line AA ′ of FIG. 1. FIG. 5 is a cross-sectional structure diagram of Example 2 of a trench gate type semiconductor device according to the invention. It is sectional drawing of Example 3 of the trench gate type semiconductor device concerning this invention. 10 is a process flow in the third embodiment.

(Example 1)
1 and 2 show a first embodiment of a trench gate type semiconductor device of the present invention. In this figure, a termination region 124, a gate terminal 112, and a plurality of emitter terminals 114 are arranged on the surface of a trench gate type semiconductor device. A gate wiring 125 is formed at the boundary of the emitter terminal 114, and a collector terminal 116 is disposed on the back surface. The voltage applied to the gate terminal 112 is transmitted to the trench gate electrode through the gate wiring 125.

  The collector electrode 116 shown in FIG. 2 is electrically connected to a first conductivity type first semiconductor layer formed on one end of the semiconductor substrate, for example, a p conductivity type collector layer 101. A second conductivity type second semiconductor layer, for example, an n conductivity type semiconductor layer, is provided adjacent to the p conductivity type collector layer 101.

In this embodiment, n conductivity type semiconductor layer is adjacent to the n ⁺ conductivity type buffer layer 102 and the n ⁺ conductivity type buffer layer 102, a lower impurity concentration than the buffer layer 102 of the n ⁺ conductivity type n ^- The conductive drift layer 103 is formed. A first conductivity type third semiconductor layer, for example, a p conductivity type base layer 104 is provided adjacent to the drift layer 103.

  A plurality of gate electrodes 105 reaching the n conductivity type drift layer 103 through the p conductivity type base layer 104 from one main surface of the p conductivity type base layer 104 are provided. The outer periphery of the gate electrode 105 is covered with a gate insulating film 106, and an insulating film 107 is provided on the main surface of the p conductivity type base layer 104.

  The p conductivity type base layer 104 is divided into a first region and a second region by the plurality of gate electrodes 105. In the p conductivity type base layer 104 belonging to the first region, a second conductivity type fourth semiconductor layer in contact with the insulated gate 105, for example, an n conductivity type emitter layer 111 is formed. The emitter electrode 109 is connected to the n conductivity type emitter layer 111 and also connected to the p conductivity type base layer 104 via the p conductivity type contact layer 110. As a result, a channel is formed between the two gate electrodes 105.

  On the other hand, the p-conductivity type base layer 104 belonging to the second region is an FP layer 115 that is not directly connected to any electrode, and is connected to the emitter electrode 109 via the capacitor formed of the insulating film 121 and the polycrystalline silicon 122. The gate electrode 105, the emitter electrode 109, and the collector electrode 100 include a gate terminal 112, an emitter terminal 114, and a collector terminal 116, respectively.

  A feature of this embodiment is that a plurality of trenches are formed in the FP layer 115, and an insulating film 121 is also formed on the surface of the trench.

  Due to the effect of the trench, the surface area of the insulating film 121 is increased as compared with the case without the trench. Since the capacity of the insulator increases as the area of the insulating film increases, the capacity of the insulating film 121 increases as compared with the prior art, and the FP layer 115 and the emitter electrode 109 are short-circuited with a larger capacity of the insulator. Can do.

  Therefore, when a large noise is input between the collector and the emitter of the IGBT, the parasitic current that causes the noise is effectively bypassed to the emitter electrode 109 through the capacitor 121 of the insulator. Great effect.

  The plurality of trenches formed in the FP layer 115 may be different in width from the trenches forming the gate insulating film 106. The plurality of trenches formed in the FP layer 115 may be formed perpendicular to the trenches forming the gate insulating film 106.

  Next, the operation of this embodiment will be described with reference to FIG.

  First, a voltage of about several tens to several thousand volts is applied between the collector terminal 116 and the emitter terminal 114, and then a voltage of about 15 volts is applied between the gate terminal 112 and the emitter terminal 114. The 15 volts applied to the gate terminal 112 is transmitted to the gate electrode 105 and forms an inversion layer at the boundary between the base layer 104 and the FP layer 115 and the gate insulating film 106. The inversion layer formed in the base layer 104 electrically connects the emitter layer 111 and the drift layer 103 to form a channel.

  Through this channel, electrons are injected from the emitter layer 111 into the drift layer 103, and these electrons prompt the injection of holes from the collector layer 101. Holes injected from the collector layer 101 pass through the drift layer 103, pass through the base layer 104, and flow into the emitter electrode 109.

  In the steady state, the insulating capacitor 121 between the FP layer 115 and the emitter electrode 109 becomes high impedance, and the FP 115 and the emitter layer 109 are insulated, and in the same manner as in the prior art of Japanese Patent Laid-Open No. 2000-307116, The FP layer 115 becomes close to a floating state, and the on-voltage is lowered.

  On the other hand, in the on / off transition state of the IGBT, the impedance between the FP layer 115 and the emitter electrode 109 becomes low. Therefore, a part of the hole current flows through the FP layer 115 and flows into the capacitance between the FP layer 115 and the emitter electrode 109, the capacitance between the collector and the gate can be reduced, and noise can be prevented from entering the gate. .

  According to this embodiment, it is possible to realize a trench semiconductor device having a low on-voltage and hardly entering noise at the gate.

(Example 2)
FIG. 3 shows a second embodiment of the trench gate type semiconductor device of the present invention. This embodiment is characterized in that the insulator 121 that short-circuits the FP layer 115 and the emitter electrode 109 is silicon nitride. Silicon nitride is preferably deposited by low temperature CVD. The gate insulating film 106 is formed with a thickness of 500 to 1500 mm. The insulator 121 is preferably thin in order to increase the capacity, but it is desirable that the insulator 121 has a thickness of 100 mm or more because a uniform film quality is required to ensure a withstand voltage. Further, since the insulator 121 is formed thinner than the gate insulating film 106, it is necessary that the insulator 121 be 1500 mm or less. Further, a structure in which silicon nitride is sandwiched between 50 to 100 cm of silicon oxide film may be employed. The dielectric constant of silicon nitride is about twice that of the silicon oxide film, and a breakdown voltage equivalent to that of the silicon oxide film can be obtained with a half thickness.

  Therefore, the capacity of the insulator 121 can be increased by four times or more than the case where the capacitor is formed of a silicon oxide film. Thereby, the capacity of the insulator that short-circuits the FP layer and the emitter electrode can be increased, and malfunction of the gate due to high-frequency noise entering the gate can be prevented.

  According to this embodiment, it is possible to realize a trench gate type semiconductor device having a low on-voltage and a reduced gate noise.

Example 3
FIG. 4 shows a cross-sectional view of a third embodiment of the trench gate type semiconductor device of the present invention. This embodiment is characterized in that the insulator 121 that short-circuits the FP layer 105 and the emitter electrode 109 is thinner than the gate insulating film 106.

  Accordingly, the capacity of the insulator 121 can be increased as compared with the case where the insulator 121 is formed simultaneously with the gate insulating film 106.

  5A to 5D show a process flow for forming the insulator 121. FIG. First, in FIG. 5A, a silicon wafer 201 is trench-formed by dry etching. By forming the trench, the region is divided into a region constituting a gate having a narrow trench width and a region constituting an FP layer having a narrow trench width. Next, in FIG. 5B, the trench is oxidized to form the gate insulating film 202. The gate insulating film 202 is formed from a silicon oxide film of 500 to 1500 mm.

  Next, in FIG. 5C, the gate oxide film 202 at the center of the region constituting the FP layer is etched by wet etching, and the insulating film 203 is formed by light oxidation. The insulating film 203 is formed of a silicon oxide film. The insulator 203 is preferably thin in order to increase the capacity, but is preferably 100 mm or more because it needs to have a uniform film quality in order to ensure a withstand voltage. Further, since the insulating film 203 needs to be formed thinner than the gate oxide film 202, it is desirable that the insulating film 203 be 1500 mm or less.

  Next, in FIG. 5D, polycrystalline silicon 204 is deposited by CVD, and the insulating film 203 is the same as the gate insulating film 202 in the region constituting the gate and the region constituting the FP layer. The silicon 204 is etched.

  Through the above process, the FP layer and the emitter can be short-circuited by the insulator 203 thinner than the gate oxide film 202.

  According to this embodiment, it is possible to realize a trench gate semiconductor device with low on-voltage and low noise.

  The trench gate type semiconductor device of the present invention can be used for a power conversion element such as an inverter suitable for an air conditioner or an electric vehicle.

100 collector electrode 101 p conductivity type collector layer 102 n conductivity type buffer layer 103 n conductivity type drift layer 104 p conductivity type base layer 105 gate electrode 106 gate insulating films 107 and 203 insulating film 109 emitter electrode 110 p conductivity type Contact layer 111 n-type emitter layer 112 Gate terminal 114 Emitter terminal 115 Floating p layer 116 Collector terminal 121 Insulating layers 122 and 204 Polycrystalline silicon 124 Termination region 125 Gate wiring 126 and 127 Contact 201 Silicon wafer 202 Gate oxide film

Claims (2)

A first conductivity type first semiconductor layer formed on a semiconductor substrate, a second conductivity type second semiconductor layer adjacent to the first semiconductor layer, and a first conductivity type adjacent to the second semiconductor layer. A third semiconductor layer, and a plurality of insulated gates that pass through the third semiconductor layer from one main surface of the third semiconductor layer, reach the second semiconductor layer, and have an outer periphery covered with a gate insulating film; A region formed between the insulated gates, the first and second regions adjacent to each other, and a second conductivity type fourth semiconductor in contact with the insulated gate in the third semiconductor layer in the first region A first main electrode electrically connected to the third semiconductor layer and the fourth semiconductor layer in the first region; and a second main electrode electrically connected to the first semiconductor layer. In the trench gate type semiconductor device,
The third semiconductor layer in the second region is electrically connected to the first main electrode through a capacitor of an insulator;
The gate insulating film has a thickness of 500 to 1500 mm,
The capacitance of the insulator is 100 to 1500 mm between the third semiconductor layer and the polycrystalline silicon layer in contact with the first main electrode in the second region, and more than the gate insulating film A trench gate type semiconductor device comprising a thin silicon oxide film. A first conductivity type first semiconductor layer formed on a semiconductor substrate, a second conductivity type second semiconductor layer adjacent to the first semiconductor layer, and a first conductivity type adjacent to the second semiconductor layer. A third semiconductor layer, and a plurality of insulated gates that pass through the third semiconductor layer from one main surface of the third semiconductor layer, reach the second semiconductor layer, and have an outer periphery covered with a gate insulating film; A region formed between the insulated gates, the first and second regions adjacent to each other, and a second conductivity type fourth semiconductor in contact with the insulated gate in the third semiconductor layer in the first region A first main electrode electrically connected to the third semiconductor layer and the fourth semiconductor layer in the first region; and a second main electrode electrically connected to the first semiconductor layer. In the trench gate type semiconductor device,
The third semiconductor layer in the second region is electrically connected to the first main electrode through a capacitor of an insulator;
The gate insulating film has a thickness of 500 to 1500 mm,
The capacitance of the insulator is between 100 and 1500 mm in thickness between the third semiconductor layer and the first main electrode in the second region , and is thinner than the gate insulating film A trench gate type semiconductor device comprising a silicon nitride film.

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