KR101870825B1 - Power semiconductor device and method of fabricating the same - Google Patents

Abstract

The present invention provides a semiconductor device comprising: a substrate including an active region and an edge region, the substrate comprising a semiconductor doped with an impurity of a first conductivity type; An insulating film formed on the edge region of the substrate; A field plate pattern formed on the insulating film; At least one first doped region of the second conductivity type buried in an edge region of the substrate and extending in a direction having a vector component parallel to the top surface of the substrate; And at least one second doped region of a second conductivity type having a shape extending downward from an upper surface of the substrate in the substrate, wherein the first doped region is located laterally at a lower end of the second doped region Wherein the second conductivity type doping concentration of the first doping region is lower than the second conductivity type doping concentration of the second doping region.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power semiconductor device,

The present invention relates to a power semiconductor device and a manufacturing method thereof, and more particularly, to an insulated gate bipolar transistor (IGBT) device and a manufacturing method thereof.

Insulated Gate Bipolar Transistor (IGBT) is a crystalline material of MOS (Metal Oxide Silicon) and bipolar technology. It is characterized by low forward loss and high speed. It is applicable to applications that can not be realized with thyristors, bipolar transistors and MOSFETs. And is a next generation power semiconductor device which is used in a high efficiency and high speed power system widely used in a voltage range of 300V or more. Since the development of power MOSFETs in the 1970s, MOSFETs have been used for switching devices requiring high-speed switching, and bipolar transistors, thyristors, and GTOs have been used in a range where a large amount of current conduction is required at medium to high voltages Has come. The IGBT developed in the early 1980s has a current capability of more than a bipolar transistor in terms of output characteristics and has a gate driving characteristic like a MOSFET in terms of input characteristics, so that switching at a high speed of about 100 KHz is possible. As a result, IGBTs are being used not only for replacement of MOSFETs, bipolar transistors, and thyristors, but also for new application systems.

A related prior art is Korean Laid-Open Publication No. 20140057630 (published on May 13, 2014, entitled IGBT and its manufacturing method).

It is an object of the present invention to provide a power semiconductor device with improved robustness against element breakdown and a method of manufacturing the same. However, these problems are exemplary and do not limit the scope of the present invention.

A power semiconductor device according to one aspect of the present invention for solving the above problems is provided. The power semiconductor device comprising an active region and an edge region, the substrate comprising a semiconductor doped with an impurity of a first conductivity type; An insulating film formed on the edge region of the substrate; A field plate pattern formed on the insulating film; At least one first doped region of the second conductivity type buried in an edge region of the substrate and extending in a direction having a vector component parallel to the top surface of the substrate; And at least one second doped region of a second conductivity type having a shape extending downward from an upper surface of the substrate in the substrate, wherein the first doped region is located laterally at a lower end of the second doped region And the second conductivity type doping concentration of the first doping region is lower than the second conductivity type doping concentration of the second doping region.

In the power semiconductor device, the first doped region of the second conductivity type may extend in a direction parallel to an upper surface of the substrate.

In the power semiconductor device, the first doped region may be connected to the lower end of the second doped region and laterally protrude.

In the power semiconductor device, the first doped region may be spaced apart from the second doped region and disposed below the second doped region.

In the power semiconductor device, the at least one second doped region of the second conductivity type may include a plurality of second doped regions of a second conductivity type arranged to be spaced apart from each other, and the at least one second conductivity type The first doped region includes a plurality of second doped regions of a second conductivity type arranged to be spaced apart from each other in a shape protruding sideways from the second doped region, An interval between any one second doped region and another immediately adjacent second doped region may be further increased as the distance from the active region increases.

The power semiconductor device being formed in an active region of the substrate, the power semiconductor device comprising at least a pair of trench gate electrodes; A body region of a second conductivity type disposed between the at least one pair of trench gate electrodes; A floating region of a second conductive type surrounding the bottom surface and at least one side of the at least one pair of trench gate electrodes, And a drift region of a first conductivity type that extends from below the floating region to the body region, wherein the second conductivity type doping concentration of the first doping region is less than the second conductivity type doping concentration of the body region And the second conductivity type doping concentration of the first doping region may be lower than the second conductivity type doping concentration of the floating region.

In the power semiconductor device, a voltage distribution in a direction perpendicular to an upper surface of the substrate may be parallel to a first surface passing through the first doped region in a direction parallel to an upper surface of the substrate, A voltage reverse period may be formed between the second side of the first doped region and the second side of the first doped region to form a lowest voltage on the first side.

In the power semiconductor device, an electric field in the direction of the first surface is formed on the second surface at the interface between the substrate and the insulating film containing the semiconductor doped with the impurity of the first conductivity type by forming the voltage reversal section .

In the power semiconductor device, the vertical BV value in the direction perpendicular to the upper surface of the substrate may be higher than the vertical BV value in the other region through the first doped region.

A method for manufacturing a power semiconductor device according to another aspect of the present invention for solving the above problems is provided. The method of manufacturing a power semiconductor device includes: preparing a substrate including an active region and an edge region, the substrate including a semiconductor doped with an impurity of a first conductivity type; Forming a first doped region of at least one second conductivity type extending in a direction having a vector component parallel to the top surface of the substrate by implanting a second conductive impurity into an edge region of the substrate and performing a first heat treatment to diffuse step; Forming an epitaxial layer after forming the first doped region, forming at least a pair of trench gate electrodes in an active region of the substrate, a body region of a second conductive type disposed between the at least one pair of trench gate electrodes, A second conductivity type floating region surrounding the bottom surface and at least one side of each of the at least one pair of trench gate electrodes and spaced apart from each other and a drift region of the first conductivity type extending from below the floating region to the body region, step; Forming an epitaxial layer after forming the first doped region, implanting a second conductive impurity into an edge region of the substrate, and diffusing the second conductive impurity by a second heat treatment to form a shape extending downward from the upper surface of the substrate, Forming a second doped region of at least one second conductivity type; Wherein the first doped region is disposed so as to protrude laterally from a lower end of the second doped region, and the second doped region of the first doped region has a second doped region of the second conductivity type May be lower than the doping concentration.

According to one embodiment of the present invention as described above, a power semiconductor device capable of raising the margin of the termination vertical BV and increasing the robustness against device breakdown at a turn-off transition can be realized, and a manufacturing method thereof . Of course, the scope of the present invention is not limited by these effects.

1 is a cross-sectional view illustrating a structure of a power semiconductor device according to an embodiment of the present invention.
2 is a cross-sectional view illustrating a structure in an intermediate stage of manufacturing a power semiconductor device according to an embodiment of the present invention.
3 is an enlarged view of a configuration of the first doped region and the second doped region shown in FIG.
FIG. 4 is a graph illustrating a voltage distribution in a direction perpendicular to a top surface of a substrate in a power semiconductor device according to an exemplary embodiment of the present invention, in a direction passing through a first doped region and a second doped region.
5 is a cross-sectional view illustrating a structure of a power semiconductor device according to another embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be understood, however, that the invention is not limited to the disclosed embodiments, but may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, Is provided to fully inform the user. Also, at least some of the components may be exaggerated or reduced in size for convenience of explanation. Like numbers refer to like elements throughout the drawings.

In this specification, the first conductive type and the second conductive type have opposite conductivity types, and may be any of n-type and p-type, respectively. For example, the first conductivity type may be n-type and the second conductivity type may be p-type. In the accompanying drawings, the conductive type configuration is exemplarily assumed. However, the technical idea of the present invention is not limited thereto. For example, the first conductivity type may be p-type and the second conductivity type may be n-type.

1 is a cross-sectional view illustrating a structure of a power semiconductor device according to an embodiment of the present invention.

1, a power semiconductor device according to an embodiment of the present invention includes a substrate 10 including an active region A and an edge region B and containing a semiconductor doped with an impurity of a first conductivity type ).

The substrate 10 may be understood to include a semiconductor wafer and an epi layer epitaxially grown on the wafer. The semiconductor wafer may include, for example, a silicon wafer doped with a lightly doped impurity of the first conductivity type. Illustratively, the doping concentration of the n-type impurity in the silicon wafer may be, for example, about 10 ¹³ to 10 ¹⁶ / cm ³ . Considering the doping concentration of the n-type impurity, the substrate 100 may be referred to as an N- substrate. However, the material and the doping concentration of the substrate 100 are not limited thereto, and may be varied.

The active region A includes a plurality of active cells and a region where current conduction occurs in the vertical direction. In the active region A, gate electrodes 28a and 28b are formed by lining the gate insulating film on the inner wall of the trench formed in the substrate 10 and filling the gate insulating film with the gate electrode material, and between the gate electrodes 28a and 28b A second conductivity type body region 20 and a first conductivity type source region 22 and a second conductivity type floating region 14 formed on one side of the gate electrodes 28a and 28b. Furthermore, the first contact plug 34a that penetrates the interlayer insulating film 30 formed on the upper surface of the substrate 10 and the interlayer insulating film 30 and contacts the substrate surface can be disposed.

On the interlayer insulating film 30, a first metal film pattern 36a having a flat upper surface is provided. The first metal film pattern 36a can be in contact with the first contact plug 34a. The first metal film pattern 36a may have a shape covering most of the upper portion of the active region A. [ The first metal film pattern 36a may be provided as a film for wire bonding. In addition, the first metal film pattern 36a may serve as an emitter electrode.

A field stop region 38 may be provided on the lower surface of the substrate 10 opposite to the upper surface. The field stop region 38 may be a region doped with the first conductivity type impurity. For example, the n-type impurity concentration of the field stop region 38 may be about 10 ¹⁴ to 10 ¹⁸ / cm ³ . Considering the n-type impurity concentration of the field stop region 38, the field stop region 38 may be referred to as a N0 layer. A collector region 40 may be provided under the field stop region 38. The collector region 40 may be a doped region of the second conductivity type impurity. A second metal film 42 may be provided under the collector region 40. The second metal film 42 may be provided as a collector electrode.

The edge regions B and C are arranged adjacent to the active region A. The mutual positional relationship between the edge areas B and C and the active area A can be provided in various forms. For example, the edge regions B and C may be formed so as to surround at least a part of the active region A.

A region in which the field plate pattern 36b is formed on the insulating film 30 as a second metal film pattern different from the first metal film pattern 36a in the edge regions B and C is referred to as a peripheral region B ). The field plate pattern 36b can suppress the electric field concentration at the edge portion and the field plate pattern 36b can have a wide width in order to increase the suppression effect.

By providing the field plate pattern 36b, the field concentration can be suppressed even if the width w1 of the junction terminating extension region 16 is reduced. The field plate pattern 36b may be provided as a gate bus line electrically connected to the entire gate electrodes 28a and 28b formed in the active region A. [ The field plate pattern 36b can be formed along the periphery of the active area A. [ For example, the field plate pattern 36b may be formed in a ring shape of a closed loop, but the shape is not limited thereto.

The peripheral region B may be provided with a connection portion 28c disposed in the trench formed in the substrate 10. [ The connection portion 28c may connect one first gate electrode 28a and one second gate electrode 28b adjacent thereto. A plurality of gate electrode patterns including the first gate electrode 28a, the second gate electrode 28b, and the connection portion 28c may be provided, and the gate electrode patterns may be repeatedly disposed while being spaced apart from each other. The gate electrode pattern may have a ring shape in plan view. By having the connecting portion 28c in a rounded shape, the electric field concentration in the connecting portion 28c can be suppressed.

A junction termination extension (JTE) 16 may be provided on the substrate 10 in contact with the connection portion 28c. Junction termination extension region 16 may be doped with an impurity of the same conductivity type as floating well region 14. Junction termination extension region 106 can be doped with a high concentration second conductivity type impurity. The junction termination extension region 106 may have a ring shape surrounding the outside of the active region A in plan view.

At least one first doped region 19 of the second conductivity type buried in the substrate 10 among the edge regions B and C and extending in a direction having a vector component parallel to the upper surface of the substrate 10 And the region to be formed may be divided into an edge termination region (C). The edge termination region C is a region for supporting a high breakdown voltage.

The first doped region 19 of the second conductivity type extends in a predetermined direction, and the predetermined direction has a vector component parallel to the upper surface of the substrate 10. For example, the first doped region 19 may extend in a direction parallel to the top surface of the substrate 10. Of course, as another example, the first doped region 19 may extend in a direction forming an arbitrary first angle (but not 90 degrees) with the top surface of the substrate 10.

In the edge termination region C, the power semiconductor device according to an embodiment of the present invention includes at least one second conductive type second semiconductor substrate 10 having a shape that extends downward from the top surface of the substrate 10 in the substrate 10, Doped region 18 as shown in FIG. The second doped region 18 may have a ring shape surrounding the active region A in plan view. The second doped region 18 may be doped with a high concentration second conductivity type impurity. Also, the second doped region 18, the floating well region 14, and the junction termination extended region 16 may have the same dopant concentration and junction depth.

The first doped region 19 of the second conductivity type may have a shape protruding sideways from the second doped region 18. In the power semiconductor device shown in FIG. 1, the first doped region 19 may protrude laterally from the lower end of the second doped region 18.

At least one second doped region 18 of the second conductivity type includes a plurality of second doped regions 18 of a second conductivity type arranged spaced apart from each other, The region 19 may include a plurality of first doped regions 19 of a second conductivity type arranged to be spaced apart from each other and each having a shape protruding sideways from the second doped region 18.

In this case, the interval between any one of the second doped regions 18 and the other one of the second doped regions 18 immediately adjacent to the second doped region 18 of the second conductivity type Can be increased further away from the active region A to reduce field concentration. Each of the intervals d1, d2, d3, d4 and d5 between the second doped regions 18 is set to be smaller than the interval d1 between the active regions A and the second doped regions 18a and 18b Can be sequentially increased in order.

A third metal film pattern 36c may be provided on the interlayer insulating film 30 in the edge termination region C so as to be in contact with the contact plugs 34c. The third metal film pattern 36c may have a shape that is connected to at least one second doped region 18. In the plan view, the third metal film pattern 36c may have a ring shape. The third metal film pattern 36c may be a dummy pattern, and may not operate as a practical operation circuit. However, since the third metal film pattern 36c is provided, the concentration of the electric field can be further reduced.

FIG. 3 is an enlarged view of the configuration of the first doped region and the second doped region shown in FIG. 1. FIG. 4 is a cross-sectional view of a power semiconductor device according to an embodiment of the present invention, 1 is a graph showing a voltage distribution in a direction passing through the first doped region and the second doped region.

1 to 4, the voltage distribution in the direction perpendicular to the top surface in the edge termination region C of the substrate 10 has a first doped region 19 in a direction parallel to the top surface of the substrate 10, (D) passing through the second doped region (18) in a direction parallel to the upper surface of the substrate (10) and a second surface (C) located above the first surface (D) A reverse voltage may be formed and a lowest voltage may be formed on the first surface D. [ The electric field in the direction from the second surface C to the first surface D at the interface between the substrate 10 and the insulating film 30 containing the semiconductor doped with the impurity of the first conductivity type .

As a comparative example of the present invention, a power semiconductor device without the first doped region 19 described above can be assumed. In the comparative example of the present invention, the termination junction uses the field plate pattern to increase the horizontal electric field efficiency, but a voltage difference occurs from the substrate (silicon) to the insulating film (oxide) under the field plate pattern, The vertical electric field directed to the oxide is formed and the hole advances in the oxide direction along the electric field in the progress of the reliability to break the hydrogenated dangling bonding of the surface to cause the silicon interface charge fluctuation to generate the breakdown voltage ) Fluctuation problems may appear.

In contrast, in the power semiconductor device according to the embodiment of the present invention, the voltage reverse period is generated between the first surface D and the second surface C by introducing the first doped region 19, An electric field in the direction from the second surface (C) to the first surface (D) can be formed at the interface between the oxide and the oxide, thereby suppressing the interfacial charge variation caused by the collision of the interface with the hole, BV degradation due to dangling bond charge fluctuations can be improved.

The above description is for a termination structure using Buried Junction to improve reliability. However, since the BV balance due to charge sharing must be considered in such a structure, the vertical BV margin of the termination is not large, so that the design difficulty may be high.

In the structure described above in which the first doped region 19 is connected to the lower portion of the second doped region 18 to improve the reliability through the vertical electric field enhancement on the first surface D passing through the first doped region 19 The charge balance between the first doped region 19 and the substrate 10 must be matched so that the vertical BV of the second doped region 18 and the first doped region 19 is higher than that of the active cell region .

The inventors have previously diffused the first doped region 19 before forming a component located between the first doped region 19 and the interlayer insulating film 30 to form a second conductive type (for example, P Type) concentration so that the vertical BV of the termination portion is higher than the vertical BV of the other region.

2 is a cross-sectional view illustrating a structure in an intermediate stage of manufacturing a power semiconductor device according to an embodiment of the present invention.

2, after preparing a substrate 10 including an active region A and an edge region B and C and containing a semiconductor doped with an impurity of the first conductivity type, The second conductive type impurity is implanted into the edge regions B and C of the substrate 10 and diffused by the first heat treatment to form at least one second conductive layer extending in a direction having a vector component parallel to the upper surface of the substrate 10. [ The first doped region 19 is formed.

Although not shown in the drawing, an additional doped region may be formed by implanting the second conductive impurity into the edge region B immediately adjacent to the active region A and diffusing the first conductive impurity by a first heat treatment. Furthermore, it is possible to perform at least a part of the step of forming the floating well region 14 and / or the body region 20 simultaneously by performing the step of implanting the second conductive type impurity into the predetermined region of the active region A have.

After forming the first doped region 19 of the second conductivity type, a structure is formed over the first doped region 19, as shown in Fig. For example, after a thermal process is added to form the first doped region 19 of the second conductivity type, an epi layer is formed and at least a pair of trench gate electrodes (not shown) are formed in the active region A of the substrate 10, A body region 20 of a second conductivity type disposed between the at least one pair of trench gate electrodes 28a and 28b and a bottom region 20b of the at least one pair of trench gate electrodes 28a and 28b, And a drift region of a first conductivity type that extends from below the floating region to the body region (20); and a second conductivity type floating region And has a shape that extends downward from the upper surface of the substrate in the substrate 10 by forming an epi layer, implanting a second conductive impurity into the edge region C of the substrate 10, At least one second doped region of the second conductivity type (18), as shown in FIG.

In this case, the second conductivity type doping concentration of the first doped region 19 may be lower than the second conductivity type doping concentration of all other regions. For example, the second conductivity type doping concentration of the first doped region 19 may be lower than the second conductivity type doping concentration of the second doped region 18. Also, the second conductivity type doping concentration of the first doped region 19 may be lower than the second conductivity type doping concentration of the floating region 14 and / or the body region 20. By implementing such a low concentration junction, it is possible to configure the vertical BV of the termination portion to be higher than the vertical BV of the other region, and it is possible to easily and stably BV design by increasing the BV margin. Furthermore, the margin of the termination vertical BV can be increased to increase robustness against device breakdown at the turn off transition.

5 is a cross-sectional view illustrating a structure of a power semiconductor device according to another embodiment of the present invention.

Referring to FIG. 5, the first doped region 19 may be disposed below the second doped region 18 away from the second doped region 18. In this case also, a voltage reverse period is generated between the first surface D and the second surface C to form an electric field in the silicon-oxide interface from the second surface C to the first surface D Thereby suppressing the interfacial charge variation caused by the collision of the interface of the holes, thereby improving the BV degradation due to the silicon dangling bond charge fluctuation in the high temperature reverse voltage reliability.

The remaining components can be referred to with reference to FIGS. 1 to 4.

According to the embodiments of the present invention described above, a vertical voltage reverse voltage (from top to bottom) is formed using the potential of the junction at the oxide silicon interface of the termination junction so that the characteristic deterioration due to the silicon interface charge change Can be improved. Furthermore, by adding a thermal process to the structure, the BV margin can be increased to make stable BV design easier, and the margins of the termination vertical BV can be increased to enhance the robustness against device breakdown at the turn off transition.

While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the invention. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

10: substrate
18: second doping region
19: first doping region
20: Body region
22: source region
28a, 28b, 28c: gate electrode pattern
30: Interlayer insulating film
36b: Field plate pattern

Claims (10)

A substrate comprising an active region and an edge region, the substrate comprising a semiconductor doped with an impurity of a first conductivity type;
An insulating film formed on the edge region of the substrate;
A field plate pattern formed on the insulating film;
At least one first doped region of the second conductivity type buried in an edge region of the substrate and extending in a direction having a vector component parallel to the top surface of the substrate; And
At least one second doped region of a second conductivity type having a shape extending downward from an upper surface of the substrate in the substrate;
≪ / RTI >
Wherein the first doped region is laterally protruded from the lower end of the second doped region and the second doped concentration of the first doped region is greater than the second doped concentration of the second doped region Low,
At least one pair of trench gate electrodes formed in an active region of the substrate; A body region of a second conductivity type disposed between the at least one pair of trench gate electrodes; A floating region of a second conductive type surrounding the bottom surface and at least one side of the at least one pair of trench gate electrodes, And a drift region of a first conductivity type that extends from below the floating region to the body region,
The second conductivity type doping concentration of the first doping region is lower than the second conductivity type doping concentration of the body region and the second conductivity type doping concentration of the first doping region is less than the second conductivity type doping concentration of the body region, Lt; RTI ID = 0.0 > doping < / RTI &
Power semiconductor device. The method according to claim 1,
Wherein the first doped region of the second conductivity type extends in a direction parallel to an upper surface of the substrate. The method according to claim 1,
Wherein the first doped region is laterally connected to the lower end of the second doped region. The method according to claim 1,
Wherein the first doped region is spaced apart from the second doped region and disposed below the second doped region. The method according to claim 1,
Wherein the at least one second doped region of the second conductivity type includes a plurality of second doped regions of a second conductivity type arranged apart from each other,
Wherein the at least one first doped region of the second conductivity type includes a plurality of second doped regions of a second conductivity type arranged to be spaced apart from each other in a shape protruding laterally from the second doped region,
Wherein the gap between any one of the second doped regions and the other adjacent second doped region out of the plurality of second conductive type second doped regions is further increased as the distance from the active region increases , Power semiconductor device. delete The method according to claim 1,
Wherein a voltage distribution in a direction perpendicular to an upper surface of the substrate has a first surface passing through the first doped region in a direction parallel to an upper surface of the substrate and a second surface passing through the second doped region in a direction parallel to an upper surface of the substrate Wherein a voltage reversal section is formed between the first surface and the second surface, the second surface being located above the first surface, so that the lowest voltage can be formed on the first surface. 8. The method of claim 7,
Wherein an electric field in the direction of the first surface from the second surface can be formed at an interface between the substrate and the insulating film containing the semiconductor doped with the impurity of the first conductivity type by forming the voltage inversion section, . The method according to claim 1,
Wherein a vertical BV value in a direction perpendicular to an upper surface of the substrate is higher than a vertical BV value in a region passing through the first doped region. Preparing a substrate including an active region and an edge region and containing a semiconductor doped with an impurity of a first conductivity type;
Forming a first doped region of at least one second conductivity type extending in a direction having a vector component parallel to the top surface of the substrate by implanting a second conductive impurity into an edge region of the substrate and performing a first heat treatment to diffuse step;
Forming an epitaxial layer after forming the first doped region, forming at least a pair of trench gate electrodes in an active region of the substrate, a body region of a second conductive type disposed between the at least one pair of trench gate electrodes, A second conductivity type floating region surrounding the bottom surface and at least one side of each of the at least one pair of trench gate electrodes and spaced apart from each other and a drift region of the first conductivity type extending from below the floating region to the body region, step;
Forming an epitaxial layer after forming the first doped region, implanting a second conductive impurity into an edge region of the substrate, and diffusing the second conductive impurity by a second heat treatment to form a shape extending downward from the upper surface of the substrate, Forming a second doped region of at least one second conductivity type;
, ≪ / RTI &
Wherein the first doped region is laterally protruded from the lower end of the second doped region and the second doped concentration of the first doped region is greater than the second doped concentration of the second doped region Lt; RTI ID = 0.0 >
A method of manufacturing a power semiconductor device.

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