JP2010003762A - High breakdown voltage semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a high breakdown voltage semiconductor device that reduces an electric field relaxation region and increases the ratio of an active region even in a high breakdown voltage element. <P>SOLUTION: A nonlinear resistance film 13, in which a resistance value falls off if an electric field gets high, is formed in an electric field relaxation region of a high breakdown voltage semiconductor device comprising a semiconductor substrate 1, an epitaxial layer 2, and a semiconductor region 4, and further, a passivation film 12 is formed. The nonlinear resistance film 13 comprises polyimide resin, polyamide resin, polyimide/amide resin or epoxy resin filled up with either SiC particulate or ZnO particulate, and a resistance value falls off to an electric field impressed to the nonlinear resistance film 13. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a high breakdown voltage semiconductor device having a breakdown voltage structure called an electric field relaxation region formed on the outer periphery or end face of an active region.

  In general, in order to increase the breakdown voltage of a semiconductor device, the specific resistance of the substrate is increased, the depletion layer is easily extended into the substrate, and the chip surface pattern of the semiconductor device, the diffusion layer, etc. are devised, It is necessary to make the depletion layer on the substrate surface easy to extend in the lateral direction and to reduce the electric field strength.

  In particular, the guard ring structure on the outer periphery of the chip becomes more important as the withstand voltage increases, and it is necessary to increase the number of p + diffusion rings, so it is very susceptible to disturbances such as surface charge and interface charge. Generally, a structure in which a conductive metal film called a field plate is connected and a part of a region between guard rings is shielded.

In order to prevent the depletion layer from reaching the chip end, an impurity diffusion layer called a channel stopper having a conductivity type opposite to the guard ring is provided outside the guard ring region.
Further, in order to prevent the influence of disturbance such as surface charge and interface charge, the electric field relaxation region (guard ring region) on the outer periphery of the chip is covered with a silicon nitride film having a sheet resistance of 10 ⁸ to 10 ¹¹ Ω / □, It has also been proposed to prevent the influence of the semiconductor device, and it is possible to increase the breakdown voltage of the semiconductor device without particularly increasing the specific resistance of the substrate (see, for example, Patent Document 1).

FIG. 14 is a cross-sectional view showing the main part of the breakdown voltage structure in the conventional semiconductor device described in Patent Document 1.
In FIG. 14, a low-concentration first conductivity type (n−) epitaxial layer 2 is formed on a high-concentration first conductivity type (n +) semiconductor substrate 1. A collector electrode 3 is formed.

  At a predetermined position on the epitaxial layer 2, a high-concentration second conductivity type (p +) semiconductor region 4 serving as an active region and a plurality (for example, first regions) surrounding the semiconductor region 4 (active region) are surrounded. First to third) second conductivity type (p-type) guard rings 5a, 5b and 5c are arranged. An emitter electrode 7 is formed on the upper surface of the semiconductor region 4.

A first field plate 8 a is in ohmic contact with the first guard ring 5 a provided just outside the semiconductor region 4.
The end of the first field plate 8a is located on the epitaxial layer 2 between the semiconductor region 4 and the first guard ring 5a.

Each of the second guard ring 5b provided just outside the first guard ring 5a and the third guard ring 5c provided outside the second guard ring 5b includes an inner guard ring. The second field plate 8b whose end is located on the epitaxial layer 2 between 5a and 5b and the third field plate 8c are in ohmic contact with each other.
Each field plate 8a to 8c functions as a shield electrode for relaxing the electric field concentration portion at the end of the guard rings 5a to 5c.

  Further, in order to prevent the depletion layer from reaching a dicing line (not shown), a high-concentration first conductivity type (n +) channel stopper 6 (field stop) is provided outside the outermost guard ring 5c. Has been placed. A stopper electrode 10 is in ohmic contact with the channel stopper 6.

Insulating films 9a, 9b, 9c, and 9d formed of an oxide film (or nitride film) formed on the epitaxial layer 2 are formed between the semiconductor region 4, the guard rings 5a to 5c, and the channel stopper 6. Therefore, they are isolated and insulated.
Accordingly, the guard rings 5a to 5c, the field plates 8a to 8c, the field stopper 6, and the stopper electrode 10 are in a floating state.

Since the floating structure is very susceptible to disturbances such as surface charges and interface charges, the sheet resistance is 10 ^{8 at} the upper part of the emitter electrode 7, the field plates ^{8 a to 8} c, the insulating films 9 a to 9 d, and the stopper electrode 10. It is covered with a silicon nitride film 11 of -10 ¹¹ Ω / □. Thus, a function of leaking electric charge is provided, and a passivation film 12 is formed thereon.

However, in order to realize a high breakdown voltage that is not easily affected by disturbances such as surface charges and interface charges, a silicon nitride film 11 having a sheet resistance of 10 ⁸ to 10 ¹¹ Ω / □ is provided as shown in FIG. In such a case, the effect is small when the sheet resistance of the silicon nitride film 11 is set to a high value, and conversely, when the value is set to a low value, there is a problem that the leakage current increases.
In particular, according to the measurement experiment conducted by the applicant, it has been found that the sheet resistance is reduced by two to three orders under a high temperature (for example, 125 ° C.) environment, and the optimum sheet resistance value of the silicon nitride film 11 is limited. Obviously.

The above problem will be described below with reference to FIG. 14 and the explanatory diagram of FIG.
In FIG. 14, when a positive voltage is applied to the collector electrode 3, a negative voltage is applied to the emitter electrode 7, and a reverse voltage is applied to the junction between the semiconductor substrate 1 and the semiconductor region 4, depletion occurs. A layer is generated and extends to the electric field relaxation region where the guard rings 5a to 5c are formed.

In FIG. 15, the vertical axis represents the electric field strength at the top of the epitaxial layer 2, and the horizontal axis represents the relative position of the outer periphery of the chip.
The guard ring structure is designed below the dielectric breakdown electric field of the epitaxial layer 2 so as not to exceed the upper limit of the design electric field.

The electric field distribution on the epitaxial layer 2 indicated by a broken line in FIG. 15 is substantially “0” in the guard rings 5a to 5c, but has a peak value between the guard rings 5a to 5c.
At this time, when the sheet resistance of the silicon nitride film 11 is high, the end electric fields of the guard rings 5a to 5c and the field plates 8a to 8c are high, but when the sheet resistance is low, the gap between the guard rings 5a to 5c is high. The electric field distribution shows a tendency to be averaged.

However, if the sheet resistance of the silicon nitride film 11 is formed at the maximum value (= 10 ¹¹ Ω / □) within the above range, the electric field distribution indicated by the broken line in FIG. 15 is obtained, and the sheet resistance is set too low. Therefore, in order not to exceed the design electric field, it is necessary to increase the number of guard rings or widen the intervals between the guard rings.

In recent years, high breakdown voltage IGBTs (Insulating Gate Bipolar Transistors) have been put to practical use up to those with a breakdown voltage of 6.5 kV, but even if designed as shown in FIG. 14, the electric field relaxation region of the guard ring structure is 2 mm to 3 mm. In some cases, the area of the electric field relaxation region occupies 50% or more of the area of the chip active region.
As is well known, the improvement of the space factor of the active region with respect to the total area of the chip has become a more important issue as the chip becomes a higher withstand voltage. Therefore, reducing the area of the electric field relaxation region is an important issue.

  Conventionally, even in a high-power semiconductor device such as a thyristor, a GTO (Gate Turn Off Thyristor), or a diode used for one wafer, the withstand voltage is improved by devising the bevel (tilted portion) structure at the end of the silicon wafer. Is planned.

FIG. 16 is a cross-sectional view showing a bevel structure of a conventional semiconductor device (flat type), and a wafer end portion of a high power semiconductor device (PNP structure) such as GTO is cut into a Σ shape in order to increase the creepage dimension. The structure is shown.
FIG. 16 shows a case where the Σ shape is configured as an example, but for the same purpose, the end cross-sectional shape is polished to a slope or formed into a V shape like an arrow tip, etc. It is known that creepage dimensions can be increased.

Further, as shown in FIG. 16, after the polyimide resin 24 is thinly formed on the Σ-cut surface, the wafer end portion is molded with the silicone rubber 25 to further improve the withstand voltage of the wafer end portion.
However, in this case, in order to increase the creepage dimension of the wafer end, the wafer end must be polished, which increases the number of manufacturing process steps. In addition, it is no exaggeration to say that the withstand voltage of such a semiconductor device is dominated by the creeping insulation at the end.

Japanese Patent No. 2870553

  In the conventional high voltage semiconductor device, in the case of the structure described in Patent Document 1, the area of the electric field relaxation region cannot be reduced, so that there is a problem that the space factor of the active region cannot be improved. .

  The present invention has been made to solve the above-described problems, and an object of the present invention is to obtain a high voltage semiconductor device that can reduce the electric field relaxation region and improve the space factor of the semiconductor region. .

  A high breakdown voltage semiconductor device according to the present invention includes a first conductivity type semiconductor substrate, a low concentration first conductivity type first impurity layer formed on the semiconductor substrate, and a high concentration formed on the first impurity layer. In the first conductivity region, the semiconductor region formed of the second impurity layer of the second conductivity type, the insulating film formed on the upper surface of the first impurity layer so as to isolate the semiconductor region, and the electric field relaxation region surrounding the semiconductor region, A low-concentration second-conductivity-type guard ring selectively formed on the surface layer of the impurity layer, a field plate in contact with the guard ring and covering a part of the surface of the semiconductor region via the insulating film; A field stop made of a high-concentration first-conductivity-type impurity layer provided on the surface of the outermost portion of the first-conductivity-type semiconductor layer made of the semiconductor substrate and the first impurity layer; Electricity through the insulation film The guard ring is composed of a plurality of guard rings that are isolated from each other, and the field plate has a plurality of individually contacted with the plurality of guard rings. And a non-linear resistance film formed so as to cover the upper portion of the electric field relaxation region. The non-linear resistance film is configured to prevent an electric field applied to the non-linear resistance film. Therefore, the resistance value decreases.

  According to the present invention, the non-linear resistance film is formed in the electric field relaxation region to realize the expansion of the depletion layer, so that the resistance of the local non-linear resistance film is lowered even when a local high electric field is generated in the semiconductor surface layer. Because the electric potential difference is reduced (electric field is relaxed) and the electric field distribution of the semiconductor surface layer becomes uniform, the size of the electric field relaxation region can be reduced, and the space factor of the semiconductor region in the same size chip is improved. The chip cost can be reduced.

Embodiment 1 FIG.
1 is a cross sectional view showing an end portion electric field relaxation region of a high voltage semiconductor device according to Embodiment 1 of the present invention.
In FIG. 1, the same components as those described above (see FIG. 14) are denoted by the same reference numerals as those described above, and detailed description thereof is omitted. Note that, as described above, the case of an n + type semiconductor layer will be described as an example, but the present invention is not limited to this.

In this case, a non-linear resistance film 13 is used instead of the silicon nitride film 11 described above (FIG. 14).
That is, in order to avoid the influence of disturbances such as surface charges and interface charges in the floating structure described above, the upper portion of the emitter electrode 7, field plates 8 a to 8 c, insulating films 9 a to 9 d, and stopper electrode 10 is a non-linear resistance film 13 Further, a passivation film 12 is formed on the nonlinear resistance film 13.

The passivation film 12 is formed of, for example, a nitride film or a polyimide resin, and has a protective function for avoiding contamination from the outside.
The non-linear resistance film 13 has a characteristic that the resistance value decreases with respect to the electric field.

FIG. 2 is an explanatory diagram showing an example of resistance change characteristics of the nonlinear resistance film 13 with respect to the electric field, where the horizontal axis indicates the average electric field [kV / mm] and the vertical axis indicates the insulation resistance value [Ω] of the nonlinear resistance film 13. Yes.
Specifically, each curve in FIG. 2 insulates one filled with SiC particles having an average particle diameter φ (= 0.5 μm, 0.7 μm, 1.2 μm, 2 μm, 3 μm, 7 μm) and an epoxy resin. The characteristics are shown when applied to a cylinder and the change in insulation resistance value with respect to an average electric field of 0.05 [kV / mm] to 7 [kV / mm] is measured.

As is clear from FIG. 2, as the average particle diameter φ of the SiC particles filled in the epoxy resin decreases, the electric field at which the insulation resistance value decreases increases.
For example, considering an average electric field of 2 to 3 kV / mm in the width (= 2 to 3 [mm]) of the electric field relaxation region of the current IGBT chip (6.5 kV withstand voltage), the resistance value is a half having an electric field relaxation function. In order to obtain a characteristic of electric conductivity (10 ⁸ Ω to 10 ¹¹ Ω) and an electric field value of around 2 to 3 [kV / mm], as shown in FIG. It is desirable to use 7 [μm] SiC particles. However, the particle size is not limited to this value.

  Further, as described above, a positive voltage is applied to the collector electrode 3 in FIG. 1 and a negative voltage is applied to the emitter electrode 7, and a reverse voltage is applied to the junction between the semiconductor substrate 1 and the semiconductor region 4. As the voltage is applied, a depletion layer is generated and extends to the electric field relaxation region where the guard rings 5a to 5c are formed.

FIG. 3 is an explanatory diagram showing the electric field distribution according to Embodiment 1 of the present invention in comparison with the conventional distribution (broken line).
In FIG. 3, the vertical axis represents the electric field strength at the top of the epitaxial layer 2 and the horizontal axis represents the relative position of the outer periphery of the chip, as in the above (FIG. 15).

As is clear from FIG. 3, the electric field distribution (solid line) between the guard rings 5a to 5c on which the nonlinear resistance film 13 is formed has a lower resistance value in the peak portion than the conventional distribution (dashed line) having the peak characteristics. As a result, the potential difference is reduced and the electric field is lowered.
That is, when a high electric field location exists locally, the resistance value is reduced by the nonlinear resistance film 13 and the electric field is relaxed. In an equilibrium state, the electric field between the guard rings 5a to 5c is averaged, Ideally, the electric field distribution shown by the solid line in FIG. 3 is obtained.

For example, the electric field distribution (solid line) averaged as in the first embodiment of the present invention with respect to the characteristic having a peak as in the conventional distribution (broken line) can halve the maximum electric field. .
Further, since the dimension between the guard rings 5a to 5c is defined by the dielectric breakdown electric field of the semiconductor device, the dimension between the guard rings 5a to 5c if the maximum electric field is ½ compared to the conventional device. Can be designed to be ½, and the width of the electric field relaxation region can be drastically reduced.

  As described above, the high breakdown voltage semiconductor device according to the first embodiment (FIG. 1) of the present invention is formed on the semiconductor substrate 1 of the first conductivity type (n +) and the semiconductor substrate 1 as a configuration common to the conventional device. The low-concentration first conductivity type (n−) epitaxial layer 2 (first impurity layer) and the high-concentration second conductivity type (p +) second impurity layer formed in the epitaxial layer 2 Selectively in the surface layer of the epitaxial layer 2 in the semiconductor region 4 to be formed, the insulating films 9a to 9d formed on the upper surface of the epitaxial layer 2 so as to isolate the semiconductor region 6, and the electric field relaxation region surrounding the semiconductor region 4 The formed low-concentration second conductivity type (p) guard rings 5a to 5c and a field that contacts the guard rings 5a to 5c and covers a part of the surface of the semiconductor region 4 through the insulating films 9a to 9d Plates 8a-8c and A channel stopper 6 (field stop) made of a high-concentration first conductivity type (n +) impurity layer provided on the outermost surface of the first conductivity type semiconductor layer comprising the semiconductor substrate 1 and the epitaxial layer 2; A stopper electrode 10 is provided so as to be in contact with the channel stopper 6 and to cover a part of the surface of the electric field relaxation region via the insulating film 9d.

In addition, the guard ring includes a plurality of guard rings 5a to 5c that are separated from each other, and the field plate includes a plurality of field plates 8a to 8c that individually contact the plurality of guard rings 5a to 5c, respectively.
Furthermore, the high breakdown voltage semiconductor device according to the first embodiment of the present invention includes a non-linear resistance film 13 and a passivation film 12 formed so as to cover the upper part of the electric field relaxation region. The resistance value decreases with respect to the electric field applied to the film 13.

As a result, the non-linear resistance film 13 is formed in the electric field relaxation region to realize the spread of the depletion layer, so that the resistance of the local non-linear resistance film is lowered even when a local high electric field is generated in the semiconductor surface layer. Is reduced (electric field is relaxed), and the electric field distribution of the semiconductor surface layer becomes uniform.
Therefore, the electric field between the guard rings 5a to 5c is averaged, the withstand voltage is maintained, and the size of the electric field relaxation region can be reduced, so that the space factor of the semiconductor region 4 in the same size chip is improved. Thus, the chip cost can be reduced.

Since the chips are taken out of the wafer, the reduction in the size of the electric field relaxation region enables the production of a large number of chips from a single wafer and contributes to the reduction of energy consumption in the manufacturing stage.
In addition, since a large number of high voltage chips are mounted and finally used as power modules for electric railway drive control, etc., the reduction of the electric field relaxation area of the chip contributes to the reduction in size and weight of the drive control device. It is effective for energy saving of electric railways and contributes to reduction of energy consumption.

  Moreover, since the mixture of SiC or ZnO having an average particle size of 0.5 μm to 7 μm and polyimide resin, polyamide resin, polyimide / amide resin or epoxy resin is used as the nonlinear resistance film 13, the electric field in the electric field relaxation region is used. Can be effectively averaged (see FIG. 2), and the non-linear resistance film 13 capable of improving the withstand voltage reliability and reducing the size of the electric field relaxation region can be obtained.

In the above description, an epoxy resin filled with SiC particles is used as the non-linear resistance film 13, but the same effect can be obtained by using ZnO particles instead of SiC particles.
In addition, the same effect can be obtained by using a polyimide resin, a polyamide resin, or a polyimide / amide resin instead of the epoxy resin, and the nonlinear resistance film 13 with higher heat resistance can be realized.

  Further, the passivation film 12 formed of a nitride film or a polyimide resin is used to protect the contamination from the outside. However, as shown in FIG. 4, the passivation film is also used by combining the nonlinear resistance film 13 with a protective function. 12 may be omitted.

In FIG. 4, the non-linear resistance film 13 is made of a polyimide resin, a polyamide resin, a polyimide / amide resin, or an epoxy resin filled with SiC particles, and also serves as a passivation film protection function.
As shown in FIG. 4, by omitting the passivation film 12, the manufacturing process of the semiconductor device is simplified, so that the chip cost can be further reduced.

Embodiment 2. FIG.
In the first embodiment (FIGS. 1 to 4), the field plates 8a to 8c are formed at the corresponding positions of the guard rings 5a to 5c, but the field plates 8a to 8c are omitted as shown in FIG. Also good.
FIG. 5 is a cross-sectional view showing an end portion electric field relaxation region of the high breakdown voltage semiconductor device according to the second embodiment of the present invention. Components similar to those described above (see FIG. 1) are denoted by the same reference numerals. Detailed description is omitted.

5 is different from FIG. 1 in that the field plates 8a to 8c on the guard rings 5a, 5b, and 5c are removed and the insulating film 9 has a continuous cross-sectional shape.
As described above, the field plates 8a, 8b, and 8c function as shield electrodes for relaxing the electric field concentration portions at the ends of the guard rings 5a to 5c, but originally the nonlinear resistance film 13 has a local high electric field. There is a function of relaxing the electric field at the location.

Therefore, by using the non-linear resistance film 13, even if the field plates 8a, 8b, and 8c are removed as shown in FIG. 5, an effect of averaging the electric field between the guard rings 5a to 5c can be obtained. The dimension between 5a and 5c can be designed to be ½ that of the conventional device at the maximum, and the effect of dramatically reducing the width of the electric field relaxation region is achieved.
In addition, since it is not necessary to form the field plates 8a, 8b, and 8c, the manufacturing process can be simplified, and further cost reduction of the semiconductor device can be realized.

  As described above, the high voltage semiconductor device according to the second embodiment (FIG. 5) of the present invention is formed on the semiconductor substrate 1 of the first conductivity type (n +) and the semiconductor substrate 1 as a configuration common to the conventional device. The low-concentration first conductivity type (n−) epitaxial layer 2 (first impurity layer) and the high-concentration second conductivity type (p +) second impurity layer formed in the epitaxial layer 2 A semiconductor region 4 to be formed, an insulating film 9 formed on the upper surface of the epitaxial layer 2 so as to isolate the semiconductor region 4, and an electric field relaxation region surrounding the semiconductor region 4, and is selectively formed on the surface layer of the epitaxial layer 2. The first high-concentration first layers provided on the outermost surfaces of the first conductivity-type semiconductor layer comprising the semiconductor substrate 1 and the epitaxial layer 2 and the low-concentration second conductivity type (p) guard rings 5a to 5c. Conductivity type (n +) impurity layer A channel stopper 6 (field stop), and a stopper electrode 10 in contact with the channel stopper 6, and is provided so as to cover a part of the surface of the electric-field relaxation region via an insulating film 9.

The guard ring includes a plurality of guard rings 5a to 5c that are isolated from each other.
Furthermore, the high breakdown voltage semiconductor device according to the second embodiment of the present invention includes a nonlinear resistance film 13 and a passivation film 12 formed so as to cover the upper portion of the electric field relaxation region. Since it has the characteristic that the resistance value decreases with respect to the electric field applied to the film 13, it is possible to achieve the same effect as described above.

As described above, the nonlinear resistance film 13 is made of an epoxy resin filled with SiC particles. However, similar effects can be obtained by using ZnO particles instead of SiC particles.
In addition, the same effect can be obtained by using a polyimide resin, a polyamide resin, or a polyimide / amide resin instead of the epoxy resin, and the nonlinear resistance film 13 with higher heat resistance can be realized.

Further, although the passivation film 12 is formed on the upper surface of the nonlinear resistance film 13, the passivation film 12 may be omitted and the nonlinear resistance film 13 may also function as the passivation film 12 as shown in FIG. .
As shown in FIG. 6, by omitting the passivation film 12, the manufacturing process of the semiconductor device is simplified, so that the chip cost can be further reduced.

Embodiment 3 FIG.
Although the guard rings 5a to 5c are formed in the second embodiment (FIGS. 5 and 6), the guard rings 5a to 5c may be omitted as shown in FIG.
FIG. 7 is a cross-sectional view showing an end portion electric field relaxation region of the high breakdown voltage semiconductor device according to the third embodiment of the present invention. Components similar to those described above (see FIG. 5) are denoted by the same reference numerals. Detailed description is omitted. 7 is different from FIG. 5 only in that the guard rings 5a to 5c are removed.

In FIG. 7, the upper portions of the emitter electrode 7, the insulating film 9, and the stopper electrode 10 are covered with the non-linear resistance film 13 as described above, and the passivation film 12 is further formed on the non-linear resistance film 13.
FIG. 8 is an explanatory diagram showing the electric field distribution in the electric field relaxation region according to the third embodiment of the present invention.
In FIG. 8, the electric field distribution (solid line) when the non-linear resistance film 13 is formed as shown in FIG. 7 and the electric field distribution when there is no non-linear resistance film 13 (broken line) are shown in comparison.

  In the foregoing first and second embodiments (FIGS. 1 to 6), the electric field in the upper layer portion of the epitaxial layer 2 in the electric field relaxation region is relaxed by expanding the depletion layer by the action on the guard rings 5a to 5c. When the guard rings 5a to 5c are removed as shown in FIG. 7, the depletion layer does not expand unless the nonlinear resistance film 13 is formed. Therefore, the electric field strength of the upper layer portion of the epitaxial layer 2 is as shown in FIG. As shown by the broken line electric field distribution in FIG.

If there is no nonlinear resistance film 13 as shown by the broken line electric field distribution in FIG. 8, the upper limit of the design electric field of the semiconductor is exceeded and the function of the electric field relaxation region is not realized.
On the other hand, when the nonlinear resistance film 13 is formed as in the third embodiment (FIG. 7) of the present invention, the resistance is lowered at the electric field concentration portion at the end of the semiconductor region 4, so that the electric field is relaxed. In a stable state, the electric field between the semiconductor region 4 and the field stopper 6 is averaged.

  As described above, the high breakdown voltage semiconductor device according to the third embodiment (FIG. 7) of the present invention is formed on the semiconductor substrate 1 of the first conductivity type (n +) and the semiconductor substrate 1 as a configuration common to the conventional device. The low-concentration first conductivity type (n−) epitaxial layer 2 (first impurity layer) and the high-concentration second conductivity type (p +) second impurity layer formed in the epitaxial layer 2 A semiconductor region 4 to be formed, an insulating film 9 formed on the upper surface of the epitaxial layer 2 so as to isolate the semiconductor region 4, and a high-concentration first conductivity provided at the outermost edge of the electric field relaxation region surrounding the semiconductor region 4. A channel stopper 6 (field stop) made of a type (n +) impurity layer, and a stopper electrode 10 that is in contact with the channel stopper 6 and covers a part of the surface of the electric field relaxation region via the insulating film 9 And.

  In addition, the high breakdown voltage semiconductor device according to the third embodiment of the present invention includes the nonlinear resistance film 13 and the passivation film 12 formed so as to cover the upper portion of the electric field relaxation region. Since the resistance value decreases with respect to the electric field applied to the film 13, the electric field strength of the upper layer portion of the epitaxial layer 2 can be set lower than the design electric field upper limit value as described above.

That is, the electric field in the electric field relaxation region is averaged, the withstand voltage is maintained, and the size of the electric field relaxation region can be reduced, and the guard rings 5a to 5c and the field plates 8a to 8c are not necessary.
Further, by removing the guard rings 5a to 5c and the field plates 8a to 8c described above (FIG. 5), the manufacturing process is simplified and the cost of the semiconductor device is reduced, and the space factor of the electric field relaxation region is greatly increased. Thus, the width of the electric field relaxation region can be drastically reduced.

As described above, the nonlinear resistance film 13 is made of an epoxy resin filled with SiC particles. However, similar effects can be obtained by using ZnO particles instead of SiC particles.
In addition, the same effect can be obtained by using a polyimide resin, a polyamide resin, or a polyimide / amide resin instead of the epoxy resin, and the nonlinear resistance film 13 with higher heat resistance can be realized.

Furthermore, the passivation film 12 (nitride film or polyimide resin) is formed on the upper surface of the non-linear resistance film 13 as a protection function against contamination from the outside. However, as shown in FIG. The film 13 (polyimide resin, polyamide resin, polyimide / amide resin, or epoxy resin filled with SiC particles) may also function as the passivation film 12.
As shown in FIG. 9, by omitting the passivation film 12, the manufacturing process of the semiconductor device is simplified, so that the chip cost can be further reduced.

Embodiment 4 FIG.
In the third embodiment (FIGS. 7 to 9), the channel stopper 6 (field stop) and the stopper electrode 10 are provided at the outermost edge of the electric field relaxation region. However, as shown in FIG. The stopper electrode 10 may be omitted.
FIG. 10 is a cross-sectional view showing an end portion electric field relaxation region of the high breakdown voltage semiconductor device according to the fourth embodiment of the present invention. Components similar to those described above (see FIG. 7) are denoted by the same reference numerals. Detailed description is omitted. 10 is different from FIG. 7 only in that the channel stopper 6 and the stopper electrode 10 are removed.

In the wafer process of the semiconductor device of FIG. 10, the nonlinear resistance film 13 and the passivation film 12 are formed on the planar portion on the epitaxial layer 2. For example, the semiconductor chip is diced or diced. After that, there is a method of forming the nonlinear resistance film 13 and the passivation film 12 on the side surface of the chip.
Alternatively, in the course of the wafer process, after the nonlinear resistance film 13 and the passivation film 12 are formed on the planar portion on the epitaxial layer 2 in advance, after mounting the semiconductor chip on the power module, the nonlinear resistance film 13 and the passivation film 12 are formed on the side surface of the chip. There is also a method of forming.

  As described above, the high breakdown voltage semiconductor device according to the fourth embodiment (FIG. 10) of the present invention is formed on the semiconductor substrate 1 of the first conductivity type (n +) and the semiconductor substrate 1 as a configuration common to the conventional device. The low-concentration first conductivity type (n−) epitaxial layer 2 (first impurity layer) and the high-concentration second conductivity type (p +) second impurity layer formed in the epitaxial layer 2 A semiconductor region 4, an insulating film 9 formed on the upper surface of the epitaxial layer 2 so as to isolate the semiconductor region 4, and an electric field relaxation region surrounding the semiconductor region 4.

  Further, the high breakdown voltage semiconductor device according to the third embodiment of the present invention includes an outermost portion (upper portion of the electric field relaxation region) and a side portion of the first conductivity type semiconductor layer formed of the semiconductor substrate 1 and the epitaxial layer 2, and an electric field relaxation. The non-linear resistance film 13 and the passivation film 12 are formed so as to cover the upper part of the region, and the non-linear resistance film 13 has a characteristic that the resistance value decreases with respect to the electric field applied to the non-linear resistance film 13. Therefore, as described above, the electric field strength of the upper layer portion of the epitaxial layer 2 can be set lower than the upper limit value of the design electric field.

  That is, according to the configuration of FIG. 10, the depletion layer spreads sideways (horizontal direction in the figure) by the non-linear resistance film 13, and the electric field strength of the local high electric field portion is relaxed in the electric field distribution above the epitaxial layer 2. Therefore, the electric field strength can be flattened between the chip flat surface portion and the side surface portion.

Therefore, not only the above-described (FIG. 5) guard rings 5a-5c and field plates 8a-8c can be removed, but also the above-mentioned (FIG. 7) field stop 6 and stopper electrode 10 can be removed. The manufacturing process of the device can be further simplified.
Further, since the electric field relaxation region is effectively used up to the side surface of the chip, the electric field relaxation region can be further reduced.

  As described above, as the nonlinear resistance film 13, an epoxy resin filled with SiC particles is used. However, ZnO particles may be used instead of SiC particles, and a polyimide resin, If a polyamide resin or a polyimide / amide resin is used, the nonlinear resistance film 13 with higher heat resistance can be realized.

Further, the passivation film 12 (nitride film or polyimide resin) for protection is formed on the upper surface of the nonlinear resistance film 13, but the passivation film 12 is omitted and the nonlinear resistance film 13 (filled with SiC particles) is used as shown in FIG. The polyimide resin, polyamide resin, polyimide / amide resin, or epoxy resin) may also function as the passivation film 12.
As shown in FIG. 11, by omitting the passivation film 12, the manufacturing process of the semiconductor device is simplified, so that the chip cost can be further reduced.

Embodiment 5 FIG.
In the fourth embodiment (FIGS. 10 and 11), the creeping dimension expansion at the end of the semiconductor layer was not considered, but assuming the case where it is applied to the high power semiconductor device described above (FIG. 16), As shown in FIG. 12, the end portion may be formed in a Σ shape, and the non-linear resistance film 13 may be molded with silicone rubber 25.

12 is a cross-sectional view showing a bevel structure (edge electric field relaxation region) of a high voltage semiconductor device according to Embodiment 5 of the present invention, which is the same as described above (see FIGS. 10, 11, and 16). Are denoted by the same reference numerals as those described above and will not be described in detail.
In FIG. 12, a high-voltage semiconductor device is assumed to be a high-power semiconductor (for example, a PNP structure) such as a thyristor, GTO (Gate Turn Off Thyristor), or diode used in one wafer. The point which grind | polished to (sigma) shape and the point by which the silicone rubber 25 for molds was additionally formed on the nonlinear resistive film 13 differ from the above.

In the manufacturing process of the semiconductor device of FIG. 12, after polishing the end portion into a Σ shape, the polished end surface (around the outermost portion) is nonlinear resistance film 13 (polyimide resin, polyamide resin filled with SiC particles or ZnO particles, (Polyimide / amide resin or epoxy resin) is formed, and then molded with silicone rubber 25.
The end surface shape is not limited to the Σ shape, and may be a slope shape or a V shape. Further, the nonlinear resistance film 13 may be molded with the silicone rubber 25 regardless of the end face shape.

As a result, the non-linear resistance film 13 provided on the outermost edge portion and the side surface portion (and the electric field relaxation region) of the wafer is further molded with silicone rubber, so that withstand voltage reliability is maintained.
Further, since the end face of the electric field relaxation region at the outer peripheral edge portion of the semiconductor region is polished into a slope shape, a V shape or a Σ shape, the end surface creepage dimension can be increased.

Further, according to the configuration of FIG. 12, the depletion layer spreads horizontally and the electric field strength of the local high electric field portion is relaxed by the nonlinear resistance film 13 on the wafer end face, as in the above (FIG. 10). The intensity is flattened.
Therefore, there is a significant electric field relaxation effect at the wafer end face portion, and there is an effect of improving the withstand voltage reliability of the high withstand voltage semiconductor device.

Embodiment 6 FIG.
In the fifth embodiment (FIG. 12), the wafer end face is polished into a Σ shape. However, as shown in FIG. 13, the wafer end face is polished into a flat shape or the wafer end face is left as it is without being polished. Also good.
FIG. 13 is a cross-sectional view showing a bevel structure (edge electric field relaxation region) of a high voltage semiconductor device according to Embodiment 6 of the present invention. Components similar to those described above (see FIG. 12) are the same as those described above. The detailed description is omitted.
13 is different from the above (FIG. 12) only in that the end face is polished into a planar shape.

According to the sixth embodiment of the present invention shown in FIG. 13, the depletion layer spreads laterally and the electric field in the local high electric field portion is relaxed by the non-linear resistance film 13 as described above (FIG. 12). The electric field strength at the end face is flattened.
As a result, the electric field in the electric field relaxation region is averaged and the withstand voltage reliability is maintained, and a polishing step such as a Σ shape for enlarging the creeping dimension of the wafer end surface and a polishing step of the wafer end surface can be omitted.

It is sectional drawing which shows the principal part of the high voltage semiconductor device concerning Embodiment 1 of this invention. It is explanatory drawing which shows the insulation resistance characteristic of the nonlinear resistive film by Embodiment 1 of this invention. It is explanatory drawing which shows the electric field distribution of the electric field relaxation area | region by Embodiment 1 of this invention. It is sectional drawing which shows the principal part of the other high voltage | pressure-resistant semiconductor device which concerns on Embodiment 1 of this invention. It is sectional drawing which shows the principal part of the high voltage semiconductor device concerning Embodiment 2 of this invention. It is sectional drawing which shows the principal part of the other high voltage semiconductor device concerning Embodiment 2 of this invention. It is sectional drawing which shows the principal part of the high voltage | pressure-resistant semiconductor device which concerns on Embodiment 3 of this invention. It is explanatory drawing which shows the electric field distribution of the electric field relaxation area | region by Embodiment 3 of this invention. It is sectional drawing which shows the principal part of the other high voltage semiconductor device concerning Embodiment 3 of this invention. It is sectional drawing which shows the principal part of the high voltage semiconductor device concerning Embodiment 4 of this invention. It is sectional drawing which shows the principal part of the other high voltage semiconductor device concerning Embodiment 4 of this invention. It is sectional drawing which shows the principal part of the high voltage semiconductor device concerning Embodiment 5 of this invention. It is sectional drawing which shows the principal part of the high voltage semiconductor device concerning Embodiment 6 of this invention. It is sectional drawing which shows the principal part of the conventional high voltage semiconductor device. It is explanatory drawing which shows the electric field distribution of the electric field relaxation area | region by the conventional high voltage | pressure-resistant semiconductor device. It is sectional drawing which shows the bevel structure of the conventional high voltage semiconductor device.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Semiconductor substrate, 2 Epitaxial layer (1st impurity layer), 3 Collector electrode, 4 Semiconductor region, 5a-5c Guard ring, 6 channel stopper (field stop), 7 Emitter electrode, 8a-8c Field plate, 9, 9a ˜9d Insulating film, 10 stopper electrode, 12 passivation film, 13 nonlinear resistance film, 25 silicone rubber.

Claims (9)

A first conductivity type semiconductor substrate;
A low-concentration first conductivity type first impurity layer formed on the semiconductor substrate;
A semiconductor region formed of a second impurity layer of a high-concentration second conductivity type formed in the first impurity layer;
An insulating film formed on an upper surface of the first impurity layer so as to isolate the semiconductor region;
A low-concentration second conductivity type guard ring selectively formed in a surface layer of the first impurity layer in an electric field relaxation region surrounding the semiconductor region;
A field plate that contacts the guard ring and covers a part of the surface of the semiconductor region via the insulating film;
A field stop made of a high-concentration first-conductivity-type impurity layer provided on the surface of the outermost portion of the first-conductivity-type semiconductor layer made of the semiconductor substrate and the first impurity layer;
A stopper electrode provided in contact with the field stop and provided to cover a part of the surface of the electric field relaxation region through the insulating film;
The guard ring comprises a plurality of guard rings isolated from each other,
The field plate is a high withstand voltage semiconductor device comprising a plurality of field plates individually in contact with the plurality of guard rings,
Further comprising a non-linear resistance film and a passivation film formed so as to cover the upper part of the electric field relaxation region,
The high withstand voltage semiconductor device, wherein the non-linear resistance film has a characteristic that a resistance value decreases with respect to an electric field applied to the non-linear resistance film. A first conductivity type semiconductor substrate;
A low-concentration first conductivity type first impurity layer formed on the semiconductor substrate;
A semiconductor region formed of a second impurity layer of a high-concentration second conductivity type formed in the first impurity layer;
An insulating film formed on an upper surface of the first impurity layer so as to isolate the semiconductor region;
A low-concentration second conductivity type guard ring selectively formed in a surface layer of the first impurity layer in an electric field relaxation region surrounding the semiconductor region;
A field stop made of a high-concentration first-conductivity-type impurity layer provided on the surface of the outermost portion of the first-conductivity-type semiconductor layer made of the semiconductor substrate and the first impurity layer;
A stopper electrode provided in contact with the field stop and provided to cover a part of the surface of the electric field relaxation region through the insulating film;
The guard ring is a high voltage semiconductor device comprising a plurality of guard rings isolated from each other,
Further comprising a non-linear resistance film and a passivation film formed so as to cover the upper part of the electric field relaxation region,
The high withstand voltage semiconductor device, wherein the non-linear resistance film has a characteristic that a resistance value decreases with respect to an electric field applied to the non-linear resistance film. A first conductivity type semiconductor substrate;
A low-concentration first conductivity type first impurity layer formed on the semiconductor substrate;
A semiconductor region formed of a second impurity layer of a high-concentration second conductivity type formed in the first impurity layer;
An insulating film formed on an upper surface of the first impurity layer so as to isolate the semiconductor region;
A field stop made of a high-concentration first conductivity type impurity layer provided at the outermost edge of the electric field relaxation region surrounding the semiconductor region;
A high-voltage semiconductor device comprising a stopper electrode that is in contact with the field stop and is provided so as to cover a part of the surface of the electric field relaxation region via the insulating film,
Further comprising a non-linear resistance film and a passivation film formed so as to cover the upper part of the electric field relaxation region,
The high withstand voltage semiconductor device, wherein the non-linear resistance film has a characteristic that a resistance value decreases with respect to an electric field applied to the non-linear resistance film.   4. The high breakdown voltage semiconductor device according to claim 1, wherein the non-linear resistance film also functions as the passivation film. 5. A first conductivity type semiconductor substrate;
A low-concentration first conductivity type first impurity layer formed on the semiconductor substrate;
A semiconductor region formed of a second impurity layer of a high-concentration second conductivity type formed in the first impurity layer;
A non-linear resistance film and a passivation formed so as to cover an electric field relaxation region surrounding the semiconductor region, and an uppermost portion of the first conductivity type semiconductor layer including the semiconductor substrate and the first impurity layer and a side surface portion. Further comprising a membrane,
The high withstand voltage semiconductor device, wherein the non-linear resistance film has a characteristic that a resistance value decreases with respect to an electric field applied to the non-linear resistance film.   The high breakdown voltage semiconductor device according to claim 5, wherein the nonlinear resistance film also functions as the passivation film.   7. The high breakdown voltage semiconductor device according to claim 5, wherein the non-linear resistance film is further molded with silicone rubber.   8. The high breakdown voltage semiconductor device according to claim 7, wherein an end face of the electric field relaxation region at an outer peripheral edge of the semiconductor region is polished into a slope shape, a V shape, or a Σ shape.   The non-linear resistance film is composed of a mixture of SiC or ZnO having an average particle diameter of 0.5 μm to 7 μm and a polyimide resin, a polyamide resin, a polyimide / amide resin, or an epoxy resin. The high breakdown voltage semiconductor device according to claim 8.

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