JP2006269633A - Semiconductor device for power - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an easily designable semiconductor device for a power equipped with a high breakdown voltage termination structure whose high temperature leak currents are reduced, and whose potential is fixed, and whose resistivity to process disturbance is high. <P>SOLUTION: This semiconductor device for a power includes a first conductive stopper region 6 formed on the first main surface of a first conductive base region 1, so that the periphery of a second conductive base region 2 (P anode) can be surrounded with a predetermined distance; and a second conductive ring region 8 concentrically formed on the first main surface of the first conductive base region 1 between the second conductive base region 2 and the first conductive stopper region 6. The second conductive ring region 8 is electrically connected to the second conductive contact region 12 electrically connecting the second conductive base region 2 and the first conductive stopper region 6. A guard ring region whose potential is floating in a conventional manner is configured as a termination structure which is highly resistive to process disturbance, by fixing the potential due to the existence of a contact region connecting the base region and the stopper region. The contact region may be a polysilicon layer. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a junction termination structure of a high voltage semiconductor device for power, such as a diode, MOSFET, IGBT, thyristor, or transistor.

Conventionally, a high breakdown voltage semiconductor device has a high breakdown voltage termination structure. Taking a high-voltage diode as an example, the basic structure of this element is an N-type base region formed on a semiconductor substrate such as silicon, and a P-type anode region formed on the surface region of the first main surface of the N-type base region. The N-type cathode region is formed on the surface region of the second main surface opposite to the first main surface of the N-type base region, the anode electrode is formed on the P-type anode region, and is formed on the N-type cathode region. A diode portion composed of a cathode electrode, a P-type ring region formed in a surface region of the first main surface of the N-type base region so as to surround the diode portion, and an N-type base so as to surround the P-type ring region An electric field relaxation portion (high withstand voltage termination structure) composed of an N-type stopper region formed in the surface region of the first main surface of the region.
In this conventional device structure, a high breakdown voltage is obtained by designing an optimal arrangement of the P-type ring regions. However, this method has a problem that when the applied voltage increases, the number of P-type ring regions also increases, making it difficult to perform optimal design. Normally, the potential of each P-type ring region is not fixed, and when a high voltage is applied, the design for uniformly dispersing the electric field such as the number and interval of the rings is more difficult as the product has a higher breakdown voltage.

Even when the design is successful, if an interface state caused by heavy metal contamination or the like is generated at the interface between the insulating film formed on the surface of the semiconductor substrate and the N-type base region, it is not optimal. There was a problem of being vulnerable to disturbances during the process.
In Patent Document 1 describing the prior art, a first conductive type high resistance semiconductor layer, a second conductive type low resistance semiconductor layer formed in a ring shape on the first main surface thereof, and the first main type of high resistance semiconductor layer are described. The second conductive type low resistance semiconductor layer is repeatedly provided at a distance from the second conductive type semiconductor layer on the surface to the periphery of the element, and the second conductive type low resistance semiconductor layer is repeatedly provided. A power semiconductor device characterized by providing a second conductivity type high resistance layer is disclosed. Since the second conductivity type high resistance layer moves the electric field concentration region to the element peripheral side, the electric field concentration in the vicinity of the center of the element is relaxed, and a high breakdown voltage can be achieved.
JP 2001-15770 A

  The present invention provides a power semiconductor device that has a high withstand voltage termination structure that has a low high-temperature leakage current, has a fixed potential, and is resistant to process disturbance, and is easy to design.

  A power semiconductor device according to one embodiment of the present invention is selectively applied to a semiconductor substrate, a first conductivity type base region formed in the semiconductor substrate, and a surface region of a first main surface of the first conductivity type base region. The second conductivity type base region formed on the first conductivity type base region is surrounded by a predetermined distance, and the second conductivity type base region is formed in a surface region of the first main surface of the first conductivity type base region. The first conductivity type stopper region is located between the second conductivity type base region and the first conductivity type stopper region, and is formed at a predetermined interval on the surface region of the first main surface of the first conductivity type base region. A plurality of second conductivity type ring regions, wherein the plurality of second conductivity type ring regions electrically connect the second conductivity type base region and the first conductivity type stopper region. Characterized by being electrically connected to the contact area To have.

  According to the present invention, a power semiconductor device can be easily designed, a high temperature leakage current can be reduced, and a termination structure that is resistant to process disturbance can be obtained by fixing a potential by a contact region.

  Hereinafter, embodiments of the invention will be described with reference to examples. In each embodiment, the first conductivity type described in the claims is N-type and the second conductivity type is P-type, but the first conductivity type may be P-type and the second conductivity type may be N-type.

First, Embodiment 1 will be described with reference to FIGS.
FIG. 1 is a plan view of a power semiconductor device (electrode portion is omitted) in which the element structure of this embodiment is a high voltage diode, and FIG. 2 is a cross-sectional view of the portion along the line AA ′ in FIG. FIG. 3 is a cross-sectional view of the portion of the power semiconductor device of FIG. 1 taken along the line B-B '(the electrode portion is also described), and FIG. 4 is a power semiconductor device of this embodiment. It is a top view which shows the other example (an electrode part is abbreviate | omitted).

  As shown in FIGS. 1 to 3, the basic structure of the high voltage diode of this embodiment is an N-type base region 1 formed on a semiconductor substrate such as silicon, and a surface region of the first main surface of the N-type base region 1. A P-type anode (base) region 2 which is a P-type base region formed on the N-type cathode region 3, an N-type cathode region 3 formed on a surface region of a second main surface opposite to the first main surface of the N-type base region 1, A diode portion composed of an anode electrode 4 formed on the P-type anode region 2 and a cathode electrode 5 formed on the N-type cathode region 3, and a first portion of the N-type base region 1 surrounding the diode portion. A plurality of concentrically formed P-type ring regions 8 formed in the surface region of the main surface and the surface region of the first main surface of the N-type base region 1 so as to surround the P-type ring region 8 N-type stopper region 6 and a plurality of P-type relays And an electric field relaxation portion (high withstand voltage termination structure) composed of a P-type contact region 12 electrically connected to the P-type anode region 2 and the N-type stopper region 6. . A stopper electrode is formed on the N-type stopper region 6, and each ring electrode is formed on the P-type ring region 8. The P-type contact region 12 is formed in the surface region of the first main surface of the N-type base region 1 in the direction from the side portion of the P-type anode region 2 to the side portion of the N-type stopper region 6.

The high breakdown voltage diode of this embodiment is different from that of the conventional structure described above in that the P-type ring region 8 is electrically connected to the P-type contact region 12 in which the P-type anode region 2 and the N-type stopper region 6 are electrically connected. Is connected.
For example, as shown in FIG. 3, the P-type contact region 12 includes a P-type anode region 2, an N-type stopper region 6, and a P-type ring region 8 in the surface region of the N-type base region 1. P-type impurity diffusion region.
The P-type contact region 12 is formed, for example, by ion implantation and thermal diffusion on the main surface where the P-type anode region of the N base region 1 of the semiconductor substrate is formed with a dose amount of 1 × 10 ¹² / cm ² or more. Both the P-type ring region 8 and the N-type stopper region 6 are formed by ion implantation and thermal diffusion at 1 × 10 ¹⁴ / cm ² or more. The impurity concentration of the P-type contact region 12 is lower than that of the N-type stopper region 6 and the P-type ring region 8, and the depth from the surface of the semiconductor substrate is shallower than both.

In the P-type contact region 12, since a current flows when a high voltage is applied to the N-type stopper region 6 due to the diffusion resistance, the potential increases in order from the P-type ring region 8 close to the P-type anode region 2. That is, the potential difference of the P-type ring region 8 can be fixed, and the electric field distribution can be evenly distributed. Therefore, unlike a conventional power semiconductor device, it is not affected by disturbances such as interface states.
Further, the diffusion resistance has temperature dependence, and the resistance increases at a high temperature due to the decrease in mobility due to lattice scattering, and the leakage current is reduced. Therefore, the P-type contact region 12 can solve the problem of thermal runaway destruction due to high-temperature leakage current, which has been a problem in the past.

  Next, another element structure will be described with reference to FIG. In this example, as compared with the semiconductor device shown in FIG. 1, importance is attached to fixing the potential of the corner where electric field and current are concentrated. The basic structure of the high breakdown voltage diode shown in FIG. 4 is an N-type base region formed on a semiconductor substrate such as silicon, a P-type anode region 2 formed on the surface region of the first main surface of the N-type base region, and an N-type. An N-type cathode region formed on the surface region of the second main surface opposite to the first main surface of the base region, an anode electrode formed on the P-type anode region 2, and a cathode formed on the N-type cathode region And a plurality of concentrically formed P-type ring regions 8 and P-type rings formed on the surface region of the first main surface of the N-type base region so as to surround the diode unit. The P type anode region 2 and the N type are electrically connected to an N type stopper region 6 and a plurality of P type ring regions 8 formed in the surface region of the first main surface of the N type base region so as to surround the region 8. Stopper area 6 and electricity Electric field relaxation portion which is composed of P-type contact region 12 'to be connected to is made from (a high breakdown voltage terminating structure).

A strip electrode is formed on the N-type stopper region 6, and each ring electrode is formed on the P-type ring region 8. P-type contact region 12 'is formed in the surface region of the first main surface of the N-type base region. The P-type contact region 12 ′ is composed of a P-type impurity diffusion region formed including the P-type add region 2, the N-type stopper region 6 and the P-type ring region 8 in the surface region of the N-type base region. . The P-type contact region 12 ′ is formed in the direction from the corner portion of the P-type base region 2 to the corner portion of the N-type stopper region 6.
By using this P-type contact region, the potential of the corner portion where the electric field and current are more concentrated can be stably fixed as compared with the semiconductor device of FIG. Further, since the P-type contact region is formed in the corner portion, it becomes longer than the P-type contact region of FIG. 1, and the resistance can be increased correspondingly, and the effect of reducing the leakage current is increased.

Next, Example 2 will be described with reference to FIG.
FIG. 5 is a cross-sectional view of the power semiconductor device of this embodiment (electrode portions are omitted). This embodiment is characterized by the arrangement of the P-type ring region on the semiconductor substrate.
The basic structure of the high breakdown voltage diode shown in FIG. 5 is an N-type base region 21 formed on a semiconductor substrate such as silicon, a P-type anode region 22 formed on the surface region of the first main surface of the N-type base region 21, N-type cathode region formed on the surface region of the second main surface opposite to the first main surface of the N-type base region 21, an anode electrode formed on the P-type anode region 22, and an N-type cathode region And a plurality of concentrically formed P-type ring regions 28 formed in the surface region of the first main surface of the N-type base region 21 so as to surround the diode portion. The P-type anode is electrically connected to an N-type stopper region 26 and a plurality of P-type ring regions 28 formed in the surface region of the first main surface of the N-type base region 21 so as to surround the P-type ring region 28. Territory Electric field relaxation portion which is composed of P-type contact region 20 for electrically connecting the 22 and N-type stopper region 26 is made from (a high breakdown voltage terminating structure).

A strip electrode is formed on the N-type stopper region 26 and each ring electrode is formed on the P-type ring region 28. P-type contact region 20 is formed in the surface region of the first main surface of N-type base region 21. The P-type contact region 20 includes a P-type impurity diffusion region formed including a P-type add region 22, an N-type stopper region 26, and a P-type ring region 28 in the surface region of the N-type base region 21. . The P-type contact region 20 is formed in the surface region of the first main surface of the N-type base region 21 in the direction from the side portion of the P-type anode region 22 to the side portion of the N-type stopper region 26 (see FIG. 1). ). Of course, the P-type contact region 20 may be arranged at the corners of the P-type anode region 22 and the N-type stopper region 26 as shown in FIG. The P-type contact region 20 is formed, for example, by ion implantation and thermal diffusion on the main surface where the P-type anode region 22 of the N base region 21 of the semiconductor substrate is formed with a dose amount of 1 × 10 ¹² / cm ² or more. The P-type ring region 28 and the N-type stopper region 26 are both formed by ion implantation and thermal diffusion at 1 × 10 ¹⁴ / cm ² or more. The impurity concentration of the P-type contact region 20 is lower than that of the N-type stopper region 26 and the P-type ring region 28, and the depth from the surface of the semiconductor substrate is shallower than both.

In the P-type contact region 20, due to the diffusion resistance, a current flows when a high voltage is applied to the N-type stopper region 26, so that the potential sequentially increases from the P-type ring region 28 close to the P-type anode region 22. That is, the potential difference of the P-type ring region 28 can be fixed, and the electric field distribution can be evenly distributed. Therefore, unlike a conventional power semiconductor device, it is not affected by disturbances such as interface states.
Further, the diffusion resistance has temperature dependence, and the resistance increases at a high temperature due to the decrease in mobility due to lattice scattering, and the leakage current is reduced. Accordingly, the P-type contact region 20 can solve the problem of thermal runaway destruction due to high-temperature leakage current, which has been a problem in the past.
In this embodiment, the arrangement interval formed in the surface region of the N base region 21 of the P-type ring region 28 is configured to become longer as it approaches the N-type stopper region 26 side. The electric field distribution can be optimized by changing the interval between the P-type ring regions 28. By increasing the distance between adjacent P-type ring regions 28 toward the outside, an electric field distribution close to that of the conventional design is realized, and the structure is strong against process disturbance.

Next, Example 3 will be described with reference to FIG.
FIG. 6 is a cross-sectional view of a power semiconductor device using the high voltage diode of this embodiment as an element. This embodiment is characterized by an electrode formed in the P-type ring region. The basic structure of the high breakdown voltage diode shown in FIG. 6 is that an N-type base region 31 formed on a semiconductor substrate such as silicon, a P-type anode region 32 formed on the surface region of the first main surface of the N-type base region 31, An N-type cathode region 33 formed on the surface region of the second main surface opposite to the first main surface of the N-type base region 31, an anode electrode 34 formed on the P-type anode region 32, and the N-type cathode region 33. A plurality of concentrically formed and arranged P portions formed on the surface region of the first main surface of the N-type base region 31 so as to surround the diode portion formed from the cathode electrode 35 formed thereon. It is electrically connected to an N-type stopper region 36 and a plurality of P-type ring regions 38 formed on the surface region of the first main surface of the N-type base region 31 so as to surround the mold ring region 38 and the P-type ring region 38. Electric field relaxation portion which is composed of P-type contact regions 40 to electrically connect the P-type anode region 32 and the N-type stopper region 36 is made from (a high breakdown voltage terminating structure).

  A stopper electrode 37 is formed on the N-type stopper region 36, and a ring electrode 39 or a sense electrode 30 is formed on the P-type ring region 38. P-type contact region 40 is formed in the surface region of the first main surface of N-type base region 31. The P-type contact region 40 includes a P-type impurity diffusion region formed in the surface region of the N-type base region 31 including the P-type add region 32, the N-type stopper region 36 and the P-type ring region 38. . The P-type contact region 40 is formed in the surface region of the first main surface of the N-type base region 31 in the direction from the side portion of the P-type anode region 32 to the side portion of the N-type stopper region 36 (see FIG. 1). ). Of course, the P-type contact region 40 may be arranged at the corners of the P-type anode region 32 and the N-type stopper region 36 as shown in FIG.

The P-type contact region 40 is formed, for example, by ion implantation and thermal diffusion on the main surface where the P-type anode region 32 of the N base region 31 of the semiconductor substrate is formed with a dose amount of 1 × 10 ¹² / cm ² or more. Both the P-type ring region 38 and the N-type stopper region 36 are formed by ion implantation and thermal diffusion with a dose amount of 1 × 10 ¹⁴ / cm ² or more. The impurity concentration of the P-type contact region 40 is lower than that of the N-type stopper region 36 and the P-type ring region 38, and the depth from the surface of the semiconductor substrate is shallower than both. The P-type contact region 40 has a potential increasing in order from the P-type ring region 38 close to the P-type anode region 32 because a current flows when a high voltage is applied to the N-type stopper region 36 due to its diffusion resistance. That is, the potential difference in the P-type ring region 38 can be fixed, and the electric field distribution can be evenly distributed. Therefore, unlike a conventional power semiconductor device, it is less affected by disturbances such as interface states.

Further, the diffusion resistance has temperature dependence, and the resistance increases at a high temperature due to the decrease in mobility due to lattice scattering, and the leakage current is reduced. Therefore, in the P-type contact region 40, the problem of thermal runaway destruction due to high-temperature leakage current, which has been a problem in the past, is solved.
In this embodiment, the arrangement interval formed in the surface region of the N base region 31 of the P type ring region 38 is constant, but becomes longer as it approaches the N type stopper region 36 side as in the second embodiment. You may comprise as follows. The electric field distribution can be optimized by changing the interval between the P-type ring regions. By increasing the interval between adjacent P-type ring regions 38 toward the outside, an electric field distribution close to that of the conventional design is realized, and the structure is strong against process disturbance.

This embodiment is characterized in that the sense electrode 30 is connected to one of the P-type ring regions 38 inside the semiconductor substrate so that it can be used for a protection function when an overvoltage is applied. This utilizes the function that the potential of the P-type ring region 38 is fixed and the P-type ring region 38 inside the semiconductor substrate divides the high voltage applied to the N-type stopper region 36. This sense electrode 30 makes it possible to easily monitor the voltage applied to the semiconductor element with a low voltage output.
In the semiconductor device of FIG. 6, the sense electrode 30 is connected to the P-type ring region 38 that is inside the semiconductor substrate and adjacent to the P-type anode region. In the present invention, the P-type ring region 38 is disposed at any position. Can also be connected. However, the withstand voltage of this semiconductor device is, for example, 1000 V or more, and the closer to the inner side of the semiconductor substrate, the lower the potential (for example, 30 to 50 V in the innermost P-type ring region). It is advantageous in terms of ease of use to use the P-type ring region close to the inside for the sense electrode.

Next, Embodiment 4 will be described with reference to FIGS.
FIG. 7 is a plan view of a power semiconductor device (electrode portion is omitted) in which the element structure of this embodiment is a high voltage diode, and FIG. 8 is a cross-sectional view of the portion along the line AA ′ in FIG. The electrode portion is also described). Although the P-type ring region is used in the above embodiments, a high resistance layer can be used on the semiconductor substrate in the present invention. In this embodiment, for example, polysilicon is used as the high resistance layer.

  As shown in FIGS. 7 and 8, the basic structure of the high voltage diode of this embodiment is an N-type base region 41 formed on a semiconductor substrate such as silicon, and a surface region of the first main surface of the N-type base region 41. A P-type anode (base) region 42, which is a P-type base region, and an N-type cathode region 43 formed in a surface region of a second main surface opposite to the first main surface of the N-type base region 41, A diode portion composed of an anode electrode 44 formed on the P-type anode region 42 and a cathode electrode 45 formed on the N-type cathode region 43, and a first portion of the N-type base region 41 surrounding the diode portion. A plurality of concentrically formed and arranged P-type ring regions 48 formed in the surface region of the main surface, and formed in the surface region of the first main surface of the N-type base region 41 so as to surround the P-type ring region 48. N-type strike An electric field relaxation portion (high-level region) comprising a polysilicon contact layer 50 electrically connected to the P region 46 and the plurality of P type ring regions 48 and electrically connecting the P type anode region 42 and the N type stopper region 46. Pressure-resistant termination structure). A stopper electrode 47 is formed on the N-type stopper region 46, and each ring electrode 49 is formed on the P-type ring region 48.

The polysilicon contact layer 50 is formed on the insulating film 10 such as a silicon oxide film or a silicon nitride film that protects the surface of the semiconductor substrate. The polysilicon contact layer 50 is formed between the anode electrode 44 and the inner ring electrode 49, between the ring electrode 49, and the outer ring electrode. The stopper electrodes 47 are electrically connected to each other. Polysilicon contact layer 50 is formed on the first main surface of N-type base region 41 in the direction from the side portion of P-type anode region 42 to the side portion of N-type stopper region 46. The high voltage diode of this embodiment is different from that of the conventional structure described above in that the P-type ring region 48 is electrically connected to the polysilicon contact layer 50 in which the P-type anode region 42 and the N-type stopper region 46 are electrically connected. Is connected. Both the P-type ring region 8 and the N-type stopper region 6 are formed by ion implantation and thermal diffusion at 1 × 10 ¹⁴ / cm ² or more.
Since a current flows through the polysilicon contact layer 50 when a high voltage is applied to the N-type stopper region 46, the potential increases in order from the P-type ring region 48 close to the P-type anode region 42. That is, the potential difference of the P-type ring region 48 can be fixed, and the electric field distribution can be evenly distributed. Therefore, unlike a conventional power semiconductor device, it is not affected by disturbances such as interface states.

Next, Embodiment 5 will be described with reference to FIGS.
In the first to fourth embodiments, a diode is used as a semiconductor element connected to a termination structure of a high voltage semiconductor device. However, in the present invention, a current is applied above and below an IGBT, thyristor, MOSFET, or other semiconductor substrate as a semiconductor element. A semiconductor element through which the current flows is applied. In this embodiment, a high voltage semiconductor device in which the termination structure shown in FIGS. 1 to 3 is applied to these semiconductor elements will be described. Of course, the termination structure shown in FIGS. 4 to 8 can be applied to these semiconductor elements in the present invention.

FIG. 9A shows an example in which the termination structure of FIG. 1 is applied to a semiconductor element made of IGBT (insulated gate bipolar transistor). The basic structure of the IGBT element shown in the figure is that an N-type base region (N ^- base) formed in a semiconductor substrate such as silicon, and a P-type base region 2 formed in the surface region of the first main surface of the N-type base region. N-type emitter region (N + emitter) formed in P-type base region 2, and P-type collector region (P-type) formed in the surface region of the second main surface opposite to the first main surface of N-type base region ⁺ Collector), an N-type buffer region (N ⁺ buffer) formed between the N-type base region and the P-type collector region, an emitter electrode formed on the P-type base region 2 and the N-type emitter region region, An IGBT portion composed of a collector electrode formed on a P-type collector region, an N-type base region, an N-type emitter region, and a gate electrode (gate) formed on the P-type base region 2 via a gate insulating film And this A plurality of concentrically formed P-type ring regions 8 formed in the surface region of the first main surface of the N-type base region so as to surround the GBT portion, and the N-type base region so as to surround the P-type ring region 8 Are electrically connected to the N-type stopper region 6 and the plurality of P-type ring regions 8 formed in the surface region of the first main surface, and electrically connect the P-type base region 2 and the N-type stopper region 6. An electric field relaxation portion (termination structure) composed of the P-type contact region 12 is formed.

FIG. 9B shows an example in which the termination structure of FIG. 1 is applied to a semiconductor element made of a MOSFET (MOS transistor). The basic structure of the MOSFET element shown in the figure is an N-type base region (N ^- base) formed in a semiconductor substrate such as silicon, and a P-type base region 2 formed in the surface region of the first main surface of the N-type base region. , An N-type source region (N + source) formed in the P-type base region 2, and an N-type drain region (N) formed in a surface region of the second main surface opposite to the first main surface of the N-type base region ⁺ Drain), a source electrode formed on the P-type base region 2 and the N-type source region, a drain electrode formed on the N-type drain region, and an N-type base region, an N-type source region, and a P-type base region 2 And a plurality of MOSFETs formed on the surface region of the first main surface of the N-type base region so as to surround the MOSFETs. Concentric formation The P-type ring region 8 and the N-type stopper region 6 formed in the surface region of the first main surface of the N-type base region so as to surround the P-type ring region 8 are electrically connected to the plurality of P-type ring regions 8. To the P-type base region 2 and the P-type contact region 12 that electrically connects the N-type stopper region 6 to each other.

FIG. 10 shows an example in which the termination structure of FIG. 1 is applied to a semiconductor element made of a thyristor. The basic structure of the thyristor element shown in the figure is an N-type base region (N ^- base) formed on a semiconductor substrate such as silicon, and a P-type base region 2 formed on the surface region of the first main surface of the N-type base region. , An N-type emitter region (N ⁺ emitter) formed in the P-type base region 2, and a P-type emitter region (N-type emitter region) formed in a surface region of the second main surface opposite to the first main surface of the N-type base region ( P ⁺ emitter), an N-type buffer region (N ⁺ buffer) formed between the N-type base region and the P-type emitter region, a cathode electrode formed on the N-type emitter region, and on the P-type emitter region A thyristor portion composed of the formed anode electrode and a gate electrode (gate) formed on the P-type base region 2, and a surface region of the first main surface of the N-type base region so as to surround the thyristor portion. Multiple P-type ring regions 8 formed and arranged concentrically, an N-type stopper region 6 formed on the surface region of the first main surface of the N-type base region so as to surround the P-type ring region 8, and a plurality of P-type rings The electric field relaxation portion (termination structure) is formed of a P-type contact region 12 electrically connected to the region 8 and electrically connecting the P-type base region 2 and the N-type stopper region 6.

  As described above, the semiconductor device having a square shape in the embodiment is used, but the present invention can also be applied to a semiconductor device such as a rectangle or a circle. Four contact layers or contact regions are arranged. However, in the present invention, the number of contact layers or contact regions may be one or more. Various other modifications can be made without departing from the scope of the present invention.

The top view of the power semiconductor device (electrode part is abbreviate | omitted) which made the element structure of Example 1 which is one Example of this invention the high voltage | pressure-resistant diode. Sectional drawing of the part in alignment with the AA 'line of FIG. 1 (an electrode part is also described). Sectional drawing of the part in alignment with the BB 'line of the power semiconductor device of FIG. 1 (an electrode part is also described). FIG. 6 is a plan view showing another example of the power semiconductor device of Example 1 (electrode portions are omitted). Sectional drawing of the power semiconductor device of Example 2 which is one Example of this invention (an electrode part is abbreviate | omitted). Sectional drawing of the power semiconductor device which uses the high voltage | pressure-resistant diode of Example 3 which is one Example of this invention as an element. The top view of the power semiconductor device (electrode part is abbreviate | omitted) which made the element structure of Example 4 which is one Example of this invention the high voltage | pressure-resistant diode. Sectional drawing of the part in alignment with the AA 'line of FIG. 7 (an electrode part is also shown). Sectional drawing of the power semiconductor device which uses IGBT and MOSFET of Example 5 which is one Example of this invention as an element. Sectional drawing of the semiconductor device for electric power which uses the thyristor of Example 5 as an element.

Explanation of symbols

1, 2, 31, 41 ... N-type base region 2, 22, 32, 42 ... P-type base region (P-type anode region)
3, 33, 43 ... N-type cathode region 4, 34, 44 ... Anode electrode 5, 35, 45 ... Cathode electrode 6, 26, 36, 46 ... N-type stopper region 7, 37, 47 ... Stopper electrode 8, 28, 40 ... P-type ring region 9, 39, 49 ... Ring electrode 10 ... Insulating film 12, 12 ', 40 ... P-type contact region 30 ...・ Sense electrode 50: polysilicon contact layer

Claims (5)

A semiconductor substrate;
A first conductivity type base region formed in the semiconductor substrate;
A second conductivity type base region selectively formed in a surface region of the first main surface of the first conductivity type base region;
A first conductivity type stopper region that surrounds the second conductivity type base region at a predetermined distance and is formed in a surface region of the first main surface of the first conductivity type base region;
A plurality of second conductivity types that are between the second conductivity type base region and the first conductivity type stopper region and are formed at a predetermined interval in a surface region of the first main surface of the first conductivity type base region. With a ring area,
The plurality of second conductivity type ring regions are electrically connected to a second conductivity type contact region that electrically connects the second conductivity type base region and the first conductivity type stopper region. A power semiconductor device. A plurality of the second conductivity type contact regions are arranged, and each contact region electrically connects the second conductivity type base region, the second conductivity type ring region, and the first conductivity type stopper region. The power semiconductor device according to claim 1. 3. The power semiconductor device according to claim 1, wherein an interval between two adjacent regions of the second conductivity type ring region becomes longer as approaching the first conductivity type stopper region side. 4. 2. A sense electrode that is electrically connected to at least one of the second conductivity type ring regions and divides and detects a voltage applied to the first conductivity type stopper region. Item 4. The power semiconductor device according to any one of Items 3 to 3. The said 2nd conductivity type contact area | region is the diffused resistance formed in the surface area | region of the 1st main surface of the said 1st conductivity type base area | region, The Claim 1 thru | or 4 characterized by the above-mentioned. Power semiconductor device.

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