JP2013179327A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device that maintains an effective breakdown voltage holding without widening a breakdown voltage holding region and obtains sufficient short circuit breaking capacity with no high resistivity of a power device.SOLUTION: A semiconductor device includes: a power device formed in a semiconductor substrate having a semiconductor layer; a plurality of guard rings formed so as to surround the power device in the semiconductor substrate; and voltage application means for applying a higher voltage to the guard ring closer to an outer peripheral side among the plurality of guard rings. The power device includes: a grounded emitter electrode on the front surface side of the semiconductor substrate; a gate electrode on the front surface side of the semiconductor substrate; and a collector electrode on the rear surface side of the semiconductor substrate. The voltage application means includes a plurality of resistive elements connected in series between the outer peripheral part of the plurality of guard rings of the semiconductor layer and the emitter electrode. The guard ring closer to the outer peripheral side is connected with the resistive element closer to the outer peripheral side among the plurality of resistive elements directly or via a conductor pattern.

Description

  The present invention relates to a semiconductor device having a power device such as an IGBT (Insulated Gate Bipolar Transistor) or a power MOSFET, and more particularly to a semiconductor device having a function of holding a withstand voltage and protecting a short circuit.

  A semiconductor device having a power device to which a high voltage is applied between main electrodes needs to maintain a withstand voltage and short-circuit protection. That is, a semiconductor device having a power device is required to have a high withstand voltage and a short-circuit tolerance sufficient to prevent the power device from deteriorating for a certain time even when the main electrodes are short-circuited.

  In order to increase the breakdown voltage of a power device, a semiconductor device generally has a structure called a guard ring or a field plate. A guard ring is a PN junction region formed in a ring shape so as to surround an element region where a power device is formed. A plurality of guard rings are provided concentrically to form a pressure resistant holding region. Then, the electric field relaxation in the semiconductor layer of the semiconductor device is performed by a known function (action) of the guard ring.

  The field plate is an electrode disposed on the substrate surface between the gate electrode and the drain electrode of the power device via an insulating film. A voltage equivalent to the gate voltage of the power device is often applied to the field plate. Electric field relaxation in the semiconductor layer of the semiconductor device is performed by a known function (action) of the field plate. As described above, a guard ring or a field plate is used to maintain a pressure resistance.

  On the other hand, in order to improve the short-circuit tolerance of the power device, it is conceivable to increase the on-resistance of the power device, so that a large current flows even when a high voltage is applied between the main electrodes of the power device. Can be suppressed. Other known techniques relating to withstand voltage holding and short circuit protection are described in Patent Documents 1-7.

Japanese Patent Laid-Open No. 04-212468 JP-A-11-330456 Japanese Patent Laid-Open No. 04-000768 JP 2006-173437 A Japanese Patent Laid-Open No. 06-338512 Japanese Patent Laid-Open No. 04-332173 JP-A-2005-217152

  Since the above-described guard rings are not normally fixed (floating), there is a tendency that the electric field is strong on the element region side (inside) and the electric field is loose on the outer periphery side. In this case, there is a problem that the required breakdown voltage cannot be obtained because the effect of extending the depletion layer generated in the semiconductor layer (element side region) is insufficient. In addition, there is a problem that a wide withstand voltage holding region has to be taken in order to increase the withstand voltage. Similarly, when the field plate is used, there is a problem that the withstand voltage (withstand voltage improvement) is insufficient and the chip cannot be miniaturized or miniaturized.

  Further, increasing the on-resistance of the power device in order to improve the short-circuit withstand capability directly leads to a decrease in electrical characteristics of the power device, that is, a decrease in performance. Specifically, there is a problem that it is difficult to reduce the power consumption and output of the power device.

  The present invention has been made in order to solve the above-described problems. In particular, the present invention provides a semiconductor device having improved performance by performing effective withstand voltage maintenance without increasing the withstand voltage holding region and increasing short-circuit tolerance. The purpose is to provide.

  A semiconductor device according to the invention of the present application includes a power device formed on a semiconductor substrate having a semiconductor layer, a plurality of guard rings formed on the semiconductor substrate so as to surround the power device, and the plurality of guard rings. Voltage guard means for applying a higher voltage to the guard ring on the outer peripheral side. The power device includes a grounded emitter electrode formed on the semiconductor substrate surface, a gate electrode formed on the semiconductor substrate surface, and a collector formed on a back surface opposite to the semiconductor substrate surface. The voltage applying means includes a plurality of resistance elements connected in series between the outer peripheral portion of the plurality of guard rings of the semiconductor layer and the emitter electrode, and the outer peripheral side. The guard ring is connected to the resistance element on the outer peripheral portion side among the plurality of resistance elements directly or via a conductor pattern.

  According to the present invention, the performance of a semiconductor device can be improved.

1 is a diagram illustrating a semiconductor device of Embodiment 1. FIG. It is a figure explaining the resistive element formed in the spiral. It is a figure explaining the contact of a guard ring. It is a figure explaining the resistive element formed in linear form. It is a figure explaining the resistive element formed in the zigzag. It is a figure explaining the structure of the semiconductor device which applies a voltage to a guard ring via a capacitor. It is a figure explaining the resistive element in which the diode was partially formed. 6 is a diagram illustrating a semiconductor device of Embodiment 2. FIG. FIG. 6 is a plan view of a semiconductor device according to a second embodiment. It is a figure explaining the contact of the electrode (field plate) in an insulating film. It is a figure explaining the structure of the semiconductor device which applies a voltage to the electrode in an insulating film via a capacitor. FIG. 10 illustrates a semiconductor device according to a third embodiment. It is a figure explaining the structure by which the resistive element was directly connected with the drain electrode etc. FIG. 10 illustrates a semiconductor device according to a fourth embodiment. It is a figure explaining the waveform which defines t1 which is time required for turn-on. It is a figure explaining a measurement circuit. It is a figure explaining the waveform which defines t2 which is time until a power device deteriorates (thermal destruction). It is a figure explaining the waveform which defines t3 which is time when a delay circuit delays a gate drive signal. FIG. 6 is a circuit diagram showing a simplified configuration of the fourth embodiment. It is a figure explaining the means to perform a short circuit protection in a horizontal type power device. It is a figure explaining the resistive element formed in the spiral. It is a figure explaining the resistive element formed in linear form. It is a figure explaining the resistive element formed in the zigzag. It is a figure explaining the broken line C section enlarged plane of FIG. It is a diagram illustrating a semiconductor device in which a flip-flop circuit is formed on a substrate different from a power device. It is a figure explaining the structure which can suppress the latchup of CMOS. It is a figure explaining the structure which can suppress the latchup of CMOS. FIG. 10 illustrates a semiconductor device according to a fifth embodiment. FIG. 10 is a diagram illustrating a modification of the semiconductor device of Embodiment 5.

Embodiment 1
The present embodiment relates to a semiconductor device in which a guard ring is formed. Hereinafter, this embodiment will be described in detail with reference to FIGS. First, FIG. 1 is a cross-sectional view (partially schematic diagram) of a semiconductor device 10 of this embodiment. The semiconductor device 10 is on a semiconductor substrate forming one chip, and includes an element region 12 in which a power device is formed, and a breakdown voltage holding region 14 positioned around the element region 12. In the present embodiment, the power device refers to a vertical IGBT, and is configured by integrating a plurality of cells. In this example, the trench type is used for the IGBT cell, but a planar type may be used.

  The element region 12 and the breakdown voltage holding region 14 are formed in a common semiconductor layer 18. The semiconductor layer 18 is an n− layer, and is a portion in which conductivity modulation occurs when carriers are supplied from a collector side and an emitter side, which will be described later, when the IGBT of the element region 12 is in an on state.

  The element region 12 formed in the semiconductor layer 18 will be described. A p base layer 19 is provided on the surface of the semiconductor layer 18 in the element region 12, and a plurality of trenches (grooves) reaching from the surface to the n − layer (semiconductor layer 18) are formed and arranged. In each trench, polycrystalline silicon that becomes the gate electrode 20 is buried via the gate insulating film 15, and an insulating film 23 is provided thereon. The plurality of gate electrodes 20 are connected to a gate terminal (gate bonding pad) 32 by a gate wiring 31, and a gate drive signal is transmitted from the gate terminal 32.

  Further, an n + emitter region 21 is formed on the surface of the p base layer 19 in contact with the gate insulating film 15. An emitter electrode 30 made of aluminum or the like is formed on the upper surface of the n + emitter region 21 and the p base layer 19 so as to cover the surface of the element region 12. Therefore, as apparent from FIG. 1, when a gate drive signal for turning on the IGBT is input to the gate electrode 20, the conductivity type of the contact surface of the p base layer 19 with the gate insulating film is reversed. As a result, a carrier path (channel) is formed between the semiconductor layer 18 and the emitter electrode 30 (emitter region 21). This is the same as the operation of a general IGBT.

  Further, the collector electrode 16 is formed on the back surface of the semiconductor layer 18. The collector electrode 16 and the semiconductor layer 18 are connected via a p + collector layer 17 serving as a collector. In the present embodiment, the collector electrode 16 extends not only to the element region 12 but also to the breakdown voltage holding region 14.

  Next, the breakdown voltage holding region 14 included in the semiconductor device 10 of this embodiment will be described. A guard ring 22 is formed in the breakdown voltage holding region 14. A plurality of guard rings 22 are formed and have a conductivity type different from that of the semiconductor layer 18, which is a p + region in the present embodiment. The guard rings 22 described above are arranged so as to form concentric circles so as to surround the outer periphery of the element region 12.

  Then, the outer peripheral portion 34, which is a region on the outer periphery of the guard ring 22, of the semiconductor layer 18 and the emitter electrode 30 are connected via a high resistance element (wiring) 28. Note that an n + channel stopper region 29 having the same conductivity type as that of the semiconductor layer 18 is usually formed in the outer peripheral portion 34 described above, and the high resistance element 28 is connected thereto.

  The high resistance element 28 is electrically divided into a plurality of resistance element portions in order to extract a desired voltage. In this example, the high resistance element 28 is treated as including a resistance element 25, a resistance element 26, and a resistance element 27 connected in series. . One end of the resistance element 27 arranged on the outermost side is connected to the outer peripheral portion 34, and the other end is connected to one end of the resistance element 26. The other end of the resistance element 26 is connected to one end of the resistance element 25. The other end of the resistance element 25 is connected to the emitter electrode 30. The resistance value of the high resistance element may be determined by the specifications regarding the collector-emitter breakdown voltage and leakage current in the semiconductor device. For example, when the breakdown voltage is 600 V, a setting of about 600 M (mega) Ω is appropriate. .

  In the present embodiment, the wiring branched from the wiring (or connection point) connecting the resistance element 27 and the resistance element 26 is connected to the guard ring closer to the outer peripheral portion 34. In addition, a wiring branched from a wiring (or connection point) connecting the resistance element 26 and the resistance element 25 is connected to a guard ring far from the outer peripheral portion 34.

  By the way, the semiconductor layer 18 has substantially the same potential as the voltage applied to the collector electrode 16. Therefore, when the emitter electrode 30 is set to 0 V, for example, when a high voltage of 600 V is applied to the collector electrode 16, the same high voltage (600 V) is also applied to the outer peripheral portion 34. As described above, the high resistance element 28 connected between the emitter electrode 30 and the channel stopper region 29 of the outer peripheral portion 34 gradually reduces the voltage of the outer peripheral portion 34 by the resistance element 27, the resistance element 26, and the resistance element 25. The guard ring 22 closer to the outer peripheral portion 34 is connected so as to apply a higher voltage. Thus, the high resistance element 28 is a voltage applying means for applying a voltage to the guard ring 22. The meaning of the voltage applying means is not limited to the means for applying a voltage to the guard ring, but means means for supplying a voltage widely to a structure for maintaining a withstand voltage.

  Next, FIG. 2 which is a plan view of the semiconductor device 10 will be described. 2 that are denoted by the same reference numerals as those in FIG. 1 are the same as those in FIG. Further, although the high resistance element 28 is shown in a circuit diagram in FIG. 1, it is shown in accordance with an actual layout in FIG. In order to stabilize the potentials of the respective guard rings 22 and channel stopper regions 29, conductor patterns such as aluminum are often provided in parallel on the upper portions thereof, and the respective guard rings and channel stoppers are provided. Although the region and the conductor pattern are electrically connected, this is omitted in FIG. 2 for convenience.

  The high resistance element 28 of the present embodiment is a single polycrystalline silicon formed in a spiral shape connecting the outer peripheral portion 34 and the emitter electrode 30 as shown in FIG. The high resistance element 28 is connected to the channel stopper region 29 of the outer peripheral portion 34 by the contact 33 and is connected to the guard ring 22 by the contact 35. In order to help understanding the structure of the contact 33 and the contact 35, FIG. As described above, conductor patterns 40 and 42 such as aluminum are provided on the guard ring and channel stopper, and the conductor patterns 40 and 42 and the guard ring and channel stopper region are connected via contacts 33 and 35. By being electrically connected, the potential of the guard ring and the channel stopper is stabilized. In this figure, the high resistance element 28 achieves electrical connection with the guard ring 22 and the channel stopper region 29 via the conductor patterns 40 and 42, but may be directly connected. A contact 37 shown in FIG. 2 connects the high resistance element 28 and the emitter electrode 30.

  The configuration of the semiconductor device 10 of the present embodiment is as described above. According to the configuration of this embodiment, when a voltage is applied to the collector electrode 16, “a higher voltage can be applied to the guard ring 22 on the outer peripheral side” with respect to the plurality of guard rings 22. Therefore, the depletion layer generated in the element region 12 of the semiconductor layer 18 can be extended in the outer peripheral direction of the guard ring, which contributes to uniform electric field strength in the semiconductor layer 18. Therefore, it is possible to maintain the withstand voltage (improve the withstand voltage).

  In addition, the voltage applied to each guard ring 22 can be adjusted by changing the resistance value or resistance division ratio of the high resistance element 28 (hereinafter, the voltage applied to each guard ring 22 may be referred to as an intermediate potential). The potential means an intermediate potential between the potential of the collector electrode 16 and the potential of the emitter electrode 30). The resistance value of the high resistance element 28 is adjusted so as to extend the depletion layer in the element region 12, and an optimum intermediate potential (for holding the withstand voltage) is applied to each guard ring 22, thereby substantially reducing the electric field in the withstand voltage holding region. The breakdown voltage of the semiconductor device 10 can be improved by making it uniform. Therefore, since it is not necessary to form the breakdown voltage holding region 14 widely, the breakdown voltage holding region 14 can be reduced.

  Moreover, since the high resistance element 28 is formed in a spiral shape as described with reference to FIG. 2, the length of the high resistance element 28 can be increased. Since the high resistance element 28 can be formed long, a low resistivity can be set, and the impurity concentration of the polycrystalline silicon can be increased. Therefore, variations in resistance value can be suppressed, and a stable voltage can be accurately and stably applied to each guard ring 22. Can supply. Furthermore, since the high resistance element 28 formed in a spiral shape can be connected to each guard ring, the degree of freedom in adjusting the voltage applied to the guard ring 22 is high.

  The high resistance element 28 of the present embodiment has a spiral shape shown in FIG. 2, but the present invention is not limited to this. For example, the resistance element may have a shape as shown in FIGS. The resistance element 50 shown in FIG. 4 linearly connects the outer peripheral portion 34 of the semiconductor layer and the emitter electrode 30. Then, by forming the contact 52 with the guard ring 22 so as to divide the resistance element 50 at equal intervals, the voltage applied to each guard ring 22 decreases from the outer peripheral portion 34 toward the emitter electrode 30 in a linear function. . Therefore, the electric field in the semiconductor layer can be made uniform. Further, since an ideal voltage can be applied to each guard ring 22 for holding a withstand voltage (withstanding voltage improvement), the area of the withstand voltage holding region 14 can be reduced.

  In addition, when stepped (zigzag) like the resistance element 60 shown in FIG. 5, the voltage applied to each guard ring 22 can be reduced linearly from the outer peripheral portion 34 toward the emitter electrode 30. Furthermore, when the resistance element 60 is stepped (zigzag), the resistance element 60 can be formed long, so that polycrystalline silicon having a relatively low resistance can be used, and the voltage applied to the guard ring 22 can be stabilized. .

  In the present embodiment, the high resistance element 28 (the divided resistance element 27, the resistance element 26, and the resistance element 25) and the guard ring 22 are electrically connected directly by the contact 35, but the present invention is limited to this. Not. That is, as shown in FIG. 6, it may be connected via a capacitor 24 to the connection portion between the resistance element and the guard ring. Therefore, the effect of the present invention is not lost. The capacitor 24 is not limited to the case where the capacitor structure is formed in the contact portion, and parasitic capacitance may be used.

  As described above, various modifications of the shape, arrangement, and material of the high resistance element 28 are conceivable within the scope of the present invention. Another modification will be described with reference to FIG. 7 is a cross-sectional view taken along the broken line AA in FIG. As shown in FIG. 7, an N-type semiconductor region 54 and a P-type semiconductor region 56 are formed adjacent to each other inside the high resistance element 28. The N-type semiconductor region 54 and the P-type semiconductor region 56 form a diode having a relatively low breakdown voltage, and the voltage applied to the guard ring 22 can be adjusted by changing the diode pitch. That is, by forming a diode in the high resistance element 28, in addition to the adjustment of the resistance value by the length of the resistance element described above, the voltage applied to the guard ring 22 can be adjusted by the change in the diode pitch. The degree of freedom of setting can be increased.

  In the present embodiment, the high resistance element 28 is configured to be supplied with a voltage from the outer peripheral portion 34, but the present invention is not limited to this. The high resistance element 28 may be connected to an external power source or the like.

Embodiment 2
The present embodiment relates to a semiconductor device having a power device that is a lateral MOSFET. Hereinafter, the details of the present embodiment will be described with reference to FIGS. FIG. 8 is a cross-sectional view (partially schematic diagram) of the semiconductor device 70 of the present embodiment. A lateral MOSFET semiconductor device 70 formed on a semiconductor substrate includes a semiconductor layer 72. The semiconductor layer 72 is an n− layer, on the surface of which an n + drain 74 is formed, and a drain electrode 76 made of aluminum or the like electrically connected to the drain 74 is provided. Further, a p base region 80 is formed on the surface of the semiconductor layer 72 at a distance from the n + drain 74, and an n + source 91 and a p + region 93 are formed on the inner surface of the p base region 80. A source electrode 78 made of aluminum or the like electrically connected to the source 91 and the p + region 93 is provided. The source electrode 78 is grounded.

  An insulating film 84 is formed on the surface of the semiconductor substrate between the source electrode 78 (n + source 91) and the drain electrode 76 (n + drain 74). Although the insulating film 84 is originally composed of a plurality of insulating film layers, it is omitted for convenience. A gate electrode 82 made of polycrystalline silicon is formed on the p base region 80 in the insulating film 84. The gate electrode 82 is connected to the gate terminal 100 by a gate wiring 81 and receives a gate drive signal from the gate terminal 100. When a gate drive signal for turning on the MOSFET is input to the gate electrode 82, a channel is formed on the surface portion of the p base region 80 facing the gate electrode 82.

In a lateral MOSFET that requires a high breakdown voltage, a plurality of insulating film electrodes 86 made of the same polycrystalline silicon as the gate electrode 82 are formed in the insulating film 84 in addition to the above-described configuration. The in-insulating-film electrode 86 is sometimes referred to as a field plate, and as is well known, it relieves an electric field in the semiconductor layer 72 constituting the lateral MOSFET. Furthermore, the semiconductor device 70 of this embodiment includes a high resistance element 98 having one end connected to the drain electrode 76 and the other end connected to the source electrode 78. The high resistance element 98 is electrically divided into a plurality of resistance elements. In this example, the high resistance element 98 is treated as including the resistance elements 90, 92, 94, and 96 connected in series. One end of the resistance element 90 is connected to the drain electrode 76. The other end of the resistance element 90 is connected to one end of the resistance element 92, the other end of the resistance element 92 is connected to one end of the resistance element 94, and the other end of the resistance element 94 is connected to one end of the resistance element 96. The other end of 96 is connected to the source electrode 78. As shown in FIG. 8, the insulating film inner electrode 86 on the drain electrode 76 side is connected to the resistance element on the drain electrode 76 side.
Next, FIG. 9 which is a plan view of the semiconductor device 70 will be described. 9, since the same reference numerals as those in FIG. 8 are the same as those in FIG. 8, the description thereof is omitted. 8 described above is a cross-sectional view taken along the broken line BB in FIG. Further, although the high resistance element 98 is shown in a circuit diagram in FIG. 8, it is shown in accordance with an actual layout in FIG. As is apparent from FIG. 9, the lateral MOSFET shown in FIG. 8 has the insulating electrode 86 (the same gate electrode) and the source electrode 78 arranged and formed concentrically around the drain electrode 76. It has been done.
As shown in FIG. 9, the high resistance element 98 of the present embodiment is a single polycrystalline silicon formed in a spiral shape connecting the source electrode 78 and the drain electrode 76. The high resistance element 98 is connected to the source electrode 78 by the contact 99 and is connected to the in-insulating-film electrode 86 by the contact 97. In order to facilitate understanding of the structure of the contact 99 and the contact 97, an enlarged cross-sectional view is shown in FIG. The contact 95 connects the high resistance element 98 and the drain electrode 76.

  In the semiconductor device 70 having such a configuration, when a voltage is applied to the drain electrode 76, different voltages are applied to the plurality of insulating film electrodes 86 by the high resistance element 98. That is, the closer to the drain electrode 76 of the in-insulating electrode 86, the higher the voltage is applied. Therefore, since a voltage can be applied to the semiconductor layer 72 below the insulating film 84 so as to extend a depletion layer generated in the vicinity of the gate electrode 82, the breakdown voltage of the semiconductor device 70 can be maintained (withstand voltage improvement).

  In this embodiment, the technique of Embodiment 1 is applied to a horizontal power device. Therefore, the modification of the shape and material of the high-resistance element 98 and the means for applying a voltage to the high-resistance element 98 are not limited to being connected to the drain electrode 76.

  In the present embodiment, as shown in FIG. 8, the high resistance element 98 and the insulating film electrode 86 are electrically connected directly, but the present invention is not limited to this. For example, as shown in FIG. 11, the effect of the present invention is not lost even in a configuration in which the same portion is connected via the capacitor 88 as in the first embodiment.

Embodiment 3
The present embodiment relates to a semiconductor device having means for relaxing an electric field of a semiconductor layer inside the semiconductor layer. Hereinafter, the configuration of the present embodiment will be described with reference to FIG. FIG. 12 is a cross-sectional view (partially schematic diagram) of the semiconductor device 110 of this embodiment. The semiconductor device 110 has the same configuration as the semiconductor device 70 described in the second embodiment with reference to FIG. 8 except for the following points.

That is, the semiconductor device 110 according to the present embodiment includes the embedded insulating film 112 inside the semiconductor layer 72 that is neither the front surface nor the back surface. A plurality of buried insulating film inner electrodes 114 are formed inside the buried insulating film 112. Further, a resistance element 120 having one end capacitively coupled to the potential of the drain 74 and the other end capacitively coupled to the potential of the p base region 80 is provided. In FIG. 12, this capacitive coupling configuration is represented by a capacitor 116 and a capacitor 118 connected to both ends of the resistance element 120.
The resistive element 120 includes electrically resistive elements 122, 124, 126, and 128 that are electrically divided into a plurality of resistive element portions to extract a desired voltage. Each buried insulating film electrode 114 is connected to the resistance elements 122, 124, 126, and 128 (specifically, a branch portion between adjacent resistance elements) in order from the buried insulating film electrode 114 on the drain 74 side. Is done. By doing so, when a voltage is applied to the drain electrode 76, a higher voltage is applied to the buried insulating film electrode 114 on the drain 74 side.

  Since the configuration other than that described above is the same as that of the second embodiment, the same reference numerals as those in FIG.

  According to the configuration of this embodiment, the electric field of the semiconductor layer 72 can be relaxed by the buried insulating film electrode 114 arranged so that the voltage gradually increases from the gate electrode 82 to the drain electrode 76, so that the withstand voltage can be maintained.

  In FIG. 12, the embedded insulating film inner electrode 114 and the like are added to the structure of FIG. 8 which is the structure of the second embodiment. However, the effect of the present invention can be obtained even when the insulating film inner electrode 86 is not provided. Can do. In the present embodiment, the resistance element 120 is “capacitively coupled” to the drain 74 and the like, but the present invention is not limited to this. That is, as shown in FIG. 13, the effect of the present invention can be obtained even when the resistance element 134 is connected to the conductor 136 in contact with the drain electrode 76 and the conductor 138 in contact with the source electrode 78.

  When the resistance element 134 is “directly connected” to the drain electrode and the source electrode as shown in FIG. 13, the typical resistance value of the resistance element 134 is about 600 MΩ, but is not particularly limited to this value. In the drawing, 130 is a buried insulating film, and 132 is a plurality of buried insulating film electrodes formed in the buried insulating film. On the other hand, a typical resistance value of the resistance element 120 in the case of “capacitive coupling” as shown in FIG. 12 is about 1 k ohm, but is not particularly limited to this value.

Embodiment 4
The present embodiment relates to a semiconductor device which uses the high resistance element which is the characteristic configuration in the above-described embodiments and further provides a short-circuit protection function. Hereinafter, the semiconductor device 210 according to the present embodiment will be described in detail with reference to FIGS. This embodiment is characterized by the gate electrode control means in addition to the features of the above-described embodiments. Accordingly, the type of power device is not limited as long as the gate electrode is provided, but a vertical IGBT is taken as an example here. As shown in FIG. 14, the semiconductor device in the present embodiment is substantially the same as that in the first embodiment except for the short circuit protection circuit 501, and thus the description of the individual configurations is omitted. The film 215, the gate electrode 220, the insulating film 223, the p base layer 219, the n + emitter layer 221, the emitter electrode 230, the collector electrode 216, the p + collector layer 217, the n + channel stopper region 229 in the outer peripheral portion 234, and the guard ring 222 , High resistance elements 530 and 532, a gate wiring 231, and a gate terminal (gate bonding pad) 232.

  The short circuit protection circuit 501 includes a gate resistor 505, a delay circuit unit 510, a short circuit determination circuit unit 520, and a cutoff circuit unit 550 provided between the gate terminal 232 and the gate wiring 231. In addition to the short-circuit protection circuit 501, a collector-emitter voltage detection (level conversion) unit 528 using high resistance elements 530 and 532 made of the same resistance element as the high resistance element 28 described in the first embodiment is provided. Prepare.

The delay circuit unit 510 outputs a gate drive signal input to the gate terminal 232 with a predetermined time delay, which will be described later, and is a well-known combination of two NOT (inverter) circuits, a resistor, and a capacitor as an actual circuit. Realized by technology (see FIG. 14). The output of the delay circuit unit 510 becomes one input of the short circuit determination circuit unit 520. The collector-emitter voltage detection (level conversion) unit 528 outputs a signal proportional to the IGBT collector-emitter voltage. Specifically, the collector-emitter voltage detection (level conversion) unit 528 uses high resistance elements 530 and 532 connected between the channel stopper region 229 of the outer peripheral part 234 and the emitter electrode 230. That is, the resistors are divided so that a desired level of detection voltage (divided voltage) is obtained.
Note that the output voltage of a desired level needs to be adapted to the logic level of the signal in the short circuit protection circuit, and in a state where a high voltage of, for example, 600 V is applied to both ends of the high resistance elements 530 and 532, It is set so that 15V, which is about the same as the gate drive signal, is output.
The output of the collector-emitter voltage detection (level conversion) unit 528 becomes the other input of the short circuit determination circuit unit 520. The short circuit determination circuit unit 520 receives the output of the delay circuit unit 510 and the output of the collector-emitter voltage detection (level conversion) unit 528, and is in a normal operation state or a short circuit state depending on the combination of these two signal levels. A control signal for discriminating is output.
Specifically, the output of the delay circuit unit 510 and the output of the collector-emitter voltage detection (level conversion) unit 528, that is, the delayed gate drive signal and the resistance-divided collector-emitter signal (voltage) level. When both are at the high level, the short circuit determination circuit 520 outputs a high level signal. This is a so-called 2-input AND logic, and is realized by a NOT circuit 540 and a NAND circuit 541 as an actual circuit. The cutoff circuit unit 550 receives the output of the short circuit determination circuit unit 520 and switches the electrical connection relationship between the gate wiring 231 (gate electrode 220) and the emitter electrode 230 by turning on and off. In this example, an N-type MOS transistor is used, and when the output of the short-circuit determination circuit unit 520 is at a high level, the gate wiring 231 (gate electrode 220) is short-circuited with the emitter electrode 230 to have the same potential (gate voltage is 0V). The
The gate resistor 505 provided between the gate terminal 232 and the gate wiring 231 has a low input signal level of the gate terminal 232, that is, the delay circuit unit 510 when the gate voltage is set to 0 V by the cutoff circuit unit 550. It is to prevent it from becoming.

  Hereinafter, the operation of the semiconductor device 210 of this embodiment will be described. A gate drive signal from the gate terminal 232 is transmitted to the gate electrode 220 via the gate resistor 505. On the other hand, the gate drive signal is also input to the delay circuit unit 510. The delay circuit unit 510 delays the gate drive signal by a predetermined time and outputs it to the NAND circuit 541.

  The NAND circuit 541 transmits a low level (0) signal to the NOT circuit 540 when both the delayed gate drive signal and the input from the outer peripheral portion 234 are at a high level. The NOT circuit 540 converts a low level signal into a high level signal, and outputs the shut-off circuit unit 550 in an on state. In this case, since the gate wiring 231 is grounded, a gate drive signal for turning on the IGBT to the gate electrode 220 is not transmitted.

  Here, the NAND circuit 541 regards the gate drive signal for turning on the power device as a high level signal. The input from the outer peripheral portion 234 is regarded as a high-level signal when a voltage (high voltage) corresponding to the turn-on of the power device is applied to the n + channel stopper region 229 arranged in the outer peripheral portion 234. . Therefore, since the NAND circuit 541 can perform output so that the gate wiring 231 is grounded when the main electrode of the power device is short-circuited, the semiconductor device 210 can be short-circuit protected. As described above, since the output of the delay circuit 510 and the output from the channel stopper region 229 are used as inputs, the short-circuit determination circuit unit 520 and the cutoff circuit unit 550 are used to ground the gate wiring 231. The unit 550 is a grounding unit for the gate wiring 231. The meaning of the grounding means is not limited to the configuration of the present embodiment, and means means for grounding the gate wiring for short-circuit protection from the information of the gate drive signal and the voltage of the semiconductor layer.

  Here, the optimum delay time of the gate drive signal to be set by the delay circuit unit 510 of the present embodiment will be described. FIG. 15 shows each operation signal waveform of the IGBT during normal operation using the measurement circuit of FIG. First, the turn-on time t1 of the IGBT will be described with reference to FIG. In a general IGBT widely used today, a DC voltage of several hundred volts (hereinafter referred to as collector voltage, expressed as Vce) is applied between its collector and emitter in an off state. In this state, a voltage of about a dozen volts, generally about 15 V, is applied as a high-level signal between the gate and the emitter (hereinafter, a voltage applied between the gate and the emitter is referred to as a gate voltage and is expressed as Vge). A current flows from the collector to the emitter of the IGBT (hereinafter, this current is referred to as a collector current and expressed as Ic). As a result, the IGBT is turned on from the off state to the on state. On the other hand, when the gate voltage is set to a low level of 0 volts or minus several volts, the collector current is cut off. The turn-on time t1 is the time from when Vge starts to rise (to the high level) until Vce drops.

  Next, FIG. 17 shows each operation signal waveform of the IGBT when the short circuit is caused, that is, when the load (L) in the measurement circuit of FIG. 16 is short-circuited (SW on in the figure). With reference to this FIG. 17, t2 which is time for IGBT to deteriorate (thermal destruction) is demonstrated. For example, when the power supply is short-circuited due to a load short-circuit or malfunction of the application device (in this example, the load is short-circuited), even if Vge is set to the high level, the high voltage is maintained without lowering Vce. In such a case, the collector current Ic becomes excessive as shown in FIG. 17, causing deterioration such as thermal breakdown of the IGBT. Here, the time from when Vge starts to rise (to the high level) until Vce maintains the high level and the IGBT causes deterioration such as thermal breakdown is defined as t2.

  Based on the above, the time for which the delay circuit unit 510 delays the gate drive signal is set to t3 which is longer than t1 and shorter than t2. t3 will be described with reference to FIG. FIG. 18 shows waveforms of operation signals of the IGBT according to the present embodiment in the circuit in which a short circuit has occurred. As shown in this waveform, since t3 is longer than t1, when the IGBT performs a normal turn-on operation, the gate wiring 231 (gate electrode 220) and the emitter electrode 230 are set to the same potential (gate voltage) by the cutoff circuit unit 550. Is not 0V). On the other hand, since t3 is shorter than t2, when the power device is short-circuited and the collector current Ic becomes a large current, the gate wiring 231 (gate electrode 220) and the emitter electrode before the IGBT deteriorates (thermal destruction). 230 is set to the same potential (gate voltage is 0 V), and the IGBT is turned off. Therefore, according to the configuration of the present embodiment, short circuit protection that avoids the deterioration of the IGBT can be performed.

  FIG. 19 shows a simplified circuit diagram of the semiconductor device 231 of this embodiment.

  Various modifications can be considered for the short circuit protection circuit 501 in the present embodiment. For example, although the voltage of the outer peripheral portion 234 via the resistance element 530 is used as an input to the short circuit determination circuit unit 520, the effect of the present invention can be obtained if the short circuit determination circuit unit 520 has an input proportional to the Vce voltage. It is not limited to this. In addition, although the short circuit determination circuit unit 520 performs the grounding by connecting the emitter electrode 230 and the gate wiring 231, the gate wiring 231 may be grounded by another method.

  The power supply voltages of the delay circuit unit 510 and the short circuit determination circuit unit 520 constituting the short circuit protection circuit 501 are not only supplied via a dedicated power supply terminal, but also a voltage generated by the gate drive signal of the gate terminal 232, a high resistance A voltage obtained by resistance division using the elements 530 and 532 may be used. In this way, the semiconductor device can be miniaturized as much as no power supply bonding pad is required, as compared with the case where a dedicated power supply is provided.

By the way, the technical idea of this embodiment can be applied to a horizontal power device in which a gate, a source, and a drain are formed on the surface of a semiconductor layer, for example. FIG. 20 is a diagram showing such an example. FIG. 20 shows a semiconductor device in which the high-resistance element which is the characteristic configuration (FIG. 8) in the above-described second embodiment is further provided with a short-circuit protection function. The configuration shown in FIG. 20 is substantially the same as that of the second embodiment except for the short-circuit protection circuit 501, and the short-circuit protection circuit is the same as that described above in the present embodiment.
That is, the configuration of the power device shown in FIG. 20 includes an n− layer semiconductor layer 272, an n + drain 274, a drain electrode 276, a p base region 280, an n + source 291, a p + region 293, a source electrode 278, This embodiment is the same as Embodiment 2 in that an insulating film 284, a gate electrode 282, an in-insulating film electrode 286, a high resistance element 530, a high resistance element 532, a gate wiring 281 and a gate terminal 283 are provided. 20 includes a gate resistor 505, a delay circuit unit 510, a short circuit determination circuit unit 520, a cutoff circuit unit 550, and a high resistance element 530 provided between the gate terminal 283 and the gate wiring 281. And a drain-source voltage detection (level conversion) unit 598 using 532. Including the grounding means, which can be understood from the above description, will not be described in detail.

  Further, when the invention of short circuit protection described in the present embodiment is combined with the withstand voltage holding technology described in Embodiment 1 or 2, the performance of the semiconductor device can be further improved. Here, a resistance element used for holding a withstand voltage (referring to the high resistance element 28 in FIG. 1) and a resistance element used for short circuit protection (referring to the resistance elements 530 and 532 in FIG. 14) Can be formed by one resistive element. A plan view of such a semiconductor device is shown in FIG. 21 with the same reference numerals as those in FIG. 14 are the same as those in FIG. 14 and thus will not be described. The relationship between the two is the same as the relationship between FIG. 1 and FIG. As shown in FIG. 21, a collector-emitter voltage detection (level conversion) unit 528 formed in a single spiral shape connects the channel stopper region 229 and the emitter electrode 230. The short-circuit protection circuit 501 is formed in a region close to the gate terminal (bonding pad) 232 that can be said to be suitable for layout.

  The collector-emitter voltage detection (level conversion) unit 528 is connected to the guard ring 222 and the contact 258 in the middle thereof to form a resistance element corresponding to the high resistance element 28 in FIG. In addition, a voltage branched from between the resistance element 530 and the resistance element 532 obtained by resistance-dividing the collector-emitter voltage detection (level conversion) unit 528 is connected to one input of the short-circuit determination circuit 520 in the short-circuit protection circuit 501. . By using such a collector-emitter voltage detection (level conversion) unit 528, it is possible to protect the semiconductor device from short circuit and maintain a withstand voltage with a simple configuration.

  Various other examples of the above-described spiral collector-emitter voltage detection (level conversion) unit 528 are conceivable. For example, a linear high resistance element 270 shown in FIG. Alternatively, a step-like high resistance element 279 shown in FIG. 23 may be used. The effect of using such a resistance element is as described above. In the case of FIGS. 22 and 23, since a plurality of high resistance elements are formed, the voltage obtained by dividing each of the high resistance elements by resistance is somewhat varied regardless of whether it is for guard rings or for Vce detection. May occur. For this reason, a portion having the same potential in the design may reinforce electrical connection by aluminum wiring or the like. For example, an enlarged plan view of a region surrounded by a broken line C in FIG. 22 shown in FIG. This is realized as shown in a cross-sectional view along broken line DD in FIG. In FIG. 24, reference numerals 601 and 602 denote conductor patterns (wirings) such as aluminum, 603 denotes a contact connecting the high resistance element and the conductor pattern, and 604 denotes a contact connecting the guard ring and the conductor pattern.

  By the way, in general, in a vertical power device, in order to suppress parasitic capacitance, it is desirable that the elements constituting the short circuit protection circuit 501 described in this embodiment be formed on an SOI. It is also beneficial to facilitate adjustment of the time constant of the delay circuit unit 510 by forming (preparing) the short-circuit protection circuit 501 described in this embodiment as a chip separate from the chip that forms the power device. is there.

  Therefore, it is conceivable that the substrate on which the power device is formed and the substrate on which the delay circuit unit 510 and the short circuit determination circuit unit 520 are formed are separate substrates. In such a case, for example, the configuration shown in FIG. FIG. 25 shows a configuration in the case where the NOT circuit 540 in FIG. 14 performs output via a flip-flop circuit that is a circuit that maintains the state. When a flip-flop circuit is used, the presence / absence of a gate resistor, its resistance value, and the arrangement position can be set freely.

  As shown in FIG. 25, a semiconductor substrate 320 is formed on the emitter electrode 230 via a conductive bonding agent 318 such as solder. On the semiconductor substrate 320, a P-well region 322 and an N-well region 324 for the CMOS constituting the above-described flip-flop circuit are formed. In addition to the flip-flop circuit, a delay circuit 510 and a short circuit determination circuit unit 520 are formed on the semiconductor substrate 320. In this way, by forming a flip-flop circuit (including the delay circuit unit 510 and the short circuit determination circuit unit 520) on a substrate different from the substrate on which the power device is formed, it is possible to cope with design changes such as power devices. Can be handled with some changes.

  Furthermore, when a CMOS is formed as shown in FIG. 25, it is desirable to have a sufficient tolerance against latch-up associated with the formation of parasitic elements. Therefore, latch-up can be suppressed by forming an insulating film 356 immediately below the drain 352 of the NMOS 350 and the drain 354 of the PMOS 351 as shown in FIG. Further, by separating the P well region 322 and the N well region 324 by the T-shaped insulating film 340 as shown in FIG. 27, more effective latch-up can be suppressed. By providing these insulating films, latch-up can be suppressed and the chip can be downsized.

Embodiment 5
The present embodiment relates to a semiconductor device that applies a gate drive signal only to an on state (steady state) with respect to a specific gate electrode for short circuit protection. The configuration of this embodiment will be described with reference to FIG. A power device having a guard ring is the same as the IGBT described in the first embodiment. Differences from the first embodiment will be described. First, the gate electrode 409 is connected to the gate terminal 432 through the gate resistor 430 by the gate wiring 431. On the other hand, gate electrode 408 and gate electrode 411 are connected to gate terminal 432 via NOT circuit 428 and NOR circuit 420.

  The aforementioned NOR circuit 420 receives the output of the NOT circuit 428 and the voltage of the outer peripheral portion 34 via the resistance element 418 as inputs. More specifically, the NOR circuit 420 outputs a gate drive signal to the gate electrodes 408 and 411 when the output of the NOT circuit is low level (0) and the potential of the outer peripheral portion 34 is low level, that is, lower than Vce at the time of short circuit. Output.

  Therefore, the gate drive signal (to turn on the power device) is applied to the gate electrodes 408 and 411 because the gate drive signal transmitted from the gate terminal 432 is high (to turn on the power device). This is limited to the case where the voltage is Vce and the Vce voltage is considerably low during normal operation (low level). Therefore, in other cases, for example, at the time of turn-on or in a short circuit state, the gate drive signal for turning on the power device is not applied to the gate electrodes 408 and 411. The above-described configuration in which a gate drive signal is not directly transmitted to a specific gate electrode is particularly referred to as a gate drive signal supply unit.

  According to such a gate drive signal supply means, in the short circuit state where Vce becomes a high voltage, the gate electrodes 408 and 411 are not supplied with the gate drive signal to be turned on and are maintained in the off state. Can improve the short circuit resistance. In addition, since a gate drive signal to be turned on is applied to the gate electrodes 408 and 411 during normal operation when Vce is lowered, the element resistance in the on state of the semiconductor device 400 can be reduced, and the steady loss can be reduced. Furthermore, the resistance elements 416 and 418 can be appropriately connected to the guard ring 22 to have the above-described function of maintaining the withstand voltage.

  The feature of this embodiment is that a plurality of gate electrodes are composed of a gate electrode to which a gate drive signal is directly applied and a gate electrode that is turned on only in a steady state. Accordingly, various modifications can be made without departing from the scope of the present invention. For example, as shown in FIG. 29, a PMOS 460 that includes an OR circuit 450 that receives an input from the NOT circuit 428 and an input from the outer peripheral portion 34 and is turned on with respect to a low level output (0) of the OR circuit 450; Even if the configuration includes the NMOS 462 that is turned on with respect to the high-level output (1) of the OR circuit and grounds the gate wiring 465, the effect of the present invention is not lost.

DESCRIPTION OF SYMBOLS 10 Semiconductor device, 18 Semiconductor layer, 20 Gate electrode, 22 Guard ring, 28 High resistance element, 29 Channel stopper area | region, 30 Emitter electrode, 34 Outer peripheral part

Claims (5)

A power device formed on a semiconductor substrate having a semiconductor layer;
A plurality of guard rings formed on the semiconductor substrate so as to surround the power device;
Voltage applying means for applying a higher voltage to the outer peripheral guard ring among the plurality of guard rings,
The power device is
A grounded emitter electrode formed on the surface of the semiconductor substrate;
A gate electrode formed on the surface of the semiconductor substrate;
A collector electrode formed on the back surface, which is the surface opposite to the semiconductor substrate surface,
The voltage application means has a plurality of resistance elements connected in series between the outer peripheral portions of the plurality of guard rings of the semiconductor layer and the emitter electrode,
The semiconductor device according to claim 1, wherein the guard ring on the outer peripheral side is connected to the resistor element on the outer peripheral portion side among the plurality of resistive elements directly or via a conductor pattern. The plurality of resistance elements are on the plurality of guard rings,
The semiconductor device according to claim 1, wherein the plurality of resistance elements are formed of a single polycrystalline silicon.   The semiconductor device according to claim 2, wherein the one polycrystalline silicon is formed in a spiral shape on the plurality of guard rings.   3. The semiconductor device according to claim 2, wherein the single polycrystalline silicon is linearly formed on the plurality of guard rings.   3. The semiconductor device according to claim 2, wherein the single polycrystalline silicon is formed in a zigzag manner on the plurality of guard rings.

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