JP2007123926A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent breakdown of an insulating film by easing an electric field applied to the insulting film in which a resistor element is formed. <P>SOLUTION: A semiconductor device includes a high voltage part of a switching regulator. The perimeter of a FET for a main switch and a FET for a starter switch of the FET for the main switch is surrounded in multiple states with a plurality of field limiting rings. A field insulating film is formed on the field limiting rings. On the field insulating film, the resistor element is connected electrically to a drain and gate of the FET for the starter switch on the same layer as a gate of the FET. An interlayer dielectric film covers the resistive element. A plurality of wirings are formed on the interlayer dielectric film, and electrically connected to the gate and source of the FET, respectively. A back electrode is formed on the backside of the semiconductor substrate, and electrically connected to the drains of the FET for the main switch and the FET for the starter switch. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a technique effective when applied to a semiconductor device having a resistance that requires a high breakdown voltage.

  A semiconductor device is mounted on a substrate with other components or the like and used as an electronic device. Such an electronic device is driven by a DC power supply, and therefore, in normal use, an AC-DC converter for obtaining a DC power supply from an AC power supply that is a commercial power supply, and further, the obtained DC power supply varies from circuit to circuit. A DC-DC converter for supplying a plurality of voltages is required. Such a power supply circuit such as an AC-DC converter or a DC-DC converter supplies DC power by being incorporated in an electronic device or provided as an external adapter.

  In such a power supply circuit, components that are difficult to be integrated are used, such as a transformer for transformation, a large capacity capacitor for smoothing, and a choke coil. Therefore, the control circuit that processes a low-power signal is integrated into a discrete circuit. A combination method has been taken. For this reason, there is a limit to downsizing the power supply circuit.

  However, as electronic devices have become smaller and other circuits have become increasingly smaller due to integration, the specific gravity of the power supply circuit in the volume or weight of the electronic device has become relatively high. The power supply circuit is also required to be greatly reduced in size, and this trend will be further advanced in the future.

  As such a power source, a switching regulator is frequently used. In switching regulators, once the AC input voltage is rectified, it is converted to AC by a transistor on / off circuit, and then converted to DC again by a rectifier circuit to produce an output voltage, but the transistor is pulse-controlled on / off operation. Therefore, conversion efficiency is high because there is little loss. In addition, by increasing the switching frequency, it is possible to reduce the size of the transformer, choke coil, capacitor, and the like. A circuit example of such a switching regulator is shown in FIG.

  In the switching regulator (shown by a broken line), a high-voltage unit (shown by a two-dot chain line) including a main switch MS, a starter switch SS, and a high-resistance starting resistor SR configured by a power MISFET, and a control unit that processes a small voltage signal. It is made up of. In order to integrate such a switching regulator into an integrated circuit, it is necessary to integrate a high voltage portion.

  At present, the AC voltage of commercial power supplies varies from country to country, for example, 100V or 200V in Japan, 115V in the United States, and 220V to 240V in Europe.

  A switching regulator connected to a 240V AC rectified DC power supply requires a maximum withstand voltage of about 700V, and in order to guarantee this figure as a product value, the high voltage portion requires a design value of a maximum withstand voltage of about 750V. Become. Moreover, it is desirable that the breakdown at the time of applying a high voltage is performed at a portion other than the surface portion in an element having a large area. Specifically, it is desirable to avoid breakdown with a starting resistor element having a small area and easily yielding on the surface, and to yield with a power MISFET having a large area and difficult to yield on the surface. For this reason, if the withstand voltage of the power MISFET is set to 750V to 800V, the withstand voltage of the starting resistance element is preferably set to 800V or more.

  Among the elements constituting the high voltage section, MISFETs have been established with a technique for ensuring a withstand voltage as a single device, and these techniques can be used. However, with regard to a high breakdown voltage high resistance resistive element serving as a starting resistance, such a high breakdown voltage resistance element of 800 V or higher has not been integrated so far and there is no other example, so that new development is advanced. There is a need.

  When forming such a high breakdown voltage high resistance resistive element, it may be possible to form a resistive element on the field insulating film, but in a switching regulator, the semiconductor substrate is biased to a positive potential by the high voltage. In a normal field insulating film, a high electric field due to the high voltage is applied, and the field insulating film may be destroyed. Therefore, the withstand voltage is limited by the thickness of the field insulating film. If the field insulating film is thickened in order to prevent such breakdown of the field insulating film, the time required for the oxidation treatment for forming the field insulating film becomes long, and it is difficult to realize the actual solution. In addition, when the field insulating film is thickened, the level difference becomes large, and there arises a problem that it becomes difficult to uniformly apply the photoresist.

  In addition, it is conceivable to use a depletion type MISFET as a resistor, but there is a problem that there is a large variation in the resistance value of the formed resistor. If the impurity concentration in the depletion region is increased to a deep depletion, this variation can be suppressed to some extent, but there is a problem that the breakdown voltage is lowered. Further, the chip size is increased in order to form the resistance element in the active region.

Further, SGS Thomson Co., Ltd. has adopted a technology in which a resistance element is formed in a spiral shape when the switching regulator is integrated into a circuit, the central portion thereof is connected to a high potential, and the outer peripheral portion is connected to a ground potential. However, in the experiments by the inventors, there is a problem that the resistance value of the resistance element decreases and a large current flows when the applied voltage increases.
Further, since this resistance element is also formed in the active region, it is considered that the chip size is increased, and further, a parasitic operation is caused with other elements.
Such spiral resistance elements are described in, for example, IEEE Transaction on Electron Devices, vol 44 (No. 11, November, 1997), pages 2002 to 2010.

An object of the present invention is to provide a technique capable of solving the above-described problems and forming a resistance element having a high breakdown voltage and a high resistance.
The above and other problems and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.

In a semiconductor device in which a floating diffusion layer is formed in a ring shape on the main surface of a semiconductor substrate, a resistance element is formed on the diffusion layer via an insulating film.
Further, in a semiconductor device in which a plurality of annular diffusion layers are formed on the main surface of the semiconductor substrate, a resistance element is formed on the plurality of diffusion layers via an insulating film, and the resistance element and the diffusion layer are respectively provided. Electrically connected.

  The manufacturing method includes a step of forming a floating diffusion layer in a ring shape on the main surface of the semiconductor substrate, and a step of forming a resistance element on the diffusion layer via an insulating film.

(Function)
According to the above-described means, when a high voltage is applied, the difference between the electric field generated in the resistance element and the electric field generated in the diffusion layer becomes an electric field applied to the insulating film, so that the electric field applied to the insulating film is reduced. Therefore, it is possible to prevent the insulating film from being broken.

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
(1) According to the present invention, when a high voltage is applied, the difference between the electric field generated in the resistance element and the electric field generated in the FLR becomes an electric field applied to the field insulating film, so that the electric field applied to the field insulating film is reduced. There is an effect that can be done.
(2) According to the present invention, the effect (1) has an effect of preventing the field insulating film from being broken.
(3) According to the present invention, the effect (2) has an effect that a high voltage resistance can be formed on the field insulating film.
(4) According to the present invention, the chip size can be reduced by the effect (3).

Embodiments of the present invention will be described below.
Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
2 is a plan view showing a schematic configuration of a semiconductor device according to an embodiment of the present invention, FIG. 3 is an enlarged plan view of a main part showing a resistance element SR in FIG. 2, and FIG. 2 is a longitudinal sectional view showing the main switch MS in FIG. 2, FIG. 5 is a longitudinal sectional view showing an outer peripheral portion in which the starter switch SS and the resistance element SR in FIG. 2 are not provided, and FIG. It is a longitudinal cross-sectional view which shows the outer peripheral part in which the starter switch SS and resistance element SR in FIG. 2 were provided.

  The semiconductor device according to the present embodiment is formed by integrating a MISFET MS serving as a main switch constituting a high voltage portion of a switching regulator, a MISFET SS serving as a starter switch, and a resistance element serving as a starting resistor SR into an integrated circuit. .

  The MISFET MS and the MISFET SS are formed on a semiconductor substrate in which an n− type layer 2 is formed by, for example, epitaxial growth on an n + type semiconductor substrate 1 made of, for example, single crystal silicon.

  In these MISFETs, a plurality of cells having a planar structure are regularly arranged in a region surrounded by a field insulating film 3 provided in a rectangular ring shape having arcuate corners along the outer periphery of a semiconductor substrate. Each gate 5 of the adjacent cells provided on the main surface of the substrate via the gate insulating film 4 is connected to each other, and has a mesh gate structure in which the cells are connected in parallel. Each gate 5 of the outer peripheral cell is connected to a gate wiring 6 using, for example, polycrystalline silicon at the outer peripheral portion of the cell region, and this gate wiring 6 is connected to a gate pad which is a connection region of the gate 5.

  In each cell, the n − type layer 2 formed on the semiconductor substrate 1 serves as a drain region, and the p type layer 7 formed on the main surface of the semiconductor substrate serves as a base region in which a channel is formed. The formed n + -type layer 8 is a vertical FET serving as a source region.

  The gate wiring 6 is formed in an upper layer via an interlayer insulating film 9 and is electrically connected to a gate guard ring 10 using, for example, aluminum containing silicon. The n + type layer 8 serving as a source is electrically connected to a source wiring 11 using, for example, aluminum containing silicon, and the source wiring 11 is formed on the main surface of the semiconductor substrate via an interlayer insulating film 9. ing. In addition to the n + -type layer 8 serving as the source, the source wiring 11 is also electrically connected to a p + -type contact layer 12 provided in the p-type layer 7 in order to make the base potential constant.

An FLR (Field Limiting) in which a plurality of rings 13 made of floating p-type diffusion layers are arranged concentrically below the field insulating film 3 provided in a rectangular ring shape having arcuate corners along the outer periphery of the semiconductor substrate. Ring) is provided. In this FLR, the depletion layer extends from the inner ring 13 to the outer ring 13 and punches through before the avalanche breakdown occurs as the applied voltage increases. Yield at the junction of ring 13.
Further, as described above, it is desirable that the breakdown at the time of applying a high voltage is performed at a portion other than the surface portion of an element having a large area. For this reason, in order to avoid the breakdown in the FLR which has a small area and easily yields on the surface, and to cause the breakdown in the power MISFET which has a large area and is difficult to yield on the surface, if the power MISFET has a withstand voltage of 750V to 800V, the withstand voltage of the FLR Is 800 V or higher.

Since the breakdown voltage of this FLR is theoretically the sum of the punch-through breakdown voltage between the rings 13 and the breakdown voltage of the outermost ring, the breakdown voltage can be increased by increasing the number of rings 13, but the termination length is reduced. Considering this, there are four rings 13 in the present embodiment.
A resistance element SR is formed on the field insulating film 3 on which the FLR is formed. The resistance element SR is made of, for example, polycrystalline silicon containing p-type impurity such as boron or n-type impurity such as phosphorus, and is meandered in a direction orthogonal to each ring 13 of the FLR, as is apparent from FIG. (However, in the cross-sectional view, it is simplified in a straight line for easy understanding conceptually). The resistance element SR has a flat shape in order to increase the surface area relative to the cross-sectional area in consideration of heat dissipation.

When a high voltage is applied, the difference between the electric field generated in the resistance element SR and the electric field generated in the FLR becomes an electric field applied to the field insulating film 3 positioned therebetween. For this reason, the electric field applied to the field insulating film 3 can be relaxed by forming the resistance element SR on the field insulating film 3 on which the FLR is formed. Therefore, the resistance element SR is provided outside the outermost ring 13 of the FLR, and the electric field applied to the field insulating film 3 is minimized by making the electric field generated in the resistance element SR substantially the same as the electric field generated in the FLR. be able to.
Further, on the outer periphery of the field insulating film 3, a guard ring 14 is provided in which a wiring 14b using aluminum containing silicon is connected to an n + type semiconductor region 14a provided on the main surface of the semiconductor substrate. The wiring 14b of the ring 14 is connected to one end of the resistance element SR and is electrically connected to the drain, and the other end of the resistance element SR is connected to the gate of the starter switch SS. The drain connection region is the entire back surface of the semiconductor substrate. In addition, the drain electrode that is electrically connected to the n + type semiconductor substrate 1 is formed as a laminated film in which, for example, nickel, titanium, nickel, and silver are laminated.

  The relationship between the resistance elements SR and FLR in the semiconductor device of the present invention will be described. First, FIG. 7 is a longitudinal sectional view showing a potential distribution when a resistance element is formed on a field insulating film without providing an FLR. 7A shows a case where a high potential is directly applied to the resistance element SR, and FIG. 7B shows a case where a high potential is applied to the resistance element SR via the drain region. In any case, the equipotential lines appear densely in the lateral direction with respect to the field insulating film 3 due to the electric field generated in the resistance element SR when a high voltage is applied. That is, the potential changes rapidly in the vertical direction, and this sudden change in potential causes dielectric breakdown of the field insulating film 3.

FIG. 8 is a longitudinal sectional view showing a potential distribution in the case of the present invention in which an FLR is provided and a resistance element is formed on a field insulating film. 8A shows the case where a high potential is directly applied to the resistance element SR, and FIG. 8B shows the case where a high potential is applied to the resistance element SR via the drain region. In any case, the equipotential line extends vertically with respect to the field insulating film 3 due to the electric field generated in the resistance element SR and the electric field generated in the FLR (a depletion layer is indicated by a broken line) when a high voltage is applied. Appear at intervals. That is, the potential changes gently in the lateral direction, and the electric field applied to the field insulating film 3 can be relaxed, so that it is possible to prevent the field insulating film 3 from being broken when a high voltage is applied.
In this way, it becomes possible to prevent the dielectric breakdown of the field insulating film 3, whereby the resistance element SR can be disposed on the field insulating film 3. For this reason, it is not necessary to provide a region of a resistance element in the active region, so that the chip size can be reduced.

  On the other hand, for example, when the depletion type MISFET shown in FIG. 9 is used as the resistor, there is a problem that the resistance value of the formed resistor varies greatly. If the impurity concentration in the depletion region is increased to a deep depletion, this variation can be suppressed to some extent, but there is a problem that the breakdown voltage is lowered. Further, the chip size is increased in order to form the resistance element in the active region.

In addition, as shown in FIG. 10, when a resistance element (SJT) is formed in a spiral shape, the central portion thereof is connected to a high potential, and the outer peripheral portion is connected to a ground potential, the resistance element is increased when the applied voltage increases. There is a problem that a large current flows due to a decrease in resistance value.
Further, since this resistance element is also formed in the active region, it is considered that the chip size is increased, and further, a parasitic operation is caused between the resistance element and other elements.
On the other hand, the resistance element of the present invention does not increase the number of processes and does not cause a parasitic operation with other elements.

  FIG. 11 is a graph showing the results of measuring the voltage-current characteristics after forming the resistance element of the present invention by changing the sheet resistance. When the sheet resistance is high, the resistance value decreases due to heat generation of the resistance element as the applied voltage increases. Therefore, in order to make the voltage-current characteristic linear, the sheet resistance needs to be 10 kΩ / □ or less.

  FIG. 12 is a graph showing the results of measuring the temperature-sheet resistance characteristics after forming the resistance element of the present invention while changing the impurity concentration. It can be understood from this graph that a resistance element having a large sheet resistance has a negative temperature characteristic, and that the resistance change with temperature increases as the sheet resistance increases.

  Further, in the present embodiment, the semiconductor device in which the high voltage portion of the switching regulator is integrated and the control circuit is a separate chip has been described. With this configuration, it is possible to use semiconductor substrates suitable for the high voltage section and the control circuit. However, in the case of further integration, as shown in FIG. 13, the present invention can be applied as a switching regulator semiconductor device in which a control circuit is integrated.

Next, the manufacturing method of the semiconductor device described above will be described for each process with reference to FIGS. In each drawing, the MISFET portion is shown on the left side, and the resistance element portion in the same process is shown on the right side.
First, an n− type layer 2 is formed by epitaxial growth on an n + type semiconductor substrate 1 made of single crystal silicon into which, for example, arsenic (As) is introduced. Then, a p-type well serving as the FLR ring 13 is formed in the n − -type layer 2, a silicon oxide film is formed on the main surface of the semiconductor substrate, for example, by a thermal oxidation method, and silicon nitride is formed on the silicon oxide film. A mask of (SiN) film is formed, and the field insulating film 3 is formed by selective thermal oxidation using the silicon nitride film as a mask. This state is shown in FIG.

  Next, a gate insulating film 4 formed by laminating a silicon oxide film by CVD (Chemical Vapor Diposition) on the thermal oxide film or the thermal oxide film is formed on the main surface of the semiconductor substrate, and the gate 5 or the resistance element SR is formed on the entire main surface of the semiconductor substrate. A polycrystalline silicon film 5 ′ to be a conductive film is formed by CVD, and for example, phosphorus is formed in the region to be the gate 5 and boron is formed in the region to be the conductive film of the resistance element SR. Is introduced. This state is shown in FIG.

  Next, the polycrystalline silicon film 5 ′ is patterned by etching to form the gate 5 and the conductive film of the resistance element SR, and the p-type layer 7, n + type layer 8 and contact layer 12 of the MISFET are masked by photolithography. It is formed by ion implantation using At this time, a p + type layer (in the case where the conductive film is n-type, an n + type layer) is formed at both ends of the conductive film of the resistance element SR. This state is shown in FIG.

  Next, a PSG (Phosphorus Silicate Glass) film, for example, is deposited on the entire main surface of the semiconductor substrate, and an SOG (Spin On Glass) film is applied and formed to form an interlayer insulating film 9. An opening for exposing the connection region of the n + -type layer 8, the gate wiring 6, and the resistance element SR serving as the source region is provided. This state is shown in FIG.

  Next, a conductive film (metal film) made of, for example, aluminum containing silicon is formed on the entire surface of the main surface of the semiconductor substrate including the inside of the opening, and the metal film is patterned to form a gate guard ring 10, a source wiring 11, A guard ring 14 is formed, for example, a polyimide film is applied and laminated on a silicon oxide film by plasma CVD using tetraethoxysilane (TEOS) gas as a main source gas, and a protective insulating film 15 is formed to cover the entire main surface of the semiconductor substrate. Then, the back surface of the n + type semiconductor substrate 1 is ground, and the drain electrode 16 in which nickel, titanium, nickel, and silver are sequentially laminated is formed on the back surface by, for example, vapor deposition, resulting in the state shown in FIG.

  As described above, since the resistance element of the present invention can be formed by using another element formation process, the number of processes is not increased.

(Embodiment 2)
FIG. 19 is an enlarged plan view of a principal part showing a resistance element SR of a semiconductor device according to another embodiment of the present invention, and FIG. 20 shows an outer peripheral part provided with the starter switch SS and the resistance element SR. It is a longitudinal cross-sectional view shown. Note that the wiring 17 that connects the resistance element SR and the ring 13 includes an opening provided on the ring 13 and a resistance as shown in cross sections AA ′, BB ′, and CC ′ in FIG. The opening provided on the element SR is connected. In FIG. 20, the ring 13 and the resistance element SR are directly connected for easy understanding conceptually.

  The semiconductor device according to the present embodiment is formed by integrating a MISFET MS serving as a main switch constituting a high voltage portion of a switching regulator, a MISFET SS serving as a starter switch, and a resistance element serving as a starting resistor SR into an integrated circuit. .

  The MISFET MS and the MISFET SS are formed on a semiconductor substrate in which an n− type layer 2 is formed by, for example, epitaxial growth on an n + type semiconductor substrate 1 made of, for example, single crystal silicon.

  In these MISFETs, a plurality of cells having a planar structure are regularly arranged in a region surrounded by a field insulating film 3 provided in a rectangular ring shape having arcuate corners along the outer periphery of a semiconductor substrate. Each gate 5 of the adjacent cells provided on the main surface of the substrate via the gate insulating film 4 is connected to each other, and has a mesh gate structure in which the cells are connected in parallel. Each gate 5 of the outer peripheral cell is connected to a gate wiring 6 using, for example, polycrystalline silicon at the outer peripheral portion of the cell region, and this gate wiring 6 is connected to a gate pad which is a connection region of the gate 5.

  In each cell, the n − type layer 2 formed on the semiconductor substrate 1 serves as a drain region, and the p type layer 7 formed on the main surface of the semiconductor substrate serves as a base region in which a channel is formed. The formed n + -type layer 8 is a vertical FET serving as a source region.

  The gate wiring 6 is formed in an upper layer via an interlayer insulating film 9 and is electrically connected to a gate guard ring 10 using, for example, aluminum containing silicon. The n + type layer 8 serving as a source is electrically connected to a source wiring 11 using, for example, aluminum containing silicon, and the source wiring 11 is formed on the main surface of the semiconductor substrate via an interlayer insulating film 9. ing. In addition to the n + -type layer 8 serving as the source, the source wiring 11 is also electrically connected to a p + -type contact layer 12 provided in the p-type layer 7 in order to make the base potential constant.

  An FLR (Field Limiting) in which a plurality of rings 13 made of floating p-type diffusion layers are arranged concentrically below the field insulating film 3 provided in a rectangular ring shape having arcuate corners along the outer periphery of the semiconductor substrate. Ring) is provided. In this FLR, the depletion layer extends from the inner ring 13 to the outer ring 13 and punches through before the avalanche breakdown occurs as the applied voltage increases. Yield at the junction of ring 13.

  Further, as described above, it is desirable that the breakdown at the time of applying a high voltage is performed at a portion other than the surface portion of an element having a large area. For this reason, in order to avoid the breakdown in the FLR which has a small area and easily yields on the surface, and to cause the breakdown in the power MISFET which has a large area and hardly yields on the surface, if the power MISFET has a withstand voltage of 750V to 800V, the withstand voltage of the FLR Is 800 V or higher.

  Since the breakdown voltage of this FLR is theoretically the sum of the punch-through breakdown voltage between the rings 13 and the breakdown voltage of the outermost ring, the breakdown voltage can be increased by increasing the number of rings 13, but the termination length is reduced. Considering this, there are four rings 13 in the present embodiment.

  A resistance element SR is formed on the field insulating film 3 on which the FLR is formed. The resistive element SR is made of, for example, polycrystalline silicon containing boron, which is a p-type impurity, and is provided to meander in the direction orthogonal to each ring 13 of the FLR as shown in FIG. , Simplified in a straight line to make it easier to understand conceptually). The resistance element SR has a flat shape in order to increase the surface area relative to the cross-sectional area in consideration of heat dissipation.

  In the present embodiment, each ring 13 and the resistance element SR are electrically connected to each other at a plurality of locations by connection wirings 17 formed in openings provided in the field insulating film 3. By making such a connection, each potential is fixed.

  When a high voltage is applied, the difference between the electric field generated in the resistance element SR and the electric field generated in the FLR becomes an electric field applied to the field insulating film 3 positioned therebetween. For this reason, the electric field applied to the field insulating film 3 can be relaxed by forming the resistance element SR on the field insulating film 3 on which the FLR is formed. Therefore, the resistance element SR is provided outside the outermost ring 13 of the FLR, and the electric field applied to the field insulating film 3 is minimized by making the electric field generated in the resistance element SR substantially the same as the electric field generated in the FLR. be able to.

In the present embodiment, by connecting each ring 13 and the resistance element SR, the respective potentials are fixed, and errors generated in the electric field between the resistance elements SR and FLR are reduced, so that the field insulating film 3 is added. The electric field will be further relaxed.
Further, on the outer periphery of the field insulating film 3, a guard ring 14 is provided in which a wiring 14b using aluminum containing silicon is connected to an n + type semiconductor region 14a provided on the main surface of the semiconductor substrate. The wiring 14b of the ring 14 is connected to one end of the resistance element SR and is electrically connected to the drain, and the other end of the resistance element SR is connected to the gate of the starter switch SS. The drain connection region is the entire back surface of the semiconductor substrate. In addition, the drain electrode that is electrically connected to the n + type semiconductor substrate 1 is formed as a laminated film in which, for example, nickel, titanium, nickel, and silver are laminated.
Further, in the present embodiment, the semiconductor device in which the high voltage portion of the switching regulator is integrated and the control circuit is a separate chip has been described. With this configuration, it is possible to use semiconductor substrates suitable for the high voltage section and the control circuit. However, in the case of further integration, as shown in FIG. 13, the present invention can be applied as a switching regulator semiconductor device in which a control circuit is integrated.

  Next, a method for manufacturing the semiconductor device described above will be described. First, as shown in FIG. 14, an n − type layer 2 is formed by epitaxial growth on an n + type semiconductor substrate 1 made of, for example, single crystal silicon into which arsenic (As) is introduced. Then, a p-type well serving as the FLR ring 13 is formed in the n − -type layer 2, a silicon oxide film is formed on the main surface of the semiconductor substrate, for example, by a thermal oxidation method, and silicon nitride is formed on the silicon oxide film. A mask of (SiN) film is formed, and the field insulating film 3 is formed by selective thermal oxidation using the silicon nitride film as a mask.

  Next, a gate insulating film 4 formed by laminating a silicon oxide film by CVD (Chemical Vapor Diposition) on the thermal oxide film or the thermal oxide film is formed on the main surface of the semiconductor substrate, and the gate 5 or the resistance element SR is formed on the entire main surface of the semiconductor substrate. A polycrystalline silicon film 5 'to be a conductive film is formed by CVD. For example, phosphorus is introduced into the polycrystalline silicon film 5 ′ in the region to be the gate 5, and boron is introduced into the region to be the conductive film of the resistance element SR. This state is shown in FIG.

  Next, the polycrystalline silicon film 5 ′ is patterned by etching to form the gate 5 and the conductive film of the resistance element SR, and the p-type layer 7, n + type layer 8 and contact layer 12 of the MISFET are masked by photolithography. It is formed by ion implantation using At this time, a p + type layer (in the case where the conductive film is n-type, an n + type layer) is formed at both ends of the conductive film of the resistance element SR. This state is shown in FIG.

  Next, a PSG (Phosphorus Silicate Glass) film, for example, is deposited on the entire main surface of the semiconductor substrate, and an SOG (Spin On Glass) film is applied and formed to form an interlayer insulating film 9. An opening for exposing the connection region of the n + -type layer 8, the gate wiring 6, and the resistance element SR serving as the source region is provided. This state is shown in FIG. At this time, in a cross section different from that shown in FIG. 17, openings are also provided on the ring 13 and the resistance element SR as shown in FIG.

  Next, a conductive film (metal film) made of, for example, aluminum containing silicon is formed on the entire surface of the main surface of the semiconductor substrate including the inside of the opening, and the metal film is patterned to form a gate guard ring 10, a source wiring 11, The guard ring 14 and the wiring 13 that connects the ring 13 and the resistance element SR are formed, and polyimide is applied and laminated on a silicon oxide film formed by plasma CVD using, for example, tetraethoxysilane (TEOS) gas as a main source gas. A protective insulating film 15 that covers the entire surface of the substrate main surface is formed, the back surface of the n + type semiconductor substrate 1 is ground, and a drain electrode 16 is formed on the back surface by sequentially depositing nickel, titanium, nickel, and silver, for example, by vapor deposition. Thus, the state shown in FIGS. 18 and 19 is obtained.

Although the invention made by the present inventor has been specifically described based on the above-described embodiment, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention. Of course.
For example, the present invention can be applied to a semiconductor device provided with an IGBT (Integrated Gate Bipolar Transistor) or the like in addition to a semiconductor device provided with a power MISFET.

It is a circuit diagram which shows the structure of a switching regulator. It is a top view which shows schematic structure of the semiconductor device which is one embodiment of this invention. FIG. 3 is a partial plan view showing a resistance element in FIG. 2. It is a fragmentary longitudinal cross-section which shows the main switch in FIG. FIG. 3 is a partial longitudinal sectional view showing an outer peripheral portion in which the starter switch SS and the resistance element SR in FIG. 2 are not provided. FIG. 3 is a partial longitudinal sectional view showing an outer peripheral portion provided with a starter switch SS and a resistance element SR in FIG. 2. It is a fragmentary longitudinal cross-section which shows the electric field by the resistive element provided on the field insulating film. It is a fragmentary longitudinal cross-section which shows the electric field by the resistance element provided on the field insulating film, and FLR. It is a fragmentary longitudinal cross-section which shows a depletion type resistance element. It is a fragmentary longitudinal cross-section which shows a spiral type resistance element. It is a graph which shows the characteristic of the resistance element of this invention. It is a graph which shows the temperature characteristic of the resistive element of this invention. It is a top view which shows schematic structure of the modification of this invention. It is a longitudinal cross-sectional view which shows the principal part of the semiconductor device which is one embodiment of this invention for every manufacturing process. It is a longitudinal cross-sectional view which shows the principal part of the semiconductor device which is one embodiment of this invention for every manufacturing process. It is a longitudinal cross-sectional view which shows the principal part of the semiconductor device which is one embodiment of this invention for every manufacturing process. It is a longitudinal cross-sectional view which shows the principal part of the semiconductor device which is one embodiment of this invention for every manufacturing process. It is a longitudinal cross-sectional view which shows the principal part of the semiconductor device which is one embodiment of this invention for every manufacturing process. It is a fragmentary top view which shows the resistive element of the semiconductor device which is other embodiment of this invention. It is a fragmentary longitudinal cross-section which shows the outer peripheral part in which the starter switch SS and resistance element SR of the semiconductor device which are other embodiment of this invention were provided.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... N-type layer (drain region), 3 ... Field insulating film, 4 ... Gate insulating film, 5 ... Gate, 6 ... Gate wiring, 7 ... P-type layer (channel formation region), 8 ... n + type layer (source region), 9 ... interlayer insulating film, 10 ... gate guard ring, 11 ... source wiring, 12 ... contact layer, 13 ... ring, 14 ... guard ring, 15 ... protective insulating film, 16 ... drain electrode, 17: Connection wiring.

Claims (5)

A semiconductor device including a high voltage portion of a switching regulator,
(a) a semiconductor substrate;
(b) a main switch MOSFET that is formed on the main surface of the semiconductor substrate and constitutes the high voltage portion;
(c) a starter switch MOSFET of the main switch MOSFET formed on the main surface of the semiconductor substrate;
(d) a plurality of field limiting rings formed on the main surface of the semiconductor substrate and surrounding the main switch MOSFET and the starter switch MOSFET in multiple layers;
(e) a field insulating film formed on the field limiting ring;
(f) A resistive element formed on the field insulating film, formed in the same layer as the gates of the main switch MOSFET and starter switch MOSFET, and electrically connected to the drain and gate of the starter switch MOSFET When,
(g) an interlayer insulating film covering the resistance element;
(h) a plurality of wirings formed on the interlayer insulating film and electrically connected to the gate and the source for the main switch and the gate and the source of the MOSFET for the starter switch;
(i) A semiconductor device including a back electrode formed on the back surface of the semiconductor substrate and electrically connected to the drains of the main switch MOSFET and the starter switch MOSFET. 2. The semiconductor device according to claim 1, wherein the planar shape of the resistive element is a meandering shape in a direction intersecting with the field limiting ring layer. 2. The semiconductor device according to claim 1, wherein the field limiting ring layer is in an electrically floating state. The resistive element is formed from a field limiting ring layer positioned on the inner side to a field limiting ring layer positioned on the outer side of the plurality of field limiting ring layers,
A first end of the resistive element close to the inner field limiting ring layer is electrically connected to a first potential;
A second end of the resistive element close to the outer field limiting ring layer is electrically connected to a second potential;
The semiconductor device according to claim 1, wherein the second potential is higher than the first potential. A semiconductor device including a high voltage portion of a switching regulator,
(a) a semiconductor substrate;
(b) a starter switch MOSFET formed on the main surface of the semiconductor substrate;
(c) a plurality of field limiting rings formed on the main surface of the semiconductor substrate and surrounding the periphery of the starter switch MOSFET;
(d) a field insulating film formed on the field limiting ring;
(e) a resistance element formed on the field insulating film, formed in the same layer as the gate of the starter switch MOSFET, and electrically connected to the drain and gate of the starter switch MOSFET;
(f) an interlayer insulating film covering the resistance element;
(g) a plurality of wirings formed on the interlayer insulating film and electrically connected to the gate and source of the starter switch MOSFET;
(h) A semiconductor device including a back electrode formed on the back surface of the semiconductor substrate and electrically connected to the drain of the starter switch MOSFET.

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