TWI750626B - Bidirectional power device - Google Patents

Bidirectional power device Download PDF

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TWI750626B
TWI750626B TW109111360A TW109111360A TWI750626B TW I750626 B TWI750626 B TW I750626B TW 109111360 A TW109111360 A TW 109111360A TW 109111360 A TW109111360 A TW 109111360A TW I750626 B TWI750626 B TW I750626B
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power device
bidirectional power
semiconductor layer
region
gate
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TW202034527A (en
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張邵華
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大陸商杭州士蘭微電子股份有限公司
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Abstract

A bidirectional power device is disclosed. The bidirectional power device includes: a semiconductor layer; a trench in the semiconductor layer; a gate dielectric layer on a sidewall of the trench; a control gate at a lower part of the trench; and a channel area in the semiconductor layer and adjacent to the control gate, wherein the control gate is isolated from the semiconductor layer by the gate dielectric layer. In the bidirectional power device provided by the invention, the channel area is adjacent to the control gate at the lower part of the trench, and the length of channels can be reduced by reducing the width of the trench, thereby reducing the resistance of the channels.

Description

雙向功率器件 Bidirectional Power Devices

本發明涉及半導體製造技術領域，特別涉及一種雙向功率器件。 The invention relates to the technical field of semiconductor manufacturing, in particular to a bidirectional power device.

功率器件主要用於大功率的電源電路和控制電路中，例如作為開關元件或整流元件。在功率器件中，不同摻雜類型的摻雜區形成PN結，從而實現二極體或電晶體的功能。功率器件在應用中通常需要在高電壓下承載大電流。一方面，為了滿足高電壓應用的需求以及提高器件可靠性和壽命，功率器件需要具有高擊穿電壓。另一方面，為了降低功率器件自身的功耗和產生的熱量，功率器件需要具有低導通電阻。在電源電路中，經常會涉及到充電和放電，然後充電和放電過程中電流的流向不同，則要求功率器件具有雙向導通的功能。 Power devices are mainly used in high-power power supply circuits and control circuits, such as switching elements or rectifying elements. In power devices, doped regions of different doping types form PN junctions, thereby realizing the functions of diodes or transistors. Power devices are often required to carry large currents at high voltages in applications. On the one hand, to meet the demands of high-voltage applications and to improve device reliability and lifetime, power devices need to have high breakdown voltages. On the other hand, in order to reduce the power consumption and the generated heat of the power device itself, the power device needs to have a low on-resistance. In the power supply circuit, charging and discharging are often involved, and then the current flows in different directions during the charging and discharging process, so the power device is required to have the function of bidirectional conduction.

在美國專利US5612566和US6087740公開了雙向導通類型的功率器件。其中，該雙向功率器件包括襯底以及位於襯底上的第一輸出極和第二輸出極。襯底為P型襯底或者P型外延或者P型摻雜的阱區；兩個輸出極分別由輕摻雜N-區和以及位於輕摻雜N-區中的重摻雜N+區構成。在功率器件的導通狀態，當第一輸出極與襯底短接時，電流從第二輸出極流向第一輸出極；當第二輸出極與襯底短接時，電流從第一輸出極流向第二輸出極。 Bidirectional conduction type power devices are disclosed in US patents US5612566 and US6087740. Wherein, the bidirectional power device includes a substrate and a first output pole and a second output pole located on the substrate. The substrate is a P-type substrate or a P-type epitaxy or a P-type doped well region; the two output electrodes are respectively composed of a lightly doped N- region and a heavily doped N+ region located in the lightly doped N- region. In the conduction state of the power device, when the first output pole is shorted to the substrate, the current flows from the second output pole to the first output pole; when the second output pole is shorted to the substrate, the current flows from the first output pole to the second output pole.

然而，雙向功率器件的耐壓特性和導通電阻之間是一對衝突參數。雖然可以通過降低輕摻雜N-區的雜質濃度，提高擊穿電壓，獲得較好的耐壓特性。但是由於輕摻雜N-區的雜質濃度降低，導致導通電阻的增加，從而增加功耗。 However, there is a pair of conflicting parameters between the withstand voltage characteristics and on-resistance of bidirectional power devices. Although it is possible to increase the breakdown voltage by reducing the impurity concentration of the lightly doped N-region, better withstand voltage characteristics can be obtained. However, due to the reduced impurity concentration in the lightly doped N- region, the on-resistance increases, thereby increasing the power consumption.

在雙向功率器件中，仍然需要進一步改進以兼顧耐壓特性和導通電阻的要求。 In bidirectional power devices, further improvement is still required to take into account the requirements of withstand voltage characteristics and on-resistance.

鑒於上述問題，本發明的目的在於提供一種雙向功率器件，其中，溝道區鄰近溝槽下部的控制柵，通過溝槽的寬度控制溝道長度，減小導通電阻。 In view of the above problems, the purpose of the present invention is to provide a bidirectional power device, wherein the channel region is adjacent to the control gate at the lower part of the trench, and the channel length is controlled by the width of the trench to reduce the on-resistance.

根據本發明的第一方面，提供一種雙向功率器件，包括：半導體層；位於半導體層中的溝槽；位於所述溝槽側壁上的柵介質層；位於所述溝槽下部的控制柵；以及位於所述半導體層中且鄰近所述控制柵的溝道區；其中，所述控制柵與所述半導體層之間由所述柵介質層隔開。 According to a first aspect of the present invention, there is provided a bidirectional power device, comprising: a semiconductor layer; a trench in the semiconductor layer; a gate dielectric layer on the sidewall of the trench; a control gate at a lower portion of the trench; and A channel region located in the semiconductor layer and adjacent to the control gate; wherein, the control gate and the semiconductor layer are separated by the gate dielectric layer.

優選地，所述雙向功率器件還包括：位於所述溝槽上部的遮罩柵。 Preferably, the bidirectional power device further comprises: a mask gate located on the upper part of the trench.

優選地，所述雙向功率器件還包括：位於所述控制柵和所述遮罩柵之間的隔離層。 Preferably, the bidirectional power device further comprises: an isolation layer between the control gate and the shadow gate.

優選地，所述遮罩柵的長度為0.6~1.2um。 Preferably, the length of the shield grid is 0.6-1.2um.

優選地，所述控制柵和所述遮罩柵彼此接觸。 Preferably, the control gate and the shadow gate are in contact with each other.

優選地，所述遮罩柵的長度為0.4~0.8um。 Preferably, the length of the shield grid is 0.4~0.8um.

優選地，所述雙向功率器件還包括：位於溝槽側壁上的遮罩介質層，所述遮罩柵與所述半導體層之間由所述遮罩介質層隔開。 Preferably, the bidirectional power device further comprises: a masking dielectric layer located on the sidewall of the trench, and the masking gate and the semiconductor layer are separated by the masking dielectric layer.

優選地，所述遮罩介質層的厚度為0.1~0.25um。 Preferably, the thickness of the mask dielectric layer is 0.1-0.25um.

優選地，所述遮罩介質層的厚度大於或等於所述柵介質層的厚度。 Preferably, the thickness of the mask dielectric layer is greater than or equal to the thickness of the gate dielectric layer.

優選地，所述控制柵的寬度大於所述遮罩柵的寬度。 Preferably, the width of the control gate is larger than the width of the mask gate.

優選地，所述雙向功率器件還包括：位於所述半導體層中且鄰近所述遮罩柵的源區和漏區，所述源區和漏區從所述半導體層的第一表面延伸至與所述控制柵交疊。 Preferably, the bidirectional power device further comprises: a source region and a drain region located in the semiconductor layer and adjacent to the mask gate, the source region and the drain region extending from the first surface of the semiconductor layer to a The control gates overlap.

優選地，所述源區和漏區的長度大於所述遮罩柵和隔離層的長度之和，小於所述遮罩柵、隔離層以及所述控制柵的長度之和。 Preferably, the lengths of the source region and the drain region are greater than the sum of the lengths of the mask gate and the isolation layer, and less than the sum of the lengths of the mask gate, the isolation layer and the control gate.

優選地，所述源區和漏區的長度大於所述遮罩柵的長度，小於所述遮罩柵以及所述控制柵的長度之和。 Preferably, the length of the source region and the drain region is greater than the length of the mask gate, and less than the sum of the lengths of the mask gate and the control gate.

優選地，所述雙向功率器件還包括：位於所述溝槽上部的分壓介質層。 Preferably, the bidirectional power device further comprises: a voltage dividing dielectric layer located on the upper part of the trench.

優選地，所述雙向功率器件還包括：位於所述半導體層中且鄰近所述分壓介質層的源區和漏區，所述源區和漏區從所述半導體層的第一表面延伸至與所述控制柵交疊。 Preferably, the bidirectional power device further comprises: source and drain regions located in the semiconductor layer and adjacent to the voltage dividing dielectric layer, the source and drain regions extending from the first surface of the semiconductor layer to overlaps the control gate.

優選地，所述分壓介質層的長度大於0.3um。 Preferably, the length of the partial pressure medium layer is greater than 0.3um.

優選地，所述源區和漏區的長度大於所述分壓介質層的長度，小於所述分壓介質層和所述控制柵的長度。 Preferably, the length of the source region and the drain region is greater than the length of the voltage dividing dielectric layer, and less than the lengths of the voltage dividing dielectric layer and the control gate.

優選地，所述控制柵從所述半導體層的第一表面延伸至所述溝槽下部。 Preferably, the control gate extends from the first surface of the semiconductor layer to the lower portion of the trench.

優選地，所述雙向功率器件還包括：位於所述半導體層中且鄰近控制柵的源區和漏區，所述源區和漏區從所述半導體層的第一表面延伸至與所述溝槽下部的控制柵交疊。 Preferably, the bidirectional power device further comprises: source and drain regions located in the semiconductor layer and adjacent to the control gate, the source and drain regions extending from the first surface of the semiconductor layer to the trenches The control gates in the lower part of the trenches overlap.

優選地，所述源區和漏區在所述半導體層中延伸的長度為0.5~1.5um。 Preferably, the length of the source region and the drain region extending in the semiconductor layer is 0.5-1.5um.

優選地，所述溝槽的長度為1.2~2.2um，寬度為0.1~0.6um。 Preferably, the length of the groove is 1.2~2.2um, and the width is 0.1~0.6um.

優選地，所述半導體層的摻雜類型為第一摻雜類型，所述源區和漏區的摻雜類型為第二摻雜類型，所述溝道區的摻雜類型為第一摻雜類型或第二摻雜類型，第一摻雜類型和第二摻雜類型相反。 Preferably, the doping type of the semiconductor layer is the first doping type, the doping type of the source region and the drain region is the second doping type, and the doping type of the channel region is the first doping type type or second doping type, the first doping type and the second doping type are opposite.

優選地，所述半導體層選自半導體襯底本身、在半導體襯底上形成的外延層或者在半導體襯底中注入的阱區中的一種。 Preferably, the semiconductor layer is selected from one of the semiconductor substrate itself, an epitaxial layer formed on the semiconductor substrate, or a well region implanted in the semiconductor substrate.

優選地，所述雙向功率器件還包括：第一接觸，與所述源區相接觸以形成第一輸出電極；第二接觸，與所述漏區相接觸以形成第二輸出電極；第三接觸，與所述半導體層相接觸以形成襯底電極；第四接觸，與所述控制柵相接觸以形成柵電極。 Preferably, the bidirectional power device further comprises: a first contact, in contact with the source region to form a first output electrode; a second contact, in contact with the drain region to form a second output electrode; a third contact The fourth contact is in contact with the semiconductor layer to form a substrate electrode; the fourth contact is in contact with the control gate to form a gate electrode.

優選地，所述雙向功率器件還包括：第一引線區，位於所述源區內，其中，第一引線區的摻雜濃度大於所述源區的摻雜濃度；覆蓋介質層，位於所述半導體層的第一表面上；第一接觸孔，貫穿所述 覆蓋介質層延伸至所述源區；所述第一接觸通過第一接觸孔、第一引線區與所述源區相接觸。 Preferably, the bidirectional power device further comprises: a first lead region located in the source region, wherein the doping concentration of the first lead region is greater than the doping concentration of the source region; a cover dielectric layer located in the source region on the first surface of the semiconductor layer; the first contact hole penetrates the The cover dielectric layer extends to the source region; the first contact is in contact with the source region through a first contact hole and a first lead region.

優選地，所述雙向功率器件還包括：第二引線區，位於所述漏區內，其中，第二引線區的摻雜濃度大於所述漏區的摻雜濃度；第二接觸孔，貫穿所述覆蓋介質層延伸至所述漏區；所述第二接觸通過第二接觸孔、第二引線區與所述漏區相接觸。 Preferably, the bidirectional power device further comprises: a second lead region located in the drain region, wherein the doping concentration of the second lead region is greater than the doping concentration of the drain region; a second contact hole penetrating the drain region The cover dielectric layer extends to the drain region; the second contact is in contact with the drain region through a second contact hole and a second lead region.

優選地，所述雙向功率器件還包括：第三引線區，位於所述半導體層內且靠近所述半導體層的第一表面，其中，所述第三引線區的摻雜濃度大於半導體層的摻雜濃度；第三接觸孔，貫穿所述覆蓋介質層延伸至所述半導體層；所述第三接觸通過第三接觸孔、第三引線區與所述半導體層相接觸。 Preferably, the bidirectional power device further comprises: a third lead region located in the semiconductor layer and close to the first surface of the semiconductor layer, wherein the doping concentration of the third lead region is greater than that of the semiconductor layer impurity concentration; a third contact hole, extending through the cover dielectric layer to the semiconductor layer; the third contact is in contact with the semiconductor layer through the third contact hole and the third lead region.

優選地，所述雙向功率器件還包括：第四接觸孔，貫穿所述覆蓋介質層延伸至所述控制柵。 Preferably, the bidirectional power device further includes: a fourth contact hole extending through the cover dielectric layer to the control gate.

優選地，所述第三接觸位於所述半導體層的第二表面上。 Preferably, the third contact is on the second surface of the semiconductor layer.

優選地，所述雙向功率器件還包括：佈線層，所述佈線層包括第一佈線至第四佈線，分別通過多個導電孔與所述第一輸出電極、第二輸出電極、襯底電極以及柵電極電連接。 Preferably, the bidirectional power device further includes: a wiring layer, the wiring layer includes a first wiring to a fourth wiring, which are connected to the first output electrode, the second output electrode, the substrate electrode and the first output electrode, the second output electrode, the substrate electrode and the The gate electrode is electrically connected.

優選地，所述雙向功率器件還包括：多個金屬焊球，位於所述佈線層上，通過佈線層與所述第一輸出電極、第二輸出電極、襯底電極以及柵電極電連接。 Preferably, the bidirectional power device further comprises: a plurality of metal solder balls located on the wiring layer and electrically connected to the first output electrode, the second output electrode, the substrate electrode and the gate electrode through the wiring layer.

優選地，當所述雙向功率器件包括位於控制柵上的遮罩柵時，第四接觸還與所述遮罩柵電連接。 Preferably, when the bidirectional power device includes a shadow grid on the control gate, the fourth contact is also electrically connected to the shadow grid.

優選地，所述遮罩柵與所述半導體層或所述控制柵電連接。 Preferably, the mask gate is electrically connected to the semiconductor layer or the control gate.

優選地，在所述雙向功率器件導通時，所述襯底電極與第一輸出電極和第二輸出電極之一電連接實現電流方向的雙向選擇。 Preferably, when the bidirectional power device is turned on, the substrate electrode is electrically connected to one of the first output electrode and the second output electrode to realize bidirectional selection of current direction.

優選地，當所述襯底電極與所述第一輸出電極電連接時，電流從所述第二輸出電極流向所述第一輸出電極；當所述襯底電極與所述第二輸出電極電連接時，電流從所述第一輸出電極流向所述第二輸出 電極。 Preferably, when the substrate electrode is electrically connected to the first output electrode, current flows from the second output electrode to the first output electrode; when the substrate electrode is electrically connected to the second output electrode When connected, current flows from the first output electrode to the second output electrode.

根據本發明的第二方面，提供一種雙向功率器件，包括多個元胞結構，所述元胞結構為上述所述的雙向功率器件，多個元胞結構中的源區電連接在一起，多個元胞結構中的漏區電連接在一起。 According to a second aspect of the present invention, a bidirectional power device is provided, comprising a plurality of cell structures, wherein the cell structures are the above-mentioned bidirectional power device, the source regions in the plurality of cell structures are electrically connected together, and the plurality of cell structures are electrically connected together. The drain regions in each cell structure are electrically connected together.

本發明實施例提供的雙向功率器件，溝道區鄰近位於溝槽下部的控制柵，可以通過減小溝槽的寬度來減小溝道長度，進而減小溝道電阻。 In the bidirectional power device provided by the embodiment of the present invention, the channel region is adjacent to the control gate located at the lower part of the trench, and the channel length can be reduced by reducing the width of the trench, thereby reducing the channel resistance.

進一步地，在溝槽的下部和上部分別形成控制柵和遮罩柵，控制柵和遮罩柵彼此隔離，控制柵與半導體層之間由柵介質層隔開，遮罩柵和源區以及漏區之間由遮罩介質層隔開，在雙向功率器件截止時遮罩柵通過遮罩介質層耗盡源區和漏區的電荷，提高器件的耐壓特性；在雙向功率器件導通時，多個源區和漏區與半導體層提供低阻抗的導通路徑。 Further, a control gate and a mask gate are respectively formed in the lower part and the upper part of the trench, the control gate and the mask gate are isolated from each other, the control gate and the semiconductor layer are separated by a gate dielectric layer, the mask gate and the source region and The drain regions are separated by a mask dielectric layer. When the bidirectional power device is turned off, the mask gate depletes the charge of the source region and the drain region through the mask dielectric layer to improve the withstand voltage characteristics of the device; when the bidirectional power device is turned on, The multiple source and drain regions and the semiconductor layer provide a low-resistance conduction path.

進一步地，可以通過調整遮罩介質層的厚度、源區和漏區的摻雜濃度以及遮罩柵的長度來實現不同的閾值電壓。 Further, different threshold voltages can be achieved by adjusting the thickness of the mask dielectric layer, the doping concentrations of the source and drain regions, and the length of the mask gate.

進一步地，在溝槽的下部和上部分別形成控制柵和遮罩柵，控制柵和遮罩柵彼此接觸，控制柵與半導體層之間由柵介質層隔開，遮罩柵和源區以及漏區之間由遮罩介質層隔開，在雙向功率器件截止時遮罩柵通過遮罩介質層耗盡源區和漏區的電荷，提高器件的耐壓特性；在雙向功率器件導通時，源區和/或漏區與半導體層提供低阻抗的導通路徑。 Further, a control gate and a mask gate are respectively formed in the lower part and the upper part of the trench, the control gate and the mask gate are in contact with each other, the control gate and the semiconductor layer are separated by a gate dielectric layer, the mask gate and the source region and The drain regions are separated by a mask dielectric layer. When the bidirectional power device is turned off, the mask gate depletes the charge of the source region and the drain region through the mask dielectric layer to improve the withstand voltage characteristics of the device; when the bidirectional power device is turned on, The source and/or drain regions and the semiconductor layer provide a low-resistance conduction path.

進一步地，可以通過調整遮罩介質層的厚度、源區和漏區的摻雜濃度以及遮罩柵的長度來實現不同的閾值電壓。 Further, different threshold voltages can be achieved by adjusting the thickness of the mask dielectric layer, the doping concentrations of the source and drain regions, and the length of the mask gate.

進一步地，在溝槽的下部和上部分別形成控制柵和分壓介質層，該分壓介質層使得控制柵遠離源區和漏區。分壓介質層具有較高的介電常數，可以承受比半導體層更高的電場強度，隨著分壓介質層厚度的增加，承擔了縱向方向上源區和漏區上施加的高壓，提高雙向功率器件的耐壓特性。 Further, a control gate and a voltage dividing dielectric layer are respectively formed on the lower and upper parts of the trench, and the voltage dividing dielectric layer keeps the control gate away from the source region and the drain region. The partial pressure dielectric layer has a higher dielectric constant and can withstand a higher electric field strength than the semiconductor layer. With the increase of the thickness of the partial pressure dielectric layer, it bears the high voltage applied to the source and drain regions in the longitudinal direction, improving the bidirectional Withstand voltage characteristics of power devices.

進一步地，可以通過調整分壓介質層的厚度以及源區和 漏區的摻雜濃度來實現不同的閾值電壓。 Further, by adjusting the thickness of the partial pressure dielectric layer and the source region and The doping concentration of the drain region can achieve different threshold voltages.

進一步地，在雙向功率器件導通時，將所述襯底電極與第一輸出電極和第二輸出電極之一電連接實現電流方向的雙向選擇。當所述襯底電極與所述第一輸出電極電連接時，電流從所述第二輸出電極流向所述第一輸出電極；當所述襯底電極與所述第二輸出電極電連接時，電流從所述第一輸出電極流向所述第二輸出電極。 Further, when the bidirectional power device is turned on, the substrate electrode is electrically connected to one of the first output electrode and the second output electrode to realize bidirectional selection of the current direction. When the substrate electrode is electrically connected to the first output electrode, current flows from the second output electrode to the first output electrode; when the substrate electrode is electrically connected to the second output electrode, current flows from the second output electrode to the first output electrode; Current flows from the first output electrode to the second output electrode.

進一步地，溝槽內的控制柵從半導體層的第一表面延伸至溝槽下部，源區和漏區從半導體層的第一表面延伸至於溝槽下部的控制柵交疊。源區和漏區延伸的長度較長，使得源區和漏區在雙向功率器件截止時可以承擔縱向方向上源區和漏區上施加的高壓，提高雙向功率器件的耐壓特性。 Further, the control gate in the trench extends from the first surface of the semiconductor layer to the lower portion of the trench, and the source region and the drain region extend from the first surface of the semiconductor layer to overlap the control gate at the lower portion of the trench. The source region and the drain region have a longer extension length, so that the source region and the drain region can bear the high voltage applied to the source region and the drain region in the longitudinal direction when the bidirectional power device is turned off, thereby improving the withstand voltage characteristics of the bidirectional power device.

進一步地，可以通過調整柵介質層的厚度以及溝道區的摻雜濃度來實現不同的閾值電壓。 Further, different threshold voltages can be achieved by adjusting the thickness of the gate dielectric layer and the doping concentration of the channel region.

進一步地，通過佈線層將雙向功率器件的襯底電極、第一輸出電極、第二輸出電極以及柵電極引出至半導體襯底的表面，並在佈線層上形成金屬焊球。由於採用了植球的工藝，省略了傳統封裝的打線，減小了封裝的寄生電感和寄生電阻，減小雙向功率器件的封裝電阻；由於沒有塑封料的包封，使得散熱更加容易，減小功耗，提高雙向功率器件的可靠性和安全性。 Further, the substrate electrode, the first output electrode, the second output electrode and the gate electrode of the bidirectional power device are drawn out to the surface of the semiconductor substrate through the wiring layer, and metal solder balls are formed on the wiring layer. Due to the use of the ball-mounting process, the wire bonding of the traditional package is omitted, the parasitic inductance and parasitic resistance of the package are reduced, and the package resistance of the bidirectional power device is reduced; power consumption, improving the reliability and safety of bidirectional power devices.

進一步地，雙向功率器件可以由多個元胞結構組成，所有元胞結構的源區電連接在一起作為第一輸出電極，漏區電連接在一起作為第二輸出電極，通過增加元胞結構的數量，提高雙向功率器件的電流能力。 Further, the bidirectional power device can be composed of a plurality of cell structures, the source regions of all the cell structures are electrically connected together as the first output electrode, and the drain regions are electrically connected together as the second output electrode. quantity, improving the current capability of bidirectional power devices.

G:栅電極 G: Gate electrode

S1:第一輸出電極 S1: The first output electrode

S2:第二輸出電極 S2: The second output electrode

Sub:襯底、襯底電極 Sub: substrate, substrate electrode

D1,D2:體二極體 D1, D2: Body Diode

1:襯底 1: Substrate

2:遮罩柵 2: Shading grille

10:半導體層 10: Semiconductor layer

11:覆蓋介質層 11: Cover the dielectric layer

20:溝槽 20: Groove

20a:第一溝槽 20a: First groove

20b:第二溝槽 20b: Second groove

20c:第三溝槽 20c: Third groove

21:栅介質層 21: Gate dielectric layer

22:控制栅 22: Control grid

23:遮罩柵 23: Shading grid

24:隔離層 24: isolation layer

25:遮罩介質層 25: Mask dielectric layer

26:分壓介質層 26: Partial pressure dielectric layer

31:源區 31: Source area

32:漏區 32: Drain area

40:溝道區 40: Channel region

50:接觸孔 50: Contact hole

51:第一接觸孔 51: The first contact hole

52:第二接觸孔 52: The second contact hole

53:第三接觸孔 53: The third contact hole

54:第四接觸孔 54: Fourth contact hole

54a:控制栅22的接觸孔 54a: Contact hole of control gate 22

54b:遮罩柵23的接觸孔 54b: Contact hole of the mask grid 23

60:金屬層 60: Metal layer

61:第一接觸 61: First Contact

62:第二接觸 62: Second Contact

63:第三接觸 63: Third Contact

64:第四接觸 64: Fourth Contact

70:佈線層 70: wiring layer

71:第一佈線 71: First wiring

72:第二佈線 72: Second wiring

73:第三佈線 73: Third wiring

74:第四佈線 74: Fourth wiring

80,81,82,83,84:金屬焊球 80, 81, 82, 83, 84: Metal solder balls

90:導電孔 90: Conductive hole

101:第三引線區 101: The third lead area

311:第一引線區 311: The first lead area

321:第二引線區 321: Second lead area

M1:第一金屬層 M1: first metal layer

M2:第二金屬層 M2: Second metal layer

M3:第三金屬層 M3: third metal layer

W1,W2:寬度 W1,W2: width

L1,L2,L3,L4,K:長度 L1,L2,L3,L4,K: length

AA’,BB’:線 AA',BB': line

第1圖示出了本發明實施例的雙向功率器件的電路示意圖。 Figure 1 shows a schematic circuit diagram of a bidirectional power device according to an embodiment of the present invention.

第2圖-第4圖分別示出了本發明第一實施例的雙向功率器件的不同剖面的截面圖和俯視圖。 FIG. 2 to FIG. 4 respectively show a cross-sectional view and a top view of different sections of the bidirectional power device according to the first embodiment of the present invention.

第5圖示出了本發明第一實施例的多個元胞結構的截面圖。 FIG. 5 shows a cross-sectional view of a plurality of cell structures according to the first embodiment of the present invention.

第6圖示出了本發明第二實施例的雙向功率器件的俯視圖。 FIG. 6 shows a top view of a bidirectional power device according to a second embodiment of the present invention.

第7圖示出了本發明第三實施例的雙向功率器件的截面圖。 FIG. 7 shows a cross-sectional view of a bidirectional power device according to a third embodiment of the present invention.

第8圖-第10圖分別示出了本發明第四實施例的雙向功率器件的不同剖面的截面圖和俯視圖。 FIG. 8 to FIG. 10 respectively show a cross-sectional view and a top view of different sections of the bidirectional power device according to the fourth embodiment of the present invention.

第11圖示出了本發明第四實施例的多個元胞結構的截面圖。 FIG. 11 shows a cross-sectional view of a plurality of cell structures of a fourth embodiment of the present invention.

第12圖示出了本發明第五實施例的雙向功率器件的截面圖。 FIG. 12 shows a cross-sectional view of a bidirectional power device according to a fifth embodiment of the present invention.

第13圖-第15圖分別示出了本發明第六實施例的雙向功率器件的不同剖面的截面圖和俯視圖。 13 to 15 respectively show a cross-sectional view and a top view of different sections of the bidirectional power device according to the sixth embodiment of the present invention.

第16圖示出了本發明第六實施例的多個元胞結構的截面圖。 FIG. 16 shows a cross-sectional view of a plurality of cell structures according to a sixth embodiment of the present invention.

第17圖示出了本發明第七實施例的雙向功率器件的截面圖。 FIG. 17 shows a cross-sectional view of a bidirectional power device according to a seventh embodiment of the present invention.

第18圖-第20圖分別示出了本發明第八實施例的雙向功率器件的不同剖面的截面圖和俯視圖。 FIG. 18 to FIG. 20 respectively show a cross-sectional view and a top view of different sections of the bidirectional power device according to the eighth embodiment of the present invention.

第21圖示出了本發明第八實施例的多個元胞結構的截面圖。 FIG. 21 shows a cross-sectional view of a plurality of cell structures according to an eighth embodiment of the present invention.

第22圖-第25圖分別示出了本發明第九實施例的雙向功率器件的截面圖。 22 to 25 respectively show cross-sectional views of the bidirectional power device according to the ninth embodiment of the present invention.

第26圖示出了本發明第九實施例的雙向功率器件的俯視圖。 FIG. 26 shows a top view of a bidirectional power device according to a ninth embodiment of the present invention.

第27圖示出了本發明第九實施例的雙向功率器件的封裝引腳示意圖。 FIG. 27 shows a schematic diagram of package pins of the bidirectional power device according to the ninth embodiment of the present invention.

第28圖示出了本發明第十實施例的雙向功率器件的截面圖。 FIG. 28 shows a cross-sectional view of a bidirectional power device according to a tenth embodiment of the present invention.

以下將參照圖式更詳細地描述本發明的各種實施例。在各個圖式中，相同的元件採用相同或類似的圖式標記來表示。為了清楚起見，圖式中的各個部分沒有按比例繪製。 Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In the various figures, the same elements are designated by the same or similar reference numerals. For the sake of clarity, various parts in the drawings have not been drawn to scale.

下面結合圖式和實施例，對本發明的具體實施方式作進一步詳細描述。 The specific embodiments of the present invention will be described in further detail below with reference to the drawings and examples.

第1圖示出了本發明實施例提供的雙向功率器件的電路示意圖，該雙向功率器件由一個電晶體形成，具有雙向導體功能。如第1圖所示，該雙向功率器件包括襯底Sub以及位於襯底Sub上的兩個輸出極S1和S2，以及兩個寄生的體二極體D1和D2。當輸出極S2和襯底Sub短接，柵極G施加高電壓時，電壓高於雙向功率器件的閾值電壓，雙向功率 器件導通，電流從輸出極S1流向輸出極S2；當輸出極S1和襯底Sub短接，柵極G施加高電壓時，電壓高於雙向功率器件的閾值電壓，雙向功率器件導通，電流從輸出極S2流向輸出極S1；當襯底Sub接零電壓，柵極G施加低電壓，電壓低於閾值電壓，雙向功率器件截止。 Figure 1 shows a schematic circuit diagram of a bidirectional power device provided by an embodiment of the present invention. The bidirectional power device is formed by a transistor and has a bidirectional conductor function. As shown in FIG. 1, the bidirectional power device includes a substrate Sub, two output poles S1 and S2 on the substrate Sub, and two parasitic body diodes D1 and D2. When the output pole S2 and the substrate Sub are short-circuited and a high voltage is applied to the gate G, the voltage is higher than the threshold voltage of the bidirectional power device, and the bidirectional power The device is turned on, and the current flows from the output pole S1 to the output pole S2; when the output pole S1 and the substrate Sub are short-circuited and a high voltage is applied to the gate G, the voltage is higher than the threshold voltage of the bidirectional power device, the bidirectional power device is turned on, and the current flows from the output The pole S2 flows to the output pole S1; when the substrate Sub is connected to zero voltage, a low voltage is applied to the gate G, and the voltage is lower than the threshold voltage, and the bidirectional power device is turned off.

第一實施例 first embodiment

第2圖-第4圖分別示出了本發明第一實施例的雙向功率器件的截面圖和俯視圖；其中，第2圖為第4圖所示俯視圖中沿AA’線獲取的截面圖，第3圖為第4圖所示俯視圖中沿BB’線獲取的截面圖。在該實施例中，雙向功率器件為溝槽型器件，可以是金屬氧化物半導體場效應電晶體(MOSFET)、IGBT器件或者二極體。在下文中，以N型MOSFET為例進行說明，然而，本發明並不限於此。 Figures 2 to 4 respectively show a cross-sectional view and a top view of the bidirectional power device according to the first embodiment of the present invention; wherein, Figure 2 is a cross-sectional view taken along the line AA' in the top view shown in Figure 4, Figure 3 is a cross-sectional view taken along the line BB' in the top view shown in Figure 4. In this embodiment, the bidirectional power device is a trench type device, which may be a metal oxide semiconductor field effect transistor (MOSFET), an IGBT device or a diode. Hereinafter, an N-type MOSFET is taken as an example for description, however, the present invention is not limited to this.

在第2圖中所示的雙向功率器件只包含了一個元胞結構的縱向結構示意圖，而實際產品當中，元胞結構的數量可以為一個或者多個。參見第2圖-第4圖，所述雙向功率器件包括半導體層10、位於所述半導體層10內的溝槽20，位於所述溝槽20側壁上的柵介質層21、位於所述溝槽20下部的控制柵22、位於所述溝槽20上部的遮罩柵23以及位於所述控制柵22和所述遮罩柵23之間的隔離層24。 The bidirectional power device shown in Figure 2 only contains a schematic diagram of the longitudinal structure of one cell structure, but in actual products, the number of cell structures can be one or more. Referring to FIG. 2 to FIG. 4, the bidirectional power device includes a semiconductor layer 10, a trench 20 located in the semiconductor layer 10, a gate dielectric layer 21 located on the sidewall of the trench 20, and a gate dielectric layer 21 located in the trench. A control gate 22 at the lower part of the trench 20 , a mask gate 23 located at the upper part of the trench 20 , and an isolation layer 24 between the control gate 22 and the mask gate 23 .

在本實施例中，半導體層10例如是半導體襯底本身，或者在半導體襯底上形成的外延層，或者在半導體襯底中注入的阱區。半導體層10的摻雜濃度為7E14~3E16cm-3。半導體層10例如為矽襯底、或者是在矽襯底上形成的外延層、或者是在矽襯底中形成的阱區，摻雜類型為P型，半導體層10與矽襯底的摻雜類型相同。半導體層10有相對的第一表面和第二表面。 In this embodiment, the semiconductor layer 10 is, for example, the semiconductor substrate itself, or an epitaxial layer formed on the semiconductor substrate, or a well region implanted in the semiconductor substrate. The doping concentration of the semiconductor layer 10 is 7E14˜3E16 cm −3 . The semiconductor layer 10 is, for example, a silicon substrate, or an epitaxial layer formed on the silicon substrate, or a well region formed in the silicon substrate, and the doping type is P-type. The doping of the semiconductor layer 10 and the silicon substrate same type. The semiconductor layer 10 has opposing first and second surfaces.

其中，所述控制柵22與所述半導體層10之間由所述柵介質層21隔開。 The control gate 22 is separated from the semiconductor layer 10 by the gate dielectric layer 21 .

進一步地，所述雙向功率器件還包括位於溝槽20側壁上的遮罩介質層25，遮罩柵23與半導體層10之間由遮罩介質層25隔開。 Further, the bidirectional power device further includes a mask dielectric layer 25 located on the sidewall of the trench 20 , and the mask gate 23 and the semiconductor layer 10 are separated by the mask dielectric layer 25 .

在本實施例中，所述柵介質層21、隔離層24、遮罩介質層25的材料可以是二氧化矽或者氮化矽或者二氧化矽和氮化矽的複合結構， 三者的材料可以相同也可以不同。 In this embodiment, the materials of the gate dielectric layer 21 , the isolation layer 24 and the mask dielectric layer 25 may be silicon dioxide or silicon nitride or a composite structure of silicon dioxide and silicon nitride. The materials of the three can be the same or different.

柵介質層21的厚度為200~1000埃，即0.02~0.1um，遮罩介質層25的厚度為1000~2500埃，即0.1~0.25um。遮罩介質層25的厚度大於或等於柵介質層21的厚度。 The thickness of the gate dielectric layer 21 is 200-1000 angstroms, that is, 0.02-0.1 um, and the thickness of the mask dielectric layer 25 is 1000-2500 angstroms, that is, 0.1-0.25 um. The thickness of the mask dielectric layer 25 is greater than or equal to the thickness of the gate dielectric layer 21 .

控制柵22的寬度W1大於遮罩柵23的寬度W2，控制柵的長度L1小於遮罩柵23的長度L2。遮罩柵23的長度L2為0.6~1.2um。 The width W1 of the control gate 22 is greater than the width W2 of the mask gate 23 , and the length L1 of the control gate is smaller than the length L2 of the mask gate 23 . The length L2 of the shield grid 23 is 0.6-1.2um.

進一步地，在半導體層10內形成沿縱向延伸的摻雜類型為N型的源區31和漏區32，其中，源區31和漏區32可以互換；以及在半導體層10內形成鄰近所述控制柵22的溝道區40。 Further, a source region 31 and a drain region 32 of N-type doping type extending in the longitudinal direction are formed in the semiconductor layer 10, wherein the source region 31 and the drain region 32 can be interchanged; Channel region 40 of gate 22 is controlled.

在本實施例中，所述半導體層10的摻雜類型為第一摻雜類型，所述源區31和漏區32的摻雜類型為第二摻雜類型，所述溝道區40的摻雜類型為第一摻雜類型或第二摻雜類型，第一摻雜類型和第二摻雜類型相反。 In this embodiment, the doping type of the semiconductor layer 10 is the first doping type, the doping type of the source region 31 and the drain region 32 is the second doping type, and the doping type of the channel region 40 is the second doping type. The doping type is the first doping type or the second doping type, and the first doping type and the second doping type are opposite.

在本實施例中，所述源區31和漏區32從所述半導體層10的第一表面延伸至與所述控制柵22交疊。所述源區31和漏區32在所述半導體層10中延伸的長度K大於遮罩柵23在半導體層10中延伸的長度L2，優選地，大於所述遮罩柵23和隔離層24在半導體層10中延伸的長度之和L2+L3，但小於遮罩柵23、隔離層24以及控制柵22在半導體層10中延伸的長度之和L1+L2+L3，即L2+L3<K<L1+L2+L3。 In this embodiment, the source region 31 and the drain region 32 extend from the first surface of the semiconductor layer 10 to overlap with the control gate 22 . The length K of the source region 31 and the drain region 32 extending in the semiconductor layer 10 is greater than the length L2 of the mask gate 23 extending in the semiconductor layer 10, preferably, greater than the mask gate 23 and the isolation layer 24. The sum of the lengths L2+L3 extended in the semiconductor layer 10 is less than the sum of the lengths of the mask gate 23, the isolation layer 24 and the control gate 22 extended in the semiconductor layer 10 L1+L2+L3, that is, L2+L3<K< L1+L2+L3.

遮罩柵23與源區31和/或漏區32之間由遮罩介質層25隔開。在雙向功率器件截止時遮罩柵通過遮罩介質層耗盡源區和漏區的電荷，提高器件的耐壓特性；在雙向功率器件導通時，源區和漏區與半導體層提供低阻抗的導通路徑。由此可以調整遮罩介質層的厚度、源區和漏區的摻雜濃度以及遮罩柵的長度來實現不同的閾值電壓。 The mask gate 23 is separated from the source region 31 and/or the drain region 32 by a mask dielectric layer 25 . When the bidirectional power device is turned off, the shield gate depletes the charge in the source and drain regions through the shielding dielectric layer to improve the withstand voltage characteristics of the device; when the bidirectional power device is turned on, the source and drain regions and the semiconductor layer provide low impedance conduction path. Therefore, the thickness of the mask dielectric layer, the doping concentration of the source and drain regions, and the length of the mask gate can be adjusted to achieve different threshold voltages.

由於溝道區40鄰近位於溝槽20下部的控制柵22，可以通過減小溝槽的寬度來減小溝道長度，進而減小溝道電阻。 Since the channel region 40 is adjacent to the control gate 22 located at the lower part of the trench 20, the channel length can be reduced by reducing the width of the trench, thereby reducing the channel resistance.

進一步地，在所述源區31和所述漏區32中形成第一引線區311和第二引線區321。其中，第一引線區311的摻雜類型與源區31的摻雜類型相同，且第一引線區311的摻雜濃度大於源區31的摻雜濃度。第 二引線區321的摻雜類型與漏區32的摻雜類型相同，且第二引線區321的摻雜濃度大於漏區32的摻雜濃度。 Further, a first lead region 311 and a second lead region 321 are formed in the source region 31 and the drain region 32 . The doping type of the first lead region 311 is the same as that of the source region 31 , and the doping concentration of the first lead region 311 is greater than that of the source region 31 . the first The doping type of the second lead region 321 is the same as that of the drain region 32 , and the doping concentration of the second lead region 321 is greater than that of the drain region 32 .

進一步地，在所述半導體層10中形成第三引線區101，所述第三引線區101靠近所述半導體層10的第一表面，其中，第三引線區101的摻雜類型與半導體層10的摻雜類型相同，且第三引線區101的摻雜濃度大於半導體層10的摻雜濃度。 Further, a third lead region 101 is formed in the semiconductor layer 10 , the third lead region 101 is close to the first surface of the semiconductor layer 10 , wherein the doping type of the third lead region 101 is the same as that of the semiconductor layer 10 The doping types are the same, and the doping concentration of the third lead region 101 is greater than the doping concentration of the semiconductor layer 10 .

進一步地，在半導體層10的第一表面上形成覆蓋介質層11以及形成貫穿覆蓋介質層11的接觸孔50，所述接觸孔50包括第一接觸孔51、第二接觸孔52、第三接觸孔53以及第四接觸孔54。其中，第一接觸孔51位於所述源區31上，貫穿所述覆蓋介質層11延伸至所述源區31，所述第二接觸孔位於所述漏區32上，貫穿所述覆蓋介質層11延伸至所述漏區32。 Further, a cover dielectric layer 11 is formed on the first surface of the semiconductor layer 10 and a contact hole 50 penetrating the cover dielectric layer 11 is formed, the contact hole 50 includes a first contact hole 51 , a second contact hole 52 and a third contact hole hole 53 and fourth contact hole 54 . The first contact hole 51 is located on the source region 31 and extends through the cover dielectric layer 11 to the source region 31 , and the second contact hole is located on the drain region 32 and penetrates through the cover dielectric layer. 11 extends to the drain region 32 .

第三接觸孔53位於所述溝槽20兩側貫穿所述覆蓋介質層11延伸至所述半導體層10。 The third contact holes 53 are located on both sides of the trench 20 and extend through the cover dielectric layer 11 to the semiconductor layer 10 .

第四接觸孔54位於所述溝槽20上，貫穿所述覆蓋介質層11延伸至所述溝槽20中的控制柵22和/或遮罩柵23。 The fourth contact hole 54 is located on the trench 20 and extends through the cover dielectric layer 11 to the control gate 22 and/or the mask gate 23 in the trench 20 .

在本實施例中，覆蓋介質層11可以是未摻雜的矽玻璃(USG)和摻雜硼磷的矽玻璃(BPSG)。 In this embodiment, the cover dielectric layer 11 may be undoped silicon glass (USG) or boron phosphorous doped silicon glass (BPSG).

在所述覆蓋介質層11上沉積金屬層60，金屬層60填充第一接觸孔51至第四接觸孔54分別形成第一接觸61至第四接觸64。第一接觸61通過第一接觸孔51、第一引線區311與所述源區31相接觸以形成第一輸出電極S1，第二接觸62通過第二接觸孔52、第二引線區321與所述漏區32相接觸以形成第二輸出電極S2，所述第三接觸63通過第三接觸孔53、第三引線區101與所述半導體層10相接觸以形成襯底電極Sub。如第3圖所示，第四接觸64經由第四接觸孔54與控制柵22和/或遮罩柵23相接觸以形成柵電極。如第4圖所示，第四接觸孔54包括控制柵22的接觸孔54a和遮罩柵23的接觸孔54b。在本實施例中，控制柵22和遮罩柵23連接在一起。 A metal layer 60 is deposited on the cover dielectric layer 11 , and the metal layer 60 fills the first contact hole 51 to the fourth contact hole 54 to form the first contact 61 to the fourth contact 64 , respectively. The first contact 61 contacts the source region 31 through the first contact hole 51 and the first lead region 311 to form the first output electrode S1, and the second contact 62 contacts the source region 31 through the second contact hole 52 and the second lead region 321. The drain region 32 is in contact with the semiconductor layer 10 to form the second output electrode S2, and the third contact 63 is in contact with the semiconductor layer 10 through the third contact hole 53 and the third lead region 101 to form the substrate electrode Sub. As shown in FIG. 3 , the fourth contact 64 is in contact with the control gate 22 and/or the mask gate 23 through the fourth contact hole 54 to form a gate electrode. As shown in FIG. 4 , the fourth contact hole 54 includes a contact hole 54 a of the control gate 22 and a contact hole 54 b of the shadow gate 23 . In this embodiment, the control grid 22 and the mask grid 23 are connected together.

在本實施例中，金屬層60的材料可以為鈦和氮化鈦、鋁 銅、鋁矽銅或者鋁矽。 In this embodiment, the material of the metal layer 60 may be titanium, titanium nitride, aluminum Copper, AlSiCu or AlSi.

第2圖中一個元胞只包含了三個溝槽、一個源區和一個漏區，而實際產品當中，源區31和漏區32的數量不止一個。以第2圖所示的為例，三個溝槽結構分別為第一溝槽20a、第二溝槽20b和第三溝槽20c。其中，第一接觸61將源區31引出至半導體層10表面形成第一輸出電極S1，第二接觸62將漏區32引出至半導體層10表面形成第二輸出電極S2，第三接觸63將半導體層10引出形成襯底電極Sub，第四接觸64a和64b將溝槽20中的控制柵22以及遮罩柵23引出至半導體層10表面形成柵電極G，其中，控制柵22和遮罩柵23電連接在一起。第一溝槽20a和第三溝槽20c對稱設置在源區31和漏區32外。其中，第一輸出電極S1和第二輸出電極S2分別是源區31和漏區32引出至半導體層10表面形成的，兩者可以互換。當控制柵22上施加的電壓大於閾值電壓時，雙向功率器件導通，第二溝槽20b中的溝道區有電流流過，通過選擇其中一個輸出端電極與襯底電極連接，實現電流方向的選擇，例如，當第一輸出電極S1與襯底電極Sub連接時，電流從第二輸出電極S2流向第一輸出電極S1；當第二輸出電極S2與襯底電極Sub連接時，電流從第一輸出電極S1流向第二輸出電極S2。 One cell in Figure 2 only includes three trenches, one source region and one drain region, but in the actual product, the number of source regions 31 and drain regions 32 is more than one. Taking the example shown in FIG. 2, the three trench structures are a first trench 20a, a second trench 20b and a third trench 20c, respectively. The first contact 61 leads the source region 31 to the surface of the semiconductor layer 10 to form the first output electrode S1, the second contact 62 leads the drain region 32 to the surface of the semiconductor layer 10 to form the second output electrode S2, and the third contact 63 leads the semiconductor layer 10 to the surface of the semiconductor layer 10 to form the second output electrode S2. The layer 10 is drawn out to form the substrate electrode Sub, and the fourth contacts 64a and 64b lead out the control gate 22 and the mask gate 23 in the trench 20 to the surface of the semiconductor layer 10 to form the gate electrode G, wherein the control gate 22 and the mask gate 23 electrically connected together. The first trench 20 a and the third trench 20 c are symmetrically disposed outside the source region 31 and the drain region 32 . Wherein, the first output electrode S1 and the second output electrode S2 are formed by leading the source region 31 and the drain region 32 to the surface of the semiconductor layer 10 respectively, and the two can be interchanged. When the voltage applied to the control gate 22 is greater than the threshold voltage, the bidirectional power device is turned on, and current flows through the channel region in the second trench 20b. By selecting one of the output electrodes to connect with the substrate electrode, the direction of the current is realized. For example, when the first output electrode S1 is connected to the substrate electrode Sub, the current flows from the second output electrode S2 to the first output electrode S1; when the second output electrode S2 is connected to the substrate electrode Sub, the current flows from the first output electrode S2 to the substrate electrode Sub. The output electrode S1 flows to the second output electrode S2.

當控制柵22上施加的電壓小於閾值電壓時，雙向功率器件截止，由於控制柵22和遮罩柵23電連接在一起，此時遮罩柵23上施加的電壓為低電壓，第一輸出電極S1和第二輸出電極S2上施加高電壓，在源區31、漏區32和遮罩柵23之間形成電壓差。第一溝槽20a和第三溝槽20c中的遮罩柵23通過遮罩介質層25在源區31和漏區32中感應出電荷，可以通過調整遮罩介質層25的厚度和材料以及源區31和漏區32的雜質濃度，最終完全耗盡源區和漏區，達到提高器件的耐壓的目的。同時由於源區31和漏區32的雜質濃度增加，也極大的減小了器件的電阻。 When the voltage applied on the control gate 22 is less than the threshold voltage, the bidirectional power device is turned off. Since the control gate 22 and the mask gate 23 are electrically connected together, the voltage applied on the mask gate 23 is a low voltage at this time, and the first output electrode A high voltage is applied to S1 and the second output electrode S2 to form a voltage difference between the source region 31 , the drain region 32 and the mask gate 23 . The mask gate 23 in the first trench 20a and the third trench 20c induces charges in the source region 31 and the drain region 32 through the mask dielectric layer 25. The thickness and material of the mask dielectric layer 25 and the source region can be adjusted by adjusting the thickness and material of the mask dielectric layer 25. The impurity concentration of the region 31 and the drain region 32 will eventually completely deplete the source region and the drain region, so as to achieve the purpose of improving the withstand voltage of the device. At the same time, due to the increase of the impurity concentration of the source region 31 and the drain region 32, the resistance of the device is also greatly reduced.

第5圖僅示出了兩個元胞結構的示意圖，多個第一接觸61連接在一起形成第一輸出電極S1，多個第二接觸62連接在一起形成第二輸出電極S2，以提高器件的電流能力。替代地，對於其他類型的雙向功率器件，通過增加元胞的數量，即選擇兩個及更多元胞結構並聯連接，可 以提高器件的電流能力。 FIG. 5 only shows a schematic diagram of two cell structures, a plurality of first contacts 61 are connected together to form a first output electrode S1, and a plurality of second contacts 62 are connected together to form a second output electrode S2, so as to improve the device current capability. Alternatively, for other types of bidirectional power devices, by increasing the number of cells, i.e. choosing two or more cell structures connected in parallel, it is possible to to improve the current capability of the device.

第二實施例 Second Embodiment

本實施例與第一實施例採用基本相同的科技方案，不同之處在於，第一實施例中，控制柵22和遮罩柵23連接在一起，而本實施例中，遮罩柵23和半導體層10連接在一起，如第6圖所示，遮罩柵23的接觸孔54b與襯底電極的接觸孔53連接，使遮罩柵23和襯底電極Sub電連接在一起。 This embodiment adopts basically the same technical solution as the first embodiment, the difference lies in that, in the first embodiment, the control gate 22 and the mask gate 23 are connected together, while in this embodiment, the mask gate 23 and the semiconductor The layers 10 are connected together. As shown in FIG. 6 , the contact hole 54b of the mask grid 23 is connected to the contact hole 53 of the substrate electrode, so that the mask grid 23 and the substrate electrode Sub are electrically connected together.

本實施例中，雙向功率器件的其餘部分與第一實施例基本相同，具體結構不再贅述。 In this embodiment, the rest of the bidirectional power device is basically the same as that of the first embodiment, and the specific structure will not be repeated.

第一實施例中控制柵22和遮罩柵23連接在一起，遮罩柵23和源區31和漏區32有交疊，存在寄生電容。當控制柵22和遮罩柵23的電壓升高時，對該寄生電容充電，雙向功率器件導通；當控制柵22和遮罩柵2的電壓降低時，該寄生電容放電，雙向功率器件截止。雙向功率器件進行高速開關的時候，該寄生電容的充放電時間會降低開關頻率，同時寄生電容充放電產生額外的功耗。 In the first embodiment, the control gate 22 and the mask gate 23 are connected together, and the mask gate 23 overlaps with the source region 31 and the drain region 32 and has parasitic capacitance. When the voltage of the control gate 22 and the mask gate 23 increases, the parasitic capacitance is charged, and the bidirectional power device is turned on; when the voltage of the control gate 22 and the mask gate 2 decreases, the parasitic capacitance is discharged, and the bidirectional power device is turned off. When the bidirectional power device performs high-speed switching, the charging and discharging time of the parasitic capacitance will reduce the switching frequency, and at the same time, the charging and discharging of the parasitic capacitance will generate additional power consumption.

第二實施例中遮罩柵23和半導體層10連接在一起，遮罩柵23的電壓在器件開關過程中是固定的，可避免遮罩柵23電壓變化而帶來寄生電容的充放電，可以提高雙向功率器件的開關頻率，減少功耗。在某些要求雙向功率器件不僅要有盡可能低的電阻，還要有小的寄生電容的應用場合，可以做高速開關使用。 In the second embodiment, the shielding grid 23 and the semiconductor layer 10 are connected together, and the voltage of the shielding grid 23 is fixed during the switching process of the device, which can avoid the charging and discharging of the parasitic capacitance caused by the voltage change of the shielding grid 23. Increase the switching frequency of bidirectional power devices and reduce power consumption. In some applications that require bidirectional power devices not only to have the lowest possible resistance, but also to have small parasitic capacitances, they can be used as high-speed switches.

第三實施例 Third Embodiment

本實施例與第一實施例採用基本相同的技術方案，不同之處在於，第一實施例中，第三接觸63形成在半導體層10的第一表面上，通過第三接觸孔53、第三引線區101與所述半導體層10相接觸以形成襯底電極Sub。而本實施例中，第三接觸63形成在半導體層10的第二表面上，如第7圖所示。具體地，將雙向功率器件形成在摻雜濃度較高的襯底1上，然後在襯底1的背面蒸發金屬層形成第三接觸63。 This embodiment adopts basically the same technical solution as the first embodiment, the difference lies in that, in the first embodiment, the third contact 63 is formed on the first surface of the semiconductor layer 10 , through the third contact hole 53 , the third contact The lead region 101 is in contact with the semiconductor layer 10 to form the substrate electrode Sub. In this embodiment, however, the third contact 63 is formed on the second surface of the semiconductor layer 10 , as shown in FIG. 7 . Specifically, the bidirectional power device is formed on the substrate 1 with higher doping concentration, and then the third contact 63 is formed by evaporating a metal layer on the backside of the substrate 1 .

第一實施例中，雙向功率器件的柵極、襯底電極、第一輸出電極和第二輸出電極均從半導體層10的第一表面引出，適合晶片級封 裝(CSP)。 In the first embodiment, the gate electrode, the substrate electrode, the first output electrode and the second output electrode of the bidirectional power device are all drawn from the first surface of the semiconductor layer 10, which is suitable for wafer level packaging. installed (CSP).

第三實施例中，雙向功率器件的襯底電極從半導體層10的第二表面引出，既能適應傳統的器件封裝形式(例如SOP8、DIP8)，同時增加了雙向功率器件的散熱能力。 In the third embodiment, the substrate electrode of the bidirectional power device is drawn out from the second surface of the semiconductor layer 10 , which not only adapts to traditional device packaging forms (eg, SOP8, DIP8), but also increases the heat dissipation capability of the bidirectional power device.

本實施例中，雙向功率器件的其餘部分與第一實施例基本相同，具體結構不再贅述。 In this embodiment, the rest of the bidirectional power device is basically the same as that of the first embodiment, and the specific structure will not be repeated.

第四實施例 Fourth Embodiment

第8圖-第10圖分別示出了本發明第四實施例的雙向功率器件的截面圖和俯視圖；其中，第8圖為第10圖所示俯視圖中沿AA’線獲取的截面圖，第9圖為第10圖所示俯視圖中沿BB’線獲取的截面圖。 Figures 8 to 10 respectively show a cross-sectional view and a top view of the bidirectional power device according to the fourth embodiment of the present invention; wherein, Figure 8 is a cross-sectional view taken along the line AA' in the top view shown in Figure 10, Fig. 9 is a cross-sectional view taken along the line BB' in the top view shown in Fig. 10 .

在第8圖中所示的雙向功率器件只包含了一個元胞的縱向結構示意圖，而實際產品當中，元胞結構的數量可以為一個或者多個。參見第8圖-第10圖， The bidirectional power device shown in Figure 8 only contains a schematic diagram of the longitudinal structure of one cell, but in an actual product, the number of cell structures can be one or more. See Figures 8-10,

所述雙向功率器件包括半導體層10、位於所述半導體層10內的溝槽20，位於所述溝槽20側壁上的柵介質層21、位於所述溝槽20下部的控制柵22、位於所述溝槽20上部的遮罩柵23。其中，控制柵22和遮罩柵23彼此接觸。 The bidirectional power device includes a semiconductor layer 10, a trench 20 located in the semiconductor layer 10, a gate dielectric layer 21 located on the sidewall of the trench 20, a control gate 22 located under the trench 20, The mask grid 23 on the upper part of the trench 20 is described. Among them, the control gate 22 and the shadow gate 23 are in contact with each other.

在本實施例中，半導體層10例如是半導體襯底本身，或者在半導體襯底上形成的外延層，或者在半導體襯底中注入的阱區。半導體層10的摻雜濃度為7E14~3E16cm-3。半導體層10例如為矽襯底、或者是在矽襯底上形成的外延層、或者是在矽襯底中形成的阱區，摻雜類型為P型，半導體層10與矽襯底的摻雜類型相同。半導體層10有相對的第一表面和第二表面。 In this embodiment, the semiconductor layer 10 is, for example, the semiconductor substrate itself, or an epitaxial layer formed on the semiconductor substrate, or a well region implanted in the semiconductor substrate. The doping concentration of the semiconductor layer 10 is 7E14˜3E16 cm −3 . The semiconductor layer 10 is, for example, a silicon substrate, or an epitaxial layer formed on the silicon substrate, or a well region formed in the silicon substrate, and the doping type is P-type. The doping of the semiconductor layer 10 and the silicon substrate same type. The semiconductor layer 10 has opposing first and second surfaces.

其中，所述控制柵22與所述半導體層10之間由所述柵介質層21隔開。 The control gate 22 is separated from the semiconductor layer 10 by the gate dielectric layer 21 .

進一步地，所述雙向功率器件還包括位於溝槽20側壁上的遮罩介質層25，遮罩柵23與半導體層10之間由遮罩介質層25隔開。 Further, the bidirectional power device further includes a mask dielectric layer 25 located on the sidewall of the trench 20 , and the mask gate 23 and the semiconductor layer 10 are separated by the mask dielectric layer 25 .

在本實施例中，所述柵介質層21、遮罩介質層25的材料可以是二氧化矽或者氮化矽或者二氧化矽和氮化矽的複合結構，兩者的材 料可以相同也可以不同。 In this embodiment, the materials of the gate dielectric layer 21 and the mask dielectric layer 25 may be silicon dioxide or silicon nitride or a composite structure of silicon dioxide and silicon nitride. The materials can be the same or different.

柵介質層21的厚度為200~1000埃，遮罩介質層25的厚度為1000~2500埃，即0.1~0.25um。遮罩介質層25的厚度大於或等於柵介質層21的厚度。遮罩柵23的長度L2為0.4~0.8um。 The thickness of the gate dielectric layer 21 is 200-1000 angstroms, and the thickness of the mask dielectric layer 25 is 1000-2500 angstroms, that is, 0.1-0.25um. The thickness of the mask dielectric layer 25 is greater than or equal to the thickness of the gate dielectric layer 21 . The length L2 of the shield grid 23 is 0.4-0.8um.

進一步地，在半導體層10內形成沿縱向延伸的摻雜類型為N型的源區31和漏區32，其中，源區31和漏區32可以互換；以及在半導體層10內形成鄰近所述控制柵22的溝道區40。 Further, a source region 31 and a drain region 32 of N-type doping type extending in the longitudinal direction are formed in the semiconductor layer 10, wherein the source region 31 and the drain region 32 can be interchanged; Channel region 40 of gate 22 is controlled.

在本實施例中，所述半導體層10的摻雜類型為第一摻雜類型，所述源區31和漏區32的摻雜類型為第二摻雜類型，所述溝道區40的摻雜類型為第一摻雜類型或第二摻雜類型，第一摻雜類型和第二摻雜類型相反。 In this embodiment, the doping type of the semiconductor layer 10 is the first doping type, the doping type of the source region 31 and the drain region 32 is the second doping type, and the doping type of the channel region 40 is the second doping type. The doping type is the first doping type or the second doping type, and the first doping type and the second doping type are opposite.

在本實施例中，所述源區31和漏區32從所述半導體層10的第一表面延伸至與所述控制柵22交疊。所述源區31和漏區32在所述半導體層10中延伸的長度K大於遮罩柵23在半導體層10中延伸的長度L2，但小於遮罩柵23以及控制柵22在半導體層10中延伸的長度之和L1+L2，即L2<K<L1+L2。 In this embodiment, the source region 31 and the drain region 32 extend from the first surface of the semiconductor layer 10 to overlap with the control gate 22 . The length K of the source region 31 and the drain region 32 extending in the semiconductor layer 10 is greater than the length L2 of the mask gate 23 extending in the semiconductor layer 10 , but smaller than the mask gate 23 and the control gate 22 in the semiconductor layer 10 The sum of the extended lengths is L1+L2, that is, L2<K<L1+L2.

遮罩柵23與源區31和/或漏區32之間由遮罩介質層25隔開。在雙向功率器件截止時遮罩柵通過遮罩介質層耗盡源區和漏區的電荷，提高器件的耐壓特性；在雙向功率器件導通時，源區和漏區與半導體層提供低阻抗的導通路徑。由此可以調整遮罩介質層的厚度、源區和漏區的摻雜濃度以及遮罩柵的長度來實現不同的閾值電壓。 The mask gate 23 is separated from the source region 31 and/or the drain region 32 by a mask dielectric layer 25 . When the bidirectional power device is turned off, the shield gate depletes the charge in the source and drain regions through the shielding dielectric layer to improve the withstand voltage characteristics of the device; when the bidirectional power device is turned on, the source and drain regions and the semiconductor layer provide low impedance conduction path. Therefore, the thickness of the mask dielectric layer, the doping concentration of the source and drain regions, and the length of the mask gate can be adjusted to achieve different threshold voltages.

由於溝道區40鄰近位於溝槽20下部的控制柵22，可以通過減小溝槽的寬度來減小溝道長度，進而減小溝道電阻。 Since the channel region 40 is adjacent to the control gate 22 located at the lower part of the trench 20, the channel length can be reduced by reducing the width of the trench, thereby reducing the channel resistance.

進一步地，在所述源區31和所述漏區32中形成第一引線區311和第二引線區321。其中，第一引線區311的摻雜類型與源區31的摻雜類型相同，且第一引線區311的摻雜濃度大於源區31的摻雜濃度。第二引線區321的摻雜類型與漏區32的摻雜類型相同，且第二引線區321的摻雜濃度大於漏區32的摻雜濃度。 Further, a first lead region 311 and a second lead region 321 are formed in the source region 31 and the drain region 32 . The doping type of the first lead region 311 is the same as that of the source region 31 , and the doping concentration of the first lead region 311 is greater than that of the source region 31 . The doping type of the second lead region 321 is the same as that of the drain region 32 , and the doping concentration of the second lead region 321 is greater than that of the drain region 32 .

進一步地，在所述半導體層10中形成第三引線區101， 所述第三引線區101靠近所述半導體層10的第一表面，其中，第三引線區101的摻雜類型與半導體層10的摻雜類型相同，且第三引線區101的摻雜濃度大於半導體層10的摻雜濃度。 Further, a third lead region 101 is formed in the semiconductor layer 10, The third lead region 101 is close to the first surface of the semiconductor layer 10 , wherein the doping type of the third lead region 101 is the same as that of the semiconductor layer 10 , and the doping concentration of the third lead region 101 is greater than Doping concentration of the semiconductor layer 10 .

進一步地，在半導體層10的第一表面上形成覆蓋介質層11以及形成貫穿覆蓋介質層11的接觸孔50，所述接觸孔50包括第一接觸孔51、第二接觸孔52、第三接觸孔53以及第四接觸孔54。其中，第一接觸孔51位於所述源區31上，貫穿所述覆蓋介質層11延伸至所述源區31，所述第二接觸孔位於所述漏區32上，貫穿所述覆蓋介質層11延伸至所述漏區32。 Further, a cover dielectric layer 11 is formed on the first surface of the semiconductor layer 10 and a contact hole 50 penetrating the cover dielectric layer 11 is formed, the contact hole 50 includes a first contact hole 51 , a second contact hole 52 and a third contact hole hole 53 and fourth contact hole 54 . The first contact hole 51 is located on the source region 31 and extends through the cover dielectric layer 11 to the source region 31 , and the second contact hole is located on the drain region 32 and penetrates through the cover dielectric layer. 11 extends to the drain region 32 .

第三接觸孔53位於所述溝槽20兩側貫穿所述覆蓋介質層11延伸至所述半導體層10。 The third contact holes 53 are located on both sides of the trench 20 and extend through the cover dielectric layer 11 to the semiconductor layer 10 .

第四接觸孔54位於所述溝槽20上，貫穿所述覆蓋介質層11延伸至所述溝槽20中的控制柵22和/或遮罩柵23。 The fourth contact hole 54 is located on the trench 20 and extends through the cover dielectric layer 11 to the control gate 22 and/or the mask gate 23 in the trench 20 .

在本實施例中，覆蓋介質層11可以是未摻雜的矽玻璃(USG)和摻雜硼磷的矽玻璃(BPSG)。 In this embodiment, the cover dielectric layer 11 may be undoped silicon glass (USG) or boron phosphorous doped silicon glass (BPSG).

在所述覆蓋介質層11上沉積金屬層60，金屬層60填充第一接觸孔51至第四接觸孔54分別形成第一接觸61至第四接觸64。第一接觸61通過第一接觸孔51、第一引線區311與所述源區31相接觸以形成第一輸出電極S1，第二接觸62通過第二接觸孔52、第二引線區321與所述漏區32相接觸以形成第二輸出電極S2，所述第三接觸63通過第三接觸孔53、第三引線區101與所述半導體層10相接觸以形成襯底電極Sub。如第9圖所示，第四接觸64經由第四接觸孔54與控制柵22和/或遮罩柵23相接觸以形成柵電極。 A metal layer 60 is deposited on the cover dielectric layer 11 , and the metal layer 60 fills the first contact hole 51 to the fourth contact hole 54 to form the first contact 61 to the fourth contact 64 , respectively. The first contact 61 contacts the source region 31 through the first contact hole 51 and the first lead region 311 to form the first output electrode S1, and the second contact 62 contacts the source region 31 through the second contact hole 52 and the second lead region 321. The drain region 32 is in contact with the semiconductor layer 10 to form the second output electrode S2, and the third contact 63 is in contact with the semiconductor layer 10 through the third contact hole 53 and the third lead region 101 to form the substrate electrode Sub. As shown in FIG. 9 , the fourth contact 64 is in contact with the control gate 22 and/or the mask gate 23 through the fourth contact hole 54 to form a gate electrode.

在本實施例中，金屬層60的材料可以為鈦和氮化鈦、鋁銅、鋁矽銅或者鋁矽。 In this embodiment, the material of the metal layer 60 may be titanium and titanium nitride, aluminum copper, aluminum silicon copper, or aluminum silicon.

第8圖中一個元胞只包含了三個溝槽、一個源區和一個漏區，而實際產品當中，源區31和漏區32的數量不止一個。以第8圖所示的為例，三個溝槽結構分別為第一溝槽20a、第二溝槽20b和第三溝槽20c。其中，第一接觸61將源區31引出至半導體層10表面形成第一輸出 電極S1，第二接觸62將漏區32引出至半導體層10表面形成第二輸出電極S2，第三接觸63將半導體層10引出形成襯底電極Sub，第四接觸64將控制柵22以及遮罩柵23引出至半導體層10表面形成柵電極G，其中，控制柵22和遮罩柵23電連接在一起。第一溝槽20a和第三溝槽20c對稱設定在源區31和漏區32外。其中，第一輸出電極S1和第二輸出電極S2分別是源區31和漏區32引出至半導體層10表面形成的，兩者可以互換。 One cell in Fig. 8 only includes three trenches, one source region and one drain region, but in the actual product, the number of source regions 31 and drain regions 32 is more than one. Taking the example shown in FIG. 8, the three trench structures are a first trench 20a, a second trench 20b and a third trench 20c, respectively. The first contact 61 leads the source region 31 to the surface of the semiconductor layer 10 to form the first output The electrode S1, the second contact 62 leads the drain region 32 to the surface of the semiconductor layer 10 to form the second output electrode S2, the third contact 63 leads the semiconductor layer 10 to form the substrate electrode Sub, and the fourth contact 64 controls the gate 22 and the mask. The gate 23 is drawn out to the surface of the semiconductor layer 10 to form a gate electrode G, wherein the control gate 22 and the mask gate 23 are electrically connected together. The first trench 20 a and the third trench 20 c are symmetrically set outside the source region 31 and the drain region 32 . Wherein, the first output electrode S1 and the second output electrode S2 are formed by leading the source region 31 and the drain region 32 to the surface of the semiconductor layer 10 respectively, and the two can be interchanged.

當控制柵22上施加的電壓大於閾值電壓時，雙向功率器件導通，僅源區31和漏區32之間的第二溝槽20b的溝道區有電流，通過選擇其中一個輸出端電極與襯底電極連接，實現電流方向的選擇，例如，當第一輸出電極S1與襯底電極Sub連接時，電流從第二輸出電極S2流向第一輸出電極S1；當第二輸出電極S2與襯底電極Sub連接時，電流從第一輸出電極S1流向第二輸出電極S2。 When the voltage applied to the control gate 22 is greater than the threshold voltage, the bidirectional power device is turned on, and only the channel region of the second trench 20b between the source region 31 and the drain region 32 has current flow. The bottom electrode is connected to realize the selection of the current direction. For example, when the first output electrode S1 is connected to the substrate electrode Sub, the current flows from the second output electrode S2 to the first output electrode S1; when the second output electrode S2 is connected to the substrate electrode When the Sub is connected, current flows from the first output electrode S1 to the second output electrode S2.

當控制柵22上施加的電壓小於閾值電壓時，雙向功率器件截止。由於控制柵22和遮罩柵23電連接在一起，此時遮罩柵23上施加的電壓為低電壓，第一輸出電極S1和第二輸出電極S2上施加高電壓，在源區31、漏區32和遮罩柵23之間形成電壓差。第一溝槽20a和第三溝槽20c中的遮罩柵23通過遮罩介質層25在源區31和漏區32中感應出電荷，可以通過調整遮罩介質層25的厚度和材料以及源區31和漏區32的雜質濃度，最終完全耗盡源區和漏區，達到提高器件的耐壓的目的。同時由於源區31和漏區32的雜質濃度增加，也極大的減小了器件的電阻。 When the voltage applied on the control gate 22 is less than the threshold voltage, the bidirectional power device is turned off. Since the control gate 22 and the mask gate 23 are electrically connected together, the voltage applied to the mask gate 23 is a low voltage at this time, a high voltage is applied to the first output electrode S1 and the second output electrode S2, and the source region 31, the drain electrode A voltage difference is formed between region 32 and mask gate 23 . The mask gate 23 in the first trench 20a and the third trench 20c induces charges in the source region 31 and the drain region 32 through the mask dielectric layer 25. The thickness and material of the mask dielectric layer 25 and the source region can be adjusted by adjusting the thickness and material of the mask dielectric layer 25. The impurity concentration of the region 31 and the drain region 32 will eventually completely deplete the source region and the drain region, so as to achieve the purpose of improving the withstand voltage of the device. At the same time, due to the increase of the impurity concentration of the source region 31 and the drain region 32, the resistance of the device is also greatly reduced.

第11圖僅示出了兩個元胞結構的示意圖，多個第一接觸61連接在一起形成第一輸出電極S1，多個第二接觸62連接在一起形成第二輸出電極S2，以提高器件的電流能力。替代地，對於其他類型的雙向功率器件，通過增加元胞的數量，即選擇兩個及更多元胞結構並聯連接，可以提高器件的電流能力。 FIG. 11 only shows a schematic diagram of two cell structures, a plurality of first contacts 61 are connected together to form a first output electrode S1, and a plurality of second contacts 62 are connected together to form a second output electrode S2, so as to improve the device current capability. Alternatively, for other types of bidirectional power devices, the current capability of the device can be improved by increasing the number of cells, ie selecting two or more cell structures to be connected in parallel.

第五實施例 Fifth Embodiment

本實施例與第四實施例採用基本相同的技術方案，不同之處在於，第四實施例中，第三接觸63形成在半導體層10的第一表面上，通過第三接觸孔53、第三引線區101與所述半導體層10相接觸以形成襯底 電極Sub。而本實施例中，第三接觸63形成在半導體層10的第二表面上，如第12圖所示。具體地，將雙向功率器件形成在摻雜濃度較高的襯底1上，然後在襯底1的背面蒸發金屬層形成第三接觸63。第四實施例中，雙向功率器件的柵極、襯底電極、第一輸出電極和第二輸出電極均從半導體層10的第一表面引出，適合晶片級封裝(CSP)。 This embodiment adopts basically the same technical solution as the fourth embodiment, the difference lies in that, in the fourth embodiment, the third contact 63 is formed on the first surface of the semiconductor layer 10, and the third contact hole 53, the third contact hole 53, the third The lead region 101 is in contact with the semiconductor layer 10 to form a substrate Electrode Sub. In this embodiment, the third contact 63 is formed on the second surface of the semiconductor layer 10, as shown in FIG. 12 . Specifically, the bidirectional power device is formed on the substrate 1 with higher doping concentration, and then the third contact 63 is formed by evaporating a metal layer on the backside of the substrate 1 . In the fourth embodiment, the gate electrode, the substrate electrode, the first output electrode and the second output electrode of the bidirectional power device are all drawn out from the first surface of the semiconductor layer 10 , which are suitable for wafer level packaging (CSP).

第五實施例中，雙向功率器件的襯底電極從半導體層10的第二表面引出，既能適應傳統的器件封裝形式(例如SOP8、DIP8)，同時增加了雙向功率器件的散熱能力。 In the fifth embodiment, the substrate electrode of the bidirectional power device is drawn out from the second surface of the semiconductor layer 10 , which not only adapts to traditional device packaging forms (eg, SOP8, DIP8), but also increases the heat dissipation capability of the bidirectional power device.

本實施例中，雙向功率器件的其餘部分與第四實施例基本相同，具體結構不再贅述。 In this embodiment, the rest of the bidirectional power device is basically the same as that of the fourth embodiment, and the specific structure will not be repeated.

第六實施例 Sixth Embodiment

第13圖-第15圖分別示出了本發明第六實施例的雙向功率器件的截面圖和俯視圖；其中，第13圖為第15圖所示俯視圖中沿AA’線獲取的截面圖，第14圖為第15圖所示俯視圖中沿BB’線獲取的截面圖。 Figures 13 to 15 respectively show a cross-sectional view and a top view of the bidirectional power device according to the sixth embodiment of the present invention; wherein, Figure 13 is a cross-sectional view taken along the line AA' in the top view shown in Figure 15, and the first Fig. 14 is a cross-sectional view taken along line BB' in the top view shown in Fig. 15 .

在第13圖中所示的雙向功率器件只包含了一個元胞的縱向結構示意圖，而實際產品當中，元胞結構的數量可以為一個或者多個。 參見第13圖-第15圖，所述雙向功率器件包括半導體層10、位於所述半導體層10內的溝槽20，位於所述溝槽20側壁上的柵介質層21、位於所述溝槽20下部的控制柵22、位於所述溝槽20上部的分壓介質層26。 The bidirectional power device shown in Figure 13 only contains a schematic diagram of the longitudinal structure of one cell, but in an actual product, the number of cell structures can be one or more. Referring to FIG. 13 to FIG. 15, the bidirectional power device includes a semiconductor layer 10, a trench 20 located in the semiconductor layer 10, a gate dielectric layer 21 located on the sidewall of the trench 20, and a gate dielectric layer 21 located in the trench. The control gate 22 at the lower part of the trench 20 and the voltage divider dielectric layer 26 at the upper part of the trench 20 .

在本實施例中，半導體層10例如是半導體襯底本身，或者在半導體襯底上形成的外延層，或者在半導體襯底中注入的阱區。半導體層10的摻雜濃度為7E14~3E16cm-3。半導體層10例如為矽襯底、或者是在矽襯底上形成的外延層、或者是在矽襯底中形成的阱區，摻雜類型為P型，半導體層10與矽襯底的摻雜類型相同。半導體層10有相對的第一表面和第二表面。 In this embodiment, the semiconductor layer 10 is, for example, the semiconductor substrate itself, or an epitaxial layer formed on the semiconductor substrate, or a well region implanted in the semiconductor substrate. The doping concentration of the semiconductor layer 10 is 7E14˜3E16 cm −3 . The semiconductor layer 10 is, for example, a silicon substrate, or an epitaxial layer formed on the silicon substrate, or a well region formed in the silicon substrate, and the doping type is P-type. The doping of the semiconductor layer 10 and the silicon substrate same type. The semiconductor layer 10 has opposing first and second surfaces.

其中，所述控制柵22與所述半導體層10之間由所述柵介質層21隔開。 The control gate 22 is separated from the semiconductor layer 10 by the gate dielectric layer 21 .

在本實施例中，柵介質層21、分壓介質層26的材料可以 是二氧化矽或者氮化矽或者二氧化矽和氮化矽的複合結構，兩者的材料可以相同也可以不同。 In this embodiment, the materials of the gate dielectric layer 21 and the voltage dividing dielectric layer 26 may be It is a composite structure of silicon dioxide or silicon nitride or silicon dioxide and silicon nitride, and the materials of the two can be the same or different.

柵介質層21的厚度為200~1000埃，分壓介質層26的長度至少大於0.3um。 The thickness of the gate dielectric layer 21 is 200-1000 angstroms, and the length of the partial pressure dielectric layer 26 is at least greater than 0.3um.

進一步地，在半導體層10內形成沿縱向延伸的摻雜類型為N型的源區31和漏區32，其中，源區31和漏區32可以互換；以及在半導體層10內形成鄰近所述控制柵22的溝道區40。 Further, a source region 31 and a drain region 32 of N-type doping type extending in the longitudinal direction are formed in the semiconductor layer 10, wherein the source region 31 and the drain region 32 can be interchanged; Channel region 40 of gate 22 is controlled.

在本實施例中，所述半導體層10的摻雜類型為第一摻雜類型，所述源區31和漏區32的摻雜類型為第二摻雜類型，所述溝道區40的摻雜類型為第一摻雜類型或第二摻雜類型，第一摻雜類型和第二摻雜類型相反。 In this embodiment, the doping type of the semiconductor layer 10 is the first doping type, the doping type of the source region 31 and the drain region 32 is the second doping type, and the doping type of the channel region 40 is the second doping type. The doping type is the first doping type or the second doping type, and the first doping type and the second doping type are opposite.

在本實施例中，所述源區31和漏區32從所述半導體層10的第一表面延伸至與所述控制柵22交疊。所述源區31和漏區32在所述半導體層10中延伸的長度K大於所述分壓介質層26的長度L4，小於分壓介質層26和控制柵22在半導體層10中延伸的長度之和L1+L4。分壓介質層26使得控制柵22遠離源區31和漏區32。 In this embodiment, the source region 31 and the drain region 32 extend from the first surface of the semiconductor layer 10 to overlap with the control gate 22 . The length K of the source region 31 and the drain region 32 extending in the semiconductor layer 10 is greater than the length L4 of the voltage dividing dielectric layer 26 and smaller than the length K that the voltage dividing dielectric layer 26 and the control gate 22 extend in the semiconductor layer 10 The sum L1+L4. The voltage divider dielectric layer 26 keeps the control gate 22 away from the source region 31 and the drain region 32 .

分壓介質層具有較高的介電常數，可以承受比半導體層更高的電場強度，隨著分壓介質層厚度的增加，承擔了縱向方向上源區和漏區上施加的高壓，提高雙向功率器件的耐壓特性。由此可以通過調整分壓介質層的厚度以及源區和漏區的摻雜濃度來實現不同的閾值電壓。 The partial pressure dielectric layer has a higher dielectric constant and can withstand a higher electric field strength than the semiconductor layer. With the increase of the thickness of the partial pressure dielectric layer, it bears the high voltage applied to the source and drain regions in the longitudinal direction, improving the bidirectional Withstand voltage characteristics of power devices. Therefore, different threshold voltages can be achieved by adjusting the thickness of the voltage dividing dielectric layer and the doping concentration of the source and drain regions.

由於溝道區40鄰近位於溝槽20下部的控制柵22，可以通過減小溝槽的寬度來減小溝道長度，進而減小溝道電阻。 Since the channel region 40 is adjacent to the control gate 22 located at the lower part of the trench 20, the channel length can be reduced by reducing the width of the trench, thereby reducing the channel resistance.

進一步地，在所述源區31和所述漏區32中形成第一引線區311和第二引線區321。其中，第一引線區311的摻雜類型與源區31的摻雜類型相同，且第一引線區311的摻雜濃度大於源區31的摻雜濃度。第二引線區321的摻雜類型與漏區32的摻雜類型相同，且第二引線區321的摻雜濃度大於漏區32的摻雜濃度。 Further, a first lead region 311 and a second lead region 321 are formed in the source region 31 and the drain region 32 . The doping type of the first lead region 311 is the same as that of the source region 31 , and the doping concentration of the first lead region 311 is greater than that of the source region 31 . The doping type of the second lead region 321 is the same as that of the drain region 32 , and the doping concentration of the second lead region 321 is greater than that of the drain region 32 .

進一步地，在所述半導體層10中形成第三引線區101，所述第三引線區101靠近所述半導體層10的第一表面，其中，第三引線區 101的摻雜類型與半導體層10的摻雜類型相同，且第三引線區101的摻雜濃度大於半導體層10的摻雜濃度。 Further, a third lead region 101 is formed in the semiconductor layer 10, and the third lead region 101 is close to the first surface of the semiconductor layer 10, wherein the third lead region The doping type of 101 is the same as that of the semiconductor layer 10 , and the doping concentration of the third lead region 101 is greater than that of the semiconductor layer 10 .

進一步地，在半導體層10的第一表面上形成覆蓋介質層11以及形成貫穿覆蓋介質層11的接觸孔50，所述接觸孔50包括第一接觸孔51、第二接觸孔52、第三接觸孔53以及第四接觸孔54。其中，第一接觸孔51位於所述源區31上，貫穿所述覆蓋介質層11延伸至所述源區31，所述第二接觸孔位於所述漏區32上，貫穿所述覆蓋介質層11延伸至所述漏區32。 Further, a cover dielectric layer 11 is formed on the first surface of the semiconductor layer 10 and a contact hole 50 penetrating the cover dielectric layer 11 is formed, the contact hole 50 includes a first contact hole 51 , a second contact hole 52 and a third contact hole hole 53 and fourth contact hole 54 . The first contact hole 51 is located on the source region 31 and extends through the cover dielectric layer 11 to the source region 31 , and the second contact hole is located on the drain region 32 and penetrates through the cover dielectric layer. 11 extends to the drain region 32 .

第三接觸孔53位於所述溝槽20兩側貫穿所述覆蓋介質層11延伸至所述半導體層10。 The third contact holes 53 are located on both sides of the trench 20 and extend through the cover dielectric layer 11 to the semiconductor layer 10 .

第四接觸孔54位於所述溝槽20上，貫穿所述覆蓋介質層11延伸至所述溝槽20中的控制柵22。 The fourth contact hole 54 is located on the trench 20 and extends through the cover dielectric layer 11 to the control gate 22 in the trench 20 .

在本實施例中，覆蓋介質層11可以是未摻雜的矽玻璃(USG)和摻雜硼磷的矽玻璃(BPSG)。 In this embodiment, the cover dielectric layer 11 may be undoped silicon glass (USG) or boron phosphorous doped silicon glass (BPSG).

在所述覆蓋介質層11上沉積金屬層60，金屬層60填充第一接觸孔51至第四接觸孔54分別形成第一接觸61至第四接觸64。第一接觸61通過第一接觸孔51、第一引線區311與所述源區31相接觸以形成第一輸出電極S1，第二接觸62通過第二接觸孔52、第二引線區321與所述漏區32相接觸以形成第二輸出電極S2，所述第三接觸63通過第三接觸孔53、第三引線區101與所述半導體層10相接觸以形成襯底電極Sub。如第14圖所示，第四接觸64經由第四接觸孔54與控制柵22相接觸以形成柵電極。 A metal layer 60 is deposited on the cover dielectric layer 11 , and the metal layer 60 fills the first contact hole 51 to the fourth contact hole 54 to form the first contact 61 to the fourth contact 64 , respectively. The first contact 61 contacts the source region 31 through the first contact hole 51 and the first lead region 311 to form the first output electrode S1, and the second contact 62 contacts the source region 31 through the second contact hole 52 and the second lead region 321. The drain region 32 is in contact with the semiconductor layer 10 to form the second output electrode S2, and the third contact 63 is in contact with the semiconductor layer 10 through the third contact hole 53 and the third lead region 101 to form the substrate electrode Sub. As shown in FIG. 14 , the fourth contact 64 is in contact with the control gate 22 through the fourth contact hole 54 to form a gate electrode.

在本實施例中，金屬層60的材料可以為鈦和氮化鈦、鋁銅、鋁矽銅或者鋁矽。 In this embodiment, the material of the metal layer 60 may be titanium and titanium nitride, aluminum copper, aluminum silicon copper, or aluminum silicon.

第13圖中一個元胞只包含了三個溝槽、一個源區和一個漏區，而實際產品當中，源區31和漏區32的數量不止一個。以第13圖所示的為例， One cell in Figure 13 only includes three trenches, one source region and one drain region, but in the actual product, the number of source regions 31 and drain regions 32 is more than one. Taking the example shown in Figure 13,

三個溝槽結構分別為第一溝槽20a、第二溝槽20b和第三溝槽20c。其中，第一接觸61將源區31引出至半導體層10表面形成第一 輸出電極S1，第二接觸62將漏區32引出至半導體層10表面形成第二輸出電極S2，第三接觸63將半導體層10引出形成襯底電極Sub，第四接觸64將控制柵22引出至半導體層10表面形成柵電極G。第一溝槽20a和第三溝槽20c對稱設定在源區31和漏區32外。其中，第一輸出電極S1和第二輸出電極S2分別是源區31和漏區32引出至半導體層10表面形成的，兩者可以互換。 The three trench structures are a first trench 20a, a second trench 20b and a third trench 20c, respectively. The first contact 61 leads the source region 31 to the surface of the semiconductor layer 10 to form the first contact The output electrode S1, the second contact 62 leads the drain region 32 to the surface of the semiconductor layer 10 to form the second output electrode S2, the third contact 63 leads the semiconductor layer 10 to form the substrate electrode Sub, and the fourth contact 64 leads the control gate 22 to A gate electrode G is formed on the surface of the semiconductor layer 10 . The first trench 20 a and the third trench 20 c are symmetrically set outside the source region 31 and the drain region 32 . Wherein, the first output electrode S1 and the second output electrode S2 are formed by leading the source region 31 and the drain region 32 to the surface of the semiconductor layer 10 respectively, and the two can be interchanged.

當控制柵22上施加的電壓大於閾值電壓時，雙向功率器件導通，第二溝槽20b中的溝道區有電流流過，通過選擇其中一個輸出端電極與襯底電極連接，實現電流方向的選擇，例如，當第一輸出電極S1與襯底電極Sub連接時，電流從第二輸出電極S2流向第一輸出電極S1；當第二輸出電極S2與襯底電極Sub連接時，電流從第一輸出電極S1流向第二輸出電極S2。 When the voltage applied to the control gate 22 is greater than the threshold voltage, the bidirectional power device is turned on, and current flows through the channel region in the second trench 20b. By selecting one of the output electrodes to connect with the substrate electrode, the direction of the current is realized. For example, when the first output electrode S1 is connected to the substrate electrode Sub, the current flows from the second output electrode S2 to the first output electrode S1; when the second output electrode S2 is connected to the substrate electrode Sub, the current flows from the first output electrode S2 to the substrate electrode Sub. The output electrode S1 flows to the second output electrode S2.

當控制柵22上施加的電壓小於閾值電壓時，雙向功率器件截止，第一輸出電極S1和第二輸出電極S2上施加高電壓，第一溝槽20a和第三溝槽20c中的分壓介質層26可以承受比半導體層更高的電場強度，隨著分壓介質層26的長度增加，承擔了源區31和漏區32上施加的高電壓，提高雙向功率器件的耐壓特性。 When the voltage applied on the control gate 22 is less than the threshold voltage, the bidirectional power device is turned off, a high voltage is applied on the first output electrode S1 and the second output electrode S2, and the voltage dividing medium in the first trench 20a and the third trench 20c The layer 26 can withstand a higher electric field intensity than the semiconductor layer. As the length of the voltage dividing dielectric layer 26 increases, it bears the high voltage applied to the source region 31 and the drain region 32, thereby improving the withstand voltage characteristics of the bidirectional power device.

第16圖僅示出了兩個元胞結構的示意圖，多個第一接觸61連接在一起形成第一輸出電極S1，多個第二接觸62連接在一起形成第二輸出電極S2，以提高器件的電流能力。替代地，對於其他類型的雙向功率器件，通過增加元胞的數量，即選擇兩個及更多元胞結構並聯連接，可以提高器件的電流能力。 FIG. 16 only shows a schematic diagram of two cell structures, a plurality of first contacts 61 are connected together to form a first output electrode S1, and a plurality of second contacts 62 are connected together to form a second output electrode S2, so as to improve the device current capability. Alternatively, for other types of bidirectional power devices, the current capability of the device can be improved by increasing the number of cells, ie selecting two or more cell structures to be connected in parallel.

第七實施例 Seventh Embodiment

本實施例與第六實施例採用基本相同的技術方案，不同之處在於，第六實施例中，第三接觸63形成在半導體層10的第一表面上，通過第三接觸孔53、第三引線區101與所述半導體層10相接觸以形成襯底電極Sub。而本實施例中，第三接觸63形成在半導體層10的第二表面上，如第17圖所示。具體地，將雙向功率器件形成在摻雜濃度較高的襯底1上，然後在襯底1的背面蒸發金屬層形成第三接觸63。 This embodiment adopts basically the same technical solution as the sixth embodiment, the difference is that in the sixth embodiment, the third contact 63 is formed on the first surface of the semiconductor layer 10, and the third contact hole 53, the third contact hole 53, the third The lead region 101 is in contact with the semiconductor layer 10 to form the substrate electrode Sub. In this embodiment, the third contact 63 is formed on the second surface of the semiconductor layer 10, as shown in FIG. 17 . Specifically, the bidirectional power device is formed on the substrate 1 with higher doping concentration, and then the third contact 63 is formed by evaporating a metal layer on the backside of the substrate 1 .

第六實施例中，雙向功率器件的柵極、襯底電極、第一輸出電極和第二輸出電極均從半導體層10的第一表面引出，適合晶片級封裝(CSP)。 In the sixth embodiment, the gate electrode, the substrate electrode, the first output electrode and the second output electrode of the bidirectional power device are all drawn from the first surface of the semiconductor layer 10 , which are suitable for wafer level packaging (CSP).

第七實施例中，雙向功率器件的襯底電極從半導體層10的第二表面引出，既能適應傳統的器件封裝形式(例如SOP8、DIP8)，同時增加了雙向功率器件的散熱能力。 In the seventh embodiment, the substrate electrode of the bidirectional power device is drawn from the second surface of the semiconductor layer 10 , which not only adapts to traditional device packaging forms (eg, SOP8, DIP8), but also increases the heat dissipation capability of the bidirectional power device.

本實施例中，雙向功率器件的其餘部分與第六實施例基本相同，具體結構不再贅述。 In this embodiment, the rest of the bidirectional power device is basically the same as that of the sixth embodiment, and the specific structure will not be repeated.

第八實施例 Eighth Embodiment

第18圖-第20圖分別示出了本發明第八實施例的雙向功率器件的截面圖和俯視圖；其中，第18圖為第20圖所示俯視圖中沿AA’線獲取的截面圖，第19圖為第20圖所示俯視圖中沿BB’線獲取的截面圖。 Figures 18 to 20 respectively show a cross-sectional view and a top view of the bidirectional power device according to the eighth embodiment of the present invention; wherein, Figure 18 is a cross-sectional view taken along the line AA' in the top view shown in Figure 20, and the first Fig. 19 is a cross-sectional view taken along the line BB' in the top view shown in Fig. 20 .

在第18圖中所示的雙向功率器件只包含了一個元胞的縱向結構示意圖，而實際產品當中，元胞結構的數量可以為一個或者多個。參見第18圖-第20圖，所述雙向功率器件包括半導體層10、位於所述半導體層10內的溝槽20，位於所述溝槽20側壁上的柵介質層21以及位於所述溝槽20內的控制柵22。 The bidirectional power device shown in Figure 18 only contains a schematic diagram of the longitudinal structure of one cell, but in an actual product, the number of cell structures can be one or more. Referring to FIG. 18 to FIG. 20 , the bidirectional power device includes a semiconductor layer 10 , a trench 20 located in the semiconductor layer 10 , a gate dielectric layer 21 located on the sidewall of the trench 20 , and a gate dielectric layer 21 located in the trench Control gate 22 within 20 .

在本實施例中，半導體層10例如是半導體襯底本身，或者在半導體襯底上形成的外延層，或者在半導體襯底中注入的阱區。半導體層10的摻雜濃度為7E14~3E16cm-3。半導體層10例如為矽襯底、或者是在矽襯底上形成的外延層、或者是在矽襯底中形成的阱區，摻雜類型為P型，半導體層10與矽襯底的摻雜類型相同。半導體層10有相對的第一表面和第二表面。 In this embodiment, the semiconductor layer 10 is, for example, the semiconductor substrate itself, or an epitaxial layer formed on the semiconductor substrate, or a well region implanted in the semiconductor substrate. The doping concentration of the semiconductor layer 10 is 7E14˜3E16 cm −3 . The semiconductor layer 10 is, for example, a silicon substrate, or an epitaxial layer formed on the silicon substrate, or a well region formed in the silicon substrate, and the doping type is P-type. The doping of the semiconductor layer 10 and the silicon substrate same type. The semiconductor layer 10 has opposing first and second surfaces.

其中，所述控制柵22從所述半導體層10的第一表面延伸至所述溝槽20下部，所述控制柵22與所述半導體層10之間由所述柵介質層21隔開。 Wherein, the control gate 22 extends from the first surface of the semiconductor layer 10 to the lower part of the trench 20 , and the gate dielectric layer 21 is separated between the control gate 22 and the semiconductor layer 10 .

在本實施例中，柵介質層21、分壓介質層26的材料可以是二氧化矽或者氮化矽或者二氧化矽和氮化矽的複合結構，兩者的材料可 以相同也可以不同。溝槽20的寬度為0.1~0.6um，長度為1.2~2.2um。 In this embodiment, the materials of the gate dielectric layer 21 and the voltage dividing dielectric layer 26 can be silicon dioxide or silicon nitride or a composite structure of silicon dioxide and silicon nitride, and the materials of the two can be The same may be different. The width of the trench 20 is 0.1~0.6um, and the length is 1.2~2.2um.

進一步地，在半導體層10內形成沿縱向延伸的摻雜類型為N型的源區31和漏區32，其中，源區31和漏區32可以互換；以及在半導體層10內形成鄰近所述溝槽下部的控制柵22的溝道區40。 Further, a source region 31 and a drain region 32 with an N-type doping type extending in the longitudinal direction are formed in the semiconductor layer 10, wherein the source region 31 and the drain region 32 can be interchanged; The channel region 40 of the control gate 22 in the lower part of the trench.

在本實施例中，所述半導體層10的摻雜類型為第一摻雜類型，所述源區31和漏區32的摻雜類型為第二摻雜類型，所述溝道區40的摻雜類型為第一摻雜類型或第二摻雜類型，第一摻雜類型和第二摻雜類型相反。 In this embodiment, the doping type of the semiconductor layer 10 is the first doping type, the doping type of the source region 31 and the drain region 32 is the second doping type, and the doping type of the channel region 40 is the second doping type. The doping type is the first doping type or the second doping type, and the first doping type and the second doping type are opposite.

在本實施例中，所述源區31和漏區32從所述半導體層10的第一表面延伸至與所述溝槽下部的控制柵22交疊。所述源區31和漏區32在所述半導體層10中延伸的長度不超過溝槽20在半導體層10中延伸的長度。所述源區31和漏區32在所述半導體層10中延伸的長度為0.5~1.5um。 In this embodiment, the source region 31 and the drain region 32 extend from the first surface of the semiconductor layer 10 to overlap with the control gate 22 at the lower part of the trench. The length of the source region 31 and the drain region 32 extending in the semiconductor layer 10 does not exceed the length of the trench 20 extending in the semiconductor layer 10 . The length of the source region 31 and the drain region 32 extending in the semiconductor layer 10 is 0.5-1.5um.

溝槽20兩側的源區31和漏區32在半導體層中延伸的長度較長，與溝槽20下部的控制柵22交疊，在器件截止時，源區31和漏區32可以承擔了縱向方向上源區31和漏區32上施加的高壓，提高雙向功率器件的耐壓特性。 The source region 31 and the drain region 32 on both sides of the trench 20 extend in the semiconductor layer for a longer length and overlap with the control gate 22 at the lower part of the trench 20. When the device is turned off, the source region 31 and the drain region 32 can undertake The high voltage applied to the source region 31 and the drain region 32 in the longitudinal direction improves the withstand voltage characteristic of the bidirectional power device.

由於溝道區40鄰近位於所述溝槽20下部的控制柵22，可以通過減小溝槽的寬度來減小溝道長度，進而減小溝道電阻。 Since the channel region 40 is adjacent to the control gate 22 located at the lower part of the trench 20, the channel length can be reduced by reducing the width of the trench, thereby reducing the channel resistance.

進一步地，可以通過調整柵介質層21的厚度以及溝道區40的摻雜濃度來實現不同的閾值電壓。 Further, different threshold voltages can be achieved by adjusting the thickness of the gate dielectric layer 21 and the doping concentration of the channel region 40 .

進一步地，在所述源區31和所述漏區32中形成第一引線區311和第二引線區321。其中，第一引線區311的摻雜類型與源區31的摻雜類型相同，且第一引線區311的摻雜濃度大於源區31的摻雜濃度。第二引線區321的摻雜類型與漏區32的摻雜類型相同，且第二引線區321的摻雜濃度大於漏區32的摻雜濃度。 Further, a first lead region 311 and a second lead region 321 are formed in the source region 31 and the drain region 32 . The doping type of the first lead region 311 is the same as that of the source region 31 , and the doping concentration of the first lead region 311 is greater than that of the source region 31 . The doping type of the second lead region 321 is the same as that of the drain region 32 , and the doping concentration of the second lead region 321 is greater than that of the drain region 32 .

進一步地，在所述半導體層10中形成第三引線區101，所述第三引線區101靠近所述半導體層10的第一表面，其中，第三引線區101的摻雜類型與半導體層10的摻雜類型相同，且第三引線區101的摻雜 濃度大於半導體層10的摻雜濃度。 Further, a third lead region 101 is formed in the semiconductor layer 10 , the third lead region 101 is close to the first surface of the semiconductor layer 10 , wherein the doping type of the third lead region 101 is the same as that of the semiconductor layer 10 of the same doping type, and the doping of the third lead region 101 The concentration is higher than the doping concentration of the semiconductor layer 10 .

進一步地，在半導體層10的第一表面上形成覆蓋介質層11以及形成貫穿覆蓋介質層11的接觸孔50，所述接觸孔50包括第一接觸孔51、第二接觸孔52、第三接觸孔53以及第四接觸孔54。其中，第一接觸孔51位於所述源區31上，貫穿所述覆蓋介質層11延伸至所述源區31，所述第二接觸孔位於所述漏區32上，貫穿所述覆蓋介質層11延伸至所述漏區32。 Further, a covering dielectric layer 11 is formed on the first surface of the semiconductor layer 10 and a contact hole 50 penetrating the covering dielectric layer 11 is formed, and the contact hole 50 includes a first contact hole 51 , a second contact hole 52 and a third contact hole 53 and fourth contact hole 54 . The first contact hole 51 is located on the source region 31 and extends through the cover dielectric layer 11 to the source region 31 , and the second contact hole is located on the drain region 32 and penetrates through the cover dielectric layer. 11 extends to the drain region 32 .

第三接觸孔53位於所述溝槽20兩側貫穿所述覆蓋介質層11延伸至所述半導體層10。 The third contact holes 53 are located on both sides of the trench 20 and extend through the cover dielectric layer 11 to the semiconductor layer 10 .

第四接觸孔54位於所述溝槽20上，貫穿所述覆蓋介質層11延伸至所述溝槽20中的控制柵22。 The fourth contact hole 54 is located on the trench 20 and extends through the cover dielectric layer 11 to the control gate 22 in the trench 20 .

在本實施例中，覆蓋介質層11可以是未摻雜的矽玻璃(USG)和摻雜硼磷的矽玻璃(BPSG)。 In this embodiment, the cover dielectric layer 11 may be undoped silicon glass (USG) or boron phosphorous doped silicon glass (BPSG).

在所述覆蓋介質層11上沉積金屬層60，金屬層60填充第一接觸孔51至第四接觸孔54分別形成第一接觸61至第四接觸64。第一接觸61通過第一接觸孔51、第一引線區311與所述源區31相接觸以形成第一輸出電極S1，第二接觸62通過第二接觸孔52、第二引線區321與所述漏區32相接觸以形成第二輸出電極S2，所述第三接觸63通過第三接觸孔53、第三引線區101與所述半導體層10相接觸以形成襯底電極Sub。如第19圖所示，第四接觸64經由第四接觸孔54與控制柵22相接觸以形成柵電極。 A metal layer 60 is deposited on the cover dielectric layer 11 , and the metal layer 60 fills the first contact hole 51 to the fourth contact hole 54 to form the first contact 61 to the fourth contact 64 , respectively. The first contact 61 contacts the source region 31 through the first contact hole 51 and the first lead region 311 to form the first output electrode S1, and the second contact 62 contacts the source region 31 through the second contact hole 52 and the second lead region 321. The drain region 32 is in contact with the semiconductor layer 10 to form the second output electrode S2, and the third contact 63 is in contact with the semiconductor layer 10 through the third contact hole 53 and the third lead region 101 to form the substrate electrode Sub. As shown in FIG. 19 , the fourth contact 64 is in contact with the control gate 22 through the fourth contact hole 54 to form a gate electrode.

在本實施例中，金屬層60的材料可以為鈦和氮化鈦、鋁銅、鋁矽銅或者鋁矽。 In this embodiment, the material of the metal layer 60 may be titanium and titanium nitride, aluminum copper, aluminum silicon copper, or aluminum silicon.

第18圖中一個元胞只包含了三個溝槽、一個源區和一個漏區，而實際產品當中，源區31和漏區32的數量不止一個。以第18圖所示的為例， One cell in Figure 18 only includes three trenches, one source region and one drain region, but in the actual product, the number of source regions 31 and drain regions 32 is more than one. Taking the example shown in Figure 18,

三個溝槽分別為第一溝槽20a、第二溝槽20b和第三溝槽20c。其中，第一接觸61將源區31引出至半導體層10表面形成第一輸出電極S1，第二接觸62將漏區32引出至半導體層10表面形成第二輸出電極 S2，第三接觸63將半導體層10引出形成襯底電極Sub，第四接觸64將控制柵22引出至半導體層10表面形成柵電極G。第一溝槽20a和第三溝槽20c對稱設定在源區31和漏區32外。其中，第一輸出電極S1和第二輸出電極S2分別是源區31和漏區32引出至半導體層10表面形成的，兩者可以互換。 The three trenches are a first trench 20a, a second trench 20b and a third trench 20c, respectively. The first contact 61 leads the source region 31 to the surface of the semiconductor layer 10 to form the first output electrode S1, and the second contact 62 leads the drain region 32 to the surface of the semiconductor layer 10 to form the second output electrode S2, the third contact 63 leads the semiconductor layer 10 to form the substrate electrode Sub, and the fourth contact 64 leads the control gate 22 to the surface of the semiconductor layer 10 to form the gate electrode G. The first trench 20 a and the third trench 20 c are symmetrically set outside the source region 31 and the drain region 32 . Wherein, the first output electrode S1 and the second output electrode S2 are formed by leading the source region 31 and the drain region 32 to the surface of the semiconductor layer 10 respectively, and the two can be interchanged.

當控制柵22上施加的電壓大於閾值電壓時，雙向功率器件導通，第二溝槽20b中的溝道區有電流流過，通過選擇其中一個輸出端電極與襯底電極連接，實現電流方向的選擇，例如，當第一輸出電極S1與襯底電極Sub連接時，電流從第二輸出電極S2流向第一輸出電極S1；當第二輸出電極S2與襯底電極Sub連接時，電流從第一輸出電極S1流向第二輸出電極S2。 When the voltage applied to the control gate 22 is greater than the threshold voltage, the bidirectional power device is turned on, and current flows through the channel region in the second trench 20b. By selecting one of the output electrodes to connect with the substrate electrode, the direction of the current is realized. For example, when the first output electrode S1 is connected to the substrate electrode Sub, the current flows from the second output electrode S2 to the first output electrode S1; when the second output electrode S2 is connected to the substrate electrode Sub, the current flows from the first output electrode S2 to the substrate electrode Sub. The output electrode S1 flows to the second output electrode S2.

當控制柵22上施加的電壓小於閾值電壓時，雙向功率器件截止，第一輸出電極S1和第二輸出電極S2上施加高電壓，隨著源區31和漏區32在半導體中延伸的長度增加，承擔了源區31和漏區32上施加的高電壓，提高雙向功率器件的耐壓特性。 When the voltage applied to the control gate 22 is less than the threshold voltage, the bidirectional power device is turned off, and a high voltage is applied to the first output electrode S1 and the second output electrode S2, as the length of the source region 31 and the drain region 32 in the semiconductor increases. , bears the high voltage applied on the source region 31 and the drain region 32, and improves the withstand voltage characteristic of the bidirectional power device.

第21圖僅示出了兩個元胞結構的示意圖，多個第一接觸61連接在一起形成第一輸出電極S1，多個第二接觸62連接在一起形成第二輸出電極S2，以提高器件的電流能力。替代地，對於其他類型的雙向功率器件，通過增加元胞的數量，即選擇兩個及更多元胞結構並聯連接，可以提高器件的電流能力。 FIG. 21 only shows a schematic diagram of two cell structures, a plurality of first contacts 61 are connected together to form a first output electrode S1, and a plurality of second contacts 62 are connected together to form a second output electrode S2, so as to improve the device current capability. Alternatively, for other types of bidirectional power devices, the current capability of the device can be improved by increasing the number of cells, ie selecting two or more cell structures to be connected in parallel.

第九實施例 Ninth Embodiment

本實施例與第一實施例、第四實施例、第六實施例以及第八實施例相比，本實施例還包括佈線層70和位於佈線層70上的多個金屬焊球80。 Compared with the first embodiment, the fourth embodiment, the sixth embodiment and the eighth embodiment, this embodiment further includes a wiring layer 70 and a plurality of metal solder balls 80 on the wiring layer 70 .

由於溝槽20的間距很小，溝槽結構引出的柵電極比較窄小，使得寄生電阻很大。為了減小寄生電阻，在第一實施例、第四實施例、第六實施例以及第八實施例提供的雙向功率器件上方增加佈線層70。 Since the distance between the trenches 20 is small, the gate electrode drawn from the trench structure is relatively narrow, resulting in a large parasitic resistance. In order to reduce the parasitic resistance, a wiring layer 70 is added above the bidirectional power devices provided in the first embodiment, the fourth embodiment, the sixth embodiment and the eighth embodiment.

如第22圖-第26圖所示，佈線層70位於所述雙向功率器件的表面上，用於將第一接觸61、第二接觸62、第三接觸63和第四接觸 64形成的第一輸出電極S1、第二輸出電極S2、襯底電極Sub以及柵電極G引出至所述雙向功率器件表面。 As shown in FIGS. 22-26, the wiring layer 70 is located on the surface of the bidirectional power device, and is used to connect the first contact 61, the second contact 62, the third contact 63 and the fourth contact The first output electrode S1, the second output electrode S2, the substrate electrode Sub and the gate electrode G formed by 64 are led out to the surface of the bidirectional power device.

其中，第一接觸61、第二接觸62、第三接觸63和第四接觸64位於第一金屬層M1中，佈線層70位於第二金屬層M2中，第一金屬層M1和第二金屬層M2之間由覆蓋介質層11隔離。佈線層70與第一接觸61、第二接觸62、第三接觸63和第四接觸64通過多個導電孔90實現電連接。佈線層70包括第一佈線71、第二佈線72、第三佈線73和第四佈線74(圖中未示出)，其中，第一佈線71與第一接觸61電連接；第二佈線72與第二接觸62電連接；第三佈線73與第三接觸63電連接；第四布線74與第四接觸64電連接。 Wherein, the first contact 61, the second contact 62, the third contact 63 and the fourth contact 64 are located in the first metal layer M1, the wiring layer 70 is located in the second metal layer M2, the first metal layer M1 and the second metal layer The M2 is isolated by the cover dielectric layer 11 . The wiring layer 70 is electrically connected to the first contact 61 , the second contact 62 , the third contact 63 and the fourth contact 64 through a plurality of conductive holes 90 . The wiring layer 70 includes a first wiring 71, a second wiring 72, a third wiring 73 and a fourth wiring 74 (not shown in the figure), wherein the first wiring 71 is electrically connected to the first contact 61; the second wiring 72 is electrically connected to The second contact 62 is electrically connected; the third wiring 73 is electrically connected to the third contact 63 ; the fourth wiring 74 is electrically connected to the fourth contact 64 .

在本實施例中，佈線層70採用更寬的金屬線引出以減小金屬層的寄生電阻。 In this embodiment, wider metal lines are used to lead out the wiring layer 70 to reduce the parasitic resistance of the metal layer.

多個金屬焊球80，位於所述佈線層70上，通過佈線層70與所述第一輸出電極S1、第二輸出電極S2、襯底電極Sub以及柵電極G電連接。其中，金屬焊球80包括與所述第一輸出電極S1電連接的金屬焊球81、與所述第二輸出電極S2電連接的金屬焊球82、與所述襯底電極Sub電連接的金屬焊球83以及與所述柵電極G電連接的金屬焊球84(圖中未示出)。 A plurality of metal solder balls 80 are located on the wiring layer 70 and are electrically connected to the first output electrode S1 , the second output electrode S2 , the substrate electrode Sub and the gate electrode G through the wiring layer 70 . The metal solder balls 80 include metal solder balls 81 electrically connected to the first output electrode S1, metal solder balls 82 electrically connected to the second output electrode S2, and metal solder balls electrically connected to the substrate electrode Sub The solder balls 83 and the metal solder balls 84 electrically connected to the gate electrode G (not shown in the figure).

在本實施例中，採用植球工藝在佈線層上形成多個金屬焊球80，完成晶片級封裝。金屬焊球81為第一輸出電極S1與外部電連接的焊盤引腳，金屬焊球82為第二輸出電極S2與外部電連接的焊盤引腳，金屬焊球83為襯底電極與外部電連接的焊盤引腳，金屬焊球84為柵電極與外部電連接的焊盤引腳。 In this embodiment, a plurality of metal solder balls 80 are formed on the wiring layer by a ball-mounting process to complete the wafer-level package. The metal solder balls 81 are the pad pins for the electrical connection between the first output electrode S1 and the outside, the metal solder balls 82 are the pad pins for the electrical connection between the second output electrode S2 and the outside, and the metal solder balls 83 are for the substrate electrodes and the outside. Electrically connected pad pins, the metal solder balls 84 are pad pins electrically connected to the gate electrode and the outside.

在一個優選地實施例中，金屬焊球80與佈線層70之間還形成有電鍍金屬層M3，使得金屬焊球80與佈線層70之間的結合更加牢固。 In a preferred embodiment, an electroplating metal layer M3 is further formed between the metal solder balls 80 and the wiring layer 70 , so that the bonding between the metal solder balls 80 and the wiring layer 70 is more firm.

第一輸出電極S1和第二輸出電極S2由於需要通過過大電流，囙此分佈了比較多的金屬焊球81和82，如第27圖所示，可以增加了雙向功率器件和外部系統之間的電流分佈。 Since the first output electrode S1 and the second output electrode S2 need to pass excessive current, more metal solder balls 81 and 82 are distributed, as shown in Figure 27, which can increase the distance between the bidirectional power device and the external system. current distribution.

第九實施例由於採用了植球的工藝，省略了傳統封裝的打線，減小了封裝的寄生電感和寄生電阻，減小雙向功率器件的封裝電阻；由於沒有塑封料的包封，使得散熱更加容易，減小功耗，提高雙向功率器件的可靠性和安全性。 Since the ninth embodiment adopts the ball-mounting process, the wire bonding of the traditional package is omitted, the parasitic inductance and parasitic resistance of the package are reduced, and the package resistance of the bidirectional power device is reduced. It is easy to reduce power consumption and improve the reliability and safety of bidirectional power devices.

第十實施例 Tenth Embodiment

本實施例與第八實施例採用基本相同的技術方案，不同之處在於，第八實施例中，第三接觸63形成在半導體層10的第一表面上，通過第三接觸孔53、第三引線區101與所述半導體層10相接觸以形成襯底電極Sub。而本實施例中，第三接觸63形成在半導體層10的第二表面上，如第28圖所示。具體地，將雙向功率器件形成在摻雜濃度較高的襯底1上，然後在襯底1的背面蒸發金屬層形成第三接觸63。 This embodiment adopts basically the same technical solution as the eighth embodiment, the difference lies in that, in the eighth embodiment, the third contact 63 is formed on the first surface of the semiconductor layer 10, and the third contact hole 53, the third contact hole 53, the third The lead region 101 is in contact with the semiconductor layer 10 to form the substrate electrode Sub. In this embodiment, however, the third contact 63 is formed on the second surface of the semiconductor layer 10 , as shown in FIG. 28 . Specifically, the bidirectional power device is formed on the substrate 1 with higher doping concentration, and then the third contact 63 is formed by evaporating a metal layer on the backside of the substrate 1 .

第八實施例中，雙向功率器件的柵極、襯底電極、第一輸出電極和第二輸出電極均從半導體層10的第一表面引出，適合晶片級封裝(CSP)。 In the eighth embodiment, the gate electrode, the substrate electrode, the first output electrode and the second output electrode of the bidirectional power device are all drawn out from the first surface of the semiconductor layer 10 , which are suitable for wafer level packaging (CSP).

第十實施例中，雙向功率器件的襯底電極從半導體層10的第二表面引出，既能適應傳統的器件封裝形式(例如SOP8、DIP8)，同時增加了雙向功率器件的散熱能力。 In the tenth embodiment, the substrate electrode of the bidirectional power device is drawn out from the second surface of the semiconductor layer 10 , which not only adapts to traditional device packaging forms (eg, SOP8, DIP8), but also increases the heat dissipation capability of the bidirectional power device.

本實施例中，雙向功率器件的其餘部分與第八實施例基本相同，具體結構不再贅述。 In this embodiment, the rest of the bidirectional power device is basically the same as that of the eighth embodiment, and the specific structure will not be repeated.

依照本發明的實施例如上文所述，這些實施例並沒有詳盡敘述所有的細節，也不限制該發明僅為所述的具體實施例。顯然，根據以上描述，可作很多的修改和變化。本說明書選取並具體描述這些實施例，是為了更好地解釋本發明的原理和實際應用，從而使所屬技術領域技術人員能很好地利用本發明以及在本發明基礎上的修改使用。本發明僅受申請專利範圍和等效物的限制。 Embodiments in accordance with the present invention are described above, but these embodiments do not exhaust all the details and do not limit the invention to only the specific embodiments described. Obviously, many modifications and variations are possible in light of the above description. This specification selects and specifically describes these embodiments in order to better explain the principle and practical application of the present invention, so that those skilled in the art can make good use of the present invention and modifications based on the present invention. The present invention is limited only by the scope of the claims and equivalents.

10:半導體層 10: Semiconductor layer

11:覆蓋介質層 11: Cover the dielectric layer

20a:第一溝槽 20a: First groove

20b:第二溝槽 20b: Second groove

20c:第三溝槽 20c: Third groove

21:栅介質層 21: Gate dielectric layer

22:控制栅 22: Control grid

23:遮罩柵 23: Shading grid

24:隔離層 24: isolation layer

25:遮罩介質層 25: Mask dielectric layer

31:源區 31: Source area

32:漏區 32: Drain area

40:溝道區 40: Channel region

51:第一接觸孔 51: The first contact hole

52:第二接觸孔 52: The second contact hole

53:第三接觸孔 53: The third contact hole

61:第一接觸 61: First Contact

62:第二接觸 62: Second Contact

63:第三接觸 63: Third Contact

101:第三引線區 101: The third lead area

311:第一引線區 311: The first lead area

321:第二引線區 321: Second lead area

W1,W2:寬度 W1,W2: width

L1,L2,L3,K:長度 L1,L2,L3,K: length

Claims (36)

一種雙向功率器件，其特徵在於，包括：半導體層；位於半導體層中的溝槽；位於所述溝槽側壁上的柵介質層；位於所述溝槽下部的控制柵；以及位於所述半導體層中且鄰近所述控制柵的溝道區；其中，所述控制柵與所述半導體層之間由所述柵介質層隔開，所述溝道區的摻雜類型為第一摻雜類型或第二摻雜類型。 A bidirectional power device, comprising: a semiconductor layer; a trench located in the semiconductor layer; a gate dielectric layer located on the sidewall of the trench; a control gate located at the lower part of the trench; in and adjacent to the channel region of the control gate; wherein, the control gate and the semiconductor layer are separated by the gate dielectric layer, and the doping type of the channel region is the first doping type or The second doping type. 如請求項1所述的雙向功率器件，其特徵在於，還包括：位於所述溝槽上部的遮罩柵。 The bidirectional power device according to claim 1, further comprising: a shield grid located on the upper part of the trench. 如請求項2所述的雙向功率器件，其特徵在於，還包括：位於所述控制柵和所述遮罩柵之間的隔離層。 The bidirectional power device according to claim 2, further comprising: an isolation layer between the control gate and the mask gate. 如請求項3所述的雙向功率器件，其特徵在於，所述遮罩柵的長度為0.6~1.2um。 The bidirectional power device according to claim 3, wherein the length of the shield grid is 0.6-1.2um. 如請求項2所述的雙向功率器件，其特徵在於，所述控制柵和所述遮罩柵彼此接觸。 The bidirectional power device of claim 2, wherein the control gate and the shadow gate are in contact with each other. 如請求項5所述的雙向功率器件，其特徵在於，所述遮罩柵的長度為0.4~0.8um。 The bidirectional power device according to claim 5, wherein the length of the shield grid is 0.4-0.8um. 如請求項2-6任一項所述的雙向功率器件，其特徵在於，還包括：位於溝槽側壁上的遮罩介質層，所述遮罩柵與所述半導體層之間由所述遮罩介質層隔開。 The bidirectional power device according to any one of claims 2 to 6, further comprising: a shielding dielectric layer located on the sidewall of the trench, and the shielding gate and the semiconductor layer are formed by the shielding dielectric layer. The cover dielectric layer is separated. 如請求項7所述的雙向功率器件，其特徵在於，所述遮罩介質層的厚度為0.1~0.25um。 The bidirectional power device according to claim 7, wherein the thickness of the mask dielectric layer is 0.1-0.25um. 如請求項7所述的雙向功率器件，其特徵在於，所述遮罩介質層的厚度大於或等於所述柵介質層的厚度。 The bidirectional power device according to claim 7, wherein the thickness of the mask dielectric layer is greater than or equal to the thickness of the gate dielectric layer. 如請求項2所述的雙向功率器件，其特徵在於，所述控制柵的寬度大於所述遮罩柵的寬度。 The bidirectional power device according to claim 2, wherein the width of the control gate is greater than the width of the mask gate. 如請求項7所述的雙向功率器件，其特徵在於，還包括：位於所述半導體層中且鄰近所述遮罩柵的源區和漏區，所述源區和漏區從所述半導體層的第一表面延伸至與所述控制柵交迭。 The bidirectional power device of claim 7, further comprising: a source region and a drain region located in the semiconductor layer and adjacent to the mask gate, the source region and the drain region extending from the semiconductor layer The first surface extends to overlap the control gate. 如請求項11所述的雙向功率器件，其特徵在於，所述源區和漏區的長度大於所述遮罩柵和隔離層的長度之和，小於所述遮罩柵、隔離層以及所述控制柵的長度之和。 The bidirectional power device according to claim 11, wherein the lengths of the source region and the drain region are greater than the sum of the lengths of the mask gate and the isolation layer, and are less than the length of the mask gate, the isolation layer and the The sum of the lengths of the control gates. 如請求項11所述的雙向功率器件，其特徵在於，所述源區和漏區的長度大於所述遮罩柵的長度，小於所述遮罩柵以及所述控制柵的長度之和。 The bidirectional power device according to claim 11, wherein the length of the source region and the drain region is greater than the length of the mask gate and less than the sum of the lengths of the mask gate and the control gate. 如請求項1所述的雙向功率器件，其特徵在於，還包括：位於所述溝槽上部的分壓介質層。 The bidirectional power device according to claim 1, further comprising: a voltage dividing dielectric layer located on the upper part of the trench. 如請求項14所述的雙向功率器件，其特徵在於，還包括：位於所述半導體層中且鄰近所述分壓介質層的源區和漏區，所述源區和漏區從所述半導體層的第一表面延伸至與所述控制柵交迭。 The bidirectional power device of claim 14, further comprising: a source region and a drain region located in the semiconductor layer and adjacent to the voltage dividing dielectric layer, the source region and the drain region extending from the semiconductor layer The first surface of the layer extends to overlap the control gate. 如請求項14所述的雙向功率器件，其特徵在於，所述分壓介質層的長度大於0.3um。 The bidirectional power device according to claim 14, wherein the length of the pressure dividing medium layer is greater than 0.3um. 如請求項14所述的雙向功率器件，其特徵在於，所述源區和漏區的長度大於所述分壓介質層的長度，小於所述分壓介質層和所述控制柵的長度。 The bidirectional power device according to claim 14, wherein the lengths of the source region and the drain region are greater than the length of the voltage dividing dielectric layer, and less than the lengths of the voltage dividing dielectric layer and the control gate. 如請求項1所述的雙向功率器件，其特徵在於，所述控制柵從所述半導體層的第一表面延伸至所述溝槽下部。 The bidirectional power device of claim 1, wherein the control gate extends from the first surface of the semiconductor layer to a lower portion of the trench. 如請求項18所述的雙向功率器件，其特徵在於，還包括：位於所述半導體層中且鄰近控制柵的源區和漏區，所述源區和漏區從所述半導體層的第一表面延伸至與所述溝槽下部的控制柵交迭。 The bidirectional power device of claim 18, further comprising: a source region and a drain region located in the semiconductor layer and adjacent to the control gate, the source region and the drain region extending from the first The surface extends to overlap the control gate in the lower portion of the trench. 如請求項19所述的雙向功率器件，其特徵在於，所述源區和漏區在所述半導體層中延伸的長度為0.5~1.5um。 The bidirectional power device according to claim 19, wherein the length of the source region and the drain region extending in the semiconductor layer is 0.5-1.5um. 如請求項1所述的雙向功率器件，其特徵在於，所述溝槽的長度為1.2~2.2um，寬度為0.1~0.6um。 The bidirectional power device according to claim 1, wherein the trench has a length of 1.2-2.2 um and a width of 0.1-0.6 um. 如請求項11、15、和19中任一項所述的雙向功率器件，其特徵在於，所述半導體層的摻雜類型為第一摻雜類型，所述源區和漏區的摻雜類型為第二摻雜類型，所述溝道區的摻雜類型為第一摻雜類型或第二摻雜類型，第一摻雜類型和第二摻雜類型相反。 The bidirectional power device according to any one of claims 11, 15, and 19, wherein the doping type of the semiconductor layer is the first doping type, and the doping type of the source region and the drain region is the first doping type. is the second doping type, the doping type of the channel region is the first doping type or the second doping type, and the first doping type and the second doping type are opposite. 如請求項1所述的雙向功率器件，其特徵在於，所述半導體層選自半導體襯底本身、在半導體襯底上形成的外延層或者在半導體襯底中注入的阱區中的一種。 The bidirectional power device according to claim 1, wherein the semiconductor layer is selected from one of the semiconductor substrate itself, an epitaxial layer formed on the semiconductor substrate, or a well region implanted in the semiconductor substrate. 如請求項22所述的雙向功率器件，其特徵在於，還包括：第一接觸，與所述源區相接觸以形成第一輸出電極；第二接觸，與所述漏區相接觸以形成第二輸出電極；第三接觸，與所述半導體層相接觸以形成襯底電極；第四接觸，與所述控制柵相接觸以形成柵電極。 The bidirectional power device of claim 22, further comprising: a first contact contacting the source region to form a first output electrode; a second contact contacting the drain region to form a first output electrode Two output electrodes; a third contact, in contact with the semiconductor layer to form a substrate electrode; and a fourth contact, in contact with the control gate to form a gate electrode. 如請求項24所述的雙向功率器件，其特徵在於，還包括：第一引線區，位於所述源區內，其中，第一引線區的摻雜濃度大於所述源區的摻雜濃度；覆蓋介質層，位於所述半導體層的第一表面上；第一接觸孔，貫穿所述覆蓋介質層延伸至所述源區；所述第一接觸通過第一接觸孔、第一引線區與所述源區相接觸。 The bidirectional power device according to claim 24, further comprising: a first lead region located in the source region, wherein the doping concentration of the first lead region is greater than the doping concentration of the source region; A cover dielectric layer is located on the first surface of the semiconductor layer; a first contact hole extends through the cover dielectric layer to the source region; the first contact passes through the first contact hole, the first lead region and the contact with the source region. 如請求項25所述的雙向功率器件，其特徵在於，還包括：第二引線區，位於所述漏區內，其中，第二引線區的摻雜濃度大於所述漏區的摻雜濃度；第二接觸孔，貫穿所述覆蓋介質層延伸至所述漏區；所述第二接觸通過第二接觸孔、第二引線區與所述漏區相接觸。 The bidirectional power device according to claim 25, further comprising: a second lead region located in the drain region, wherein the doping concentration of the second lead region is greater than the doping concentration of the drain region; The second contact hole extends through the cover dielectric layer to the drain region; the second contact is in contact with the drain region through the second contact hole and the second lead region. 如請求項26所述的雙向功率器件，其特徵在於，還包括：第三引線區，位於所述半導體層內且靠近所述半導體層的第一表面，其中，所述第三引線區的摻雜濃度大於半導體層的摻雜濃度；第三接觸孔，貫穿所述覆蓋介質層延伸至所述半導體層；所述第三接觸通過第三接觸孔、第三引線區與所述半導體層相接觸。 The bidirectional power device of claim 26, further comprising: a third lead region located in the semiconductor layer and close to the first surface of the semiconductor layer, wherein the third lead region is doped The impurity concentration is greater than the doping concentration of the semiconductor layer; the third contact hole extends through the covering dielectric layer to the semiconductor layer; the third contact is in contact with the semiconductor layer through the third contact hole and the third lead region . 如請求項26所述雙向功率器件，其特徵在於，還包括：第四接觸孔，貫穿所述覆蓋介質層延伸至所述控制柵。 The bidirectional power device of claim 26, further comprising: a fourth contact hole extending through the cover dielectric layer to the control gate. 如請求項26所述的雙向功率器件，其特徵在於，所述第三接觸位於所述半導體層的第二表面上。 The bidirectional power device of claim 26, wherein the third contact is on the second surface of the semiconductor layer. 如請求項24所述的雙向功率器件，其特徵在於，還包括：佈線層，所述佈線層包括第一佈線至第四佈線，分別通過多個導電孔與所述第一輸出電極、第二輸出電極、襯底電極以及柵電極電連接。 The bidirectional power device according to claim 24, further comprising: a wiring layer, wherein the wiring layer includes a first wiring to a fourth wiring, which are connected to the first output electrode and the second output electrode through a plurality of conductive holes, respectively. The output electrode, the substrate electrode, and the gate electrode are electrically connected. 如請求項30所述的雙向功率器件，其特徵在於，還包括：多個金屬焊球，位於所述佈線層上，通過佈線層與所述第一輸出電極、第二輸出電極、襯底電極以及柵電極電連接。 The bidirectional power device according to claim 30, further comprising: a plurality of metal solder balls located on the wiring layer and connected to the first output electrode, the second output electrode and the substrate electrode through the wiring layer and the gate electrode is electrically connected. 如請求項24所述的雙向功率器件，其特徵在於，當所述雙向功率器件包括位於控制柵上的遮罩柵時，第四接觸還與所述遮罩柵電連接。 The bidirectional power device of claim 24, wherein when the bidirectional power device includes a shadow grid on the control grid, the fourth contact is further electrically connected to the shadow grid. 如請求項32所述的雙向功率器件，其特徵在於，所述遮罩柵與所述半導體層或所述控制柵電連接。 The bidirectional power device of claim 32, wherein the shadow gate is electrically connected to the semiconductor layer or the control gate. 如請求項11、15和19中任一項所述的雙向功率器件，其特徵在於，在所述雙向功率器件導通時，所述襯底電極與第一輸出電極和第二輸出電極之一電連接實現電流方向的雙向選擇。 The bidirectional power device according to any one of claims 11, 15 and 19, wherein when the bidirectional power device is turned on, the substrate electrode is electrically connected to one of the first output electrode and the second output electrode The connection enables bidirectional selection of current direction. 如請求項34所述的雙向功率器件，其特徵在於，當所述襯底電極與所述第一輸出電極電連接時，電流從所述第二輸出電極流向所述第一輸出電極；當所述襯底電極與所述第二輸出電極電連接時，電流從所述第一輸出電極流向所述第二輸出電極。 The bidirectional power device of claim 34, wherein when the substrate electrode is electrically connected to the first output electrode, current flows from the second output electrode to the first output electrode; When the substrate electrode is electrically connected to the second output electrode, current flows from the first output electrode to the second output electrode. 一種雙向功率器件，其特徵在於，包括多個元胞結構，所述元胞結構為如請求項11、12、13、15及19任一項所述的雙向功率器件；其中，多個元胞結構中的源區電連接在一起，多個元胞結構中的漏區電連接在一起。 A bidirectional power device, characterized in that it includes a plurality of cell structures, and the cell structures are the bidirectional power device according to any one of claim 11, 12, 13, 15, and 19; wherein, the plurality of cells The source regions in the structure are electrically connected together, and the drain regions in the plurality of cell structures are electrically connected together.
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