JP2024007911A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device which is high in switching speed not only in a low breakdown voltage range but also in a high breakdown voltage range and which is low in on-resistance.SOLUTION: A semiconductor device includes a first semiconductor element 71 and a second semiconductor element 72. These elements each include: parallel pn structures 32, 32B where a striped first column region 3 of a first conductivity type and a striped second column region 4 of a second conductivity type are alternately arranged; first electrode 10, 12; a second electrode 11; a channel stopper 40 of the second conductivity type; and a first semiconductor region 3C of the first conductivity type. The second electrode 11 of the first semiconductor element 71 and the second electrode 11 of the second semiconductor element 72 are electrically connected. The channel stopper 40 of the first semiconductor element 71 and the channel stopper 40 of the second semiconductor element 72 are electrically connected. Longitudinal sides in the first column region 3 and the second column region 4 are orthogonal to sides where the first semiconductor element and the second semiconductor element are adjacent to each other.SELECTED DRAWING: Figure 8

Description

The present invention relates to a semiconductor device.

Conventionally, as a method for improving the power conversion efficiency of a power supply device, there is an AT-NCT (Advanced T-type Neutral-point-Clamped) having a neutral point clamp. In this method, a bidirectional switch circuit using an IGBT (Insulated Gate Bipolar Transistor) is used. FIG. 19 is an example of a bidirectional switch circuit using a conventional IGBT. As shown in FIG. 19, since the IGBT 110 has no reverse withstand voltage, it is connected in series with an FWD (Free Wheeling Diode) 111, and two sets of these are connected in antiparallel, so that the order of the diode (FWD) 111 can be adjusted. It blocks directional current, has reverse withstand voltage, and enables bidirectional operation.

However, in this method, a forward voltage is applied to the diode 111 during conduction, resulting in a large conduction loss. For this reason, there are products that use an RB-IGBT (Reverse Blocking-IGBT) 112 that has a reverse withstand voltage, eliminate the need for a diode that has a reverse withstand voltage, and reduce conduction loss (for example, see the following non-patent document 1). ). FIG. 20 is an example of a bidirectional switch circuit using a conventional RB-IGBT.

In addition, MOSFETs (Metal Oxide Semiconductor Field Effect Transistors: Insulated Gate Field Effect Transistors) have reverse battery connection protection by connecting MOSFETs in antiparallel, which has a reverse withstand voltage due to the built-in parasitic diode and blocks forward current. , a device that enables bidirectional operation has been proposed (for example, see Patent Document 1 below).

Further, two switching elements are provided on one semiconductor substrate, and a first element region FCM (first switching element) having a P-type column CLM and a second element region RCM (second switching element) have a common drain D12. A semiconductor device that is electrically connected in series via a semiconductor device is known (for example, see Patent Document 2 below). Further, a semiconductor device is known that includes an SJ-MOSFET and a junction FET having a parallel pn region in an edge termination region on the same frame electrode (for example, see Patent Document 3 below).

JP2020-47660A JP2020-65021A JP 2021-190683 Publication

Manabu Takei et al., Applied technology of reverse blocking IGBT, Fuji Jiho Vol. 75 No. 8 2002

However, although devices using IGBTs are effective in high voltage and large current ranges, they suffer from large switching losses due to their slow switching speeds compared to MOSFETs, and poor conduction losses in voltage ranges below 200V. be. On the other hand, MOSFETs have a fast switching speed, so switching loss is small, and in the voltage range below 200V, the on-resistance is low, allowing for large currents, and there is little conduction loss, but in the voltage range exceeding 200V, the on-resistance increases rapidly. There is a problem that conduction loss increases.

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems with the conventional technology, it is an object of the present invention to provide a semiconductor device that has high switching speed and low on-resistance (low conduction loss) not only in the low voltage region but also in the high voltage region. shall be.

In order to solve the above problems and achieve the objects of the present invention, a semiconductor device according to the present invention has the following features. The semiconductor device includes a first semiconductor element and a second semiconductor element, each having an active region and a termination structure disposed outside the active region and surrounding the active region. In the first semiconductor element and the second semiconductor element, a first conductivity type drift layer having a lower impurity concentration than the semiconductor substrate is provided on the front surface of a first conductivity type semiconductor substrate. In the active region, a striped first first column region of a first conductivity type provided in the drift layer toward the semiconductor substrate, and a striped first second column region of a second conductivity type. and are repeatedly alternately arranged in a direction parallel to the front surface. In the termination structure section, a striped second first column region of the first conductivity type provided in the drift layer and provided from the surface of the drift layer toward the semiconductor substrate; A second parallel pn structure is provided in which conductive type second column regions are repeatedly and alternately arranged in a direction parallel to the front surface. A base region of a second conductivity type is provided in the surface layer of the first parallel pn structure. A source region of a first conductivity type is selectively provided in a surface layer of the base region. A trench is provided that penetrates the source region and the base region and reaches the first column region. A gate electrode is provided inside the trench with a gate insulating film interposed therebetween. A first electrode is provided in contact with the source region and the base region. A second electrode is provided on the back surface of the semiconductor substrate. A channel stopper of a second conductivity type is provided on a surface layer of the drift layer of the termination structure. A first semiconductor region of a first conductivity type in contact with the channel stopper is selectively provided in the drift layer of the termination structure. The second electrode of the first semiconductor element and the second electrode of the second semiconductor element are electrically connected. The channel stopper of the first semiconductor element and the channel stopper of the second semiconductor element are electrically connected at a side where the first semiconductor element and the second semiconductor element are adjacent to each other. A longitudinal side of the first column region and the second column region is perpendicular to a side where the first semiconductor element and the second semiconductor element are adjacent to each other.

Further, in the semiconductor device according to the above-described invention, in the side where the first semiconductor element and the second semiconductor element are adjacent to each other, the first semiconductor region of the first semiconductor element and the second semiconductor element are adjacent to each other. A second semiconductor region of a first conductivity type having a lower impurity concentration than the first semiconductor region is provided between the first semiconductor region and the first semiconductor region.

Further, in the semiconductor device according to the above-described invention, in the side where the first semiconductor element and the second semiconductor element are adjacent to each other, the first semiconductor region of the first semiconductor element and the second semiconductor element are adjacent to each other. A third semiconductor region of a second conductivity type is provided between the first semiconductor region and the first semiconductor region.

In order to solve the above problems and achieve the objects of the present invention, a semiconductor device according to the present invention has the following features. The semiconductor device includes a first semiconductor element and a second semiconductor element, each having an active region and a termination structure disposed outside the active region and surrounding the active region. In the first semiconductor element and the second semiconductor element, a first conductivity type drift layer having a lower impurity concentration than the semiconductor substrate is provided on the front surface of a first conductivity type semiconductor substrate. In the active region, a striped first first column region of a first conductivity type provided in the drift layer toward the semiconductor substrate, and a striped first second column region of a second conductivity type. and are repeatedly alternately arranged in a direction parallel to the front surface. In the termination structure section, a striped second first column region of the first conductivity type provided in the drift layer and provided from the surface of the drift layer toward the semiconductor substrate; A second parallel pn structure is provided in which conductive type second column regions are repeatedly and alternately arranged in a direction parallel to the front surface. A base region of a second conductivity type is provided in the surface layer of the first parallel pn structure. A source region of a first conductivity type is selectively provided in a surface layer of the base region. A trench is provided that extends through the source region and the base region to reach the first column region. A gate electrode is provided inside the trench with a gate insulating film interposed therebetween. A first electrode is provided in contact with the source region and the base region. A second electrode is provided on the back surface of the semiconductor substrate. A channel stopper of a second conductivity type is provided on a surface layer of the drift layer of the termination structure. A first semiconductor region of a first conductivity type in contact with the channel stopper is selectively provided in the drift layer of the termination structure. The second electrode of the first semiconductor element and the second electrode of the second semiconductor element are electrically connected. The channel stopper of the first semiconductor element and the channel stopper of the second semiconductor element are electrically connected at a side where the first semiconductor element and the second semiconductor element are adjacent to each other. A longitudinal side of the first column region and the second column region is parallel to a side where the first semiconductor element and the second semiconductor element are adjacent to each other.

In order to solve the above problems and achieve the objects of the present invention, a semiconductor device according to the present invention has the following features. The semiconductor device includes a first semiconductor element and a second semiconductor element, each having an active region and a termination structure disposed outside the active region and surrounding the active region. In the first semiconductor element and the second semiconductor element, a first conductivity type drift layer having a lower impurity concentration than the semiconductor substrate is provided on the front surface of a first conductivity type semiconductor substrate. In the active region, a striped first first column region of a first conductivity type provided in the drift layer toward the semiconductor substrate, and a striped first second column region of a second conductivity type. and are repeatedly alternately arranged in a direction parallel to the front surface. In the termination structure section, a striped second first column region of the first conductivity type provided in the drift layer and provided from the surface of the drift layer toward the semiconductor substrate; A second parallel pn structure is provided in which conductive type second column regions are repeatedly and alternately arranged in a direction parallel to the front surface. A base region of a second conductivity type is provided in the surface layer of the first parallel pn structure. A source region of a first conductivity type is selectively provided in a surface layer of the base region. A trench is provided that extends through the source region and the base region to reach the first column region. A gate electrode is provided inside the trench with a gate insulating film interposed therebetween. A first electrode is provided in contact with the source region and the base region. A second electrode is provided on the back surface of the semiconductor substrate. A channel stopper of a second conductivity type is provided on a surface layer of the drift layer of the termination structure. A first semiconductor region of a first conductivity type in contact with the channel stopper is selectively provided in the drift layer of the termination structure. The second electrode of the first semiconductor element and the second electrode of the second semiconductor element are electrically connected to a frame electrode. At a side where the first semiconductor element and the second semiconductor element are adjacent to each other, the channel stopper of the first semiconductor element and the channel stopper of the second semiconductor element are separated from each other.

Further, in the semiconductor device according to the above-described invention, the length of the side where the first semiconductor element and the second semiconductor element are adjacent to each other is at least twice the length of the side orthogonal to the adjacent side. It is characterized by a length of .

Further, in the semiconductor device according to the above-described invention, the first electrode of the first semiconductor element is a source electrode, the first electrode of the second semiconductor element is a drain electrode, and the first electrode of the first semiconductor element is a drain electrode. The device is characterized by having a highly functional structure having a sensing element.

Further, in the semiconductor device according to the above-described invention, a buffer layer of a first conductivity type is provided between the semiconductor substrate, the drift layer, the first parallel pn region, and the second parallel pn region. It is characterized by being prepared.

Further, the semiconductor device according to the present invention is characterized in that, in the above-described invention, the base region is provided on the upper surface of the first second column region.

According to the above-mentioned invention, by connecting SJ-MOSFETs in antiparallel, it has a reverse breakdown voltage due to the built-in parasitic diode, and the switching speed is fast not only in the low breakdown voltage region but also in the high breakdown voltage region, and the on-resistance is low ( This enables semiconductor devices with low conduction loss. Furthermore, when conducting, it is possible to control each SJ-MOSFET according to the polarity current and polarity voltage of the load and reduce conduction loss by operating a MOSFET with lower resistance compared to the forward direction of a diode, similar to synchronous rectification. Become.

Further, the SJ-MOSFET has parallel pn regions in which n-type column regions and p-type column regions are alternately arranged within the element. Since the depletion layer spreads in both the n-type column region and the p-type column region, the breakdown voltage is improved even with the same electric field strength. For this reason, the impurity concentration in the n-type column region can be increased by one order of magnitude compared to conventional MOSFETs, making it possible to significantly reduce on-resistance. reduce

According to the semiconductor device according to the present invention, the switching speed is fast not only in the low breakdown voltage region but also in the high breakdown voltage region, and the on-resistance is low (low conduction loss).

1 is a top view showing the structure of a semiconductor device according to a first embodiment; FIG. FIG. 2 is a sectional view taken along line XX in FIG. 1 showing the structure of the semiconductor device according to the first embodiment. 2 is an enlarged top view of region S in FIG. 1 showing the structure of the semiconductor device according to the first embodiment. FIG. 2 is an enlarged top view of region T in FIG. 1 showing the structure of the semiconductor device according to the first embodiment. FIG. 4 is a cross-sectional view taken along Y1-Y1 in FIG. 3 showing the structure of the semiconductor device according to the first embodiment. FIG. 4 is a cross-sectional view taken along Y2-Y2 in FIG. 3 showing the structure of the semiconductor device according to the first embodiment. FIG. 1 is an equivalent circuit diagram of a semiconductor device according to a first embodiment; FIG. FIG. 2 is a YY cross-sectional view of FIG. 1 showing another structure of the semiconductor device according to the first embodiment. 4 is a sectional view taken along Y1-Y1 in FIG. 3 showing the structure of a semiconductor device according to a second embodiment. FIG. 4 is a sectional view taken along Y2-Y2 in FIG. 3 showing the structure of a semiconductor device according to a second embodiment. FIG. 4 is a cross-sectional view taken along Y1-Y1 in FIG. 3 showing another structure of the semiconductor device according to the second embodiment. FIG. 4 is a sectional view taken along Y2-Y2 in FIG. 3 showing another structure of the semiconductor device according to the second embodiment. FIG. FIG. 3 is a cross-sectional view showing the structure of a semiconductor device according to a third embodiment. FIG. 2 is a top view showing a structure in which a current sensing section is built into a semiconductor device according to Embodiments 1 to 3; 3 is a top view showing a structure in which a temperature sensing section is built into a semiconductor device according to Embodiments 1 to 3. FIG. FIG. 3 is a top view showing a structure in which a current sensing section and a temperature sensing section are built into the semiconductor devices according to Embodiments 1 to 3; FIG. 3 is a top view showing details of the high-performance portion of the semiconductor device according to Embodiments 1 to 3 (Part 1). FIG. 3 is a top view showing details of the high-performance portion of the semiconductor device according to Embodiments 1 to 3 (part 2); This is an example of a bidirectional switch circuit using a conventional IGBT. This is an example of a bidirectional switch circuit using a conventional RB-IGBT.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of a semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, a layer or region prefixed with n or p means that electrons or holes are the majority carriers, respectively. Furthermore, + and - appended to n and p mean that the impurity concentration is higher or lower than that of a layer or region to which n or p is not appended, respectively. If the notation of n or p including + and - is the same, it indicates that the concentrations are close, but the concentrations are not necessarily the same. Note that in the following description of the embodiment and the accompanying drawings, similar components are denoted by the same reference numerals, and overlapping description will be omitted. It is preferable that the description of the same or equivalent includes up to 5% in consideration of manufacturing variations.

(Embodiment 1)
FIG. 1 is a top view showing the structure of a semiconductor device according to a first embodiment. As shown in FIG. 1, the semiconductor device 70 according to the first embodiment has two MOSFET (hereinafter referred to as SJ-MOSFET) devices having a super junction (SJ) structure connected in antiparallel. There is. The source electrode pad 36 of one SJ-MOSFET 71 is set to source potential, the source electrode pad 36 of the other SJ-MOSFET 72 is set to drain potential, and the back electrodes (not shown), which are drain terminals, are set to the same potential. This ensures reverse withstand voltage and enables bidirectional switching. Note that the source electrode pad 36 of one SJ-MOSFET 71 may be set to the drain potential, and the source electrode pad 36 of the other SJ-MOSFET 72 may be set to the source potential.

The semiconductor device 70 includes an active region 50 for each of the SJ-MOSFET 71 and the SJ-MOSFET 72, and an edge termination region 60 surrounding the active region 50. Therefore, the SJ-MOSFET 71 and the SJ-MOSFET 72 are connected at the p ^- type channel stopper region 40 described later, and the edge termination regions 60 are adjacent to each other. Active region 50 is a region through which current flows when in the on state. The edge termination region 60 includes a breakdown voltage holding region that relieves the electric field on the surface (front surface) 81 side of the semiconductor substrate 80 in the drift region and maintains the breakdown voltage.

FIG. 2 is a sectional view taken along line XX in FIG. 1 showing the structure of the semiconductor device according to the first embodiment. Since the SJ-MOSFET 71 and the SJ-MOSFET 72 have the same structure, FIG. 2 shows the structure of the SJ-MOSFET 71. The SJ-MOSFET 71 shown in FIG. 2 has a MOS (Metal Oxide Semiconductor) gate on the surface 81 (surface on the p ^- type base region 5 side) of a semiconductor substrate 80 (semiconductor element) made of silicon (Si). It is a MOSFET. In FIG. 2, two unit cells (functional units of an element) are shown, and other unit cells adjacent to these are omitted from illustration. Here, the unit cell is from the center of the trench 18 to the center of the adjacent trench 18.

The n ⁺ type semiconductor substrate (first conductivity type semiconductor substrate) 1 is, for example, a silicon single crystal substrate doped with arsenic (As) or phosphorus (P). An n ⁻ type drift layer (first conductivity type drift layer) 2 is provided on the n ⁺ type semiconductor substrate 1 . The n ⁻ type drift layer 2 has an impurity concentration lower than that of the n ⁺ type semiconductor substrate 1, and is a low concentration n type layer doped with phosphorus, for example. Hereinafter, the n ⁺ -type semiconductor substrate 1 and the n ^- -type drift layer 2 will be collectively referred to as a semiconductor substrate 80 . The upper surface of the semiconductor substrate 80 is defined as a surface 81. A MOS gate structure (device structure) is formed on the surface 81 side of the semiconductor substrate 80. Further, on the back surface of the semiconductor substrate 80, a back electrode 11 that serves as a drain electrode is provided. The n ⁺ type semiconductor substrate 1 corresponds to a drain region.

The active region 50 of the SJ-MOSFET 71 is provided with a parallel pn region 32 in which n-type column regions 3 and p-type column regions 4 are alternately and repeatedly arranged. The edge termination region 60 is provided with a parallel pn region 32B (described later) in which n-type column regions 3B and p-type column regions 4B are alternately and repeatedly arranged. Note that, as described later, the widths of the n-type column region 3 and the p-type column region 4 of the parallel pn region 32 are different from the widths of the n-type column region 3B and the p-type column region 4B of the parallel pn region 32B. Note that the widths of the n-type column region 3 and the p-type column region 4 of the parallel pn region 32 may be the same. Further, the widths of the n-type column region 3B and the p-type column region 4B of the parallel pn region 32B may be the same. The boundary between the active region 50 and the edge termination region 60 is defined by the width of the n-type column region 3 and the n-type column region 3B where the parallel pn region 32 and the parallel pn region 32B touch, and the width of the p-type column region 4 and the p-type column region 4B. This is the point where the width of the area changes.

In the parallel pn regions 32, 32B, by making the amount of impurities contained in the p-type column regions 4, 4B and the n-type column regions 3, 3B approximately equal (the amount of impurity is impurity concentration x area), in the off state, the p-type A depletion layer is formed laterally in the p-type column regions 4, 4B and the n-type column regions 3, 3B from the PN junction of the column regions 4, 4B and n-type column regions 3, 3B (p-type column region 4 and n-type column region 3, 3B). 3 in the direction in which they are repeated alternately). This makes it easier for the depletion layers to connect in the lateral direction, making it possible to achieve a high breakdown voltage. Therefore, even if the impurity concentration of the n-type column region 3 is increased, the withstand voltage does not decrease, making it possible to reduce the on-resistance.

A p ⁻ type base region (second conductivity type base region) 5 is selectively provided on the p type column region 4 of the active region 50 . The bottom surface of the p ⁻ type base region 5 of the active region 50 is in contact with the top surface of the p type column region 4 . P ⁻ type base region 5 of active region 50 is provided on the surface 81 side of semiconductor substrate 80 . P-type column region 4 is provided from surface 81 of semiconductor substrate 80 toward n ⁺ -type semiconductor substrate 1 . An n ⁻ type buffer layer 21 is provided between the p type column region 4 and the n ⁺ type semiconductor substrate 1. The width of the upper surface of the p ^- type base region 5 is made wider than the width of the p type column region 4. Similar to the p-type column region 4, the n-type column region 3 is also provided from the surface 81 of the semiconductor substrate 80 toward the n ⁺ -type semiconductor substrate 1, and between the n-type column region 3 and the n ⁺ -type semiconductor substrate 1. An n ^- type buffer layer 21 is provided.

The impurity concentration of the n-type column region 3 is lower than the impurity concentration of the n ⁺ -type semiconductor substrate 1. Furthermore, the impurity concentration in the n-type column region 3 and the impurity concentration in the p-type column region 4 may be equal. The impurity concentration of the n ^- type buffer layer 21 and the impurity concentration of the n ^- type drift layer 2 may be equal. On the surface side of the p ⁻ type base region 5 of the active region 50, an n ⁺ type source region (first conductivity type source region) 6 is selectively provided. A p ++ type contact region 33 in contact with the n ⁺ type source region 6 may be selectively provided on the surface side of the p ^{− type} base region 5 of the active region 50 .

A trench structure is formed on the first main surface side (p ^- type base region 5 side) of the semiconductor substrate. The trench structure includes a trench 18, a gate insulating film 7, and a gate electrode 8. Specifically, the trench 18 extends from the surface of the p ^- type base region 5 on the side opposite to the n ⁺ type semiconductor substrate 1 side (the first main surface side of the semiconductor substrate) to the p ^- type base region 5 and the n ⁺ The parallel pn region 32 is reached through the type source region 6 . As a result, the sidewalls of trench 18 are in contact with p ^- type base region 5 and n ⁺ type source region 6. A gate insulating film 7 is formed on the bottom and sidewalls of the trench 18 along the inner wall of the trench 18 , and a gate electrode 8 is provided inside the gate insulating film 7 in the trench 18 . Gate electrode 8 is insulated from p ^- type base region 5 by gate insulating film 7 . A portion of the gate electrode 8 may protrude toward the source electrode 10 from above the trench 18 (the side where the source electrode 10 described later is provided). Note that the n ⁺ type source region 6 does not need to be provided on the sidewall of the trench 18 closest to the edge termination region 60 of the active region 50 . The p ⁻ type base region 5 closest to the edge termination region 60 of the active region 50 may be provided inside the p ⁻ type resurf region 31, which will be described later.

An oxide film (not shown) may be provided on the surface 81 of the semiconductor substrate 80 so as to cover the gate electrode 8 and the n ⁺ type source region 6. An interlayer insulating film 9 may be provided on the oxide film over the entire first main surface side of the semiconductor substrate so as to cover the gate electrode 8 embedded in the trench 18. The oxide film is formed so that the interlayer insulating film 9 doped with impurities at a high concentration does not come into direct contact with the silicon substrate. The oxide film is, for example, a HTO (High Temperature Oxide) film, a TEOS (Tetraethyl Orthosilicate) film, or a thermal oxide film.

Source electrode 10 contacts n ⁺ -type source region 6 and p ^- -type base region 5 via contact hole 34 formed in interlayer insulating film 9 . If a p ⁺⁺ type contact region 33 is provided on the surface side of the p ⁻ type base region 5 that contacts the source electrode 10 via this contact hole 34 , this contact hole 34 penetrates the n ⁺ type source region 6 . It may also be provided so as to be in contact with the p ⁺⁺ type contact region 33. Source electrode 10 is electrically insulated from gate electrode 8 by interlayer insulating film 9 . A barrier metal 15 may be provided between the source electrode 10 and the interlayer insulating film 9, for example, to prevent metal atoms from diffusing from the source electrode 10 to the gate electrode 8 side.

Further, the contact plug 14 may be embedded in the contact hole 34 formed in the interlayer insulating film 9. The contact plug 14 is, for example, a metal film made of tungsten (W), which is highly embeddable. In this case, a trench contact structure is preferable because parasitic bipolar operation can be suppressed by extracting holes in p ^- type base region 5 at a position deeper than n ⁺ type source region 6 during avalanche operation. Here, the trench contact structure means that a trench is provided that penetrates the n ⁺ type source region 6 and is in contact with the p ^{+ +} type contact region 33, and a contact hole 34 penetrates the interlayer insulating film 9 and the n ⁺ type source region 6. This is a contact structure provided so as to be in contact with the p ⁺⁺ type contact region 33. A protective film (not shown) such as a passivation film made of polyimide is selectively provided on the source electrode 10 . Further, a barrier metal 15 may be provided to prevent diffusion of metal atoms from the source electrode 10 to the gate electrode 8 side, for example.

Further, in the edge termination region 60 that maintains a breakdown voltage, a field oxide film 20 is provided on the surface 81 side of the semiconductor substrate 80, and a polycrystalline silicon film that will become the gate electrode 8 is provided on the field oxide film 20. A gate wiring 27 is provided on the gate electrode 8 to be electrically connected to a gate electrode pad (not shown). Gate wiring 27 is in contact with gate electrode 8 via contact hole 35 formed in interlayer insulating film 9 . Further, the contact plug 14 may be embedded in the contact hole 35 formed in the interlayer insulating film 9 with the barrier metal 15 interposed therebetween.

Further, the edge termination region 60 may be provided with a voltage-resistant structure such as a p ^--- type RESURF region 31 and a p-type guard ring 28 . A p ⁻ type channel stopper region 40 may be provided outside the voltage withstanding structure, and a field plate 38 may be provided on the p ⁻ type channel stopper region 40 . The p ^-- type resurf region 31 is provided over both the active region 50 and the edge termination region 60. A p ^- type base region 5 may be provided inside the p ^- type RESURF region 31 on the side of the active region 50 so as to be in contact with the side wall of the trench 18 . Furthermore, the p ^-- type RESURF region 31 is provided in an annular shape in plan view. The guard ring 28 is annularly provided in the edge termination region 60 in plan view. Note that the p ^- type channel stopper region 40 is provided across (in contact with) both the SJ-MOSFET 71 and the SJ-MOSFET 72, and is further divided into two at the outermost periphery of the semiconductor device 70. Further, the p ⁻ type channel stopper region 40 may be provided on the n type column region 3C.

In the region facing the source electrode 10 and the gate wiring 27 in the edge termination region 60 in the downward direction (n ⁺ type semiconductor substrate 1 side), the p ^-- type resurf region 31 exposed on the surface 81 of the semiconductor substrate 80 is an n type It is provided so as to be in contact with the upper part of column region 3B and p-type column region 4B.

A parallel pn region 32B is provided in the edge termination region 60 of the SJ-MOSFET 71. Also in the edge termination region 60, the parallel pn regions 32B are provided from the surface 81 of the semiconductor body 80 toward the n ⁺ -type semiconductor substrate 1. An n ⁻ type buffer layer 21 is provided between the p type column region 4 and the n ⁺ type semiconductor substrate 1. In the SJ-MOSFET 71, if the impurity concentration of the parallel pn region 32 is made too high in order to reduce the on-resistance, the depletion layer will be difficult to expand and the withstand voltage will decrease. In order to maximize the characteristics of the active region 50, the breakdown voltage of the edge termination region 60 is set higher than that of the active region 50. Similarly to the active region 50, in the edge termination region 60, electrons and holes move and combine at the junction between the adjacent n-type column region 3B and p-type column region 4B in the parallel pn region 32B, resulting in a depletion layer. It is formed. When a reverse bias is applied to the SJ-MOSFET 71, the depletion layer spreads into the p-type column region 4B and the n-type column region 3B. The depletion layer is formed along the electric field distribution from the p-type column regions 4, 4B and n-type column regions 3, 3B near the active region 50 of the edge termination region 60 to the outer periphery of the edge termination region 60 (on the p ^- type channel stopper region 40 side). ). At this time, the edge termination region 60 is affected by its shape and surface condition, making it difficult for the depletion layer to expand outward and making it difficult to increase the withstand voltage. As a method of making the breakdown voltage of the edge termination region 60 higher than that of the active region 50, the pitch of the parallel pn regions 32B of the edge termination region 60 and the width of the p-type column region 4B and the n-type column region 3B can be changed to the parallel pn region 32 of the active region 50. It is made narrower to make it easier to expand the depletion layer. That is, the widths of the n-type column region 3B and the p-type column region 4B of the parallel pn region 32B are narrower than the widths of the n-type column region 3 and the p-type column region 4 of the parallel pn region 32.

In edge termination region 60, n ^- type drift layer 2 is provided outside parallel pn region 32B. Although the n ^- type buffer layer 21 is provided on the lower surface of the n ^- type drift layer 2, the impurity concentrations of the n ^- type drift layer 2 and the n ^- type buffer layer 21 may be equal. Therefore, the n ^- type drift layer 2 is electrically connected to the n ⁺ type semiconductor substrate 1. A p ^- type channel stopper region 40 is provided outside the n ^- type drift layer 2 in order to prevent the depletion layer from expanding too much. An n-type column region 3C (first semiconductor region of first conductivity type) is provided under the p ^- type channel stopper region 40. An n ⁻ type buffer layer 21 is provided on the lower surface of the n type column region 3C. In the n-type column region 3C, a p ^- type channel stopper region 40 is provided on the upper surface, and an n ^- type buffer layer 21 is provided on the lower surface. Further, the lower surface of the n ⁻ type buffer layer 21 is in contact with the n ⁺ type semiconductor substrate 1 . That is, the n ⁻ type buffer layer 21 is provided on the upper surface of the n ⁺ type semiconductor substrate 1 in the active region 50 and the edge termination region 60 . If the n ⁺ -type semiconductor substrate 1 with a high impurity concentration comes into direct contact with the lower surface of the parallel pn regions 32, 32B, a depletion layer will not spread between the parallel pn regions 32, 32B and the n ⁺ -type semiconductor substrate 1, resulting in a decrease in breakdown voltage. There is a risk of Therefore, by providing an n ^- type buffer layer 21 between the parallel pn region 32 of the active region 50 and the parallel pn region 32B of the edge termination region 60 and the n ⁺ type semiconductor substrate 1, the reduction in breakdown voltage is suppressed. be able to.

FIG. 3 is an enlarged top view of region S in FIG. 1 showing the structure of the semiconductor device according to the first embodiment. In FIG. 3, in order to show the parallel pn regions 32 and 32B of the semiconductor device 70, the source electrode 10, gate wiring 27, barrier metal 15, interlayer insulating film 9, etc. provided on the upper surface of the semiconductor substrate 80 are omitted. Further, the n ⁺ type source region 6, p ^{+ +} type contact region 33, p ^- type resurf region 31, guard ring 28, etc. provided in the surface layer of the semiconductor substrate 80 are also omitted. As shown in FIG. 3, the n-type column region 3 and the p-type column region 4 of the active region 50 of the semiconductor device 70 have a stripe shape. Further, the n-type column region 3B and the p-type column region 4B in the edge termination region 60 also have a stripe shape. The longitudinal sides of the n-type column regions 3, 3B and the p-type column regions 4, 4B are perpendicular to the sides on which the two semiconductor elements, SJ-MOSFET 71 and SJ-MOSFET 72, are adjacent. The widths of the n-type column region 3B and the p-type column region 4B of the parallel pn region 32B are narrower than the widths of the n-type column region 3 and the p-type column region 4 of the parallel pn region 32. Although there is only one p ^- type channel stopper region 40 on adjacent sides, it is divided into two directions at the end of the semiconductor device 70 and surrounds the outermost periphery of the SJ-MOSFET 71 and the SJ-MOSFET 72 in an annular shape. Although the parallel pn region 32 and the parallel pn region 32B shown in FIG. 3 are provided so as to be in contact with each other, an intermediate region may be provided between the parallel pn region 32 and the parallel pn region 32B (not shown). The intermediate region is a region in which the n-type column regions 3, 3B and the p-type column regions 4, 4B provided in the parallel pn region 32 and the parallel pn region 32B may or may not be in contact with each other. be. In addition, in the active regions 50 of the SJ-MOSFET 71 and the SJ-MOSFET 72, ^a trench 18 is provided on the upper surface of the n-type column region 3, and a contact plug 14 ( contact hole 34).

FIG. 4 is an enlarged top view of region T in FIG. 1 showing the structure of the semiconductor device according to the first embodiment. FIG. 4 shows the corners of the active regions 50 of SJ-MOSFETs 71 and SJ-MOSFETs 72 and edge termination regions 60 surrounding the corners of the respective active regions 50. FIG. In FIG. 4, the source electrode 10, gate wiring 27, contact plug 14, barrier metal 15, interlayer insulating film 9, etc. provided on the upper surface of the semiconductor substrate 80 are omitted. Furthermore, the trench 18, contact holes 34, 35, p ^- type base region 5, etc. are also omitted. As shown in FIG. 4, in the semiconductor device 70, the SJ-MOSFET 71 and the SJ-MOSFET 72 are adjacent to each other with the p ^- type channel stopper region 40 touching. The p ^- type channel stopper region 40 is provided across the SJ-MOSFET 71 and the SJ-MOSFET 72. Furthermore, p ^- type channel stopper region 40 is provided along the edge of semiconductor device 70 . Further, the p ⁻ type channel stopper region 40 is provided on the n type column region 3C. In FIG. 4, the longitudinal direction of the n-type column regions 3, 3B and p-type column regions 4, 4B of the SJ-MOSFET 71 and the longitudinal direction of the n-type column regions 3, 3B and the p-type column regions 4, 4B of the SJ-MOSFET 72 are , parallel to the Y-axis direction. In addition, in FIG. 4, the direction in which the n-type column regions 3, 3B and the p-type column regions 4, 4B of the SJ-MOSFET 71 are repeatedly arranged alternately (the short side of the n-type column regions 3, 3B and the p-type column regions 4, 4B direction) and the direction in which the n-type column regions 3, 3B and p-type column regions 4, 4B of the SJ-MOSFET 72 are repeatedly arranged alternately (the lateral direction of the n-type column regions 3, 3B and p-type column regions 4, 4B) are , parallel to the X-axis direction. The p ^-- type resurf region 31 is provided over both the active region 50 and the edge termination region 60 in each of the SJ-MOSFET 71 and the SJ-MOSFET 72. Further, the p ^-- type RESURF region 31 is provided in an annular shape in plan view. The guard ring 28 is provided in the edge termination region 60 in an annular shape when viewed from above.

FIG. 5 is a cross-sectional view taken along the line Y1-Y1 in FIG. 3, showing the structure of the semiconductor device according to the first embodiment. FIG. 6 is a cross-sectional view taken along the line Y2-Y2 in FIG. 3, showing the structure of the semiconductor device according to the first embodiment. 5 and 6, the longitudinal sides of the n-type column regions 3 and 3B and the p-type column regions 4 and 4B of the SJ-MOSFETs 71 and 72 are orthogonal to the sides where the SJ-MOSFETs 71 and SJ-MOSFETs 72 are adjacent to each other. It is a semiconductor device connected in parallel, and has a structure in which SJ-MOSFETs are arranged in antiparallel. Further, FIG. 7 is an equivalent circuit diagram of the semiconductor device according to the first embodiment.

As shown in FIGS. 5 to 7, the semiconductor device according to the first embodiment is provided with two SJ-MOSFETs 71 and 72 connected in antiparallel within the same semiconductor substrate. The source electrode of the SJ-MOSFET 71 is the source electrode 10 of the semiconductor device 70, and the source electrode of the SJ-MOSFET 72 is the drain electrode 12 of the semiconductor device 70. Thereby, by using the common back electrode 11 of the SJ-MOSFETs 71 and 72 as a neutral point, bidirectional reverse breakdown voltage is ensured by the parasitic diode built into the MOSFET, and bidirectional switching becomes possible. During conduction, by operating a MOSFET with lower resistance compared to the forward direction of a diode, similar to synchronous rectification, it is possible to control each SJ-MOSFET 71 and 72 according to the polarity current and polarity voltage of the load and reduce conduction loss. becomes.

Further, the SJ-MOSFETs 71 and 72 have parallel pn regions 32 and 32B in which n-type column regions 3 and 3B and p-type column regions 4 and 4B are alternately arranged within the device. Since the depletion layer spreads in both the n-type column regions 3, 3B and the p-type column regions 4, 4B, the breakdown voltage is improved even with the same electric field strength. Therefore, compared to conventional MOSFETs, the impurity concentration in the n-type column region 3 can be increased by one order of magnitude, making it possible to significantly reduce the on-resistance. reduce

Furthermore, as in the first embodiment, when two SJ-MOSFETs 71 and 72 having a breakdown voltage structure are formed side by side in the same semiconductor substrate to form antiparallel configurations, the SJ-MOSFETs 71 and 72 shown in FIG. It is preferable that the length L is at least twice the length M of the side perpendicular to the adjacent side (L≧2M). This makes it possible to reduce the increase in resistance caused by the current path. Note that the longitudinal direction of the n-type column regions 3, 3B and the p-type column regions 4, 4B is parallel to the length M shown in FIG. 5 and 6, the impurity concentration of p ^-- type resurf region 31 and the impurity concentration of guard ring 28 may be the same, and the depths from surface 81 of semiconductor substrate 80 may be the same depth. Further, the impurity concentration of p ^- type base region 5 and the impurity concentration of p ^- type channel stopper region 40 may be equal, and the depth from surface 81 of semiconductor substrate 80 may be the same depth. In the two SJ-MOSFETs 71 and 72, the n-type column region 3C and the p ^- type channel stopper region 40 are in contact with each other and are electrically connected.

FIG. 8 is a YY cross-sectional view of FIG. 1 showing another structure of the semiconductor device according to the first embodiment. As shown in FIG. 8, the longitudinal sides of the n-type column regions 3 and 3B and the p-type column regions 4 and 4B of the SJ-MOSFETs 71 and 72 are connected in parallel to the sides where the SJ-MOSFETs 71 and SJ-MOSFETs 72 are adjacent to each other. This semiconductor device has a structure in which SJ-MOSFETs are arranged in antiparallel. However, as shown in FIGS. 5 and 6, it is better to connect the n-type column region 3 and the p-type column region 4 so that the adjacent sides are perpendicular to each other to further reduce the increase in resistance caused by the current path. .

As described above, according to the first embodiment, by connecting the SJ-MOSFETs in antiparallel, the built-in parasitic diode provides reverse breakdown voltage, and the switching speed is increased not only in the low breakdown voltage region but also in the high breakdown voltage region. Fast, low on-resistance (low conduction loss) semiconductor devices become possible. Furthermore, during conduction, by operating a MOSFET with lower resistance compared to the forward direction of a diode, as with synchronous rectification, it is possible to control each SJ-MOSFET according to the polarity current and polarity voltage of the load, reducing conduction loss. .

Further, the SJ-MOSFET has parallel pn regions in which n-type column regions and p-type column regions are alternately arranged within the element. Since the depletion layer spreads in both the n-type column regions 3, 3B and the p-type column regions 4, 4B, the breakdown voltage is improved even with the same electric field strength. For this reason, the impurity concentration in the n-type column region can be increased by one order of magnitude compared to conventional MOSFETs, making it possible to significantly reduce on-resistance. reduce

(Embodiment 2)
Next, a semiconductor device according to a second embodiment of the present invention will be described. The top view of the semiconductor device according to the second embodiment is the same as that of the first embodiment, so its description will be omitted (see FIG. 1). Further, since the XX cross-sectional view in FIG. 1 and the enlarged top view of the region S in FIG. 1 are the same as in the first embodiment, their description will be omitted (see FIGS. 2 and 3). FIG. 9 is a cross-sectional view taken along the line Y1-Y1 in FIG. 3 showing the structure of the semiconductor device according to the second embodiment. FIG. 10 is a cross-sectional view taken along the line Y2-Y2 in FIG. 3 showing the structure of the semiconductor device according to the second embodiment. FIG. 11 is a cross-sectional view taken along Y1-Y1 in FIG. 3 showing another structure of the semiconductor device according to the second embodiment. FIG. 12 is a cross-sectional view taken along the line Y2-Y2 in FIG. 3 showing another structure of the semiconductor device according to the second embodiment.

In the SJ-MOSFETs 71 and 72, in the case of an n-channel, an n-type column region 3C is formed below the p ^- type channel stopper region 40 so that the depletion layer in the edge termination region 60 does not expand too much. Since the current flows in a region with low resistance, most of the current flows through the back electrode 11. When the resistance of the n-type column region 3C and the n ^- type drift region 2 becomes lower, the current flowing through the n-type column region 3C and the n ^- type drift region 2 may increase. In a normal n-channel MOSFET, the channel stopper region may be n-type. In the first embodiment, when the p ^- type channel stopper region 40 is an n ^- type channel stopper region, the n ^- type channel stopper region provided across the adjacent SJ-MOSFET 71 and SJ-MOSFET 72 is an n-type column region. Contact with 3C. Since the n ⁻ type channel stopper region is in contact with the n type column region 3C, the resistance of the n ⁻ type channel stopper region and the n type column region 3C is lowered, so that current tends to concentrate on the surface 81. When the p ^- type channel stopper region 40 is provided as in the first embodiment, since the p ^- type channel stopper region 40 is in contact with the n type column region 3C, the surface 81 is smaller than when the n ^- type channel stopper region is provided. It is possible to suppress the current flowing to the

As shown in FIG. 8 of the first embodiment, the sides in the longitudinal direction of the n-type column regions 3 and 3B and the p-type column regions 4 and 4B of the SJ-MOSFETs 71 and 72 and the sides where the SJ-MOSFETs 71 and SJ-MOSFETs 72 are adjacent to each other When connected in parallel, parallel pn regions 32 and 32B are arranged between SJ-MOSFET 71 and SJ-MOSFET 72, and current flows through the low resistance n-type column regions 3 and 3B, so p ^- type Concentration of electric field and current on channel stopper region 40 and n-type column region 3C can be alleviated. On the other hand, as shown in FIGS. 5 and 6 of the first embodiment, the longitudinal direction of the n-type column regions 3 and 3B and the p-type column regions 4 and 4B of the SJ-MOSFETs 71 and 72 and the SJ-MOSFETs 71 and 72 are When connecting adjacent sides perpendicularly, the n-type column regions 3 and 3B on the source side (SJ-MOSFET 71) connect to the drain side (SJ-MOSFET 71) via the n-type column region 3C under the p ^- type channel stopper region 40. The potential is almost the same as that of the n-type column regions 3 and 3B of the MOSFET 72), and the current on the surface 81 is reduced compared to the case where an n ^- type channel stopper region is provided. Electric fields and currents tend to concentrate, and withstand capacity tends to decrease.

Therefore, in the second embodiment, the longitudinal directions of the n-type column regions 3 and 3B and the p-type column regions 4 and 4B of the SJ-MOSFETs 71 and 72 are orthogonal to the sides where the SJ-MOSFETs 71 and SJ-MOSFETs 72 are adjacent to each other. When connected, an n ^- type region (second semiconductor region of first conductivity type) 65 or A p-type region (third semiconductor region of second conductivity type) 66 is provided. The n ⁻ type region 65 may be formed by leaving the n − type drift layer 2 in a part of the region under the p ⁻ type channel stopper region 40 without forming the n ^type column region 3 . In this case, n ^- type region 65 and n ^- type drift layer 2 have the same impurity concentration. 9 and 10 show a structure in which an n ⁻ type region 65 is provided, and FIGS. 11 and 12 show a structure in which a p type region 66 is provided.

The n ⁻ type region 65 and the p type region 66 are provided in contact with the p ⁻ type channel stopper region 40 and facing the n ⁺ type semiconductor substrate 1 similarly to the n type column regions 3C-1 and 3C-2. An n ⁻ type buffer layer 21 is provided between the n − type region 65 and the p type region 66 and ^the n ⁺ type semiconductor substrate 1. The n ⁻ type region 65 and the p type region 66 may have a stripe shape along the sides of the adjacent SJ-MOSFET 71 and SJ-MOSFET 72.

By providing an n ^- type region 65 or a p type region 66 between the n type column region 3C-1 and the n type column region 3C-2 below the p ^- type channel stopper region 40, the source side (SJ-MOSFET 71 ) and the n-type column regions 3, 3B on the drain side (SJ-MOSFET72) are no longer at the same potential, and electric fields and currents are not concentrated on adjacent sides. , it is possible to prevent an increase in on-resistance and a decrease in withstand capability.

As described above, the second embodiment has the same effects as the first embodiment. Furthermore, by providing an n ^- type region 65 or a p type region 66 between the n type column regions 3C-1 and 3C-2 under the p ^- type channel stopper region 40, an electric field and a current can be generated on the adjacent sides. There is no concentration, and it is possible to prevent an increase in on-resistance and a decrease in withstand capability.

(Embodiment 3)
Next, a semiconductor device according to a third embodiment of the present invention will be described. FIG. 13 is a cross-sectional view showing the structure of a semiconductor device according to the third embodiment. As shown in FIG. 13, this is a structure in which an SJ-MOSFET 71 and an SJ-MOSFET 72 are arranged and assembled in the same package. The SJ-MOSFET 71 and the SJ-MOSFET 72 are individual semiconductor elements, and the back electrode 11 of the SJ-MOSFET 71 and the back electrode 11 of the SJ-MOSFET 72 are electrically connected by the frame electrode 16 via the solder 19. The frame electrode 16 may be a lead frame, a ceramic substrate, an insulating substrate, or the like. A gap 85 is provided between adjacent SJ-MOSFET 71 and SJ-MOSFET 72.

In FIG. 13, the n-type column regions 3 and 3B and the p-type column regions 4 and 4B of the SJ-MOSFET 71 and the SJ-MOSFET 72 are arranged so that their lateral directions are in the same direction with a gap 85 in between. Note that the longitudinal directions of the n-type column regions 3 and 3B and the p-type column regions 4 and 4B of the SJ-MOSFET 71 and the SJ-MOSFET 72 may be arranged in the same direction with the gap 85 in between. Further, as in the first embodiment, the length L of the adjacent sides of the SJ-MOSFETs 71 and 72 shown in FIG. is preferred. This makes it possible to reduce the increase in resistance caused by the current path.

In the structure in which the SJ-MOSFET 71 and the SJ-MOSFET 72 are arranged and assembled in the same package as in the third embodiment, current flows more easily and the on-resistance is lower than in the semiconductor devices of the first and second embodiments. can be lowered. However, in the semiconductor devices of the first and second embodiments, since there is no gap 85 between the SJ-MOSFET 71 and the SJ-MOSFET 72, the size of the semiconductor device can be made smaller than that of the third embodiment.

In the third embodiment as well, the parasitic diode built into the MOSFET ensures bidirectional reverse breakdown voltage and bidirectional switching is possible.By operating the MOSFET when conductive, each SJ- It becomes possible to control the MOSFETs 71 and 72 and reduce conduction loss. In addition, the impurity concentration in the n-type column region 3 can be increased by one order of magnitude compared to conventional MOSFETs, making it possible to significantly reduce on-resistance. reduce

As described above, according to the third embodiment, even a structure in which the SJ-MOSFET 71 and the SJ-MOSFET 72 are arranged and assembled in the same package has the same effect as the first embodiment. Furthermore, the on-resistance can be lowered by uniformly connecting the source electrode 10 of the SJ-MOSFET 71 and the drain electrode 12 of the SJ-MOSFET 72 with wire wiring (not shown).

In order to further improve reliability, the SJ-MOSFET 71 on the source electrode 10 side may have a highly functional structure that includes a sensing element such as a current sensing section that detects current and voltage and protects against overcurrent. . Highly functional parts such as a current sensing part 42, a temperature sensing part 43, and an overvoltage protection diode part are arranged in the highly functional structure. FIG. 14 is a top view showing a structure in which a current sensing section is built into the semiconductor device according to the first to third embodiments. FIG. 15 is a top view showing a structure in which a temperature sensing section is built into the semiconductor device according to the first to third embodiments. FIG. 16 is a top view showing a structure in which a current sensing section and a temperature sensing section are built into the semiconductor devices according to the first to third embodiments. The gate electrode pad 30 is provided on both SJ-MOSFETs 71 and 72, and no high-performance portion is provided on the SJ-MOSFET 72 on the drain electrode 12 side. In a normal n-channel MOSFET, the drain region (on the back electrode side, corresponding to the n ⁺ type semiconductor substrate 1) is at a positive potential, and the n ⁺ type source region (on the front electrode side, corresponding to the source electrode 10) is at a ground potential. When the current sensing section 42 is built into the SJ-MOSFET 71 having the source electrode 10 on the upper surface, the gate voltage applied to the current sensing section 42 is with respect to the ground potential, so it is the same as a normal n-channel MOSFET. Note that when the current sensing section 42 is built into the SJ-MOSFET 72 having the drain electrode 12 on the upper surface, the gate voltage is increased because the gate voltage applied to the current sensing section 42 is relative to the drain potential (positive potential). There is a need. Further, when the temperature sensing section 43 is built into the SJ-MOSFET 71 having the source electrode 10 on the upper surface, the potential difference between the n ⁺ type source region 6 and the temperature sensing section 43 is small. Note that when the temperature sensing section 43 is built into the SJ-MOSFET 72 having the drain electrode 12 on the upper surface, the n ⁺ type source region 6 connected to the drain electrode 12 is not at the source potential but at the drain potential (plus potential). A high voltage is applied between the n ⁺ -type source region 6 connected to the drain electrode 12 and the temperature sensing section 43 . Therefore, in order to provide the SJ-MOSFET 72 with a high-performance section, control corresponding to the current sensing section 42 and the temperature sensing section 43 is required. Therefore, the SJ-MOSFET 72 does not need to be provided with a high-performance section. 14 and 16, the current sensing section 42 is arranged next to the gate electrode pad 30. In FIG. 15 and 16, the current sensing section 43 includes a temperature detection diode section 44, an anode pad, and a cathode pad connected to the temperature detection diode section 44. The anode pad and the cathode pad are provided next to the gate electrode pad 30, and the temperature detection diode section 44 is provided near the center of the SJ-MOSFET 71. Note that in FIGS. 14 to 16, the anode pad and cathode pad of the current sensing section 42 and temperature sensing section 43 are provided next to the gate electrode pad 30, but they may be provided at desired positions. Furthermore, although the temperature detection diode section 44 is provided near the center of the SJ-MOSFET 71, it may be provided at any desired position.

17 and 18 are top views showing details of the high-function parts of the semiconductor devices according to the first to third embodiments. As shown in FIG. 17, the current sensing section 42 is provided with a parallel pn region 32C. Parallel pn region 32C may have the same structure as parallel pn region 32 of active region 50. That is, the parallel pn region 32C and the parallel pn region 32 have the same width and impurity concentration as the n-type column region 3 and the p-type column region 4. Further, as shown in FIG. 18, the current sensing section 42 is also provided with a parallel pn region 32C, and the parallel pn region 32C may have the same structure as the parallel pn region 32B of the edge termination region 60. That is, the parallel pn region 32C and the parallel pn region 32B have the same width and impurity concentration as the n-type column region 3B and the p-type column region 4B.

INDUSTRIAL APPLICABILITY As described above, the semiconductor device according to the present invention is useful as a high-voltage semiconductor device used in power converters, power supplies for various industrial machines, and the like.

1 n ⁺ type semiconductor substrate 2 n ^- type drift layer 3, 3B, 3C, 3C-1, 3C-2 n type column region 4, 4B p type column region 5 p ^- type base region 6 n ⁺ type source region 7 gate Insulating film 8 Gate electrode 9 Interlayer insulating film 10 Source electrode 11 Back electrode 12 Drain electrode 14 Contact plug 15 Barrier metal 16 Frame electrode 18 Trench 19 Solder 20 Field oxide film 21 Buffer layer 27 Gate wiring 28 Guard ring 30 Gate electrode pad 31 p ^--- type RESURF regions 32, 32B, 32C Parallel pn region 33 P ⁺⁺ type contact regions 34, 35 Contact hole 36 Source electrode pad 38 Field plate 40 P ^- type channel stopper region 42 Current sense section 43 Temperature sense section 44 Temperature detection Diode section 50 Active region 60 Edge termination region 65 N ^- type region 66 P type region 70 Semiconductor devices 71, 72 SJ-MOSFET
80 Semiconductor base 81 Surface 85 Gap 110 IGBT
111 Diode 112 RB-IGBT

Claims (9)

A first semiconductor element and a second semiconductor element each have an active region and a termination structure disposed outside the active region and surrounding the active region,
a first conductivity type drift layer provided on a front surface of a first conductivity type semiconductor substrate and having a lower impurity concentration than the semiconductor substrate;
In the active region,
A striped first column region of a first conductivity type provided in the drift layer and facing the semiconductor substrate, and a striped first second column region of a second conductivity type provided in the drift layer. first parallel pn structures repeatedly and alternately arranged in a direction parallel to the front surface;
In the termination structure part,
a striped second first column region of the first conductivity type provided in the drift layer and provided from the surface of the drift layer toward the semiconductor substrate; and a striped second column region of the second conductivity type provided in the drift layer. a second parallel pn structure in which second column regions are repeatedly and alternately arranged in a direction parallel to the front surface;
a second conductivity type base region provided in the surface layer of the first parallel pn structure;
a first conductivity type source region selectively provided in a surface layer of the base region;
a trench penetrating the source region and the base region and reaching the first column region;
a gate electrode provided inside the trench with a gate insulating film interposed therebetween;
a first electrode in contact with the source region and the base region;
a second electrode provided on the back surface of the semiconductor substrate;
a second conductivity type channel stopper provided on the surface layer of the drift layer of the termination structure;
a first semiconductor region of a first conductivity type that is selectively provided in the drift layer of the termination structure and is in contact with the channel stopper;
Equipped with
the second electrode of the first semiconductor element and the second electrode of the second semiconductor element are electrically connected,
The channel stopper of the first semiconductor element and the channel stopper of the second semiconductor element are electrically connected at a side where the first semiconductor element and the second semiconductor element are adjacent to each other,
A semiconductor device, wherein longitudinal sides of the first column region and the second column region are orthogonal to a side where the first semiconductor element and the second semiconductor element are adjacent to each other. On the side where the first semiconductor element and the second semiconductor element are adjacent to each other, the first semiconductor region is located between the first semiconductor region of the first semiconductor element and the first semiconductor region of the second semiconductor element. 2. The semiconductor device according to claim 1, further comprising a second semiconductor region of the first conductivity type having a lower impurity concentration than the second semiconductor region. On the side where the first semiconductor element and the second semiconductor element are adjacent to each other, a second conductivity type is formed between the first semiconductor region of the first semiconductor element and the first semiconductor region of the second semiconductor element. 2. The semiconductor device according to claim 1, further comprising a third semiconductor region. A first semiconductor element and a second semiconductor element each have an active region and a termination structure disposed outside the active region and surrounding the active region,
a first conductivity type drift layer provided on a front surface of a first conductivity type semiconductor substrate and having a lower impurity concentration than the semiconductor substrate;
In the active region,
a striped first column region of a first conductivity type provided in the drift layer and provided toward the semiconductor substrate; and a striped first column region of a second conductivity type provided in the drift layer. first parallel pn structures repeatedly and alternately arranged in a direction parallel to the front surface;
In the termination structure part,
a striped second first column region of the first conductivity type provided in the drift layer and provided from the surface of the drift layer toward the semiconductor substrate; and a striped second column region of the second conductivity type provided in the drift layer. a second parallel pn structure in which second column regions are repeatedly and alternately arranged in a direction parallel to the front surface;
a second conductivity type base region provided in the surface layer of the first parallel pn structure;
a first conductivity type source region selectively provided in a surface layer of the base region;
a trench penetrating the source region and the base region and reaching the first column region;
a gate electrode provided inside the trench with a gate insulating film interposed therebetween;
a first electrode in contact with the source region and the base region;
a second electrode provided on the back surface of the semiconductor substrate;
a second conductivity type channel stopper provided on the surface layer of the drift layer of the termination structure;
a first semiconductor region of a first conductivity type that is selectively provided in the drift layer of the termination structure and is in contact with the channel stopper;
Equipped with
the second electrode of the first semiconductor element and the second electrode of the second semiconductor element are electrically connected,
The channel stopper of the first semiconductor element and the channel stopper of the second semiconductor element are electrically connected at a side where the first semiconductor element and the second semiconductor element are adjacent to each other,
A semiconductor device, wherein a longitudinal side of the first column region and the second column region is parallel to a side where the first semiconductor element and the second semiconductor element are adjacent to each other. A first semiconductor element and a second semiconductor element each have an active region and a termination structure disposed outside the active region and surrounding the active region,
a first conductivity type drift layer provided on a front surface of a first conductivity type semiconductor substrate and having a lower impurity concentration than the semiconductor substrate;
In the active region,
a striped first column region of a first conductivity type provided in the drift layer and provided toward the semiconductor substrate; and a striped first column region of a second conductivity type provided in the drift layer. first parallel pn structures repeatedly and alternately arranged in a direction parallel to the front surface;
In the termination structure part,
a striped second first column region of the first conductivity type provided in the drift layer and provided from the surface of the drift layer toward the semiconductor substrate; and a striped second column region of the second conductivity type provided in the drift layer. a second parallel pn structure in which second column regions are repeatedly and alternately arranged in a direction parallel to the front surface;
a second conductivity type base region provided in the surface layer of the first parallel pn structure;
a first conductivity type source region selectively provided in a surface layer of the base region;
a trench penetrating the source region and the base region and reaching the first column region;
a gate electrode provided inside the trench with a gate insulating film interposed therebetween;
a first electrode in contact with the source region and the base region;
a second electrode provided on the back surface of the semiconductor substrate;
a second conductivity type channel stopper provided on the surface layer of the drift layer of the termination structure;
a first semiconductor region of a first conductivity type that is selectively provided in the drift layer of the termination structure and is in contact with the channel stopper;
Equipped with
The second electrode of the first semiconductor element and the second electrode of the second semiconductor element are electrically connected to a frame electrode,
A semiconductor device, wherein the channel stopper of the first semiconductor element and the channel stopper of the second semiconductor element are separated from each other on a side where the first semiconductor element and the second semiconductor element are adjacent to each other. Claims 1 to 5, wherein the length of an adjacent side of the first semiconductor element and the second semiconductor element is at least twice the length of a side perpendicular to the adjacent side. The semiconductor device according to any one of the above. The first electrode of the first semiconductor element is a source electrode, the first electrode of the second semiconductor element is a drain electrode,
6. The semiconductor device according to claim 1, wherein the first semiconductor element includes a highly functional structure having a sensing element. 6. A buffer layer of a first conductivity type is provided between the semiconductor substrate, the drift layer, the first parallel pn region, and the second parallel pn region. The semiconductor device described in . 6. The semiconductor device according to claim 1, wherein the base region is provided on the upper surface of the first and second column regions.

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