WO2020199706A1 - Bi-directional power device and fabrication method therefor - Google Patents

Abstract

Disclosed are a bi-directional power device and a fabrication method therefor, the bi-directional power device comprising: a semiconductor layer; a trench located in the semiconductor layer; a gate dielectric layer located on a sidewall of the trench; a control gate located on a lower portion of the trench; and a shield gate located on an upper portion of the trench. The control gate and the screen gate are in contact with one another, and the control gate and the semiconductor layer are separated by the gate dielectric layer. The shield gate of the present application is located above a control gate in contact with same, and is isolated from a source region and a drain region by means of a shielding dielectric layer. When the bi-directional power device is off, the shield gate consumes all of the electric charge of a second doped region by means of the shielding dielectric layer, improving voltage endurance. When the bi-directional power device is on, the source region and/or the drain region are provided with a low-impedance conductive path with the semiconductor layer.

Description

Bidirectional power device and manufacturing method thereof

This application claims the priority of the Chinese patent application filed on April 3, 2019 with the application number 201910267734.9 and the invention title "Bidirectional Power Device and Manufacturing Method", the entire content of which is incorporated into this application by reference.

Technical field

The present disclosure relates to the technical field of semiconductor manufacturing, in particular to a bidirectional power device and a manufacturing method thereof.

Background technique

Power devices are mainly used in high-power power supply circuits and control circuits, such as switching elements or rectifying elements. In power devices, doped regions of different doping types form a PN junction, thereby realizing the function of a diode or a transistor. Power devices usually need to carry large currents at high voltages in applications. On the one hand, in order to meet the requirements of high-voltage applications and improve device reliability and life, power devices need to have a high breakdown voltage. On the other hand, in order to reduce the power consumption and the heat generated by the power device itself, the power device needs to have low on-resistance. In the power supply circuit, charging and discharging are often involved, and the current flow direction is different during the charging and discharging process, which requires the power device to have the function of bidirectional conduction.

U.S. patents US5612566 and US6087740 disclose bidirectional conduction type power devices. Wherein, the bidirectional power device includes a substrate and a first output pole and a second output pole located on the substrate. The substrate is a P-type substrate or a P-type epitaxial or P-type doped well region; the two output electrodes are respectively composed of a lightly doped N- region and a heavily doped N+ region in the lightly doped N- region. In the conduction state of the power device, when the first output pole is shorted to the substrate, the current flows from the second output pole to the first output pole; when the second output pole is shorted to the substrate, the current flows from the first output pole Flow to the second output pole.

However, the withstand voltage characteristics and on-resistance of bidirectional power devices are a pair of contradictory parameters. Although the impurity concentration of the lightly doped N-region can be reduced, the breakdown voltage can be increased, and better withstand voltage characteristics can be obtained. However, due to the decrease of the impurity concentration of the lightly doped N-region, the on-resistance increases, thereby increasing the power consumption.

In bidirectional power devices, further improvements are still needed to take into account both the withstand voltage characteristics and the on-resistance requirements.

Summary of the invention

In view of the above problems, the purpose of the present disclosure is to provide a bidirectional power device and a manufacturing method thereof, wherein the control gate is located at the lower part of the trench, the shielding gate is located at the upper part of the trench, and the shielding gate and the control gate are in contact with each other to take into account both withstand voltage characteristics and conduction. Requirements of through-resistance.

According to a first aspect of the present disclosure, there is provided a bidirectional power device, including: a semiconductor layer; a trench located in the semiconductor layer; a gate dielectric layer located on the sidewall of the trench; a control gate located under the trench Shielding gate located above the trench; wherein the control gate and the shielding gate are in contact with each other, and the control gate and the semiconductor layer are separated by the gate dielectric layer.

Preferably, the bidirectional power device further includes: a source region and a drain region located in the semiconductor layer and adjacent to the shield gate, and a channel region located in the semiconductor layer and adjacent to the control gate.

Preferably, the source region and the drain region extend from the first surface of the semiconductor layer to overlap with the control gate.

Preferably, the doping type of the semiconductor layer is a first doping type, the doping type of the source and drain regions is a second doping type, and the doping type of the channel region is a first doping Type or second doping type, the first doping type and the second doping type are opposite.

Preferably, the bidirectional power device further includes: a shielding dielectric layer located on the sidewall of the trench, and the shielding gate and the semiconductor layer are separated by the shielding dielectric layer.

Preferably, the thickness of the shielding dielectric layer is 0.1-0.25um.

Preferably, the length of the shielding grid is 0.4-0.8um.

Preferably, the thickness of the shielding dielectric layer is greater than or equal to the thickness of the gate dielectric layer.

Preferably, the width of the control gate is greater than the width of the shield gate.

Preferably, the length of the source region and the drain region is greater than the length of the shielding gate and smaller than the sum of the lengths of the shielding gate and the control gate.

Preferably, the semiconductor layer is selected from one of the semiconductor substrate itself, an epitaxial layer formed on the semiconductor substrate, or a well region implanted in the semiconductor substrate.

Preferably, the bidirectional power device further includes: a first contact that contacts the source region to form a first output electrode; a second contact that contacts the drain region to form a second output electrode; and a third contact , In contact with the semiconductor layer to form a substrate electrode; and a fourth contact, in contact with the control gate and/or shielding gate to form a gate electrode.

Preferably, the bidirectional power device further includes: a first lead region located in the source region, wherein the doping concentration of the first lead region is greater than the doping concentration of the source region; and the covering dielectric layer is located in the source region. On the first surface of the semiconductor layer; a first contact hole extending through the cover dielectric layer to the source region; the first contact contacting the source region through the first contact hole and the first lead region.

Preferably, the bidirectional power device further includes: a second lead region located in the drain region, wherein the doping concentration of the second lead region is greater than the doping concentration of the drain region; and the second contact hole penetrates the drain region. The cover dielectric layer extends to the drain region; the second contact is in contact with the drain region through a second contact hole and a second lead region.

Preferably, the bidirectional power device further includes: a third lead region located in the semiconductor layer and close to the first surface of the semiconductor layer, wherein the doping concentration of the third lead region is greater than that of the semiconductor layer. Impurity concentration; a third contact hole extending through the cover dielectric layer to the semiconductor layer; the third contact is in contact with the semiconductor layer through a third contact hole and a third lead region.

Preferably, the fourth contact hole extends through the cover dielectric layer to the control gate and/or shield gate.

Preferably, the third contact is located on the second surface of the semiconductor layer.

Preferably, the bidirectional power device further includes: a wiring layer, the wiring layer includes a first wiring to a fourth wiring, and the first output electrode, the second output electrode, the substrate electrode and The gate electrode is electrically connected.

Preferably, the bidirectional power device further includes: a plurality of metal solder balls located on the wiring layer and electrically connected to the first output electrode, the second output electrode, the substrate electrode and the gate electrode through the wiring layer.

Preferably, the length of the control grid is greater than the length of the shield grid.

Preferably, when the bidirectional power device is turned on, the substrate electrode is electrically connected to one of the first output electrode and the second output electrode to realize bidirectional selection of the current direction.

Preferably, when the substrate electrode is electrically connected to the first output electrode, current flows from the second output electrode to the first output electrode; when the substrate electrode and the second output electrode are electrically connected When connected, current flows from the first output electrode to the second output electrode.

According to a second aspect of the present disclosure, there is provided a bidirectional power device, including a plurality of cell structures, the cell structure being the aforementioned cell structure; source regions in the plurality of cell structures are electrically connected together, The drain regions in the multiple cell structures are electrically connected together.

According to a third aspect of the present disclosure, there is provided a method for manufacturing a bidirectional power device, including: forming a trench in a semiconductor layer; forming a gate dielectric layer on the sidewall of the trench; and forming a control gate at the bottom of the trench Forming a shielding gate on the upper part of the trench; wherein the control gate and the shielding gate are in contact with each other; the control gate and the semiconductor layer are separated by the gate dielectric layer.

Preferably, the method further includes: forming a source region and a drain region adjacent to the shield gate in the semiconductor layer; and forming a channel region adjacent to the control gate in the semiconductor layer.

Preferably, the source region and the drain region extend from the first surface of the semiconductor layer to overlap with the control gate.

Preferably, the method further includes: forming a shielding dielectric layer on the sidewall of the trench, and the shielding gate and the semiconductor layer are separated by the shielding dielectric layer.

Preferably, the thickness of the shielding dielectric layer is 0.1-0.25um.

Preferably, the length of the shielding grid is 0.4-0.8um.

Preferably, the thickness of the shielding dielectric layer is greater than or equal to the thickness of the gate dielectric layer.

Preferably, the width of the control gate is greater than the width of the shield gate.

Preferably, the length of the source region and the drain region is greater than the length of the shielding gate and smaller than the sum of the lengths of the shielding gate and the control gate.

Preferably, the method further includes: forming a first contact in contact with the source region, the first contact forming a first output electrode; forming a second contact in contact with the drain region, the second contact Contacting to form a second output electrode; forming a third contact in contact with the semiconductor layer, and the third contact forming a substrate electrode; forming a fourth contact in contact with the control gate and/or shielding gate, the The fourth contact forms the gate electrode.

Preferably, the steps of forming the first contact, the second contact and the fourth contact include:

Forming a first lead region and a second lead region in the source region and the drain region, respectively;

Forming a covering dielectric layer on the first surface of the semiconductor layer;

Forming a first contact hole, a second contact hole, and a fourth contact hole extending through the cover dielectric layer to the source region and the drain region;

Filling a metal layer on the cover dielectric layer, the metal layer filling the first contact hole, the second contact hole and the fourth contact hole to form a first contact, a second contact and a fourth contact;

Wherein, the first contact is in contact with the source region through the first contact hole, the first lead region, the second contact is in contact with the drain region through the second contact hole, the second lead region, and the fourth contact is through the fourth contact hole. The contact hole is in contact with the control gate and/or the shield gate.

Preferably, the step of forming the third contact includes: forming a third lead region in the semiconductor layer, the third lead region being close to the first surface of the semiconductor layer; The third contact hole of the semiconductor layer; a metal layer is filled on the cover dielectric layer, and the metal layer fills the third contact hole to form a third contact; wherein the third contact passes through the third contact hole and the third lead area In contact with the semiconductor layer.

Preferably, the step of forming the third contact includes: forming a substrate on the second surface of the semiconductor layer; evaporating a metal layer on the substrate to form a third contact; wherein the third contact is in contact with the semiconductor layer contact.

Preferably, the method further includes: forming a wiring layer on the surface of the bidirectional power device, the wiring layer includes a first wiring to a fourth wiring, which is connected to the first output electrode and the first output electrode through a plurality of conductive holes, respectively. The two output electrodes, the substrate electrode and the gate electrode are electrically connected.

Preferably, the method further includes: forming a plurality of metal solder balls on the wiring layer, and the plurality of metal solder balls communicate with the first output electrode, the second output electrode, the substrate electrode and the gate through the wiring layer. The electrodes are electrically connected.

Preferably, the method further includes: when the bidirectional power device is turned on, electrically connecting the substrate electrode with one of the first output electrode and the second output electrode to realize bidirectional selection of the current direction.

Preferably, when the substrate electrode is electrically connected to the first output electrode, current flows from the second output electrode to the first output electrode; when the substrate electrode and the second output electrode are electrically connected When connected, current flows from the first output electrode to the second output electrode.

In the bidirectional power device and the manufacturing method thereof provided by the embodiments of the present disclosure, a control gate and a shielding gate are respectively formed on the lower and upper parts of the trench, the control gate and the shielding gate are in contact with each other, and the control gate and the semiconductor layer are separated by a gate dielectric layer , The shielding gate is separated from the source and drain regions by a shielding dielectric layer. When the bidirectional power device is turned off, the shielding gate depletes the charge in the source and drain regions through the shielding dielectric layer to improve the withstand voltage characteristics of the device; When the device is turned on, the source region and/or the drain region and the semiconductor layer provide a low-impedance conduction path.

Further, when the bidirectional power device is turned on, the substrate electrode is electrically connected to one of the first output electrode and the second output electrode to realize bidirectional selection of the current direction. When the substrate electrode is electrically connected to the first output electrode, current flows from the second output electrode to the first output electrode; when the substrate electrode is electrically connected to the second output electrode, Electric current flows from the first output electrode to the second output electrode.

Further, different threshold voltages can be achieved by adjusting the thickness of the shielding dielectric layer, the doping concentration of the source and drain regions, and the length of the shielding gate.

Further, the channel region is adjacent to the control gate located under the trench, and the channel length can be reduced by reducing the width of the trench, thereby reducing the channel resistance.

Further, the substrate electrode, the first output electrode, the second output electrode, and the gate electrode of the bidirectional power device are drawn to the surface of the semiconductor substrate through the wiring layer, and metal solder balls are formed on the wiring layer. Due to the use of the ball planting process, the traditional package wire bonding is omitted, the parasitic inductance and parasitic resistance of the package are reduced, and the package resistance of the bidirectional power device is reduced; because there is no plastic encapsulation material, it makes heat dissipation easier and reduces Low power consumption improves the reliability and safety of bidirectional power devices.

Further, the bidirectional power device can be composed of multiple cell structures. The source regions of all cell structures are electrically connected together as the first output electrode, and the drain regions are electrically connected together as the second output electrode. Quantity, improve the current capability of bidirectional power devices.

Description of the drawings

Through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, the above and other objectives, features, and advantages of the present disclosure will be more apparent. In the accompanying drawings:

Fig. 1 shows a schematic circuit diagram of a bidirectional power device according to an embodiment of the present disclosure;

2 to 4 respectively show a cross-sectional view and a top view of different cross-sections of the bidirectional power device of the first embodiment of the present disclosure;

Fig. 5 shows a cross-sectional view of a plurality of cell structures of the first embodiment of the present disclosure;

Fig. 6 shows a top view of a bidirectional power device according to a second embodiment of the present disclosure;

Fig. 7 shows a cross-sectional view of a bidirectional power device according to a third embodiment of the present disclosure;

Fig. 8 shows a top view of a bidirectional power device according to a third embodiment of the present disclosure;

FIG. 9 shows a schematic diagram of package pins of a bidirectional power device according to a third embodiment of the present disclosure;

10a to 10i show cross-sectional views at different stages of a method for manufacturing a bidirectional power device according to a fourth embodiment of the present disclosure.

detailed description

Hereinafter, various embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are represented by the same or similar reference numerals. For the sake of clarity, the various parts in the drawings are not drawn to scale.

The specific embodiments of the present disclosure will be described in further detail below with reference to the accompanying drawings and embodiments.

FIG. 1 shows a schematic circuit diagram of a bidirectional power device provided by an embodiment of the present disclosure. The bidirectional power device is formed by a transistor and has a bidirectional conduction function. As shown in FIG. 1, the bidirectional power device includes a substrate Sub, two output poles S1 and S2 located on the substrate Sub, and two parasitic body diodes D1 and D2. When the output pole S2 is shorted to the substrate Sub and a high voltage is applied to the gate G, the voltage is higher than the threshold voltage of the bidirectional power device, the bidirectional power device is turned on, and the current flows from the output pole S1 to the output pole S2; when the output pole S1 and The substrate Sub is short-circuited, and when a high voltage is applied to the gate G, the voltage is higher than the threshold voltage of the bidirectional power device, the bidirectional power device is turned on, and the current flows from the output pole S2 to the output pole S1; when the substrate Sub is connected to zero voltage, the gate G applies a low voltage, the voltage is lower than the threshold voltage, the bidirectional power device is cut off.

First embodiment

2 to 4 respectively show a cross-sectional view and a top view of the bidirectional power device of the first embodiment of the present disclosure; among them, FIG. 2 is a cross-sectional view taken along line AA' in the top view shown in FIG. 4, and FIG. 3 is FIG. 4. A cross-sectional view taken along the line BB' in the top view shown. In this embodiment, the bidirectional power device is a trench device, which may be a metal oxide semiconductor field effect transistor (MOSFET), an IGBT device or a diode. In the following, an N-type MOSFET is taken as an example for description, however, the present disclosure is not limited to this.

The bidirectional power device shown in FIG. 2 only includes a longitudinal structural diagram of a cell structure, but in actual products, the number of cell structures can be one or more. 2 to 4, the bidirectional power device includes a semiconductor layer 10, a trench 20 located in the semiconductor layer 10, a gate dielectric layer 21 located on the sidewalls of the trench 20, and located in the trench 20 The lower control gate 22 and the shield gate 23 located on the upper part of the trench 20. Among them, the control gate 22 and the shield gate 23 are in contact with each other.

In this embodiment, the semiconductor layer 10 is, for example, the semiconductor substrate itself, or an epitaxial layer formed on the semiconductor substrate, or a well region implanted in the semiconductor substrate. The doping concentration of the semiconductor layer 10 is 7E14 to 3E16 cm ^-3 . The semiconductor layer 10 is, for example, a silicon substrate, or an epitaxial layer formed on a silicon substrate, or a well region formed in a silicon substrate, the doping type is P-type, and the semiconductor layer 10 is doped with the silicon substrate Same type. The semiconductor layer 10 has opposite first and second surfaces.

Wherein, the control gate 22 and the semiconductor layer 10 are separated by the gate dielectric layer 21.

Furthermore, the bidirectional power device further includes a shielding dielectric layer 25 on the sidewall of the trench 20, and the shielding gate 23 and the semiconductor layer 10 are separated by the shielding dielectric layer 25.

In this embodiment, the materials of the gate dielectric layer 21 and the shielding dielectric layer 25 may be silicon dioxide or silicon nitride or a composite structure of silicon dioxide and silicon nitride, and the materials of the two may be the same or different.

The thickness of the gate dielectric layer 21 is 200-1000 angstroms, and the thickness of the shielding dielectric layer 25 is 1000-2500 angstroms, that is, 0.1-0.25um. The thickness of the shielding dielectric layer 25 is greater than or equal to the thickness of the gate dielectric layer 21. The length L2 of the shielding grid 23 is 0.4-0.8um.

Further, a source region 31 and a drain region 32 with an N-type doping type extending in the longitudinal direction are formed in the semiconductor layer 10, wherein the source region 31 and the drain region 32 can be interchanged; and the adjacent regions are formed in the semiconductor layer 10 The channel region 40 of the control gate 22 is described.

In this embodiment, the doping type of the semiconductor layer 10 is the first doping type, the doping type of the source region 31 and the drain region 32 is the second doping type, and the doping type of the channel region 40 is The doping type is the first doping type or the second doping type, and the first doping type and the second doping type are opposite.

In this embodiment, the source region 31 and the drain region 32 extend from the first surface of the semiconductor layer 10 to overlap with the control gate 22. The length K of the source region 31 and the drain region 32 extending in the semiconductor layer 10 is greater than the length L2 of the shielding gate 23 extending in the semiconductor layer 10, but less than that of the shielding gate 23 and the control gate 22 extending in the semiconductor layer 10 The sum of length L1+L2, that is, L2<K<L1+L2.

The shielding gate 23 is separated from the source region 31 and/or the drain region 32 by a shielding dielectric layer 25. When the bidirectional power device is turned off, the shielding gate depletes the charge in the source and drain regions through the shielding dielectric layer to improve the withstand voltage characteristics of the device; when the bidirectional power device is turned on, the source and drain regions and the semiconductor layer provide low impedance conduction Pass path. Therefore, the thickness of the shielding dielectric layer, the doping concentration of the source and drain regions, and the length of the shielding gate can be adjusted to achieve different threshold voltages.

Since the channel region 40 is adjacent to the control gate 22 located below the trench 20, the channel length can be reduced by reducing the width of the trench, thereby reducing the channel resistance.

Further, a first lead region 311 and a second lead region 321 are formed in the source region 31 and the drain region 32. The doping type of the first lead region 311 is the same as the doping type of the source region 31, and the doping concentration of the first lead region 311 is greater than the doping concentration of the source region 31. The doping type of the second lead region 321 is the same as that of the drain region 32, and the doping concentration of the second lead region 321 is greater than the doping concentration of the drain region 32.

Further, a third lead region 101 is formed in the semiconductor layer 10, and the third lead region 101 is close to the first surface of the semiconductor layer 10. The doping type of the third lead region 101 is the same as that of the semiconductor layer 10. The doping types are the same, and the doping concentration of the third lead region 101 is greater than the doping concentration of the semiconductor layer 10.

Further, a cover dielectric layer 11 is formed on the first surface of the semiconductor layer 10 and a contact hole 50 penetrating the cover dielectric layer 11 is formed. The contact hole 50 includes a first contact hole 51, a second contact hole 52, and a third contact hole. Hole 53 and fourth contact hole 54. Wherein, the first contact hole 51 is located on the source region 31 and extends through the cover dielectric layer 11 to the source region 31, and the second contact hole is located on the drain region 32 and penetrates the cover dielectric layer. 11 extends to the drain region 32.

The third contact hole 53 is located on both sides of the trench 20 and extends through the cover dielectric layer 11 to the semiconductor layer 10.

The fourth contact hole 54 is located on the trench 20 and extends through the cover dielectric layer 11 to the control gate 22 and/or the shield gate 23 in the trench 20.

In this embodiment, the cover dielectric layer 11 may be undoped silicon glass (USG) and boron-phosphorus doped silicon glass (BPSG).

A metal layer 60 is deposited on the cover dielectric layer 11, and the metal layer 60 fills the first contact hole 51 to the fourth contact hole 54 to form the first contact 61 to the fourth contact 64, respectively. The first contact 61 contacts the source region 31 through the first contact hole 51 and the first lead region 311 to form the first output electrode S1, and the second contact 62 contacts the source region 31 through the second contact hole 52 and the second lead region 321. The drain region 32 contacts to form the second output electrode S2, and the third contact 63 contacts the semiconductor layer 10 through the third contact hole 53 and the third lead region 101 to form the substrate electrode Sub. As shown in FIG. 3, the fourth contact 64 contacts the control gate 22 and/or the shield gate 23 via the fourth contact hole 54 to form a gate electrode.

In this embodiment, the material of the metal layer 60 may be titanium, titanium nitride, aluminum copper, aluminum silicon copper, or aluminum silicon.

In FIG. 2, one cell only includes three trenches, one source region and one drain region, but in actual products, the number of source regions 31 and drain regions 32 is more than one. Taking the example shown in FIG. 2 as an example, the three trench structures are the first trench 20 a, the second trench 20 b, and the third trench 20 c. The first contact 61 leads the source region 31 to the surface of the semiconductor layer 10 to form a first output electrode S1, the second contact 62 leads the drain region 32 to the surface of the semiconductor layer 10 to form a second output electrode S2, and the third contact 63 leads the semiconductor layer The layer 10 is drawn to form a substrate electrode Sub, and the fourth contact 64 leads the control gate 22 and the shielding gate 23 to the surface of the semiconductor layer 10 to form a gate electrode G, wherein the control gate 22 and the shielding gate 23 are electrically connected together. The first trench 20 a and the third trench 20 c are symmetrically arranged outside the source region 31 and the drain region 32. Wherein, the first output electrode S1 and the second output electrode S2 are formed by leading the source region 31 and the drain region 32 to the surface of the semiconductor layer 10 respectively, and they can be interchanged.

When the voltage applied to the control gate 22 is greater than the threshold voltage, the bidirectional power device is turned on, and only the channel region of the second trench 20b between the source region 31 and the drain region 32 has current. By selecting one of the output terminal electrodes and The substrate electrode is connected to realize the selection of the current direction. For example, when the first output electrode S1 is connected to the substrate electrode Sub, the current flows from the second output electrode S2 to the first output electrode S1; when the second output electrode S2 is connected to the substrate When the electrode Sub is connected, current flows from the first output electrode S1 to the second output electrode S2.

When the voltage applied to the control gate 22 is less than the threshold voltage, the bidirectional power device is turned off. Since the control gate 22 and the shielding gate 23 are electrically connected together, the voltage applied to the shielding gate 23 is a low voltage at this time, and a high voltage is applied to the first output electrode S1 and the second output electrode S2, in the source region 31 and the drain region 32. A voltage difference is formed between and the shielding gate 23. The shielding gate 23 in the first trench 20a and the third trench 20c induces charges in the source region 31 and the source region 32 through the shielding dielectric layer 25. The thickness and material of the shielding dielectric layer 25 and the source region 31 and The impurity concentration of the drain region 32 finally completely depletes the source region and the drain region, achieving the purpose of improving the withstand voltage of the device. At the same time, as the impurity concentration of the source region 31 and the drain region 32 increases, the resistance of the device is also greatly reduced.

FIG. 5 only shows a schematic diagram of two cell structures. A plurality of first contacts 61 are connected together to form a first output electrode S1, and a plurality of second contacts 62 are connected together to form a second output electrode S2 to improve the device performance Current capability. Alternatively, for other types of bidirectional power devices, by increasing the number of cells, that is, selecting two or more cell structures to connect in parallel, the current capability of the device can be improved.

Second embodiment

This embodiment uses basically the same technical solution as the first embodiment. The difference is that in the first embodiment, the third contact 63 is formed on the first surface of the semiconductor layer 10 through the third contact hole 53, the third The lead region 101 is in contact with the semiconductor layer 10 to form a substrate electrode Sub. In this embodiment, the third contact 63 is formed on the second surface of the semiconductor layer 10, as shown in FIG. 6. Specifically, the bidirectional power device is formed on the substrate 1 with a higher doping concentration, and then the metal layer is evaporated on the back surface of the substrate 1 to form the third contact 63.

In the first embodiment, the gate, substrate electrode, first output electrode, and second output electrode of the bidirectional power device are all drawn from the first surface of the semiconductor layer 10, which is suitable for chip scale packaging (CSP).

In the second embodiment, the substrate electrode of the bidirectional power device is drawn from the second surface of the semiconductor layer 10, which can adapt to traditional device packaging forms (such as SOP8, DIP8) and increase the heat dissipation capability of the bidirectional power device.

In this embodiment, the remaining parts of the bidirectional power device are basically the same as those in the first embodiment, and the specific structure is not repeated here.

The third embodiment

This embodiment adopts basically the same technical solution as the first embodiment. Compared with the first embodiment, this embodiment further includes a wiring layer 70 (not shown in the figure) and a plurality of metal solder balls located on the wiring layer 70 80.

Due to the small spacing of the trenches 20, the gate electrode derived from the trench structure is relatively narrow, resulting in a large parasitic resistance. In order to reduce the parasitic resistance, a wiring layer 70 is added above the power device provided in the first embodiment.

As shown in FIGS. 7 and 8, the wiring layer 70 (not shown in the figure) is located on the surface of the power device for connecting the first contact 61, the second contact 62, the third contact 63 and the fourth contact 64 The formed first output electrode S1, second output electrode S2, substrate electrode Sub, and gate electrode G are led to the surface of the power device.

Among them, the first contact 61, the second contact 62, the third contact 63 and the fourth contact 64 are located in the first metal layer M1, the wiring layer 70 is located in the second metal layer M2, and the first metal layer M1 and the second metal layer M2 is separated by a covering dielectric layer 11. The wiring layer 70 is electrically connected to the first contact 61, the second contact 62, the third contact 63, and the fourth contact 64 through a plurality of conductive holes 90. The wiring layer 70 includes a first wiring 71, a second wiring 72, a third wiring 73, and a fourth wiring 74 (not shown in the figure), wherein the first wiring 71 is electrically connected to the first contact 61; the second wiring 72 is The second contact 62 is electrically connected; the third wiring 73 is electrically connected to the third contact 63; the fourth wiring 74 is electrically connected to the fourth contact 64.

In this embodiment, the wiring layer 70 is led out by a wider metal wire to reduce the parasitic resistance of the metal layer.

A plurality of metal solder balls 80 are located on the wiring layer 70 and are electrically connected to the first output electrode S1, the second output electrode S2, the substrate electrode Sub, and the gate electrode G through the wiring layer 70. The metal solder ball 80 includes a metal solder ball 81 electrically connected to the first output electrode S1, a metal solder ball 82 electrically connected to the second output electrode S2, and a metal solder ball electrically connected to the substrate electrode Sub. The solder ball 83 and the metal solder ball 84 (not shown in the figure) electrically connected to the gate electrode G.

In this embodiment, a plurality of metal solder balls 80 are formed on the wiring layer using a ball planting process to complete chip-level packaging. The metal solder ball 81 is the pad pin that connects the first output electrode S1 to the outside, the metal solder ball 82 is the pad pin that connects the second output electrode S2 to the outside, and the metal solder ball 83 is the substrate electrode and the outside. The pad pins are electrically connected, and the metal solder ball 84 is a pad pin electrically connected to the gate electrode and the outside.

In a preferred embodiment, an electroplated metal layer M3 is further formed between the metal solder ball 80 and the wiring layer 70, so that the bond between the metal solder ball 80 and the wiring layer 70 is stronger.

Since the first output electrode S1 and the second output electrode S2 need to pass an excessive current, a relatively large number of metal solder balls 81 and 82 are distributed, as shown in FIG. 9, where a plurality of metal solder balls 81 are connected in parallel, and more Two metal solder balls 82 are connected in parallel, which can increase the current distribution between the power device and the external system.

The third embodiment uses the ball planting process, omits the traditional package wire bonding, reduces the parasitic inductance and parasitic resistance of the package, and reduces the package resistance of the power device; because there is no plastic encapsulation, the heat dissipation is more It is easy to reduce power consumption and improve the reliability and safety of power devices.

Fourth embodiment

10a-10i show cross-sectional views at different stages of a method for manufacturing a bidirectional power device according to a fourth embodiment of the present disclosure.

As shown in FIG. 10a, the basic structure of the method for manufacturing a bidirectional power device according to the fourth embodiment of the present disclosure is shown. The formation steps of the structure include: depositing a barrier layer 12 on the surface of the semiconductor layer 10; forming an etching window by photolithography, and The etching window etches the barrier layer 12 and the semiconductor layer 10 to form a trench 20. The depth of the trench 20 reaches 1.2-2.0um.

In this embodiment, the semiconductor layer 10 is, for example, the semiconductor substrate itself, or an epitaxial layer formed on the semiconductor substrate, or a well region implanted in the semiconductor substrate. The doping concentration of the semiconductor layer 10 is 7E14 to 3E16 cm ^-3 . The barrier layer 12 may be silicon dioxide, silicon nitride, or a composite structure of silicon dioxide and silicon nitride. The semiconductor layer 10 is, for example, a silicon substrate, or an epitaxial layer formed on a silicon substrate, or a well region formed in a silicon substrate, the doping type is P-type, and the semiconductor layer 10 is doped with the silicon substrate Same type.

As shown in FIG. 10b, the barrier layer 12 on the surface of the semiconductor layer 10 is removed, and the trench 20 is subjected to sacrificial oxidation to repair the surface of the trench 20. The thickness of the sacrificial oxidation is about 300-1000 angstroms; and then the first conductivity type ion The implantation forms a channel region 40.

In this embodiment, the first conductivity type is P type, and the implanted first conductivity type ions are boron (B) or boron fluoride (BF ₂ ); the implantation dose is 5E11-2E13ions/cm ² .

As shown in FIG. 10c, a gate dielectric layer 21 is grown on the surface of the trench 20, and then polysilicon is deposited on the surface of the gate dielectric layer 21; after chemical mechanical polishing, the polysilicon on the surface of the semiconductor layer 10 is removed, and the height of the polysilicon in the trench 20 is It is flush with the surface of the semiconductor layer 10.

In this embodiment, the material of the gate dielectric layer 21 is silicon dioxide or silicon nitride, and the thickness is 200-1000 angstroms. The thickness of polysilicon deposition is 5000-10000 angstroms.

As shown in FIG. 10d, the gate dielectric layer 21 is wet etched to form a cavity 27 between the upper polysilicon of the trench and the semiconductor layer 10. The depth of the cavity 27 is 0.4-0.8um. The polysilicon covered by the gate dielectric layer 21 at the bottom of the trench is the control gate 22.

As shown in FIG. 10e, through oxidation, an oxide layer is grown in the cavity to form a shielding dielectric layer 25. Due to the high polycrystalline concentration of polysilicon, the oxidation speed is fast during the oxidation process, and the thickness of the grown oxide layer is also thicker, that is, a shielding dielectric layer 25 with a certain thickness is formed. The material of the shielding dielectric layer 25 may be silicon dioxide or silicon nitride or a composite structure of silicon dioxide and silicon nitride.

As shown in FIG. 10f, the steps of wet etching and growth of the oxide layer in FIG. 10d and FIG. 10e are repeated to reach a shielding dielectric layer 25 with a predetermined thickness. The thickness of the shielding dielectric layer 25 is 1000-2500 angstroms, that is, 0.1-0.25um. The polysilicon covered by the shielding dielectric layer on the control gate 22 is the shielding gate 23. The control gate 22 and the shield gate 23 are in contact with each other.

As shown in FIG. 10g, the implantation window is formed by photolithography; the second conductivity type ion implantation is performed according to the implantation window, and the junction is pushed through a temperature of 1000°C to 1150°C to form the source region 31 and the drain region 32.

In this embodiment, the second conductivity type is N type, the implanted second conductivity type ions are phosphorus (P), and the implant dose is 1E13-6E13ions/cm ² .

As shown in FIG. 10h, ion implantation of the second conductivity type is performed in the source region 31 and the drain region 32, and the first lead region 311 and the second lead region 321 are formed after rapid annealing or a temperature of 800°C to 1000°C. . The doping concentration of the first lead region 311 is greater than that of the source region 31; the doping concentration of the second lead region 321 is greater than that of the drain region 32.

In this embodiment, the second conductivity type is N type, the implanted second conductivity type ions are phosphorus (P) or arsenic (As), and the implant dose is 1E15-1E16ions/cm ² .

As shown in FIG. 10i, ion implantation of the first conductivity type is performed in the semiconductor layer 10 to form a third lead region 101. The doping concentration of the third lead region 101 is greater than the doping concentration of the semiconductor layer 10. Undoped silica glass (USG) and boron-phosphorus-doped silica glass (BPSG) are deposited on the surface of the semiconductor layer 10 to form a cover dielectric layer 11; the cover dielectric layer 11 is etched to form a contact hole 50 (not shown in the figure) , Including the contact hole 51 and the contact hole 52 in contact with the source region 31 and the drain region 32, the contact hole 53 in contact with the semiconductor layer 10, and the contact in contact with the control gate 22 and/or the shield gate 23 in the trench 20 Hole 54 (not shown in the figure). The first contact hole 51 contacts the source region 31 through the first lead region to form a first output electrode S1; the second contact hole 52 contacts the drain region 32 through the second lead region to form a second output electrode S2. The contact hole 50 extends to 0.1-0.5 um below the surface of the semiconductor layer 10.

In this embodiment, the first conductivity type is P type, and the implanted first conductivity type ions are boron (B) or boron fluoride (BF ₂ ); the implantation dose is 5E14-8E15ions/cm ² .

As shown in FIG. 10j, a metal layer 60 is deposited in the contact hole 50 to form a surface electrode, that is, a first contact 61, a second contact 62, a third contact 63, and a fourth contact 64 (not shown in the figure) are formed.

In this embodiment, the first contact 61 is the first output electrode S1, the second contact 62 is the second output electrode S2, the third contact 63 is the substrate electrode Sub, and the fourth contact 64 is the gate electrode G. The fourth contact 64 is electrically connected to the control gate 22 and/or the shielding gate 23.

Fifth embodiment

This embodiment adopts basically the same technical solution as the fourth embodiment. The difference is that the steps of forming the third contact 63 are different. The bidirectional power device is formed on the substrate 1 with a higher doping concentration, and then on the substrate 1 The back surface evaporation metal layer 60 of 1 forms a third contact 63, and the third contact 63 forms a substrate electrode. For example, the material of the metal layer 60 in this step includes titanium nickel silver or titanium nickel gold in a traditional process.

In this embodiment, the remaining steps of the method for manufacturing a bidirectional power device are basically the same as those in the fourth embodiment, and the specific structure will not be repeated.

Sixth embodiment

This embodiment adopts basically the same technical solution as the fourth embodiment. Compared with the fourth embodiment, this embodiment further includes forming a wiring layer 70 on the surface of the power device, connecting the first contact 61 and the second contact 62. The first output electrode S1, the second output electrode S2, the substrate electrode Sub, and the gate electrode G formed by the third contact 63 and the fourth contact 64 are led to the surface of the power device; and a plurality of electrodes are formed on the wiring layer. The plurality of metal solder balls 80 are electrically connected to the substrate electrode Sub, the first output electrode S1, the second output electrode S2, and the gate electrode G through the wiring layer 70.

Among them, the first contact 61, the second contact 62 and the third contact 63 are located in the first metal layer M1, the wiring layer 70 is located in the second metal layer M2, and the first metal layer M1 and the second metal layer M2 are covered by The dielectric layer 11 is isolated, and the wiring layer 70 is electrically connected to the first contact 61, the second contact 62 and the third contact 63 through a plurality of conductive holes 90.

In this embodiment, the wiring layer 70 is led out by a wider metal wire to reduce the parasitic resistance of the metal layer. A plurality of metal solder balls 80 are formed on the wiring layer by the ball planting process to complete the chip-level packaging.

In the above embodiment, the doping type of the semiconductor layer 10 is the first doping type, the doping type of the source region 31 and the drain region 32 is the second doping type, the first doping type is P-type doping, and the first doping type is P-type doping. The second doping type is N-type doping to form an N-type bidirectional power device.

In an alternative embodiment, the doping type of the semiconductor layer 10 is exchanged with the doping type of the source region 31 and the drain region 32, that is, the first doping type is N-type doping, and the second doping type is P Type doping to form a P-type bidirectional power device.

According to the embodiments of the present disclosure as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to only the specific embodiments described. Obviously, based on the above description, many modifications and changes can be made. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present disclosure, so that those skilled in the art can make good use of the present disclosure and modifications based on the present disclosure. The present disclosure is only limited by the claims and their full scope and equivalents.

Claims (40)

1. A bidirectional power device, characterized in that it comprises:

   Semiconductor layer

   A trench in the semiconductor layer;

   A gate dielectric layer located on the sidewall of the trench;

   A control gate located under the trench;

   A shielding gate located above the trench;

   Wherein, the control gate and the shielding gate are in contact with each other,

   The control gate and the semiconductor layer are separated by the gate dielectric layer.
2. The bidirectional power device according to claim 1, further comprising: source and drain regions located in the semiconductor layer and adjacent to the shielding gate, and located in the semiconductor layer and adjacent to the control gate. Channel area.
3. The bidirectional power device according to claim 2, wherein the source region and the drain region extend from the first surface of the semiconductor layer to overlap with the control gate.
4. The bidirectional power device according to claim 2, wherein the doping type of the semiconductor layer is a first doping type, and the doping type of the source and drain regions is a second doping type, and The doping type of the channel region is the first doping type or the second doping type, and the first doping type and the second doping type are opposite.
5. The bidirectional power device according to claim 1, further comprising: a shielding dielectric layer on the sidewall of the trench, and the shielding gate and the semiconductor layer are separated by the shielding dielectric layer.
6. The bidirectional power device according to claim 5, wherein the thickness of the shielding dielectric layer is 0.1-0.25um.
7. The bidirectional power device according to claim 1, wherein the length of the shielding gate is 0.4-0.8um.
8. The bidirectional power device according to claim 5, wherein the thickness of the shielding dielectric layer is greater than or equal to the thickness of the gate dielectric layer.
9. The bidirectional power device according to claim 1, wherein the width of the control gate is greater than the width of the shielding gate.
10. 4. The bidirectional power device according to claim 2, wherein the length of the source region and the drain region is greater than the length of the shielding gate, and smaller than the sum of the lengths of the shielding gate and the control gate.
11. The bidirectional power device according to claim 1, wherein the semiconductor layer is selected from one of the semiconductor substrate itself, an epitaxial layer formed on the semiconductor substrate, or a well region implanted in the semiconductor substrate.
12. The bidirectional power device according to claim 2, further comprising:

    A first contact, in contact with the source region to form a first output electrode;

    A second contact, in contact with the drain region to form a second output electrode;

    The third contact is in contact with the semiconductor layer to form a substrate electrode;

    The fourth contact is in contact with the control gate and/or the shielding gate to form a gate electrode.
13. The bidirectional power device according to claim 12, further comprising:

    The first lead region is located in the source region, wherein the doping concentration of the first lead region is greater than the doping concentration of the source region;

    Covering the dielectric layer, located on the first surface of the semiconductor layer;

    A first contact hole extending through the cover dielectric layer to the source region;

    The first contact is in contact with the source region through a first contact hole and a first lead region.
14. The bidirectional power device according to claim 13, further comprising:

    The second lead region is located in the drain region, wherein the doping concentration of the second lead region is greater than the doping concentration of the drain region;

    A second contact hole extending through the cover dielectric layer to the drain region;

    The second contact is in contact with the drain region through a second contact hole and a second lead region.
15. The bidirectional power device according to claim 14, further comprising:

    A third lead region located in the semiconductor layer and close to the first surface of the semiconductor layer, wherein the doping concentration of the third lead region is greater than the doping concentration of the semiconductor layer;

    A third contact hole extending through the cover dielectric layer to the semiconductor layer;

    The third contact is in contact with the semiconductor layer through a third contact hole and a third lead region.
16. The bidirectional power device according to claim 14, further comprising:

    The fourth contact hole extends through the cover dielectric layer to the control gate and/or shield gate.
17. The bidirectional power device according to claim 14, wherein the third contact is located on the second surface of the semiconductor layer.
18. The bidirectional power device according to claim 12, further comprising:

    The wiring layer includes a first wiring to a fourth wiring, and is electrically connected to the first output electrode, the second output electrode, the substrate electrode, and the gate electrode through a plurality of conductive holes, respectively.
19. The bidirectional power device according to claim 18, further comprising:

    A plurality of metal solder balls are located on the wiring layer and are electrically connected to the first output electrode, the second output electrode, the substrate electrode and the gate electrode through the wiring layer.
20. The bidirectional power device according to claim 1, wherein the length of the control gate is greater than the length of the shielding gate.
21. The bidirectional power device according to claim 12, wherein when the bidirectional power device is turned on, the substrate electrode is electrically connected to one of the first output electrode and the second output electrode to realize bidirectional selection of current direction .
22. 22. The bidirectional power device according to claim 21, wherein when the substrate electrode is electrically connected to the first output electrode, current flows from the second output electrode to the first output electrode;

    When the substrate electrode is electrically connected to the second output electrode, current flows from the first output electrode to the second output electrode.
23. A bidirectional power device, characterized by comprising a plurality of cell structures, the cell structure being the cell structure according to any one of claims 1-22;

    The source regions in the multiple cell structures are electrically connected together, and the drain regions in the multiple cell structures are electrically connected together.
24. A method for manufacturing a bidirectional power device, characterized in that it comprises:

    Forming a trench in the semiconductor layer;

    Forming a gate dielectric layer on the sidewall of the trench;

    Forming a control gate under the trench;

    Forming a shielding gate on the upper part of the trench;

    Wherein, the control grid and the shielding grid are in contact with each other;

    The control gate and the semiconductor layer are separated by the gate dielectric layer.
25. The method according to claim 24, further comprising:

    Forming a source region and a drain region adjacent to the shield gate in the semiconductor layer; and

    A channel region adjacent to the control gate is formed in the semiconductor layer.
26. The method according to claim 24, wherein the source region and the drain region extend from the first surface of the semiconductor layer to overlap with the control gate.
27. The method according to claim 24, further comprising:

    A shielding dielectric layer is formed on the sidewall of the trench, and the shielding gate and the semiconductor layer are separated by the shielding dielectric layer.
28. The method according to claim 27, wherein the thickness of the shielding dielectric layer is 0.1-0.25um.
29. The method according to claim 24, wherein the length of the shielding grid is 0.4-0.8um.
30. The method according to claim 27, wherein the thickness of the shielding dielectric layer is greater than or equal to the thickness of the gate dielectric layer.
31. The method of claim 24, wherein the width of the control gate is greater than the width of the shield gate.
32. The method according to claim 25, wherein the length of the source region and the drain region is greater than the length of the shielding gate, and smaller than the sum of the lengths of the shielding gate and the control gate.
33. The method according to claim 25, further comprising:

    Forming a first contact in contact with the source region, the first contact forming a first output electrode;

    Forming a second contact in contact with the drain region, the second contact forming a second output electrode;

    Forming a third contact in contact with the semiconductor layer, the third contact forming a substrate electrode;

    A fourth contact is formed in contact with the control gate and/or the shield gate, and the fourth contact forms a gate electrode.
34. The method of claim 33, wherein the step of forming the first contact, the second contact and the fourth contact comprises:

    Forming a first lead region and a second lead region in the source region and the drain region, respectively;

    Forming a covering dielectric layer on the first surface of the semiconductor layer;

    Forming a first contact hole, a second contact hole, and a fourth contact hole extending through the cover dielectric layer to the source region and the drain region;

    Filling a metal layer on the cover dielectric layer, the metal layer filling the first contact hole, the second contact hole and the fourth contact hole to form a first contact, a second contact and a fourth contact;

    Wherein, the first contact is in contact with the source region through the first contact hole, the first lead region, the second contact is in contact with the drain region through the second contact hole, the second lead region, and the fourth contact is through the fourth contact hole. The contact hole is in contact with the control gate and/or the shield gate.
35. The method of claim 34, wherein the step of forming the third contact comprises:

    Forming a third lead region in the semiconductor layer, the third lead region being close to the first surface of the semiconductor layer;

    Forming a third contact hole extending through the cover dielectric layer to the semiconductor layer;

    Filling a metal layer on the cover dielectric layer, the metal layer filling a third contact hole to form a third contact;

    Wherein, the third contact is in contact with the semiconductor layer through the third contact hole and the third lead area.
36. The method of claim 34, wherein the step of forming the third contact comprises:

    Forming a substrate on the second surface of the semiconductor layer;

    Evaporating a metal layer on the substrate to form a third contact;

    Wherein, the third contact is in contact with the semiconductor layer.
37. The method according to claim 33, further comprising:

    A wiring layer is formed on the surface of the bidirectional power device. The wiring layer includes a first wiring to a fourth wiring, and is connected to the first output electrode, the second output electrode, the substrate electrode, and the gate through a plurality of conductive holes. The electrodes are electrically connected.
38. The method according to claim 37, further comprising:

    A plurality of metal solder balls are formed on the wiring layer, and the plurality of metal solder balls are electrically connected to the first output electrode, the second output electrode, the substrate electrode, and the gate electrode through the wiring layer.
39. The method according to claim 33, further comprising:

    When the bidirectional power device is turned on, the substrate electrode is electrically connected to one of the first output electrode and the second output electrode to realize bidirectional selection of current direction.
40. The method according to claim 39, wherein when the substrate electrode is electrically connected to the first output electrode, current flows from the second output electrode to the first output electrode;

    When the substrate electrode is electrically connected to the second output electrode, current flows from the first output electrode to the second output electrode.

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