CN209896064U - Bidirectional power device - Google Patents
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- CN209896064U CN209896064U CN201920447432.5U CN201920447432U CN209896064U CN 209896064 U CN209896064 U CN 209896064U CN 201920447432 U CN201920447432 U CN 201920447432U CN 209896064 U CN209896064 U CN 209896064U
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
Abstract
Disclosed is a bidirectional power device including: a semiconductor layer; a trench in the semiconductor layer; the gate dielectric layer is positioned on the side wall of the groove; a control gate located at a lower portion of the trench; the shielding gate is positioned at the upper part of the groove; and the isolation layer is positioned between the control gate and the shielding gate, wherein the control gate is separated from the semiconductor layer by the gate dielectric layer. In the application, the shielding grid is positioned above the control grids which are isolated from each other and is isolated from the source region and the drain region through the shielding dielectric layer, when the bidirectional power device is cut off, the shielding grid exhausts charges of the source region and the drain region through the shielding dielectric layer, and the voltage withstanding characteristic is improved; when the bidirectional power device is conducted, the source region and/or the drain region and the semiconductor layer provide a low-impedance conduction path.
Description
Technical Field
The utility model relates to a semiconductor manufacturing technology field, in particular to two-way power device.
Background
The power device is mainly used in a power supply circuit and a control circuit for high power, for example, as a switching element or a rectifying element. In the power device, doped regions of different doping types form a PN junction, thereby realizing the function of a diode or a transistor. Power devices are typically required to carry large currents at high voltages in applications. On the one hand, in order to meet the demand of high voltage applications and to improve device reliability and lifetime, power devices need to have a high breakdown voltage. On the other hand, in order to reduce power consumption and generated heat of the power device itself, the power device needs to have a low on-resistance. In a power supply circuit, charging and discharging are often involved, and then the current flow direction is different during the charging and discharging processes, so that the power device is required to have a bidirectional conduction function.
Power devices of the bidirectional conduction type are disclosed in US patents 5612566 and 6087740. The bidirectional power device comprises a substrate and a first output pole and a second output pole which are arranged on the substrate. The substrate is a P-type substrate or a P-type epitaxial or P-type doped well region; the two output electrodes are respectively composed of a lightly doped N-region and a heavily doped N + region positioned in the lightly doped N-region. In the conducting state of the power device, when the first output electrode is in short circuit with the substrate, current flows from the second output electrode to the first output electrode; when the second output pole is short-circuited to the substrate, current flows from the first output pole to the second output pole.
However, a pair of contradictory parameters is provided between the voltage resistance and the on-resistance of the bidirectional power device. Although the breakdown voltage can be improved by reducing the impurity concentration of the lightly doped N-region, a better withstand voltage characteristic is obtained. But the on-resistance is increased due to the decrease of the impurity concentration of the lightly doped N-region, thereby increasing power consumption.
In the bidirectional power device, further improvement is still required to satisfy both requirements of withstand voltage characteristics and on-resistance.
SUMMERY OF THE UTILITY MODEL
In view of the above, an object of the present invention is to provide a bidirectional power device, wherein the control gate is located at the lower portion of the trench, the shielding gate is located at the upper portion of the trench, and the shielding gate and the control gate are isolated by the isolation layer, so as to meet the requirements of voltage withstanding and on-resistance.
According to the utility model discloses an aspect provides a two-way power device, include: a semiconductor layer; a trench in the semiconductor layer; the gate dielectric layer is positioned on the side wall of the groove; a control gate located at a lower portion of the trench; the shielding gate is positioned at the upper part of the groove; and the isolation layer is positioned between the control gate and the shielding gate, wherein the control gate is separated from the semiconductor layer by the gate dielectric layer.
Preferably, the bidirectional power device further includes: source and drain regions in the semiconductor layer and adjacent to the shield gate, and a channel region in the semiconductor layer and adjacent to the control gate.
Preferably, the source and drain regions extend from the first surface of the semiconductor layer to overlap the control gate.
Preferably, the doping type of the semiconductor layer is a first doping type, the doping types of the source region and the drain region are a second doping type, the doping type of the channel region is a first doping type or a second doping type, and the first doping type and the second doping type are opposite.
Preferably, the bidirectional power device further includes: and the shielding grid is separated from the semiconductor layer by the shielding dielectric layer.
Preferably, the thickness of the shielding dielectric layer is 0.1-0.25 um.
Preferably, the length of the shielding grid is 0.6-1.2 um.
Preferably, the thickness of the shielding dielectric layer is greater than or equal to the thickness of the gate dielectric layer.
Preferably, the width of the control gate is greater than the width of the shield gate.
Preferably, the lengths of the source region and the drain region are greater than the sum of the lengths of the shielding gate and the isolation layer and less than the sum of the lengths of the shielding gate, the isolation layer and the control gate.
Preferably, the semiconductor layer is selected from one of the semiconductor substrate itself, an epitaxial layer formed on the semiconductor substrate, or a well region implanted in the semiconductor substrate.
Preferably, the bidirectional power device further includes: a first contact contacting the source region to form a first output electrode; a second contact contacting the drain region to form a second output electrode; a third contact in contact with the semiconductor layer to form a substrate electrode; a fourth contact contacting the control gate and/or shield gate to form a gate electrode.
Preferably, the bidirectional power device further includes: the first lead area is positioned in the source area, wherein the doping concentration of the first lead area is greater than that of the source area; a cover dielectric layer located on the first surface of the semiconductor layer; the first contact hole penetrates through the covering dielectric layer and extends to the source region; the first contact is in contact with the source region through the first contact hole and the first lead region.
Preferably, the bidirectional power device further includes: the second lead region is positioned in the drain region, wherein the doping concentration of the second lead region is greater than that of the drain region; the second contact hole penetrates through the covering dielectric layer and extends to the drain region; the second contact is in contact with the drain region through a second contact hole and a second lead region.
Preferably, the bidirectional power device further includes: a third lead region located within the semiconductor layer and proximate to the first surface of the semiconductor layer, wherein a doping concentration of the third lead region is greater than a doping concentration of the semiconductor layer; the third contact hole penetrates through the covering dielectric layer and extends to the semiconductor layer; the third contact is in contact with the semiconductor layer through a third contact hole and a third lead region.
Preferably, the fourth contact hole extends to the control gate and/or the shielding gate through the covering dielectric layer.
Preferably, the third contact is located on the second surface of the semiconductor layer.
Preferably, the bidirectional power device further includes: a wiring layer including first to fourth wirings electrically connected to the first output electrode, the second output electrode, the substrate electrode, and the gate electrode through a plurality of conductive holes, respectively.
Preferably, the bidirectional power device further includes: and the metal welding balls are positioned on the wiring layer and are electrically connected with the first output electrode, the second output electrode, the substrate electrode and the gate electrode through the wiring layer.
Preferably, the shield gate is electrically connected to the control gate.
Preferably, the shielding gate is electrically connected to the semiconductor layer.
Preferably, when the bidirectional power device is turned on, the substrate electrode is electrically connected to one of the first output electrode and the second output electrode to realize bidirectional selection of a current direction.
Preferably, when the substrate electrode is electrically connected to the first output electrode, a current flows from the second output electrode to the first output electrode; when the substrate electrode is electrically connected to the second output electrode, a current flows from the first output electrode to the second output electrode.
According to a second aspect of the present invention, there is provided a bidirectional power device, comprising a plurality of cell structures, wherein the cell structures are the bidirectional power devices as described above; the source regions in the plurality of cell structures are electrically connected together and the drain regions in the plurality of cell structures are electrically connected together.
The embodiment of the utility model provides a two-way power device forms control gate and shielding grid respectively on the lower part and the upper portion of slot, and control gate and shielding grid keep apart each other, are separated by the grid dielectric layer between control gate and the semiconductor layer, are separated by the shielding dielectric layer between shielding grid and source region and the drain region, and the shielding grid exhausts the electric charge in source region and drain region through the shielding dielectric layer when two-way power device ends, improves the withstand voltage characteristic of device; when the bidirectional power device is conducted, the source region and/or the drain region and the semiconductor layer provide a low-impedance conduction path.
Further, when the bidirectional power device is conducted, the substrate electrode is electrically connected with one of the first output electrode and the second output electrode, so that bidirectional selection of the current direction is achieved. When the substrate electrode is electrically connected to the first output electrode, a current flows from the second output electrode to the first output electrode; when the substrate electrode is electrically connected to the second output electrode, a current flows from the first output electrode to the second output electrode
Further, different threshold voltages can be realized by adjusting the thickness of the shielding dielectric layer, the doping concentration of the source region and the drain region and the length of the shielding gate.
Further, the channel region is adjacent to the control gate located at the lower portion of the trench, and the channel length can be reduced by reducing the width of the trench, thereby reducing the channel resistance.
Further, the substrate electrode, the first output electrode, the second output electrode, and the gate electrode of the bidirectional power device are led out to the surface of the semiconductor substrate through the wiring layer, and a metal solder ball is formed on the wiring layer. Due to the adoption of the ball-planting process, the traditional packaging routing is omitted, the parasitic inductance and the parasitic resistance of the packaging are reduced, and the packaging resistance of the bidirectional power device is reduced; because no plastic package material is used for encapsulation, the heat dissipation is easier, the power consumption is reduced, and the reliability and the safety of the bidirectional power device are improved.
Furthermore, the bidirectional power device can be composed of a plurality of cell structures, source regions of all the cell structures are electrically connected together to serve as a first output electrode, drain regions of all the cell structures are electrically connected together to serve as a second output electrode, and the current capacity of the bidirectional power device is improved by increasing the number of the cell structures.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
fig. 1 shows a schematic circuit diagram of a bidirectional power device according to an embodiment of the present invention;
fig. 2-4 show a cross-sectional view and a top view, respectively, of different sections of a bidirectional power device according to a first embodiment of the invention;
fig. 5 shows a cross-sectional view of a plurality of cell structures of a first embodiment of the present invention;
fig. 6 shows a top view of a bidirectional power device illustrating a second embodiment of the present invention;
fig. 7 shows a cross-sectional view of a bidirectional power device illustrating a third embodiment of the present invention;
fig. 8 shows a cross-sectional view of a bidirectional power device according to a fourth embodiment of the present invention;
fig. 9 shows a top view of a bidirectional power device according to a fourth embodiment of the present invention;
fig. 10 shows a pin diagram of a bidirectional power device according to a fourth embodiment of the present invention;
fig. 11a to 11i are sectional views showing different stages of a manufacturing method of a bidirectional power device according to a fifth embodiment of the present invention.
Detailed Description
Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by the same or similar reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale.
The following detailed description of the embodiments of the present invention is provided with reference to the accompanying drawings and examples.
Fig. 1 shows a schematic circuit diagram of a bidirectional power device, which is formed by one transistor and has a bidirectional conduction function. As shown in fig. 1, the bidirectional power device includes a substrate Sub and two output electrodes S1 and S2 on the substrate Sub, and two parasitic body diodes D1 and D2. When the output electrode S2 is in short circuit with the substrate Sub, and high voltage is applied to the grid G, the voltage is higher than the threshold voltage of the bidirectional power device, the bidirectional power device is conducted, and current flows from the output electrode S1 to the output electrode S2; when the output electrode S1 is in short circuit with the substrate Sub, and high voltage is applied to the grid G, the voltage is higher than the threshold voltage of the bidirectional power device, the bidirectional power device is conducted, and current flows from the output electrode S2 to the output electrode S1; when the substrate Sub is connected with zero voltage, the grid G applies low voltage, the voltage is lower than the threshold voltage, and the bidirectional power device is cut off.
First embodiment
Fig. 2 to 4 show a cross-sectional view and a top view, respectively, of a bidirectional power device according to a first embodiment of the present invention; fig. 2 is a cross-sectional view taken along line AA 'in the top view shown in fig. 4, and fig. 3 is a cross-sectional view taken along line BB' in the top view shown in fig. 4. In this embodiment, the bi-directional power device is a trench type device, which may be a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), an IGBT device, or a diode. Hereinafter, an N-type MOSFET is exemplified, however, the present invention is not limited thereto.
The bidirectional power device shown in fig. 2 only includes a vertical structure diagram of a cell structure, and in an actual product, the number of the cell structures may be one or more. Referring to fig. 2-4, the bidirectional power device includes a semiconductor layer 10, a trench 20 located in the semiconductor layer 10, a gate dielectric layer 21 located on a sidewall of the trench 20, a control gate 22 located at a lower portion of the trench 20, a shield gate 23 located at an upper portion of the trench 20, and an isolation layer 24 located between the control gate 22 and the shield gate 23.
In the present embodiment, the semiconductor layer 10 is, for example, a semiconductor substrate itself, or an epitaxial layer formed on the semiconductor substrate, or a well region implanted in the semiconductor substrate. The doping concentration of the semiconductor layer 10 is 7E 14-3E 16cm-3. The semiconductor layer 10 is, for example, a silicon substrate, an epitaxial layer formed on the silicon substrate, or a well region formed in the silicon substrate, the doping type is P-type, and the doping type of the semiconductor layer 10 is the same as that of the silicon substrate. The semiconductor layer 10 has opposite first and second surfaces.
Wherein the control gate 22 is separated from the semiconductor layer 10 by the gate dielectric layer 21.
Further, the bidirectional power device further comprises a shielding dielectric layer 25 located on the sidewall of the trench 20, and the shielding gate 23 is separated from the semiconductor layer 10 by the shielding dielectric layer 25.
In this embodiment, the gate dielectric layer 21, the isolation layer 24, and the shielding dielectric layer 25 may be made of silicon dioxide or silicon nitride or a composite structure of silicon dioxide and silicon nitride, and the materials of the three may be the same or different.
The thickness of the gate dielectric layer 21 is 200-1000 angstroms, i.e., 0.02-0.1 um, and the thickness of the shielding dielectric layer 25 is 1000-2500 angstroms, i.e., 0.1-0.25 um. The thickness of the shielding dielectric layer 25 is greater than or equal to the thickness of the gate dielectric layer 21.
The width W1 of the control gate 22 is greater than the width W2 of the shield gate 23, and the length L1 of the control gate is less than the length L2 of the shield gate 23. The length L2 of the shielding grid 23 is 0.6-1.2 um.
Further, a source region 31 and a drain region 32, which are doped with N-type dopant and extend in the longitudinal direction, are formed in the semiconductor layer 10, wherein the source region 31 and the drain region 32 can be interchanged; and forming a channel region 40 adjacent to the control gate 22 within the semiconductor layer 10.
In this embodiment, the doping type of the semiconductor layer 10 is a first doping type, the doping types of the source region 31 and the drain region 32 are a second doping type, the doping type of the channel region 40 is the first doping type or the second doping type, and the first doping type and the second doping type are opposite.
In the present embodiment, the source region 31 and the drain region 32 extend from the first surface of the semiconductor layer 10 to overlap with the control gate 22. The length K of the source region 31 and the drain region 32 extending in the semiconductor layer 10 is greater than the length L2 of the shielding gate 23 extending in the semiconductor layer 10, preferably greater than the sum L2+ L3 of the lengths of the shielding gate 23 and the isolation layer 24 extending in the semiconductor layer 10, but less than the sum L1+ L2+ L3 of the lengths of the shielding gate 23, the isolation layer 24 and the control gate 22 extending in the semiconductor layer 10, i.e., L2+ L3 < K < L1+ L2+ L3.
Since channel region 40 is adjacent to control gate 22 located in a lower portion of trench 20, the channel length, and thus the channel resistance, can be reduced by reducing the width of the trench.
Further, a first lead region 311 and a second lead region 321 are formed in the source region 31 and the drain region 32. The doping type of the first lead line region 311 is the same as the doping type of the source region 31, and the doping concentration of the first lead line region 311 is greater than the doping concentration of the source region 31. The doping type of the second lead region 321 is the same as the doping type of the drain region 32, and the doping concentration of the second lead region 321 is greater than the doping concentration of the drain region 32.
Further, a third lead region 101 is formed in the semiconductor layer 10, the third lead region 101 being close to the first surface of the semiconductor layer 10, wherein a doping type of the third lead region 101 is the same as a doping type of the semiconductor layer 10, and a doping concentration of the third lead region 101 is greater than a doping concentration of the semiconductor layer 10.
Further, a capping dielectric layer 11 is formed on the first surface of the semiconductor layer 10 and contact holes 50 penetrating the capping dielectric layer 11 are formed, the contact holes 50 including a first contact hole 51, a second contact hole 52, a third contact hole 53 and a fourth contact hole 54. The first contact hole 51 is located on the source region 31, penetrates through the cover dielectric layer 11, and extends to the source region 31, and the second contact hole is located on the drain region 32, penetrates through the cover dielectric layer 11, and extends to the drain region 32.
The third contact holes 53 are located at two sides of the trench 20 and extend to the semiconductor layer 10 through the cover dielectric layer 11.
A fourth contact hole 54 is located on the trench 20, and extends through the capping dielectric layer 11 to the control gate 22 and/or the shield gate 23 in the trench 20.
In the present embodiment, the capping dielectric layer 11 may be Undoped Silicate Glass (USG) or boron-phosphorus doped silicate glass (BPSG).
And depositing a metal layer 60 on the cover dielectric layer 11, wherein the metal layer 60 fills the first contact hole 51 to the fourth contact hole 54 to form a first contact 61 to a fourth contact 64 respectively. The first contact 61 is in contact with the source region 31 through the first contact hole 51 and the first lead region 311 to form a first output electrode S1, the second contact 61 is in contact with the drain region 32 through the second contact hole 52 and the second lead region 321 to form a second output electrode S2, and the third contact 63 is in contact with the semiconductor layer 10 through the third contact hole 53 and the third lead region 101 to form a substrate electrode Sub. As shown in fig. 3, the fourth contact 64 is in contact with the control gate 22 and/or the shield gate 23 via the fourth contact hole 54 to form a gate electrode. As shown in fig. 4, the fourth contact hole 54 includes a contact hole 54a of the control gate 22 and a contact hole 54b of the shield gate 23. In this embodiment, the control gate 22 and the shield gate 23 are connected together.
In the present embodiment, the material of the metal layer 60 may be titanium and titanium nitride, aluminum copper, aluminum silicon copper, or aluminum silicon.
In fig. 2, a cell includes only three trenches, a source region and a drain region, and in an actual product, the number of the source region 31 and the drain region 32 is more than one. Taking the example shown in fig. 2, the three trench structures are a first trench 20a, a second trench 20b and a third trench 20c, respectively. The first contact 61 leads the source region 31 to the surface of the semiconductor layer 10 to form a first output electrode S1, the second contact 62 leads the drain region 32 to the surface of the semiconductor layer 10 to form a second output electrode S2, the third contact 63 leads the semiconductor layer 10 to form a substrate electrode Sub, and the fourth contact 64 leads the control gate 22 and the shielding gate 23 in the trench 20 to the surface of the semiconductor layer 10 to form a gate electrode G, wherein the control gate 22 and the shielding gate 23 are electrically connected together. The first trench 20a and the third trench 20c are symmetrically disposed outside the source region 31 and the drain region 32. The first output electrode S1 and the second output electrode S2 are formed by leading the source region 31 and the drain region 32 to the surface of the semiconductor layer 10, respectively, and may be interchanged with each other.
When the voltage applied to the control gate 22 is greater than the threshold voltage, the bidirectional power device is turned on, a current flows through the channel region in the second trench 20b, and selection of the direction of the current is achieved by selecting one of the output electrodes to be connected to the substrate electrode, for example, when the first output electrode S1 is connected to the substrate electrode Sub, a current flows from the second output electrode S2 to the first output electrode S1; when the second output electrode S2 is connected to the substrate electrode Sub, a current flows from the first output electrode S1 to the second output electrode S2.
When the voltage applied to the control gate 22 is less than the threshold voltage, the bidirectional power device is turned off, and since the control gate 22 and the shielding gate 23 are electrically connected together, the voltage applied to the shielding gate 23 is a low voltage, and a high voltage is applied to the first output electrode S1 and the second output electrode S2, a voltage difference is formed between the source region 31, the drain region 32, and the shielding gate 23. The shielding gates 23 in the first trench 20a and the third trench 20c induce charges in the source region 31 and the source region 32 through the shielding dielectric layer 25, and finally the source region and the drain region can be completely depleted by adjusting the thickness and material of the shielding dielectric layer 25 and the impurity concentration of the source region 31 and the drain region 32, so that the purpose of improving the withstand voltage of the device is achieved. Meanwhile, the impurity concentration of the source region 31 and the drain region 32 is increased, so that the resistance of the device is greatly reduced.
Fig. 5 is a schematic diagram showing only a two-cell structure, in which a plurality of first contacts 61 are connected together to form a first output electrode S1, and a plurality of second contacts 62 are connected together to form a second output electrode S2, so as to improve the current capability of the device. Alternatively, for other types of bidirectional power devices, the current capability of the device may be increased by increasing the number of cells, i.e., selecting two or more cell structures to be connected in parallel.
Second embodiment
This embodiment employs substantially the same technical solution as the first embodiment, except that in the first embodiment, the control gate 22 and the shield gate 23 are connected together, whereas in this embodiment, the shield gate 23 and the semiconductor layer 10 are connected together, and as shown in fig. 6, the contact hole 54b of the shield gate 23 is connected to the contact hole 53 of the substrate electrode, so that the shield gate 23 and the substrate electrode Sub are electrically connected together.
In this embodiment, the rest of the bidirectional power device is basically the same as that in the first embodiment, and the detailed structure is not described again.
In the first embodiment, the control gate 22 and the shield gate 23 are connected together, and the shield gate 23 overlaps the source region 31 and the drain region 32, so that parasitic capacitance exists. When the voltages of the control gate 22 and the shielding gate 23 are increased, the parasitic capacitance is charged, and the bidirectional power device is conducted; when the voltages of the control gate 22 and the shield gate 23 are lowered, the parasitic capacitance discharges and the bidirectional power device turns off. When the bidirectional power device is switched on and off at a high speed, the charging and discharging time of the parasitic capacitor can reduce the switching frequency, and the parasitic capacitor is charged and discharged to generate extra power consumption.
In the second embodiment, the shielding grid 23 is connected with the semiconductor layer 10, and the voltage of the shielding grid 23 is fixed in the switching process of the device, so that the charging and discharging of parasitic capacitance caused by the voltage change of the shielding grid 23 can be avoided, the switching frequency of the bidirectional power device can be improved, and the power consumption can be reduced. The bidirectional power device can be used as a high-speed switch in certain application occasions requiring that the bidirectional power device not only has the lowest resistance as possible, but also has small parasitic capacitance.
Third embodiment
This embodiment employs substantially the same technical solution as the first embodiment, except that in the first embodiment, a third contact 63 is formed on the first surface of the semiconductor layer 10, and is in contact with the semiconductor layer 10 through a third contact hole 53 and a third lead region 101 to form a substrate electrode Sub. In this embodiment, the third contact 63 is formed on the second surface of the semiconductor layer 10, as shown in fig. 7. Specifically, the bidirectional power device is formed on the substrate 1 with higher doping concentration, and then the metal layer 60 is evaporated on the back surface of the substrate 1 to form the third contact 63.
In the first embodiment, the gate electrode, the substrate electrode, the first output electrode, and the second output electrode of the bidirectional power device are all led out from the first surface of the semiconductor layer 10, and are suitable for Chip Scale Packaging (CSP).
In the third embodiment, the substrate electrode of the bidirectional power device is led out from the second surface of the semiconductor layer 10, which can not only accommodate the conventional device packaging form (such as SOP8 and DIP8), but also increase the heat dissipation capability of the bidirectional power device.
In this embodiment, the rest of the bidirectional power device is basically the same as that in the first embodiment, and the detailed structure is not described again.
Fourth embodiment
This embodiment adopts substantially the same technical solution as the first embodiment, and compared with the first embodiment, this embodiment further includes a wiring layer 70 (not shown in the figure) and a plurality of metal solder balls 80 on the wiring layer 70.
Due to the small pitch of the trenches 20, the gate electrodes drawn out of the trench structure are relatively narrow, resulting in a large parasitic resistance. In order to reduce parasitic resistance, a wiring layer 70 is added above the power device provided in the first embodiment.
As shown in fig. 8 and 9, a wiring layer 70 (not shown in the drawings) is located on the surface of the power device for leading out the first output electrode S1, the second output electrode S2, the substrate electrode Sub, and the gate electrode G formed by the first contact 61, the second contact 62, the third contact 63, and the fourth contact 64 to the surface of the power device.
The first contact 61, the second contact 62, the third contact 63 and the fourth contact 64 are located in the first metal layer M1, the wiring layer 70 is located in the second metal layer M2, and the first metal layer M1 and the second metal layer M2 are isolated by the cover dielectric layer 11. The wiring layer 70 is electrically connected to the first contact 61, the second contact 62, the third contact 63, and the fourth contact 64 through a plurality of conductive vias 90. The wiring layer 70 includes a first wiring 71, a second wiring 72, a third wiring 73, and a fourth wiring 74 (not shown in the figure), wherein the first wiring 71 is electrically connected to the first contact 61; the second wiring 72 is electrically connected to the second contact 62; the third wiring 73 is electrically connected to the third contact 63; the fourth wiring 74 is electrically connected to the fourth contact 64.
In the present embodiment, the wiring layer 70 employs a wider metal line lead-out to reduce the parasitic resistance of the metal layer.
And a plurality of metal solder balls 80 on the wiring layer 70 and electrically connected to the first output electrode S1, the second output electrode S2, the substrate electrode Sub, and the gate electrode G through the wiring layer 70. The metal solder ball 80 includes a metal solder ball 81 electrically connected to the first output electrode S1, a metal solder ball 82 electrically connected to the second output electrode S2, a metal solder ball 83 electrically connected to the substrate electrode Sub, and a metal solder ball 84 electrically connected to the gate electrode G (not shown in the figure).
In this embodiment, a plurality of metal solder balls 80 are formed on the wiring layer by a ball-mounting process, thereby completing the chip scale package. The metal solder ball 81 is a pad lead for electrically connecting the first output electrode S1 with the outside, the metal solder ball 82 is a pad lead for electrically connecting the second output electrode S2 with the outside, the metal solder ball 83 is a pad lead for electrically connecting the substrate electrode with the outside, and the metal solder ball 84 is a pad lead for electrically connecting the gate electrode with the outside.
In a preferred embodiment, a plated metal layer M3 is further formed between the metal solder ball 80 and the wiring layer 70, so that the bonding between the metal solder ball 80 and the wiring layer 70 is stronger.
Since the first output electrode S1 and the second output electrode S2 need to pass an excessive current, a relatively large number of metal solder balls 81 and 82 are distributed, as shown in fig. 10, in which a plurality of metal solder balls 81 are connected in parallel and a plurality of metal solder balls 82 are connected in parallel, which can increase the current distribution between the power device and an external system.
The fourth embodiment adopts the ball-planting process, so that the traditional packaging routing is omitted, the parasitic inductance and the parasitic resistance of the packaging are reduced, and the packaging resistance of the power device is reduced; because no plastic packaging material is used for packaging, the heat dissipation is easier, the power consumption is reduced, and the reliability and the safety of the power device are improved.
Fifth embodiment
Fig. 11a to 11i are cross-sectional views illustrating different stages of a manufacturing method of a bidirectional power device according to a fifth embodiment of the present invention.
As shown in fig. 11a, a basic structure of a manufacturing method of a bidirectional power device according to a fifth embodiment of the present invention is shown, and the forming step of the structure includes: depositing a barrier layer 12 on the surface of the semiconductor layer 10; an etching window is formed by photolithography, and the barrier layer 12 and the semiconductor layer 10 are etched through the etching window to form the trench 20. The depth of the groove 20 reaches 1.2-2.0 um.
In the present embodiment, the semiconductor layer 10 is, for example, a semiconductor substrate itself, or an epitaxial layer formed on the semiconductor substrate, or a well region implanted in the semiconductor substrate. The doping concentration of the semiconductor layer 10 is 7E 14-3E 16cm-3. Barrier layer12 may be silicon dioxide, silicon nitride or a composite structure of silicon dioxide and silicon nitride. The semiconductor layer 10 is, for example, a silicon substrate, an epitaxial layer formed on the silicon substrate, or a well region formed in the silicon substrate, the doping type is P-type, and the doping type of the semiconductor layer 10 is the same as that of the silicon substrate.
As shown in fig. 11b, removing the barrier layer 12 on the surface of the semiconductor layer 10, and performing sacrificial oxidation on the trench 20 to repair the surface of the trench 20, wherein the thickness of the sacrificial oxidation is about 300 to 1000 angstroms; then, first conductive type ion implantation is performed to form a channel region 40.
In this embodiment, the first conductivity type is P-type, and the implanted first conductivity type ions are boron (B) or Boron Fluoride (BF)2) (ii) a The injection dosage is 5E 11-2E 13ions/cm2。
As shown in fig. 11c, growing a gate dielectric layer 21 on the surface of the trench 20, and then depositing polysilicon on the surface of the gate dielectric layer 21; after the chemical mechanical polishing, the polysilicon on the surface of the semiconductor layer 10 is removed, and the height of the polysilicon in the trench 20 is flush with the surface of the semiconductor layer 10.
In the present embodiment, the gate dielectric layer 21 is made of silicon dioxide or silicon nitride, and has a thickness of 200 to 1000 angstroms. The thickness of the deposited polysilicon is 5000-10000 angstrom.
As shown in fig. 11d, an etch-back window is formed by photolithography, a part of the polysilicon in the trench 20 is etched according to the etch-back window, the remaining polysilicon forms a control gate 22, and the etch-back depth is 0.6-1.2 um; a masking dielectric layer 25 is then grown or deposited over the control gate 22 to form an isolation layer 24 and the remaining surface in the trench 20 and the surface of the semiconductor layer 10. The material of the shielding dielectric layer 25 and the isolation layer 24 may be silicon dioxide or silicon nitride or a composite structure of silicon dioxide and silicon nitride. The thickness of the shielding dielectric layer 25 and the isolation layer 24 is 1000-2500 angstroms, namely 0.1-0.25 um.
As shown in fig. 11e, polysilicon is deposited on the surface of the shield dielectric layer 25 in the trench 20; removing the polysilicon on the surface after CMP, wherein the polysilicon in the trench 20 is flush with the shielding dielectric layer 25 on the surface of the semiconductor layer 10; the polysilicon is etched back to form the shield gate 23. The distance between the shielding grid 23 and the surface of the semiconductor layer is 1000-1500 angstroms, namely 0.1-0.15 um; the masking dielectric layer 25 on the surface of the semiconductor layer 10 is then removed, leaving a portion of the masking dielectric layer 25 as a barrier for subsequent implantation. The thickness of the remaining shielding dielectric layer is 200-500 angstroms.
As shown in fig. 11f, an implantation window is formed by photolithography; and performing second conductive type ion implantation according to the implantation window, and performing junction pushing at the temperature of 1000-1150 ℃ to form a source region 31 and a drain region 32.
In the embodiment, the second conductivity type is N-type, the implanted second conductivity type ions are phosphorus (P), and the implantation dose is 1E 13-6E 13ions/cm2。
As shown in fig. 11g, a second conductive type ion implantation is performed in the source region 31 and the drain region 32, and a first lead region 311 and a second lead region 321 are formed through a rapid annealing or a junction push at a temperature of 800 to 1000 ℃. The doping concentration of the first lead region 311 is greater than that of the source region 31; the doping concentration of the second lead region 321 is greater than the doping concentration of the drain region 32.
In the embodiment, the second conductivity type is N-type, the implanted second conductivity type ions are phosphorus (P) or arsenic (As), and the implantation dose is 1E 15-1E 16ions/cm2。
As shown in fig. 11h, first conductive type ion implantation is performed in the semiconductor layer 10, forming a third lead region 101. The doping concentration of the third lead region 101 is greater than the doping concentration of the semiconductor layer 10. Depositing Undoped Silicate Glass (USG) and boron-phosphorus doped silicate glass (BPSG) on the surface of the semiconductor layer 10 to form a covering dielectric layer 11; the capping dielectric layer 11 is etched to form contact holes 50 (not shown) including contact holes 51 and 52 contacting the source and drain regions 31 and 32, contact holes 53 contacting the semiconductor layer 10, and contact holes 54 (not shown) contacting the control gate 22 and/or the shield gate 23 in the trench 20. Wherein the first contact hole 51 contacts the source region 31 via the first lead region to form a first output electrode S1; the second contact hole 52 contacts the drain region 32 via a second lead region to form a second output electrode S2. The contact hole 50 extends to 0.1-0.5 um below the surface of the semiconductor layer 10.
In this embodiment, the first conductivity type is P-type, and the implanted first conductivity type ions are boron (B) or Boron Fluoride (BF)2) (ii) a The injection dosage is 5E 14-8E 15ions/cm2。
As shown in fig. 11i, a metal layer 60 is deposited in the contact hole 50 to form a surface electrode, i.e. a first contact 61, a second contact 62, a third contact 63 and a fourth contact 64 (not shown).
In the present embodiment, the first contact 61 is the first output electrode S1, the second contact 62 is the second output electrode S2, the third contact 63 is the substrate electrode Sub, and the fourth contact 64 is the gate electrode G. The fourth contact 64 is electrically connected to the control gate 22 and the shield gate 23, respectively, and the control gate 22 and the shield gate 23 are connected together through the fourth contact 64.
Sixth embodiment
This embodiment adopts substantially the same technical solution as the fifth embodiment, except that the third contact 63 is formed by a different step, the substrate 1 is formed on the second surface of the semiconductor layer 10, then the metal layer 60 is evaporated on the back surface of the substrate 1 to form the third contact 63, and the third contact 63 forms the substrate electrode. For example, the material of the metal layer 60 in this step includes titanium nickel silver or titanium nickel gold, etc. of a conventional process.
In this embodiment, the remaining steps of the manufacturing method of the bidirectional power device are substantially the same as those in the fifth embodiment, and the detailed structure is not described again.
Seventh embodiment
The present embodiment adopts substantially the same technical solution as the fifth embodiment, and compared with the fifth embodiment, the present embodiment further includes forming a wiring layer 70 on the surface of the power device, and leading out the first output electrode S1, the second output electrode S2, the substrate electrode Sub and the gate electrode G formed by the first contact 61, the second contact 62, the third contact 63 and the fourth contact 64 to the surface of the power device; and forming a plurality of metal solder balls 80 on the wiring layer, the plurality of metal solder balls 80 being electrically connected to the substrate electrode Sub, the first output electrode S1, the second output electrode S2, and the gate electrode G through the wiring layer 70.
The first contact 61, the second contact 62 and the third contact 63 are located in the first metal layer M1, the wiring layer 70 is located in the second metal layer M2, the first metal layer M1 and the second metal layer M2 are isolated by the cover dielectric layer 11, and the wiring layer 70 is electrically connected with the first contact 61, the second contact 62 and the third contact 63 through the plurality of conductive holes 90.
In the present embodiment, the wiring layer 70 employs a wider metal line lead-out to reduce the parasitic resistance of the metal layer. And forming a plurality of metal solder balls 80 on the wiring layer by adopting a ball-planting process to finish chip-scale packaging.
In the above embodiment, the doping type of the semiconductor layer 10 is a first doping type, the doping types of the source region 31 and the drain region 32 are a second doping type, the first doping type is P-type doping, and the second doping type is N-type doping, so as to form an N-type bidirectional power device.
In an alternative embodiment, the doping type of the semiconductor layer 10 is exchanged with the doping type of the source region 31 and the drain region 32, i.e., the first doping type is N-type doping and the second doping type is P-type doping, so as to form a P-type bidirectional power device.
In accordance with the embodiments of the present invention as set forth above, these embodiments are not exhaustive and do not limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to best utilize the invention and its various embodiments with various modifications as are suited to the particular use contemplated. The present invention is limited only by the claims and their full scope and equivalents.
Claims (24)
1. A bi-directional power device, comprising:
a semiconductor layer;
a trench in the semiconductor layer;
the gate dielectric layer is positioned on the side wall of the groove;
a control gate located at a lower portion of the trench;
the shielding gate is positioned at the upper part of the groove; and
an isolation layer between the control gate and the shield gate,
the control gate and the semiconductor layer are separated by the gate dielectric layer.
2. The bi-directional power device of claim 1, further comprising: source and drain regions in the semiconductor layer and adjacent to the shield gate, and a channel region in the semiconductor layer and adjacent to the control gate.
3. The bi-directional power device of claim 2, wherein the source and drain regions extend from the first surface of the semiconductor layer to overlap the control gate.
4. The bi-directional power device of claim 2, wherein the semiconductor layer has a first doping type, the source and drain regions have a second doping type, the channel region has a first doping type or a second doping type, and the first doping type and the second doping type are opposite.
5. The bi-directional power device of claim 1, further comprising: and the shielding grid is separated from the semiconductor layer by the shielding dielectric layer.
6. The bidirectional power device of claim 5, wherein the thickness of the shielding dielectric layer is 0.1-0.25 um.
7. The bidirectional power device of claim 1, wherein the length of the shielding gate is 0.6-1.2 um.
8. The bi-directional power device of claim 5, wherein the thickness of the shielding dielectric layer is greater than or equal to the thickness of the gate dielectric layer.
9. The bi-directional power device of claim 1, wherein a width of the control gate is greater than a width of the shield gate.
10. The bi-directional power device of claim 2, wherein the lengths of the source and drain regions are greater than the sum of the lengths of the shield gate and the isolation layer and less than the sum of the lengths of the shield gate, the isolation layer and the control gate.
11. The bi-directional power device of claim 1, wherein the semiconductor layer is selected from one of the semiconductor substrate itself, an epitaxial layer formed on the semiconductor substrate, or a well region implanted in the semiconductor substrate.
12. The bi-directional power device of claim 2, further comprising:
a first contact contacting the source region to form a first output electrode;
a second contact contacting the drain region to form a second output electrode;
a third contact in contact with the semiconductor layer to form a substrate electrode;
a fourth contact contacting the control gate and/or shield gate to form a gate electrode.
13. The bi-directional power device of claim 12, further comprising:
the first lead area is positioned in the source area, wherein the doping concentration of the first lead area is greater than that of the source area;
a cover dielectric layer located on the first surface of the semiconductor layer;
the first contact hole penetrates through the covering dielectric layer and extends to the source region;
the first contact is in contact with the source region through the first contact hole and the first lead region.
14. The bi-directional power device of claim 13, further comprising:
the second lead region is positioned in the drain region, wherein the doping concentration of the second lead region is greater than that of the drain region;
the second contact hole penetrates through the covering dielectric layer and extends to the drain region;
the second contact is in contact with the drain region through a second contact hole and a second lead region.
15. The bi-directional power device of claim 14, further comprising:
a third lead region located within the semiconductor layer and proximate to the first surface of the semiconductor layer, wherein a doping concentration of the third lead region is greater than a doping concentration of the semiconductor layer;
the third contact hole penetrates through the covering dielectric layer and extends to the semiconductor layer;
the third contact is in contact with the semiconductor layer through a third contact hole and a third lead region.
16. The bi-directional power device of claim 14, further comprising:
and the fourth contact hole penetrates through the covering dielectric layer and extends to the control gate and/or the shielding gate.
17. The bi-directional power device of claim 14, wherein the third contact is located on the second surface of the semiconductor layer.
18. The bi-directional power device of claim 12, further comprising:
a wiring layer including first to fourth wirings electrically connected to the first output electrode, the second output electrode, the substrate electrode, and the gate electrode through a plurality of conductive holes, respectively.
19. The bi-directional power device of claim 18, further comprising:
and the metal welding balls are positioned on the wiring layer and are electrically connected with the first output electrode, the second output electrode, the substrate electrode and the gate electrode through the wiring layer.
20. The bi-directional power device of claim 1, wherein the shield gate is electrically connected to the control gate.
21. The bi-directional power device of claim 1, wherein the shield grid is electrically connected to the semiconductor layer.
22. The bi-directional power device of claim 12, wherein the substrate electrode is electrically connected to one of the first output electrode and the second output electrode to enable bi-directional selection of a current direction when the bi-directional power device is on.
23. The bidirectional power device of claim 22, wherein when the substrate electrode is electrically connected to the first output electrode, current flows from the second output electrode to the first output electrode;
when the substrate electrode is electrically connected to the second output electrode, a current flows from the first output electrode to the second output electrode.
24. A bidirectional power device comprising a plurality of cell structures, the cell structures being the bidirectional power device of any one of claims 1-23;
the source regions in the plurality of cell structures are electrically connected together and the drain regions in the plurality of cell structures are electrically connected together.
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| CN110137243A (en) * | 2019-04-03 | 2019-08-16 | 杭州士兰微电子股份有限公司 | Bilateral power devices and its manufacturing method |
| CN110137243B (en) * | 2019-04-03 | 2024-03-29 | 杭州士兰微电子股份有限公司 | Bidirectional power device and manufacturing method thereof |
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