CN113192884B - Bidirectional power device and manufacturing method thereof - Google Patents
Bidirectional power device and manufacturing method thereof Download PDFInfo
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- CN113192884B CN113192884B CN202011163950.8A CN202011163950A CN113192884B CN 113192884 B CN113192884 B CN 113192884B CN 202011163950 A CN202011163950 A CN 202011163950A CN 113192884 B CN113192884 B CN 113192884B
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Abstract
The application discloses two-way power device and manufacturing method thereof, the two-way power device includes: a semiconductor layer; a first doped region in the semiconductor layer; the plurality of grooves of the first groove area are positioned in the first doping area and divide the first doping area into a first sub-doping area and a second sub-doping area which are alternated; the gate dielectric layer, the control gate, the first shielding dielectric layer, the first shielding gate, the second shielding dielectric layer and the second shielding gate are positioned in the grooves, wherein the control gate and the first shielding gate are separated by the first shielding dielectric layer, the second shielding gate and the first shielding gate are separated by the second shielding dielectric layer, and the thicknesses of the second shielding dielectric layer and the gate dielectric layer are smaller than that of the first shielding dielectric layer. According to the bidirectional power device, the thicknesses of the second shielding dielectric layer and the gate dielectric layer are smaller than that of the first shielding dielectric layer, so that different electric fields can be formed by applying different voltages to the gate electrode.
Description
Technical Field
The present disclosure relates to the field of semiconductor manufacturing technologies, and more particularly, to a bidirectional power device and a manufacturing method thereof.
Background
Bidirectional power devices are widely used in charging devices having a secondary charging function. Taking the lithium battery charging and discharging device as an example, when the lithium battery charging and discharging device continuously supplies power to the terminal device to a certain extent, the lithium battery charging and discharging device needs to be prevented from over-discharging so as to prevent the terminal device from stopping running, and the lithium battery needs to be charged in time. In the process of charging the lithium battery, the lithium battery also needs to supply power to the terminal equipment, and meanwhile, the lithium battery is prevented from being overcharged. Therefore, in order to manage and control the charge/discharge state of the lithium battery, a charge/discharge protection circuit having a bidirectional switch for controlling current conduction is generally used.
As shown in fig. 1, in the first charge/discharge protection circuit, two drain-connected single planar gate NMOS transistors M1 and M2 were used as bidirectional switches. When charging is performed, a high voltage is applied to the gate G1 of M1, so that M1 is turned on, and a low voltage is applied to the gate G2 of M2, so that M2 is turned off, and at this time, current flows from the source S2 of M2 to the drain of M2 through the parasitic diode D2 of M2, and then flows from the drain of M1 to the source S1 of M1. When discharging, a low voltage is applied to gate G1 of M1, causing M1 to turn off, and a high voltage is applied to gate G2 of M2, causing M2 to turn on. At this time, the current flows from the source S1 of M1 to the drain of M1 through the parasitic diode D1 of M1, and then flows from the drain of M2 to the source S2 of M2. However, the MOS process using the planar gate structure requires a sufficient area to meet the requirement of higher withstand voltage, and the device has low on-state efficiency and large power consumption.
Therefore, it is desirable to further optimize the structure of the bidirectional power device, so that the bidirectional power device has smaller area and higher performance.
Disclosure of Invention
In view of the above problems, an object of the present invention is to provide a bidirectional power device and a method for manufacturing the same, in which a trench is used to separate a first doped region into a first type sub-doped region and a second type sub-doped region, which are alternated, to form a source region and a drain region of the bidirectional power device, thereby reducing the area of the device.
According to a first aspect of embodiments of the present invention, there is provided a bidirectional power device, including: a semiconductor layer; a first doped region in the semiconductor layer; the plurality of grooves of the first groove area are positioned in the first doping area and divide the first doping area into a first sub-doping area and a second sub-doping area which are alternated; the gate dielectric layer covers the lower side walls of the plurality of grooves of the first groove area; the control gate is positioned at the lower parts of the plurality of trenches of the first trench region and is in contact with the gate dielectric layer; the first shielding dielectric layer covers the side walls of the middle parts of the plurality of grooves of the first groove region and is positioned on the surface of the control gate; the first shielding grid is positioned in the middle of the plurality of grooves of the first groove area and is in contact with the first shielding medium layer; the second shielding dielectric layer covers the upper side walls of the plurality of grooves of the first groove region and is positioned on the surface of the first shielding grid; and the second shielding grid is positioned at the upper parts of the plurality of grooves of the first groove region and is in contact with the second shielding medium layer, wherein the control grid and the first shielding grid are separated by the first shielding medium layer, and the second shielding grid and the first shielding grid are separated by the second shielding medium layer.
Optionally, the thicknesses of the second shielding dielectric layer and the gate dielectric layer are both smaller than the thickness of the first shielding dielectric layer.
Optionally, in a case where one of the first type sub-doping region and the second type sub-doping region serves as a source region, the other of the first type sub-doping region and the second type sub-doping region serves as a drain region, and the source region and the drain region may be interchanged.
Optionally, the semiconductor device further includes a trench of a second trench region, located in the semiconductor layer and separated from the first doped region; the gate dielectric layer is also positioned on the side wall of the groove of the second groove region, and the control gate is also positioned in the groove of the second groove region and is in contact with the gate dielectric layer; the trench of the first trench region is communicated with the trench of the second trench region, and the control gate in the trench of the first trench region is connected with the control gate in the trench of the second trench region.
Optionally, the semiconductor device further includes a trench of a third trench region, located in the semiconductor layer and separated from the first doped region; the gate dielectric layer also covers the lower side wall of the groove of the third groove region, the control gate is also positioned at the lower part of the groove of the third groove region and is contacted with the gate dielectric layer, the first shielding dielectric layer also covers the upper side wall of the groove of the third groove region and is positioned on the surface of the control gate, the first shielding gate is also positioned at the upper part of the groove of the third groove region and is contacted with the first shielding dielectric layer, and the first shielding dielectric layer separates the control gate from the first shielding gate; the trench of the first trench region is communicated with the trench of the third trench region, the control gate in the trench of the first trench region is connected with the control gate in the trench of the third trench region, and the first shielding gate in the trench of the first trench region is connected with the first shielding gate in the trench of the third trench region.
Optionally, a channel region is further included in the semiconductor layer and adjacent to the control gate.
Optionally, the method further comprises: the first contact region is positioned in the first-type sub-doping region; the second contact region is positioned in the second type sub-doping region; and a third contact region in the semiconductor layer.
Optionally, the method further comprises: the covering dielectric layer is positioned on the surface of the semiconductor layer; and the substrate electrode, the first contact electrode, the second contact electrode, the first gate electrode, the second gate electrode and the third gate electrode penetrate through the covering dielectric layer, the substrate electrode is connected with the third contact area, the first contact electrode is connected with the first contact area, the second contact electrode is connected with the second contact area, the first gate electrode is connected with the control grid, the second gate electrode is connected with the first shielding grid, and the third gate electrode is connected with the second shielding grid.
Optionally, the first gate electrode, the second gate electrode and the third gate electrode are electrically isolated from each other to receive different control voltages.
Optionally, the first gate electrode, the second gate electrode and the third gate electrode are connected to each other to receive the same control voltage.
Optionally, one of the second gate electrode and the third gate electrode is connected to the first gate electrode to receive the same control voltage, and the other is electrically isolated from the first gate electrode to receive a different control voltage.
Optionally, the second gate electrode and the third gate electrode are connected to receive the same control voltage and are electrically isolated from the first gate electrode to receive different control voltages.
Optionally, the thickness range of the gate dielectric layer includes
Optionally, the depth of the plurality of trenches in the first trench region, the second trench region, and the third trench region ranges from 0.1 μm to 50 μm.
Optionally, the distance from the surface of the control gate in the first trench region to the surface of the semiconductor layer is 0.1-49 μm.
Optionally, the thickness range of the first shielding dielectric layer on the control gate surface includes
Optionally, the thickness range of the first shielding dielectric layer covering the middle sidewalls of the plurality of trenches of the first trench region includes
Optionally, the thickness range of the second shielding dielectric layer includes
Optionally, when the bidirectional power device is turned off, the shield gate depletes charges in the first sub-doped region and the second sub-doped region through the shield dielectric layer, so as to improve a withstand voltage characteristic of the bidirectional power device.
According to a second aspect of the embodiments of the present invention, there is provided a method for manufacturing a bidirectional power device, including: forming a first doped region in the semiconductor layer; forming a plurality of grooves in a first groove region, wherein the grooves of the first groove region are positioned in the first doping region and divide the first doping region into a first sub-doping region and a second sub-doping region which are alternated; forming a gate dielectric layer covering the lower side walls of the plurality of grooves of the first groove area; forming a control gate in contact with the gate dielectric layer at the lower part of the plurality of trenches in the first trench region; forming a first shielding dielectric layer covering the middle side walls of the plurality of trenches of the first trench region and the surface of the control gate; forming a first shielding grid in contact with the first shielding dielectric layer in the middle of the plurality of trenches in the first trench region; forming a second shielding dielectric layer covering the upper side walls of the plurality of trenches of the first trench region and the surface of the first shielding gate; and forming a second shielding grid in contact with the second shielding medium layer on the upper parts of the plurality of trenches in the first trench region, wherein the control grid and the first shielding grid are separated by the first shielding medium layer, and the second shielding grid and the first shielding grid are separated by the second shielding medium layer.
Optionally, the thicknesses of the second shielding dielectric layer and the gate dielectric layer are both smaller than the thickness of the first shielding dielectric layer.
Optionally, in a case where one of the first type sub-doping region and the second type sub-doping region serves as a source region, the other of the first type sub-doping region and the second type sub-doping region serves as a drain region, and the source region and the drain region may be interchanged.
Optionally, forming a trench in a second trench region, where the trench in the second trench region is located in the semiconductor layer and is separated from the first doped region; the gate dielectric layer is further formed on the side wall of the groove of the second groove region, and the control gate is further formed in the groove of the second groove region and is in contact with the gate dielectric layer; the trench of the first trench region is communicated with the trench of the second trench region, and the control gate in the trench of the first trench region is connected with the control gate in the trench of the second trench region.
Optionally, forming a trench in a third trench region, the trench of the third trench region being located in the semiconductor layer and being separated from the first doped region; the gate dielectric layer is further formed on the side wall of the lower portion of the groove of the third groove region, the control gate is further formed on the lower portion of the groove of the third groove region and is in contact with the gate dielectric layer, the first shielding dielectric layer is further formed on the side wall of the upper portion of the groove of the third groove region and is located on the surface of the control gate, the first shielding gate is further formed on the upper portion of the groove of the third groove region and is in contact with the first shielding dielectric layer, and the control gate and the first shielding gate are separated by the first shielding dielectric layer; the trench of the first trench region is communicated with the trench of the third trench region, the control gate in the trench of the first trench region is connected with the control gate in the trench of the third trench region, and the first shielding gate in the trench of the first trench region is connected with the first shielding gate in the trench of the third trench region.
Optionally, forming a channel region in the semiconductor layer and adjacent to the control gate is further included.
Optionally, the method further comprises: forming a first contact region in the first type doped region; forming a second contact region in the second type sub-doping region; and forming a third contact region in the semiconductor layer.
Optionally, the method further comprises: forming a covering dielectric layer on the surface of the semiconductor layer; and forming a substrate electrode, a first contact electrode, a second contact electrode, a first gate electrode, a second gate electrode and a third gate electrode which penetrate through the covering dielectric layer, wherein the substrate electrode is connected with the third contact area, the first contact electrode is connected with the first contact area, the second contact electrode is connected with the second contact area, the first gate electrode is connected with the control grid, the second gate electrode is connected with the first shielding grid, and the third gate electrode is connected with the second shielding grid.
Optionally, the first gate electrode, the second gate electrode and the third gate electrode are electrically isolated from each other to receive different control voltages.
Optionally, the first gate electrode, the second gate electrode and the third gate electrode are connected to each other to receive the same control voltage.
Optionally, one of the second gate electrode and the third gate electrode is connected to the first gate electrode to receive the same control voltage, and the other is electrically isolated from the first gate electrode to receive a different control voltage.
Optionally, the second gate electrode and the third gate electrode are connected to receive the same control voltage and the first gate electrode is electrically isolated to receive different control voltages.
Optionally, the gate dielectric layer is thickThe range of degrees includes
Optionally, the depth of the plurality of trenches in the first trench region, the second trench region and the third trench region ranges from 0.1 μm to 50 μm.
Optionally, the distance from the surface of the control gate in the first trench region to the surface of the semiconductor layer is 0.1-49 μm.
Optionally, the thickness range of the first shielding dielectric layer on the control gate surface includes
Optionally, the thickness range of the first shielding dielectric layer covering the middle sidewalls of the plurality of trenches of the first trench region includes
Optionally, the thickness range of the second shielding dielectric layer includes
Optionally, when the bidirectional power device is turned off, the shield gate depletes charges in the first sub-doped region and the second sub-doped region through the shield dielectric layer, so as to improve a withstand voltage characteristic of the bidirectional power device.
According to the bidirectional power device and the manufacturing method thereof provided by the embodiment of the invention, the first doped region is formed in the epitaxial layer, the first doped region is divided into the first sub-doped region and the second sub-doped region which are alternated by the groove, and the first contact region and the second contact region are respectively formed in the first sub-doped region and the second sub-doped region, so that the two doped regions of the bidirectional power device are formed, and the two doped regions are the source region and the drain region, so that the area of the device is reduced. The thickness of the second shielding dielectric layer and the thickness of the gate dielectric layer are smaller than that of the first shielding dielectric layer, so that different electric fields can be formed by applying different voltages to the gate electrode.
More specifically, the first doped region is typically deeper, and higher diffusion temperatures and longer diffusion times are required to achieve deeper junction depths. Therefore, the first doping region is formed in the first step of the manufacturing method according to the requirements of product parameters, and the requirements of product structures and parameters can be realized by selecting proper doping conditions. Under the condition that the junction depth requirement of the first doped region is shallow, the first doped region can be formed without the first step of the manufacturing method, and the first doped region can also be annealed in the annealing process of other doped regions in the subsequent manufacturing method, so that the requirements of the junction depth and parameters required by the device structure are met.
Furthermore, by forming the control gates and the shielding gates in the plurality of grooves, when the bidirectional power device is cut off, the shielding gates deplete charges in the source region and the drain region through the shielding dielectric layer, and the voltage resistance of the device is improved; in the case of conduction of the bidirectional power device, the source region and/or the drain region and the channel region provide a low-impedance conduction path.
Furthermore, the control gates and the shielding gates in the device structure are separated from each other, the control gates in the first trench area, the second trench area and the third trench area are connected and led out through electrodes, the first shielding gates in the first trench area and the third trench area are connected and led out through electrodes, and the second shielding gates in the first trench area are connected and led out through electrodes. In some other embodiments, the first shielding grid and the second shielding grid can be connected through the extraction electrode, the first shielding grid and the second shielding grid are isolated from the control grid, electric fields in the upper section and the middle section are controlled at the same time, the first shielding grid and the second shielding grid are controlled at the same time, the control of a coupling electric field in a shielding grid region can be realized by applying different voltages to the shielding grids than the control grid, and the parameter level of the device is improved. In addition, one of the first shield gate and the second shield gate may be connected to the control gate through the extraction electrode, and the other may be electrically isolated from the control gate.
Further, when the bidirectional power device is conducted, the substrate electrode connected with the substrate is in short circuit with one of the first contact electrode and the second contact electrode, and bidirectional selection of the current direction is achieved. Under the condition that the substrate electrode is in short circuit with the first contact electrode, current flows to the first contact electrode from the second contact electrode through the second type sub-doping area, the channel area and the first type sub-doping area in sequence; under the condition that the substrate electrode is in short circuit with the second contact electrode, current flows to the second contact electrode from the first contact electrode through the first type sub-doping area, the channel area and the second type sub-doping area in sequence.
Further, the channel length, and thus the channel resistance, may be reduced by reducing the width of the trench.
Furthermore, the device adopts a longitudinal control grid field structure, makes full use of a charge balance mechanism, and effectively improves the conduction efficiency and reduces the chip size by making the drift region resistance small under the condition of meeting the withstand voltage requirement.
Further, in the case that the control gate and the first shielding gate are located in the same trench, for example, in the first trench region and the third trench region, since the vertical depth of the entire trench is implemented at one time, the vertical distance from the central line of the control gate extending in the substrate thickness direction to the inner boundary of the first shielding dielectric layer located on the two side walls of the trench is the same, and the vertical distance from the central line of the control gate extending in the substrate thickness direction to the outer boundary of the first shielding dielectric layer located on the two side walls of the trench is the same, that is, the control gate is located right below the first shielding gate. And the control gate is also located directly below the second shield gate.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description only relate to some embodiments of the present application and are not limiting on the present application.
Fig. 1 shows a circuit schematic of a prior art bi-directional power device.
Fig. 2 shows a circuit schematic of a bi-directional power device of an embodiment of the invention.
Fig. 3a to 3n are block diagrams illustrating at some stages of a method of fabricating a bi-directional power device according to an embodiment of the present invention.
Detailed Description
The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, certain well known components may not be shown. For simplicity, the semiconductor structure obtained after several steps can be described in one figure.
It will be understood that when a layer or region is referred to as being "on" or "over" another layer or region in describing the structure of the device, it can be directly on the other layer or region or intervening layers or regions may also be present. And, if the device is turned over, that layer, region, or regions would be "under" or "beneath" another layer, region, or regions.
If for the purpose of describing the situation directly on another layer, another area, the expressions "directly on … …" or "on … … and adjacent thereto" will be used herein.
In the following description, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of the devices are described in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.
The present invention may be embodied in various forms, some examples of which are described below.
Fig. 2 shows a circuit schematic of a bi-directional power device of an embodiment of the invention.
The bidirectional power device of the embodiment of the invention is formed by one transistor and has a bidirectional conduction function. As shown in fig. 2, the bidirectional power device includes: a substrate Sub, two output poles S1 and S2 located on the substrate Sub, and two parasitic body diodes D1 and D2. When the output electrode S2 and the substrate Sub are in short circuit, a high voltage is applied to the gate G, the voltage is higher than the threshold voltage of the bidirectional power device, the bidirectional power device is conducted, and current flows from the output electrode S1 to the output electrode S2; when the output electrode S1 and the substrate Sub are in short circuit, a high voltage is applied to the gate G, the voltage is higher than the threshold voltage of the bidirectional power device, the bidirectional power device is conducted, and current flows from the output electrode S2 to the output electrode S1; when the substrate Sub is connected to zero voltage, a low voltage is applied to the gate G, and the voltage is lower than the threshold voltage, so that the bidirectional power device is turned off. In the embodiment of the present invention, the bidirectional power device is a trench type device, and may be a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), an IGBT device, or a diode. However, the present invention is not limited thereto.
Fig. 3a to 3n are block diagrams illustrating at some stages of a method of fabricating a bi-directional power device according to an embodiment of the present invention. It should be noted that the structure of each step of the structure diagram disclosed in this embodiment is not necessarily in a cross section, and may be placed in different regions and directions of a product through a specific design according to the requirements of a product layout, where the illustration diagram only includes 5 trenches, a source region and a drain region, and in an actual product, the number of the trenches, the source region and the drain region may be changed, and when one of the first-type sub-doped region and the second-type sub-doped region is used as a source region, the other is used as a drain region, that is, through different working and application occasions, the source region and the drain region of the structure may be interchanged. In the embodiment of the present disclosure, in order to facilitate understanding of the forming process of the device structure in each step in the embodiment process, the main structure of the device is shown in a cross section in the embodiment of the present disclosure, but it is not intended to limit the claims, and any person skilled in the art may make possible changes and modifications without departing from the spirit and scope of the embodiment, so the scope of the embodiment should be determined by the scope defined by the claims of the present disclosure.
In the present embodiment, the manufacturing process starts with a semiconductor layer having a specific doping type, as shown in fig. 3a, the semiconductor layer includes a substrate 101 and an epitaxial layer 110 located on the substrate 101, wherein the substrate 101 includes a silicon substrate, a silicon germanium substrate, a group iii-v compound substrate, or other semiconductor material substrates known to those skilled in the art, and a silicon substrate is used in the present embodiment. More specifically, the silicon substrate employed in the present embodiment may be formed with semiconductor devices such as MOS field effect transistors, IGBT insulated gate field effect transistors, schottky, and the like.
The semiconductor layer having a specific doping type refers to an N-type or P-type substrate 101 doped with a certain amount of impurities according to product characteristics and an N-type or P-type epitaxial layer 110 having a certain resistivity and thickness. For example, in the case that the bidirectional power device is an NMOS transistor, the doping types of the substrate 101 and the epitaxial layer 110 are P-type; in the case where the bidirectional power device is a PMOS, the doping types of the substrate 101 and the epitaxial layer 110 are N-type.
Further, a first doped region 120 is formed in the epitaxial layer 110, as shown in fig. 3 a.
In this step, the first doped region 120 is formed by one or more of implantation doping, diffusion source doping and coating doping, wherein the implantation energy is 20 to 800KeV and the implantation dose is 1E11 to 1E16cm 2 The annealing temperature is 600-1200 ℃.
In this embodiment, the bidirectional power device has a first trench region 103, a second trench region 104, and a third trench region 105, the first doped region 120 is located in the first trench region 103, and the doping type is opposite to that of the epitaxial layer 110, for example, in the case that the bidirectional power device is a PMOS transistor, the doping type of the first doped region 120 is P type, and the doping impurities generally adopt B +; in the case where the bidirectional power device is an NMOS device, the doping type of the first doping region 120 is an N type, and the doping impurity is usually As + or P +. The first trench region 103, the second trench region 104 and the third trench region 105 are separated, and the second trench region 104 and the third trench region 105 are located in the epitaxial layer 110.
Further, a plurality of trenches 111a to 111e are formed as shown in fig. 3 b.
In this step, for example, a barrier layer 10 is formed on the surface of the epitaxial layer 110 by using thermal oxidation or deposition, the barrier layer 10 is selectively removed by photolithography and etching processes to form an opening 11, and then the semiconductor layer is etched through the opening 11 to form a trench, and the region reserved in the barrier layer 10 is not formed with a trench.
Fig. 3b is a cross-sectional view showing a total of 5 trenches including the trench 111a, the trench 111b, the trench 111c, the trench 111d, and the trench 111 e. The trenches 111a, 111b, and 111c are located in the first trench region 103, the trench 111b is located in the second trench region 104, the trench 111e is located in the third trench region 105, and bottoms of the trenches 111a to 111e are located in the epitaxial layer 110. Specifically, the trench 111a is located in the first doping region 120, and the trenches 111d and 111c are located at the boundary of the first doping region 120, and the three trenches divide the first doping region 120 into a first sub-doping region 121 and a second sub-doping region 122. The trench 111c and the trench 111d are respectively located at two sides of the first doped region 120 and are in contact with the first doped region 120, for example, the trench 111c is in contact with the second-type sub-doped region 122, and the trench 111d is in contact with the first-type sub-doped region 121. The trenches 111b and 111e are located in the epitaxial layer 110 and are separated from the first doped region 120, wherein the trench 111e is located between the trench 111c and the trench 111 b. In a plane perpendicular to the thickness direction of the substrate 101, the trench 111d located in the first trench region 103, the trench 111a, the trench 111c, the trench 111e located in the third trench region 105, and the trench 111b located in the second trench region 104 are communicated, for example, sequentially in an "S" shape, but the implementation of the present invention is not limited thereto, and a person skilled in the art may separate at least two trenches as needed.
In the present embodiment, the widths of the plurality of trenches 111a to 111e are determined according to the product structure and the process capability, and the depths h1 of the plurality of trenches 111a to 111e are determined according to the withstand voltage of the product and the like. Specifically, the width of the plurality of grooves 111a to 111e ranges from 0.05 μm to 5 μm, and the depth h1 ranges from 0.1 μm to 50 μm. However, the embodiments of the present invention are not limited thereto, and those skilled in the art may match the depth h1 and the width of the trenches 111a to 111e according to the requirements of the product, such as epitaxy, voltage resistance, doping, gate oxide thickness, and the like. Those skilled in the art can also make other arrangements to the number of trenches in the first trench region 103 as required, so that the plurality of trenches separate the first doped region 120 into a plurality of alternating first-type sub-doped regions 121 and second-type sub-doped regions 122.
Further, a channel region 130 is formed in the epitaxial layer 110 through the bottom of the plurality of trenches 111a to 111e, as shown in fig. 3 c.
In this step, for example, the bottom of the plurality of trenches 111a to 111e is first doped through the opening 11 of the barrier layer 10 to form the channel region 130 in the epitaxial layer 110, and then the barrier layer 10 is removed. For example, a zero angle implantation process is used to form a channel region 130 at the bottom of the trenches 111a to 111E for adjusting the threshold voltage of the device, wherein the implantation energy is 20 to 800KeV and the implantation dose is 1E11 to 1E16cm 2 The annealing temperature is 600-1200 ℃.
In the present embodiment, the channel region 130 is in contact with the first-type sub-doping region 121 and the second-type sub-doping region 122, respectively, and the doping types of the channel region 130 and the first-type sub-doping region 121 and the second-type sub-doping region 122 are the same. For example, in the case that the bidirectional power device is a PMOS transistor, the doping type of the channel region 130 is P-type, and the doping impurities generally adopt B +; in the case where the bidirectional power device is an NMOS, the doping type of the channel region 130 is an N type, and the doping impurity is usually As + or P +.
Further, a first dielectric layer 141a is formed on the inner surfaces of the trenches 111a to 111e, the surface of the epitaxial layer 110, the surface of the first type sub-doping region 121 and the surface of the second type sub-doping region 122, as shown in fig. 3 d.
In this step, the first dielectric layer 141a is formed, for example, by using one or a combination of various processes such as an oxide growth process, a chemical vapor deposition process, LPCVD, SACVD, HTO, and SRO. In some preferred embodiments, the first dielectric layer 141a is formed by an oxidation growth process, and in a subsequent step, the first dielectric layer 141a will form the gate dielectric layer 141. Wherein the thickness T1 of the first dielectric layer 141a should be combined with the threshold value required by the productThe range of T1 includes voltage, depth of trench in the device structure, doping concentration of the first doped region 120, and junction depth
Further, a first conductive layer 142a is formed on the first dielectric layer 141a on the surface of the epitaxial layer 110 and in the plurality of trenches 111a to 111e, as shown in fig. 3 e.
In this step, the first conductive layer 142a is formed, for example, using a deposition process such that the first conductive layer 142a fills the plurality of trenches 111a to 111e, and the first conductive layer 142a and the first dielectric layer 141a are in contact with each other. The material of the first conductive layer 142a includes in-situ doped polysilicon. In some other embodiments, polysilicon that is not doped with impurities may be deposited first, followed by implantation of doped impurities. In the subsequent steps, the first conductive layer 142a will form the control gate 142.
In this embodiment, in the case that the bidirectional power device is a PMOS transistor, the doping type of the first conductive layer 142a is P-type; in the case that the bidirectional power device is an NMOS, the doping type of the first conductive layer 142a is an N type.
Further, the first conductive layer 142a on the surface of the first dielectric layer 141a is removed, and the first conductive layer 142a in the trenches of the first trench region 103 and the third trench region 105 is selectively removed, as shown in fig. 3 f.
In this step, for example, a combination of one or more of dry etching, wet etching and CMP processes is firstly used to remove the first conductive layer 142a outside the trenches 111a to 111e, so that the first dielectric layer 141a on the surface of the epitaxial layer 110 is exposed, and the first conductive layer 142a in the trenches 111a to 111e is flush with the first dielectric layer 141a on the surface of the epitaxial layer 110. Then, by photolithography and etching processes, the first conductive layer 142a in the trenches 111a, 111c, and 111d of the first trench region 103 and the trench 111e of the third trench region 105 is selectively removed, so that the depths of the trenches 111a, 111c, 111d, and 142a in the trenches 111e from the surface of the epitaxial layer 110 are h 2. The remaining first conductive layer 142a in the trenches 111a to 111e serves as a control gate 142. The control gate 142 is located in the lower portions of the trenches 111a, 111c, 111d, 111e of the first trench region 103 and the third trench region 105 and the entire trench 111b of the second trench region 104, wherein the control gate 142 located in the trenches of the first trench region 103, the second trench region 104, and the third trench region 105 is connected.
In the present embodiment, the depth h2 of the trench 111a, the trench 111c, the trench 111d, and the control gate 142 in the trench 111e from the surface of the epitaxial layer 110 needs to be matched with the epitaxy, the withstand voltage, the doping, the gate oxide thickness, etc. of the product, and the depth h2 ranges from 0.1 μm to 49 μm. In this embodiment, the first dielectric layer 141a is remained after the formation of the control gate 142, so that the whole process is simple.
In some other embodiments, after forming the control gate 142, wet processes and other processes may be further employed to remove the first dielectric layer 141a on the sidewalls of the trenches 111a, 111c, 111d, 111e and the surface of the epitaxial layer 110.
Further, a second dielectric layer 143a is formed on the upper sidewalls of the trenches 111a, 111c, 111d and 111e, the surface of the control gate 142 and the first dielectric layer 141a on the surface of the epitaxial layer 110, as shown in fig. 3 g.
In this step, for example, an oxide growth process, a chemical vapor deposition process: one or more of LPCVD, SACVD, HTO, and SRO processes may be combined to form second dielectric layer 143 a. In some preferred embodiments, the second dielectric layer 143a is formed using an oxide growth process. The thickness of the second dielectric layer 143a grown on the surface of the control gate 142 is T2, and the thickness of the second dielectric layer 143a grown on the upper sidewalls of the trench 111a, the trench 111c, the trench 111d, and the trench 111e is T3. Under the same oxidation growth conditions, T2 is common>T3. Wherein the range of T2 includes
The range of T3 should be considered in combination with the voltage required for the product, the depth of the trench in the device structure, the doping concentration of the first doped region, and the junction depth, and the range of T3 includes
And T3>T1。
In the present embodiment, an oxidation growth process is used to form the second dielectric layer 143a, in which a portion of the exposed control gate 142 is oxidized to form a portion of the second dielectric layer 143a, and in the subsequent steps, the second dielectric layer 143a on the surface of the control gate 142 and on the middle sidewall of the trench 111a, the trench 111c, the trench 111d, and the upper sidewall of the trench 111e forms the first shielding dielectric layer 143.
Further, a second conductive layer 144a covering the second dielectric layer 143a and filling the trenches 111a, 111c, 111d, and 111e is formed, as shown in fig. 3 h.
In this step, the second conductive layer 144a is formed, for example, using a deposition process. The material of the second conductive layer 144a includes in-situ doped polysilicon, and in some other embodiments, the polysilicon without doping impurities may be deposited first, and then the doping impurities may be implanted. In a subsequent step, the second conductive layer 144a will form the first shield gate 144.
In this embodiment, the doping type of the second conductive layer 144a is P-type in the case that the bidirectional power device is a PMOS transistor; in the case that the bidirectional power device is an NMOS, the doping type of the second conductive layer 144a is an N type.
Further, the second conductive layer 144a, the second dielectric layer 143a and the first dielectric layer 141a on the surface of the epitaxial layer 110 are removed, as shown in fig. 3 i.
In this step, for example, one or a combination of a dry etching process, a wet etching process and a CMP process is used to remove the second conductive layer 144a, the second dielectric layer 143a and the first dielectric layer 141a outside the trenches 111a to 111e, so that the surfaces of the epitaxial layer 110, the first-type sub-doped region 121 and the second-type sub-doped region 122 are exposed.
In some embodiments, the second conductive layer 144a above the epitaxial layer 110 is removed by CMP and dry etching, or by dry etching. The second dielectric layer 143a above the epitaxial layer 110 is removed by a CMP wetting process, wherein a portion of the second dielectric layer 143a remains on top of the trench 111 b.
In the present embodiment, the remaining first dielectric layer 141a in the trenches 111a to 111e serves as the gate dielectric layer 141. The gate dielectric layer 141 is located on the inner surfaces of the lower portions of the trenches 111a, 111c, 111d, 111e of the first trench region 103 and the third trench region 105 and the entire inner surface of the trench 111b of the second trench region 104.
Further, the second conductive layer 144a at the openings of the trenches 111a, 111c, and 111d in the first trench region 103 is removed to expose the second dielectric layer 143a near the openings, and the remaining second conductive layer 144a in the trenches 111a, 111c, 111d, and 111e is used as the first shielding gate 144, as shown in fig. 3 i.
In this step, portions of the second conductive layer 144a in the trenches 111a, 111c, and 111d are removed by photolithography and etching, so that the second conductive layer 144a remaining in the trenches 111a, 111c, and 111d has a depth h3 below the surface of the epitaxial layer 110. In some embodiments, a dry etch process is typically used such that h3 ranges from
The second conductive layer 144a remaining in the middle of the trenches 111a, 111c, and 111d and remaining in the middle and upper portions of the trench 111e serves as a first shield gate 144.
Further, the exposed second dielectric layer 143a in the trenches 111a, 111c, and 111d of the first trench region 103 is removed, and a second shielding dielectric layer 145 is formed at the sidewalls of the upper portions of the trenches 111a, 111c, and 111d and the surface of the first shielding gate 144 of the trench 111e, as shown in fig. 3 j.
In this step, for example, an oxidation growth process, a chemical vapor deposition process: one or more of LPCVD, SACVD, HTO, and SRO processes may be combined to form second masking dielectric layer 145. In some preferred embodiments, the second shield dielectric layer is formed using an oxide growth process. The thickness of the second shielding dielectric layer grown on the sidewalls of the upper portions of the trenches 111a, 111c, and 111d is T4. Wherein, T3>The range of T4 and T4 should be combined with the voltage and device required by the productTaking into account the depth of the trench, the doping concentration of the first doped region, and the junction depth in the structure, the range of T4 includes
Further, a second shield gate 146 is formed in the upper portion of the trenches 111a, 111c, 111d, as shown in fig. 3 k.
In this embodiment, the material of second shielding gate 146 may be the same as that of first shielding gate 144, second shielding gate 146 contacts second shielding dielectric layer 145, and second shielding gate 146 is separated from first shielding gate 144 by second shielding dielectric layer 145.
In this step, for example, a conductive material is deposited to fill the upper portions of the trenches 111a, 111c, and 111d, and then the conductive material on the surface of the epitaxial layer 110 is removed, so that the second shield gate 146 is located on the upper portions of the trenches 111a, 111c, and 111 d. Control gate 142, first shield gate 144, and second shield gate 146 are separated by first gate dielectric layer 143 and second gate dielectric layer 145, respectively.
In the case where the control gate 142 and the first shield gate 144 are located in the same trench, for example, in the first trench region 103 and the third trench region 105, since the vertical depth of the entire trench is implemented at once, the control gate 142 is located directly below the first shield gate 144, and the control gate 142 is also located directly below the second shield gate 146. The vertical distances from the central line of the control gate 142 extending along the thickness direction of the substrate 101 to the inner boundaries of the first shielding dielectric layers 143 on the two side walls of the trench are the same, i.e., d1 is d2, and the vertical distances from the central line of the control gate 142 extending along the thickness direction of the substrate 101 to the outer boundaries of the first shielding dielectric layers 143 on the two side walls of the trench are the same, i.e., d3 is d 4.
Further, a first contact region 151 is formed in the first type sub-doping region 121, a second contact region 152 is formed in the second type sub-doping region 122, and a third contact region 153 is formed in the epitaxial layer 110, as shown in fig. 3 l.
In this step, the first-type sub-doping region 121, the second-type sub-doping region 122 and the epitaxial layer 110 are doped by implantation and diffusion, for example, through a photolithography mask.Wherein the implantation energy of the doping process is 20-180 Kev, and the implantation dosage is 1E 11-1E 16cm 2 。
In the present embodiment, the doping types of the first contact region 151 and the second contact region 152 are the same as the doping type of the first sub-doping region 121, and the doping type of the third contact region 153 is the same as the doping type of the epitaxial layer 110. For example, when the bidirectional power device is a PMOS, the doping types of the first contact region 151 and the second contact region 152 are P-type, and the doping type of the third contact region 153 is N-type; when the bidirectional power device is an NMOS, the doping types of the first contact region 151 and the second contact region 152 are N-type, and the doping type of the third contact region 153 is P-type. The P-type contact region is doped with B +/BF2+ and the N-type contact region is doped with As + and P +.
Further, a capping dielectric layer 102 is formed on the epitaxial layer 110, and a plurality of contact holes 102a extending from the surface of the capping dielectric layer 102 toward the substrate direction 101 are formed, as shown in fig. 3 m.
In this step, the capping dielectric layer 102 is formed by, for example, a chemical vapor deposition process, which may include one or a combination of LPCVD, SACVD, HTO, and SRO. The material of the cover dielectric layer 102 includes one or more of undoped silicon dioxide, boron-doped silicon dioxide, phosphorus-doped silicon dioxide, silicon dioxide doped with both boron and phosphorus, undoped polysilicon, silicon nitride, and silicon oxynitride material. Then, for example, photolithography and etching processes are used to form a plurality of contact holes 102a, the extension depth of the plurality of contact holes 102a in the first contact region 151, the second contact region 152, the third contact region 153, the control gate 142, the first shielding gate 144 and the second shielding gate 146 is h4, and the range thereof includes
Further, a substrate electrode 163, a first contact electrode 161, a second contact electrode 162, a first gate electrode 164, a second gate electrode 165, and a third gate electrode 166 are formed in the plurality of contact holes, respectively, as shown in fig. 3 n.
In this step, for example, a metal conductive layer is deposited on the capping dielectric layer 102, the metal conductive layer extending from the surface of the capping dielectric layer 102 into the contact hole. Finally, photolithography and etching processes are used to form the first contact electrode 161, the second contact electrode 162, the substrate electrode 163, the first gate electrode 164, the second gate electrode 165, and the third gate electrode 166. The first contact electrode 161 and the second contact electrode 162 are a source electrode and a drain electrode, and may be interchanged.
The first contact electrode 161 is connected to the first contact region 151, the second contact electrode 162 is connected to the second contact region 152, the substrate electrode 163 is connected to the third contact region 153, the first gate electrode 164 is connected to the control gate 142, the second gate electrode 165 is connected to the first shield gate 144, and the third gate electrode 166 is connected to the second shield gate 146. The material of the metal conductive layer may be one or a combination of metals including Ti, TiN, TiSi, W, Al, AlSi, AlCu, AlSiCu, Cu, Ni, and the like. Wherein, the metal etching adopts one or more of wet etching and plasma etching to form a substrate electrode 163, a first contact electrode 161, a second contact electrode 162, a first gate electrode 164, a second gate electrode 165 and a third gate electrode 166, and voltage or current is applied through the 6 electrodes to realize the performance of the device.
In the present embodiment, the position of the first gate electrode 164 corresponds to the trench 111b, the position of the second gate electrode 165 corresponds to the trench 111e, and the position of the third gate electrode 166 corresponds to the trench 111 c. However, the embodiment of the present invention is not limited thereto, and since the plurality of trenches 111a to 111e are communicated such that the control gates 142 in the plurality of trenches 111a to 111e are connected to each other, the first shield gates 144 in the plurality of trenches are connected to each other, and the second shield gates 146 in the plurality of trenches are connected to each other, the position of the third gate electrode 166 may also correspond to the trench 111a and/or the trench 111 d. The control gate 142 in the first trench region 103, the second trench region 104, and the third trench region 105 is led out through the first gate electrode 164, the first shield gate 144 in the first trench region 103 and the third trench region 105 is led out through the second gate electrode 165, and the second shield gate 146 in the first trench region 103 is led out through the third gate electrode 166.
In some specific embodiments, the first gate electrode 164, the second gate electrode 165, and the third gate electrode 166 are connected to connect the control gate 142, the first shielding gate 144, and the second shielding gate 146, so that a single poly-like structure is formed, and the first shielding gate 144, the second shielding gate 146 overlap the first sub-doping region 121 and the second sub-doping region 122, so that parasitic capacitance exists. When the voltages of the control gate 142, the first shielding gate 144 and the second shielding gate 146 rise, the parasitic capacitance is charged, and the bidirectional power device is turned on; when the voltages of the control gate 142, the first shield gate 144, and the second shield gate 146 are lowered, the parasitic capacitance discharges and the bi-directional power device turns off. When the bidirectional power device is switched on and off at a high speed, the charging and discharging time of the parasitic capacitor can reduce the switching frequency, and the parasitic capacitor is charged and discharged to generate extra power consumption.
In other specific embodiments, the first gate electrode 164, the second gate electrode 165, and the third gate electrode 166 may be separated to receive different control voltages, and the first shielding gate 144, the second shielding gate 146, and the control gate 142 are controlled individually, so as to control the coupling electric field in the shielding gate region of each layer, and flexibly adjust the shielding effect as needed.
In other specific embodiments, the second gate electrode 165 and the third gate electrode 166 may be connected to receive the same control voltage, and are electrically isolated from the first gate electrode 164, and simultaneously control the electric fields at the upper and middle sections, thereby realizing simultaneous control of the first shielding gate 144 and the second shielding gate 146, realizing control of the coupling electric field in the shielding gate region, and improving the parameter level of the device.
In other specific embodiments, it is also possible to connect one of the first gate electrode 164 and the second gate electrode 165 to the third gate electrode 166 to receive the same control voltage, and to separate the other from the third gate electrode 166 to receive a different control voltage.
It is understood that in the present embodiment and the illustration, only a trench structure having three dielectric layers and three gate conductors is enumerated, but the trench structure is not limited to only three sets of dielectric layers and gate conductors, and may be four sets of dielectric layers and gate conductors, or even N sets of dielectric layers and gate conductors, as long as the gate conductors of the respective layers are segmented and isolated from each other by the dielectric layers. The thickness of the dielectric layer can be freely combined, and the function of the device is realized by applying proper voltage to each layer of gate conductor.
Furthermore, the embodiment of the invention discloses a bidirectional power device and a manufacturing method thereof, and can reduce the resistance of the device to the minimum in the application process and reduce the signal interference to the maximum extent by increasing metal levels and optimizing the wiring mode and method.
Further, the embodiment of the invention discloses a bidirectional power device and a manufacturing method thereof, which can be combined with the practical application of products to increase structures such as passivation layers, polyimide and the like, thereby protecting the device and enhancing the reliability.
Further, the embodiment of the invention discloses a bidirectional power device and a manufacturing method thereof, which can form a structure required by a product through subsequent processes such as thinning, back evaporation and the like to realize functions.
Further, the bidirectional power device with the bidirectional conduction function implemented by the embodiment of the present invention may draw the first gate electrode 164, the second gate electrode 165, the third gate electrode 166, the substrate electrode 163, the first contact electrode 161, and the second contact electrode 162 out of the surface of the semiconductor structure, so as to meet the packaging requirements of Chip Scale Package (CSP).
Further, the embodiment of the invention discloses a bidirectional power device and a manufacturing method thereof, which can be applied to products such as power MOSFET, CMOS, BCD, high-power transistor, IGBT and Schottky.
According to the bidirectional power device and the manufacturing method thereof provided by the embodiment of the invention, the first doped region is formed in the epitaxial layer, the first doped region is divided into the first sub-doped region and the second sub-doped region which are alternated by the groove, and the first contact region and the second contact region are respectively formed in the first sub-doped region and the second sub-doped region, so that the two doped regions of the bidirectional power device are formed, and the two doped regions are the source region and the drain region, so that the area of the device is reduced. The thickness of the second shielding dielectric layer and the thickness of the gate dielectric layer are smaller than that of the first shielding dielectric layer, so that different electric fields can be formed by applying different voltages to the gate electrode.
More specifically, the first doped region is typically deeper, and higher diffusion temperatures and longer diffusion times are required to achieve deeper junction depths. Therefore, the first doping region is formed in the first step of the manufacturing method according to the requirements of product parameters, and the requirements of product structures and parameters can be realized by selecting proper doping conditions. Under the condition that the junction depth requirement of the first doped region is shallow, the first doped region can be formed without the first step of the manufacturing method, and the first doped region can also be annealed in the annealing process of other doped regions in the subsequent manufacturing method, so that the requirements of the junction depth and parameters required by the device structure are met.
Furthermore, by forming the control gates and the shielding gates in the plurality of grooves, when the bidirectional power device is cut off, the shielding gates deplete charges in the source region and the drain region through the shielding dielectric layer, and the voltage resistance of the device is improved; in the case of conduction of the bidirectional power device, the source region and/or the drain region and the channel region provide a low-impedance conduction path.
Furthermore, the control gates and the shielding gates in the device structure are separated from each other, the control gates in the first trench area, the second trench area and the third trench area are connected and led out through electrodes, the first shielding gates in the first trench area and the third trench area are connected and led out through electrodes, and the second shielding gates in the first trench area are connected and led out through electrodes. In some other embodiments, the first shielding grid and the second shielding grid can be connected through the extraction electrode, the first shielding grid and the second shielding grid are isolated from the control grid, electric fields in the upper section and the middle section are controlled at the same time, the first shielding grid and the second shielding grid are controlled at the same time, the control of a coupling electric field in a shielding grid region can be realized by applying different voltages to the shielding grids than the control grid, and the parameter level of the device is improved. In addition, one of the first shield gate and the second shield gate may be connected to the control gate through the extraction electrode, and the other may be electrically isolated from the control gate.
Further, when the bidirectional power device is conducted, the substrate electrode connected with the substrate is in short circuit with one of the first contact electrode and the second contact electrode, and bidirectional selection of the current direction is achieved. Under the condition that the substrate electrode is in short circuit with the first contact electrode, current flows to the first contact electrode from the second contact electrode through the second type sub-doping area, the channel area and the first type sub-doping area in sequence; under the condition that the substrate electrode is in short circuit with the second contact electrode, current flows to the second contact electrode from the first contact electrode through the first type sub-doping area, the channel area and the second type sub-doping area in sequence.
Further, the channel length, and thus the channel resistance, may be reduced by reducing the width of the trench.
Furthermore, the device adopts a longitudinal control grid field structure, makes full use of a charge balance mechanism, and effectively improves the conduction efficiency and reduces the chip size by making the drift region resistance small under the condition of meeting the withstand voltage requirement.
Further, in the case that the control gate and the first shielding gate are located in the same trench, for example, in the first trench region and the third trench region, since the vertical depth of the entire trench is implemented at one time, the vertical distance from the central line of the control gate extending in the substrate thickness direction to the inner boundary of the first shielding dielectric layer located on the two side walls of the trench is the same, and the vertical distance from the central line of the control gate extending in the substrate thickness direction to the outer boundary of the first shielding dielectric layer located on the two side walls of the trench is the same, that is, the control gate is located right below the first shielding gate. And the control gate is also located directly below the second shield gate.
The embodiments of the present invention have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present invention. The scope of the invention is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the invention, and these alternatives and modifications are intended to fall within the scope of the invention.
Claims (36)
1. A method of manufacturing a bi-directional power device, comprising:
forming a first doped region in the semiconductor layer;
forming a plurality of grooves in a first groove region, wherein the grooves of the first groove region are positioned in the first doping region and divide the first doping region into a first sub-doping region and a second sub-doping region which are alternated;
forming a gate dielectric layer covering the lower side walls of the plurality of grooves of the first groove area;
forming a control gate in contact with the gate dielectric layer at the lower part of the plurality of trenches in the first trench region;
forming a first shielding dielectric layer covering the middle side walls of the plurality of trenches of the first trench region and the surface of the control gate;
forming a first shielding grid in contact with the first shielding dielectric layer in the middle of the plurality of trenches in the first trench region;
forming a second shielding dielectric layer covering the upper side walls of the plurality of trenches of the first trench region and the surface of the first shielding gate; and
forming a second shield gate in contact with the second shield dielectric layer on the upper portion of the plurality of trenches in the first trench region,
the first shielding dielectric layer separates the control gate from the first shielding gate, and the second shielding dielectric layer separates the second shielding gate from the first shielding gate.
2. The method of manufacturing of claim 1, wherein the thickness of the second shield dielectric layer and the gate dielectric layer are both less than the thickness of the first shield dielectric layer.
3. The manufacturing method according to claim 1, wherein in a case where one of the first type sub-doping region and the second type sub-doping region serves as a source region, the other of the first type sub-doping region and the second type sub-doping region serves as a drain region, and the source region and the drain region are interchangeable.
4. The method of manufacturing of claim 1, further comprising forming a trench in a second trench region, the trench of the second trench region being in the semiconductor layer and being separated from the first doped region;
the gate dielectric layer is further formed on the side wall of the groove of the second groove region, and the control gate is further formed in the groove of the second groove region and is in contact with the gate dielectric layer;
the trench of the first trench region is communicated with the trench of the second trench region, and the control gate in the trench of the first trench region is connected with the control gate in the trench of the second trench region.
5. The method of manufacturing of claim 4, further comprising forming a trench in a third trench region, the trench of the third trench region being in the semiconductor layer and being separated from the first doped region;
the gate dielectric layer is further formed on the side wall of the lower portion of the groove of the third groove region, the control gate is further formed on the lower portion of the groove of the third groove region and is in contact with the gate dielectric layer, the first shielding dielectric layer is further formed on the side wall of the upper portion of the groove of the third groove region and is located on the surface of the control gate, the first shielding gate is further formed on the upper portion of the groove of the third groove region and is in contact with the first shielding dielectric layer, and the control gate and the first shielding gate are separated by the first shielding dielectric layer;
the trench of the first trench region is communicated with the trench of the third trench region, the control gate in the trench of the first trench region is connected with the control gate in the trench of the third trench region, and the first shielding gate in the trench of the first trench region is connected with the first shielding gate in the trench of the third trench region.
6. The method of manufacturing of any of claims 1-5, further comprising forming a channel region in the semiconductor layer adjacent to the control gate.
7. The manufacturing method according to any one of claims 1 to 5, further comprising:
forming a first contact region in the first type doped region;
forming a second contact region in the second type sub-doping region; and
a third contact region is formed in the semiconductor layer.
8. The manufacturing method according to claim 7, further comprising:
forming a covering dielectric layer on the surface of the semiconductor layer; and
and forming a substrate electrode, a first contact electrode, a second contact electrode, a first gate electrode, a second gate electrode and a third gate electrode which penetrate through the covering dielectric layer, wherein the substrate electrode is connected with the third contact area, the first contact electrode is connected with the first contact area, the second contact electrode is connected with the second contact area, the first gate electrode is connected with the control grid, the second gate electrode is connected with the first shielding grid, and the third gate electrode is connected with the second shielding grid.
9. The manufacturing method according to claim 8, wherein the first gate electrode, the second gate electrode, and the third gate electrode are electrically isolated from each other to receive different control voltages.
10. The manufacturing method according to claim 8, wherein the first gate electrode, the second gate electrode, and the third gate electrode are connected to each other to receive the same control voltage.
11. The manufacturing method according to claim 8, wherein one of the second gate electrode and the third gate electrode is connected to the first gate electrode to receive the same control voltage, and the other is electrically isolated from the first gate electrode to receive a different control voltage.
12. The manufacturing method according to claim 8, wherein the second gate electrode and the third gate electrode are connected to receive the same control voltage, and the first gate electrode is electrically isolated to receive different control voltages.
13. The manufacturing method according to any one of claims 1 to 5, wherein the thickness range of the gate dielectric layer comprises
14. The manufacturing method according to claim 5, wherein a depth of a plurality of trenches in the first trench region, the second trench region and the third trench region ranges from 0.1 to 50 μm.
15. The manufacturing method according to any one of claims 1 to 5, wherein a distance from a surface of the control gate located in the first trench region to a surface of the semiconductor layer comprises 0.1 to 49 μm.
16. The manufacturing method according to any one of claims 1-5, wherein the thickness range of the first shielding dielectric layer on the control gate surface includes
17. The manufacturing method according to any one of claims 1 to 5, wherein a plurality of trenches covering the first trench regionThe thickness range of the first shielding medium layer on the middle side wall of the groove comprises
18. The method of manufacturing of any of claims 1-5, wherein the thickness range of the second shielding dielectric layer comprises
19. The manufacturing method according to any one of claims 1 to 5, wherein, in a case where the bidirectional power device is turned off, the shielding gate depletes charges of the first type sub-doped region and the second type sub-doped region through the shielding dielectric layer so as to improve a withstand voltage characteristic of the bidirectional power device.
20. A bi-directional power device comprising:
a semiconductor layer;
a first doped region in the semiconductor layer;
the plurality of grooves of the first groove area are positioned in the first doping area and divide the first doping area into a first sub-doping area and a second sub-doping area which are alternated;
the gate dielectric layer covers the lower side walls of the plurality of grooves of the first groove area;
the control gate is positioned at the lower parts of the plurality of trenches of the first trench region and is in contact with the gate dielectric layer;
the first shielding dielectric layer covers the side walls of the middle parts of the plurality of grooves of the first groove region and is positioned on the surface of the control gate;
the first shielding grid is positioned in the middle of the plurality of grooves of the first groove area and is in contact with the first shielding medium layer;
the second shielding dielectric layer covers the upper side walls of the plurality of grooves of the first groove region and is positioned on the surface of the first shielding grid; and
a second shield gate located at an upper portion of the plurality of trenches of the first trench region and in contact with the second shield dielectric layer,
wherein the first shielding dielectric layer separates the control gate from the first shielding gate, the second shielding dielectric layer separates the second shielding gate from the first shielding gate,
the bidirectional power device further includes:
the first contact region is positioned in the first-type sub-doping region;
the second contact region is positioned in the second type sub-doping region;
a third contact region in the semiconductor layer;
the covering dielectric layer is positioned on the surface of the semiconductor layer; and
the substrate electrode, the first contact electrode, the second contact electrode, the first gate electrode, the second gate electrode and the third gate electrode penetrate through the covering dielectric layer, the substrate electrode is connected with the third contact area, the first contact electrode is connected with the first contact area, the second contact electrode is connected with the second contact area, the first gate electrode is connected with the control grid, the second gate electrode is connected with the first shielding grid, and the third gate electrode is connected with the second shielding grid.
21. The bi-directional power device of claim 20, wherein the thickness of each of said second shield dielectric layer and said gate dielectric layer is less than the thickness of said first shield dielectric layer.
22. The bidirectional power device of claim 20, wherein, with one of the first and second sub-doped regions being a source region, the other of the first and second sub-doped regions being a drain region, and the source and drain regions being interchangeable.
23. The bidirectional power device of claim 20, further comprising a trench of a second trench region in the semiconductor layer and spaced apart from the first doped region;
the gate dielectric layer is also positioned on the side wall of the groove of the second groove region, and the control gate is also positioned in the groove of the second groove region and is in contact with the gate dielectric layer;
the trench of the first trench region is communicated with the trench of the second trench region, and the control gate in the trench of the first trench region is connected with the control gate in the trench of the second trench region.
24. The bidirectional power device of claim 23, further comprising a trench of a third trench region in the semiconductor layer and spaced apart from the first doped region;
the gate dielectric layer also covers the lower side wall of the groove of the third groove region, the control gate is also positioned at the lower part of the groove of the third groove region and is contacted with the gate dielectric layer, the first shielding dielectric layer also covers the upper side wall of the groove of the third groove region and is positioned on the surface of the control gate, the first shielding gate is also positioned at the upper part of the groove of the third groove region and is contacted with the first shielding dielectric layer, and the first shielding dielectric layer separates the control gate from the first shielding gate;
the trench of the first trench region is communicated with the trench of the third trench region, the control gate in the trench of the first trench region is connected with the control gate in the trench of the third trench region, and the first shielding gate in the trench of the first trench region is connected with the first shielding gate in the trench of the third trench region.
25. The bidirectional power device of any of claims 20-24, further comprising a channel region in the semiconductor layer and adjacent to the control gate.
26. The bidirectional power device of any of claims 20-24, wherein the first, second, and third gate electrodes are electrically isolated from each other to receive different control voltages.
27. The bi-directional power device of any of claims 20-24, wherein said first gate electrode, said second gate electrode and said third gate electrode are connected to each other to receive the same control voltage.
28. A bi-directional power device as claimed in any of claims 20-24, wherein one of said second and third gate electrodes is connected to said first gate electrode to receive the same control voltage and the other is electrically isolated from said first gate electrode to receive a different control voltage.
29. A bi-directional power device as claimed in any of claims 20-24, wherein said second gate electrode and said third gate electrode are connected to receive the same control voltage and are electrically isolated from said first gate electrode to receive different control voltages.
30. The bi-directional power device of any of claims 20-24, wherein said gate dielectric layer has a thickness in a range including
31. The bidirectional power device of claim 24, wherein a depth of the plurality of trenches in the first, second, and third trench regions ranges from 0.1 to 50 μ ι η.
32. The bidirectional power device of any of claims 20-24, wherein a distance from a surface of the control gate located in the first trench region to a surface of the semiconductor layer comprises 0.1-49 μ ι η.
33. According to the rightThe bi-directional power device of any of claims 20-24, wherein said first shield dielectric layer is located on said control gate surface in a thickness range including
34. The bidirectional power device of any of claims 20-24, wherein a thickness of the first shielding dielectric layer covering the central sidewalls of the plurality of trenches of the first trench region includes
35. The bi-directional power device of any of claims 20-24, wherein said second shielding dielectric layer has a thickness in a range including
36. The bidirectional power device of any of claims 20-24, wherein, with the bidirectional power device turned off, the shield gate depletes the charge of the first and second sub-doped regions through the shield dielectric layer to improve the withstand voltage characteristics of the bidirectional power device.
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| US10020302B2 (en) * | 2015-12-23 | 2018-07-10 | Nxp Usa, Inc. | Half-bridge circuit, H-bridge circuit and electronic system |
| US10128750B2 (en) * | 2016-03-04 | 2018-11-13 | Infineon Technologies Ag | Switched-mode power converter with an inductive storage element and a cascode circuit |
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| CN106571392A (en) * | 2015-10-07 | 2017-04-19 | 奥尼卡电子有限公司 | VDMOS and method for manufacturing the same |
| CN107482056A (en) * | 2017-08-07 | 2017-12-15 | 电子科技大学 | A kind of shield grid VDMOS device |
| CN110137242A (en) * | 2019-04-03 | 2019-08-16 | 杭州士兰微电子股份有限公司 | Bilateral power devices and its manufacturing method |
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