CN112309974A - Bidirectional power device and manufacturing method thereof - Google Patents
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- CN112309974A CN112309974A CN202011163996.XA CN202011163996A CN112309974A CN 112309974 A CN112309974 A CN 112309974A CN 202011163996 A CN202011163996 A CN 202011163996A CN 112309974 A CN112309974 A CN 112309974A
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Abstract
The application discloses two-way power device and manufacturing method thereof, the two-way power device includes: a semiconductor layer; a first doped region in the semiconductor layer; the plurality of grooves of the first groove area are positioned in the first doping area and divide the first doping area into a first sub-doping area and a second sub-doping area which are alternated; the gate dielectric layer covers the lower side walls of the plurality of grooves of the first groove area; the shielding dielectric layer covers the upper side walls of the plurality of grooves of the first groove area; and the grid conductor is positioned in the plurality of grooves of the first groove region and is respectively contacted with the grid dielectric layer and the shielding dielectric layer, the grid conductor comprises a control grid and a shielding grid which are connected, the control grid is contacted with the grid dielectric layer, and the shielding grid is contacted with the shielding dielectric layer, wherein the thickness of the shielding dielectric layer is inconsistent, and the thickness of at least part of the shielding dielectric layer is greater than that of the grid dielectric layer. According to the device, the withstand voltage of the device is improved by setting at least part of the thickness of the shielding dielectric layer to be larger than that of the gate dielectric layer.
Description
Technical Field
The present disclosure relates to the field of semiconductor manufacturing technologies, and more particularly, to a bidirectional power device and a manufacturing method thereof.
Background
Bidirectional power devices are widely used in charging devices having a secondary charging function. Taking the lithium battery charging and discharging device as an example, when the lithium battery charging and discharging device continuously supplies power to the terminal device to a certain extent, the lithium battery charging and discharging device needs to be prevented from over-discharging so as to prevent the terminal device from stopping running, and the lithium battery needs to be charged in time. In the process of charging the lithium battery, the lithium battery also needs to supply power to the terminal equipment, and meanwhile, the lithium battery is prevented from being overcharged. Therefore, in order to manage and control the charge/discharge state of the lithium battery, a charge/discharge protection circuit having a bidirectional switch for controlling current conduction is generally used.
As shown in fig. 1, in the first charge/discharge protection circuit, two drain-connected single planar gate NMOS transistors M1 and M2 were used as bidirectional switches. When charging is performed, a high voltage is applied to the gate G1 of M1 to turn on M1, and a low voltage is applied to the gate G2 of M2 to turn off M2, and at this time, current flows from the source S2 of M2 to the drain of M2 through the parasitic diode D2 of M2, and then flows from the drain of M1 to the source S1 of M1. When discharging, a low voltage is applied to gate G1 of M1, turning off M1, and a high voltage is applied to gate G2 of M2, turning on M2. At this time, the current flows from the source S1 of M1 to the drain of M1 through the parasitic diode D1 of M1, and then flows from the drain of M2 to the source S2 of M2. However, the MOS process using the planar gate structure requires a sufficient area to meet the requirement of higher withstand voltage, and the device has low on-state efficiency and large power consumption.
Therefore, it is desirable to further optimize the structure of the bidirectional power device, so that the bidirectional power device has smaller area and higher performance.
Disclosure of Invention
In view of the above problems, an object of the present invention is to provide a bidirectional power device and a method for manufacturing the same, in which a trench is used to separate a first doped region into a first type sub-doped region and a second type sub-doped region, which are alternated, to form a source region and a drain region of the bidirectional power device, thereby reducing the area of the device. The withstand voltage of the device is improved by setting at least part of the thickness of the shielding dielectric layer to be larger than that of the gate dielectric layer.
According to an aspect of the embodiments of the present invention, there is provided a bidirectional power device, including: a semiconductor layer; a first doped region in the semiconductor layer; the plurality of grooves of the first groove area are positioned in the first doping area and divide the first doping area into a first sub-doping area and a second sub-doping area which are alternated; the gate dielectric layer covers the lower side walls of the plurality of grooves of the first groove area; the shielding dielectric layer covers the upper side walls of the plurality of grooves of the first groove area; and the grid conductor is positioned in the plurality of grooves of the first groove region and is respectively contacted with the grid dielectric layer and the shielding dielectric layer, the grid conductor comprises a control grid and a shielding grid which are connected, the control grid is contacted with the grid dielectric layer, and the shielding grid is contacted with the shielding dielectric layer, wherein the thickness of the shielding dielectric layer is inconsistent, and at least part of the thickness of the shielding dielectric layer is greater than that of the grid dielectric layer.
Optionally, in a case where one of the first type sub-doping region and the second type sub-doping region serves as a source region, the other of the first type sub-doping region and the second type sub-doping region serves as a drain region, and the source region and the drain region may be interchanged.
Optionally, in the plurality of trenches in the first trench region, the thickness of the shielding dielectric layer gradually becomes thicker or thinner along a direction from the opening of the trench to the bottom.
Optionally, the shielding dielectric layer includes a plurality of step portions connected in sequence, and in the plurality of trenches of the first trench region, the thickness of the shielding dielectric layer changes in a gradient manner along a direction from the opening to the bottom of the trench.
Optionally, the shielding dielectric layer includes a first step portion, a second step portion and a third step portion, which are sequentially connected, in the plurality of trenches of the first trench region, the third step portion is close to the opening of the trench, and the thicknesses of the first step portion, the second step portion and the third step portion are sequentially decreased progressively.
Optionally, the thickness range of the first step portion includes:
the thickness range of the second step portion includes:
the thickness range of the third step portion includes:
and the thickness of the gate dielectric layer is smaller than that of the first step part.
Optionally, the distance range from the bottom end of the first step portion to the trench opening includes: 0.1-50 μm, the distance range from the bottom end of the second step part to the opening of the groove comprises: 0 ~ 30 mu m, the distance scope of the bottom of third step portion to slot opening includes: 0 to 20 μm.
Optionally, the semiconductor device further includes a trench of a second trench region, the trench is located in the semiconductor layer and separated from the first doped region, the gate dielectric layer further covers a lower sidewall of the trench of the second trench region, the shielding dielectric layer further covers an upper sidewall of the trench of the second trench region, the gate conductor is further located in the trench of the second trench region and is in contact with the gate dielectric layer and the shielding dielectric layer respectively, the trench of the first trench region is communicated with the trench of the second trench region, and the gate conductor located in the trench of the first trench region is connected with the gate conductor located in the trench of the second trench region.
Optionally, the trench of the first trench region has the same structure as the trench of the second trench region.
Optionally, the plurality of trenches of the first trench region includes: a first recess in the first doped region; and a second recess in the first doped region and a portion of the semiconductor layer, the second recess being located below the first recess and in communication with the first recess.
Optionally, the depth of the first concave part ranges from 0.1 to 50 μm, and the distance from the bottom end of the second concave part to the bottom end of the first concave part ranges from 0.1 to 5 μm.
Optionally, the shielding dielectric layer is located on a sidewall of the first recess, and the gate dielectric layer is located on an inner surface of the second recess.
Optionally, the method further comprises: the first contact region is positioned in the first-type sub-doping region; the second contact region is positioned in the second type sub-doping region; and a third contact region in the semiconductor layer.
Optionally, a channel region is further included in the semiconductor layer and adjacent to the control gate.
Optionally, the method further comprises: the covering dielectric layer is positioned on the surface of the semiconductor layer; and the substrate electrode, the first contact electrode, the second contact electrode and the gate electrode penetrate through the covering dielectric layer, the substrate electrode is connected with the third contact area, the first contact electrode is connected with the first contact area, the second contact electrode is connected with the second contact area, and the gate electrode is connected with the gate conductor.
Optionally, when the bidirectional power device is turned off, the shield gate depletes charges in the first sub-doped region and the second sub-doped region through the shield dielectric layer, so as to improve a withstand voltage characteristic of the bidirectional power device.
According to another aspect of the embodiments of the present invention, there is provided a method for manufacturing a bidirectional power device, including: forming a first doped region in the semiconductor layer; forming a plurality of grooves of a first groove area, wherein the grooves of the first groove area are positioned in the first doping area and divide the first doping area into a first sub-doping area and a second sub-doping area which are alternated; forming a gate dielectric layer covering the lower side walls of the plurality of grooves of the first groove area; forming a shielding medium layer covering the upper side walls of the plurality of grooves of the first groove area; and forming grid conductors which are respectively contacted with the grid dielectric layer and the shielding dielectric layer in the plurality of grooves of the first groove area, wherein the grid conductors comprise control grids and shielding grids which are connected, the control grids are contacted with the grid dielectric layer, and the shielding grids are contacted with the shielding dielectric layer, the thickness of the shielding dielectric layer is inconsistent, and the thickness of at least part of the shielding dielectric layer is larger than that of the grid dielectric layer.
Optionally, in a case where one of the first type sub-doping region and the second type sub-doping region serves as a source region, the other of the first type sub-doping region and the second type sub-doping region serves as a drain region, and the source region and the drain region may be interchanged.
Optionally, in the plurality of trenches in the first trench region, the thickness of the shielding dielectric layer gradually becomes thicker or thinner along a direction from the opening of the trench to the bottom.
Optionally, the shielding dielectric layer includes a plurality of step portions connected in sequence, and in the plurality of trenches of the first trench region, the thickness of the shielding dielectric layer changes in a gradient manner along a direction from the opening to the bottom of the trench.
Optionally, the semiconductor device further includes a trench forming a second trench region, the trench of the second trench region is located in the semiconductor layer and separated from the first doped region, the gate dielectric layer is further formed on a lower sidewall of the trench of the second trench region, the shielding dielectric layer is further formed on an upper sidewall of the trench of the second trench region, the gate conductor is further formed in the trench of the second trench region and is in contact with the gate dielectric layer and the shielding dielectric layer respectively, the trench of the first trench region is communicated with the trench of the second trench region, and the gate conductor in the trench of the first trench region is connected to the gate conductor in the trench of the second trench region.
Optionally, the trench of the first trench region has the same structure as the trench of the second trench region.
Optionally, the step of forming a plurality of trenches of the first trench region includes: forming a plurality of first recesses in the first doped region; filling a dielectric material in the first concave part; and removing a part of the dielectric material in each first concave part and removing the first doping region and a part of the semiconductor layer below the first concave part through the bottom end of each first concave part to form a second concave part, wherein the bottom end of the second concave part is positioned in the semiconductor layer, and the plurality of grooves of the first groove region are formed by the corresponding first concave part and the second concave part.
Optionally, the depth of the first concave part ranges from 0.1 to 50 μm, and the distance from the bottom end of the second concave part to the bottom end of the first concave part ranges from 0.1 to 5 μm.
Optionally, after forming the second recess, the step of forming a shielding dielectric layer covering upper sidewalls of the plurality of trenches of the first trench region includes: forming a first sacrificial layer, wherein the first sacrificial layer extends from the bottom end of the second concave part to the surface of the semiconductor layer and covers a part of the dielectric material in the first concave part; thinning the dielectric material which is positioned in the first concave part and not covered by the first sacrificial layer, wherein the dielectric material protected by the first sacrificial layer forms a first step part; replacing the first sacrificial layer with a second sacrificial layer, wherein the second sacrificial layer extends from the bottom end of the second concave part to the surface of the semiconductor layer and covers the first step part and the medium material partially positioned in the first concave part; thinning the dielectric material which is positioned in the first concave part and not covered by the second sacrificial layer to form a third step part, and forming a second step part by the dielectric material which is protected by the second sacrificial layer except the first step part.
Optionally, the thickness range of the first step portion includes:
the thickness range of the second step portion includes:
the thickness range of the third step portion includes:
and the thickness of the gate dielectric layer is smaller than that of the first step part.
Optionally, a distance range from a bottom end of the first step portion to the surface of the semiconductor layer includes: 0.1-50 μm, the distance range from the bottom end of the second step part to the surface of the semiconductor layer comprises: 0-30 μm, the distance range from the bottom end of the third step part to the surface of the semiconductor layer comprises: 0 to 20 μm.
Optionally, the method further comprises: forming a first contact region in the first type doped region; forming a second contact region in the second type sub-doping region; and forming a third contact region in the semiconductor layer.
Optionally, forming a channel region in the semiconductor layer adjacent to the control gate is further included.
Optionally, the method further comprises: forming a covering dielectric layer on the surface of the semiconductor layer; and forming a substrate electrode, a first contact electrode, a second contact electrode and a gate electrode which penetrate through the covering dielectric layer, wherein the substrate electrode is connected with the third contact area, the first contact electrode is connected with the first contact area, the second contact electrode is connected with the second contact area, and the gate electrode is connected with the gate conductor.
Optionally, when the bidirectional power device is turned off, the shield gate depletes charges in the first sub-doped region and the second sub-doped region through the shield dielectric layer, so as to improve a withstand voltage characteristic of the bidirectional power device.
According to the bidirectional power device and the manufacturing method thereof provided by the embodiment of the invention, the first doped region is formed in the epitaxial layer, the first doped region is divided into the first sub-doped region and the second sub-doped region which are alternated by the groove, and the first contact region and the second contact region are respectively formed in the first sub-doped region and the second sub-doped region, so that the two doped regions of the bidirectional power device are formed, and the two doped regions are the source region and the drain region, so that the area of the device is reduced.
More specifically, the first doped region is typically deeper, and higher diffusion temperatures and longer diffusion times are required to achieve deeper junction depths. Therefore, the first doping region is formed in the first step of the manufacturing method according to the requirements of product parameters, and the requirements of product structures and parameters can be realized by selecting proper doping conditions. Under the condition that the junction depth requirement of the first doped region is shallow, the first doped region can be formed without the first step of the manufacturing method, and the first doped region can also be annealed in the annealing process of other doped regions in the subsequent manufacturing method, so that the requirements of the junction depth and parameters required by the device structure are met.
Furthermore, the thickness of the shielding dielectric layer is set to be a structure which gradually becomes thicker from the opening of the groove to the bottom end of the groove, so that the part of the shielding dielectric layer close to the gate dielectric layer (close to the real gate oxide) is thickened, and the withstand voltage of the transverse electric field can be further improved.
Furthermore, an attachment surface of a shielding dielectric layer is provided at the upper part of the groove, an attachment surface of a gate dielectric layer is provided at the lower part of the groove, a control gate and a shielding gate are respectively formed at the lower part and the upper part of the groove, the control gate and the shielding gate are contacted with each other, the control gate, the source region, the drain region and the channel are respectively separated by the gate dielectric layer, the shielding gate, the source region and the drain region are respectively separated by the shielding dielectric layer, when the bidirectional power device is cut off, the shielding gate exhausts charges of the source region and the drain region through the shielding dielectric layer, and the voltage resistance of; and under the condition that the bidirectional power device is conducted, the source region, the drain region, the second doped region and the epitaxial layer provide a low-impedance conduction path.
Further, when the bidirectional power device is conducted, the substrate electrode connected with the substrate is in short circuit with one of the first contact electrode and the second contact electrode, and bidirectional selection of the current direction is achieved. Under the condition that the substrate electrode is in short circuit with the first contact electrode, current flows to the first contact electrode from the second contact electrode through the second type sub-doping area, the channel area and the first type sub-doping area in sequence; under the condition that the substrate electrode is in short circuit with the second contact electrode, current flows to the second contact electrode from the first contact electrode through the first type sub-doping area, the channel area and the second type sub-doping area in sequence.
Further, the channel length, and thus the channel resistance, may be reduced by reducing the width of the trench.
Furthermore, the device adopts a longitudinal control grid field structure, makes full use of a charge balance mechanism, and effectively improves the conduction efficiency and reduces the chip size by making the drift region resistance small under the condition of meeting the withstand voltage requirement.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description only relate to some embodiments of the present application and are not limiting on the present application.
Fig. 1 shows a circuit schematic of a prior art bi-directional power device.
Fig. 2 shows a circuit schematic of a bi-directional power device of an embodiment of the invention.
Fig. 3a to 3p show block diagrams of the method of manufacturing a bidirectional power device according to an embodiment of the invention at some stages.
Detailed Description
The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, certain well known components may not be shown. For simplicity, the semiconductor structure obtained after several steps can be described in one figure.
It will be understood that when a layer or region is referred to as being "on" or "over" another layer or region in describing the structure of the device, it can be directly on the other layer or region or intervening layers or regions may also be present. And, if the device is turned over, that layer, region, or regions would be "under" or "beneath" another layer, region, or regions.
If for the purpose of describing the situation directly on another layer, another area, the expressions "directly on … …" or "on … … and adjacent thereto" will be used herein.
In the following description, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of the devices are described in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.
The present invention may be embodied in various forms, some examples of which are described below.
Fig. 2 shows a circuit schematic of a bi-directional power device of an embodiment of the invention.
The bidirectional power device of the embodiment of the invention is formed by one transistor and has a bidirectional conduction function. As shown in fig. 2, the bidirectional power device includes: a substrate Sub, two output poles S1 and S2 located on the substrate Sub, and two parasitic body diodes D1 and D2. When the output electrode S2 and the substrate Sub are in short circuit, a high voltage is applied to the grid G, the voltage is higher than the threshold voltage of the bidirectional power device, the bidirectional power device is conducted, and current flows from the output electrode S1 to the output electrode S2; when the output electrode S1 and the substrate Sub are in short circuit, a high voltage is applied to the grid G, the voltage is higher than the threshold voltage of the bidirectional power device, the bidirectional power device is conducted, and current flows from the output electrode S2 to the output electrode S1; when the substrate Sub is connected to zero voltage, a low voltage is applied to the gate G, and the voltage is lower than the threshold voltage, so that the bidirectional power device is turned off. In the embodiment of the present invention, the bidirectional power device is a trench type device, and may be a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), an IGBT device, or a diode. However, the present invention is not limited thereto.
Fig. 3a to 3p show block diagrams of the method of manufacturing a bidirectional power device according to an embodiment of the invention at some stages. It should be noted that the structure of each step of the structure diagram disclosed in this embodiment is not necessarily in a cross section, and may be placed in different regions and directions of a product through a specific design according to the requirements of a product layout, where the illustration diagram only includes 4 trenches, a source region and a drain region, and in an actual product, the number of the trenches, the source region and the drain region may be changed, and when one of the first-type sub-doped region and the second-type sub-doped region is used as a source region, the other is used as a drain region, that is, through different working and application occasions, the source region and the drain region of the structure may be interchanged. In the embodiment of the present disclosure, in order to facilitate understanding of the forming process of the device structure in each step in the embodiment process, the main structure of the device is shown in a cross section in the embodiment of the present disclosure, but it is not intended to limit the claims, and any person skilled in the art may make possible changes and modifications without departing from the spirit and scope of the embodiment, so the scope of the embodiment should be determined by the scope defined by the claims of the present disclosure.
In the present embodiment, the manufacturing process starts with a semiconductor layer having a specific doping type, as shown in fig. 3a, the semiconductor layer includes a substrate 101 and an epitaxial layer 110 located on the substrate 101, wherein the substrate 101 includes a silicon substrate, a silicon germanium substrate, a group iii-v compound substrate or other semiconductor material substrates known to those skilled in the art, and a silicon substrate is used in the present embodiment. More specifically, the silicon substrate employed in the present embodiment may be formed with semiconductor devices such as MOS field effect transistors, IGBT insulated gate field effect transistors, schottky diodes, and the like.
The semiconductor layer having a specific doping type refers to an N-type or P-type substrate 101 doped with a certain amount of impurities according to product characteristics and an N-type or P-type epitaxial layer 110 having a certain resistivity and thickness. For example, in the case that the bidirectional power device is an NMOS transistor, the doping types of the substrate 101 and the epitaxial layer 110 are P-type; when the bidirectional power device is a PMOS, the doping types of the substrate 101 and the epitaxial layer 110 are N-type.
Further, a first doped region 120 is formed in the epitaxial layer 110, as shown in fig. 3 a.
In this step, the first doped region 120 is formed by one or more of implantation doping, diffusion source doping and coating doping, wherein the implantation energy is 20 to 800KeV and the implantation dose is 1E11 to 1E16cm2The annealing temperature is 600-1200 ℃.
In this embodiment, the bidirectional power device has a first trench region 103 and a second trench region 104, the first doped region 120 is located in the first trench region 103, and the doping type is opposite to that of the epitaxial layer 110, for example, in the case that the bidirectional power device is a PMOS transistor, the doping type of the first doped region 120 is P-type, and the doping impurities generally adopt B +; in the case where the bidirectional power device is an NMOS, the doping type of the first doped region 120 is an N type, and the doping impurity is usually As + or P +. The first trench region 103 is separated from the second trench region 104, and the second trench region 104 is located in the epitaxial layer 110.
Further, first recesses 111a1 to 111d1 are formed in the semiconductor layer, as shown in fig. 3 b.
In this step, for example, a barrier layer is formed on the surface of the epitaxial layer 110 by using thermal oxidation or deposition, and the barrier layer is selectively removed by photolithography and etching processes, so that a region to be formed with a trench is exposed to form an opening, so as to expose a portion of the first doping region 120 and the epitaxial layer 110. The semiconductor layer is then etched through the openings to form first recesses 111a1 through 111d 1.
FIG. 3b is a cross-sectional view, wherein the first recess 111a1 extends from the surface of the first doped region 120 toward the substrate 101, and has a bottom located in the first doped region 120; the first recesses 111b1 and 111c1 are respectively located at two sides of the first doped region and adjacent to the first doped region 120, and the first recess 111d1 is located in the epitaxial layer 110 and does not contact the first doped region 120.
In the present embodiment, the widths of the first recesses 111a1 to 111d1 are determined according to the product structure and process capability, and the depths h1 of the first recesses 111a1 to 111d1 are determined according to parameters such as the withstand voltage of the product. Specifically, the width of the first concave parts 111a 1-111 d1 is 0.05-5 μm, and the depth h1 is 0.1-50 μm. However, the embodiment of the present invention is not limited thereto, and those skilled in the art may match the depth h1 and the width of the first recess according to the requirements of the product, such as epitaxy, withstand voltage, doping, gate oxide thickness, and the like.
Further, a dielectric material is formed on the surface of the epitaxial layer 110 and in the first recesses 111a1 through 111d1, and the first dielectric layer 102 is formed by filling the first recesses 111a1 through 111d1 with the dielectric material, as shown in fig. 3 c.
In this step, the material of the first dielectric layer 102 may be undoped silicon dioxide, silicon nitride, silicon oxynitride, or the like, or one or more combinations of the silicon oxide, silicon nitride, silicon oxynitride, or the like. The first dielectric layer 102 is formed by an oxide growth process, a chemical vapor deposition process, or a combination of one or more of LPCVD, SACVD, HTO, and SRO.
In the present embodiment, the material of the first dielectric layer 102 is silicon dioxide, the thickness of which is mainly determined by the process of filling the trench, the thickness of which is usually greater than half of the width of the first recess, and the portion of the first dielectric layer 102 filled in the first recess will be used as the shielding dielectric layer 151 in the subsequent steps.
Further, a portion of the first dielectric layer 102 is removed to expose the bottom ends of the first recesses 111a 1-111 d1, as shown in fig. 3 d.
In this step, the first dielectric layer 102 partially filled in the first recesses 111a 1-111 d1 is removed by, for example, photolithography and etching processes, so as to expose the bottom ends of the first recesses 111a 1-111 d1, and the dielectric material remaining on the sidewalls of the first recesses 111a 1-111 d1 forms a shielding dielectric layer 151 with a thickness T1 in the subsequent step, wherein the range of T1 includes
Further, second recesses 111a2 to 111d2 are formed to extend from the bottom ends of the first recesses 111a1 to 111d1 to the substrate 101, respectively, and the bottom ends of the second recesses 111a2 to 111d2 are all located in the epitaxial layer 110, wherein the first recess 111a1 and the second recess 111a2 form a trench 111a, the first recess 111b1 and the second recess 111b2 form a trench 111b, the first recess 111c1 and the second recess 111c 2 form a trench 111c, and the first recess 111d1 and the second recess 111d2 form a trench 111d, as shown in fig. 3 e.
In this step, the second recesses 111a2 to 111d2 are formed by removing a portion of the first doped region 120 and the epitaxial layer 110 at the bottom ends of the first recesses 111a1 to 111d1, for example, by an etching process, wherein the bottom ends of the second recesses have a depth h2 from the bottom ends of the first recesses, which is in a range of 0.1 to 5 μm.
Fig. 3e is a cross-sectional view showing a total of 4 grooves, including the groove 111a, the groove 111b, the groove 111c, and the groove 111 d. The trenches 111a, 111b, and 111c are located in the first trench region 103, the bottoms of the trenches 111a, 111c, and 111d are located in the epitaxial layer 110, and the trench 111d is located in the second trench region 104. Specifically, the trench 111a is located in the first doping region 120, and the trenches 111b and 111c are located at the boundary of the first doping region 120, and the three trenches divide the first doping region 120 into a first sub-doping region 121 and a second sub-doping region 122. The trench 111d is located in the epitaxial layer 110 and is separated from the first doped region 120. The trench 111b and the trench 111c are respectively located at two sides of the first doped region 120 and are in contact with the first doped region 120, for example, the trench 111c is in contact with the second-type sub-doped region 122, and the trench 111b is in contact with the first-type sub-doped region 121. The groove 111c is located between the grooves 111a and 111 d. In a plane perpendicular to the thickness direction of the substrate 101, the trench 111a, the trench 111b, the trench 111c in the first trench region 103 and the trench 111d in the second trench region 104 are communicated, for example, sequentially in an "S" shape, but the implementation of the present invention is not limited thereto, and one skilled in the art may separate at least two trenches as needed.
In the present embodiment, a person skilled in the art may make other arrangements as required to the number of trenches located in the first trench region 103, so that the plurality of trenches separate the first doping region 120 into the first sub-doping region 121 and the second sub-doping region 122 alternately.
Further, a channel region 130 is formed in the epitaxial layer 110 through the bottom of the plurality of trenches 111, as shown in fig. 3 f.
In this step, a channel region 130 is formed at the bottom of the trench 111 by, for example, a zero-angle implantation process for adjusting the threshold voltage of the device, wherein the implantation energy is 20 to 800KeV, and the implantation dose is 1E11 to 1E16cm2The annealing temperature is 600-1200 ℃.
In the present embodiment, the channel region 130 is in contact with the first-type sub-doping region 121 and the second-type sub-doping region 122, respectively, and the doping types of the channel region 130 and the first-type sub-doping region 121 and the second-type sub-doping region 122 are the same. For example, in the case that the bidirectional power device is a PMOS transistor, the doping type of the channel region 130 is P-type, and the doping impurities generally adopt B +; in the case where the bidirectional power device is an NMOS, the doping type of the channel region 130 is an N type, and the doping impurity is usually As + or P +.
Further, a first sacrificial layer 203 is formed in the trench 111, as shown in fig. 3 g.
In this step, for example, the trench 111 is filled with a material such as undoped silicon dioxide, silicon nitride, silicon oxynitride, or one or more combinations of the materials such as silicon oxide, silicon nitride, silicon oxynitride, or the like, and in some other embodiments, the trench 111 is filled with a photoresist, which may be a positive photoresist or a negative photoresist. Under the condition that the material of the first sacrificial layer 203 is photoresist, the first sacrificial layer 203 extends from the bottom end of the second recess of the trench 111 to the surface of the epitaxial layer 110 by exposure and development, and covers a part of the first dielectric layer 102 located in the first recess of the trench 111, wherein the depth of the surface of the first sacrificial layer 203 from the surface of the epitaxial layer 110 is h3, the range of h3 includes 0-30 μm, and the depth h3 needs to be matched with the epitaxy, withstand voltage, doping, gate oxide thickness and the like of a product.
Further, the first dielectric layer 102 not covered by the first sacrificial layer 203 is thinned, and the first dielectric layer 102 covered and protected by the first sacrificial layer 203 forms a first step portion 151a, as shown in fig. 3 h.
In this step, for example, a wet etching process is used for thinning, the dielectric material of the first step portion 151a is remained because of being shielded by the first sacrificial layer 203, and after the thinning step is completed, the first sacrificial layer 203 is removed by a wet removal process or a dry photoresist removal and wet photoresist removal process.
In the present embodiment, the range of the thickness T1 of the first step portion 151a includes:
the distance range from the bottom end of the first step 151a to the surface of the epitaxial layer 110 includes: 0.1 to 50 μm.
Further, a second sacrificial layer 204 is formed in the trench 111, as shown in fig. 3 i.
In this step, for example, the trench 111 is filled with a material such as undoped silicon dioxide, silicon nitride, silicon oxynitride, or one or more combinations of the materials such as silicon oxide, silicon nitride, silicon oxynitride, or the like, and in some other embodiments, the trench 111 is filled with a photoresist, which may be a positive photoresist or a negative photoresist. In the case that the material of the second sacrificial layer 204 is photoresist, the second sacrificial layer is extended from the bottom end of the second recess of the trench 111 to the surface of the epitaxial layer 110 by exposure and development, and covers the first step portion 151a and the first dielectric layer 102 partially located in the first recess of the trench 111, wherein the depth of the surface of the second sacrificial layer 204 from the surface of the epitaxial layer 110 is h4, the range of h4 includes 0-20 μm, and the depth h4 needs to be matched with the thickness of the product, such as epitaxy, withstand voltage, doping, gate oxide, and the like.
Further, the first dielectric layer 102 not covered by the second sacrificial layer 204 is thinned to form a third step portion 151c, and the dielectric material covered and protected by the second sacrificial layer 204 except the first step portion 151a forms a second step portion 151b, as shown in fig. 3 j.
In this step, for example, a wet etching process is used for thinning, the dielectric materials of the first step portion 151a and the second step portion 151b are remained because of being shielded by the second sacrificial layer 204, and after the thinning step is completed, the second sacrificial layer 204 is removed by a wet removal process or a dry photoresist removal and wet photoresist removal process.
In this embodiment, the first step portion 151a, the second step portion 151b, and the third step portion 151c constitute the shielding dielectric layer 151, wherein a range of a thickness T2 of the second step portion 151b includes:
the distance range from the bottom end of the second step 151b to the surface of the epitaxial layer 110 includes: 0-30 μm, and the thickness T3 of the third step 151c is in the range:
the distance range from the bottom end of the third step 151c to the surface of the epitaxial layer 110 includes: 0 to 20 μm.
In this embodiment, the first dielectric layer 102 after two selective thinning processes is stepped on the sidewall of the first recess 111a, and the thickness changes in a gradient manner from the surface of the epitaxial layer 110 to the substrate 101: t3< T2< T1.
However, the embodiment of the present invention is not limited thereto, and a person skilled in the art may perform other settings on the number of the step portions according to needs, for example, filling the sacrificial layer and thinning the first dielectric layer N times so that the shielding dielectric layer 151 has a plurality of step-like thickness variations.
Further, a gate dielectric layer 152 is formed on the inner surface of the second recess 111b, as shown in fig. 3 k.
In this step, the material of the gate dielectric layer 152 may be undoped silicon dioxide, silicon nitride, silicon oxynitride, or the like, or one or more combinations of the silicon oxide, silicon nitride, silicon oxynitride, and the like. The gate dielectric layer 152 is formed by an oxide growth process, a chemical vapor deposition process, or a combination of one or more of LPCVD, SACVD, HTO, and SRO.
In the present embodiment, the gate dielectric layer 152 is formed by an oxide growth process, the thickness T4 is required to be combined with the threshold voltage required by the product, the trench depth, the well doping concentration and the junction depth in the device structure are matched, and T4 is smaller than T1. In the present embodiment, the range of T4 includes:
during the growth of gate dielectric layer 152, channel region 130 may be annealed. In the present embodiment, the first concave portion of the trench 111 and the shielding dielectric layer 151 mainly perform a voltage division function, and the second concave portion 111b of the trench 111 and the gate dielectric layer 152 mainly perform a channel adjustment function.
In this embodiment, the shielding dielectric layer 151 is graded, and particularly, the shielding dielectric layer 151 at the bottom (the first step portion 151a close to the gate dielectric layer 152) is thickened, so that the withstand voltage of the lateral electric field can be further improved. However, the embodiment is not limited thereto, and those skilled in the art may perform other arrangements, such as increasing or decreasing, on the gradient order of the shielding dielectric layer 151 as needed.
In some other embodiments, the thickness of the shielding dielectric layer 151 gradually increases or decreases from the surface of the epitaxial layer 110 toward the substrate 101. In other embodiments, the thickness of the shielding dielectric layer 151 may vary uniformly, but it is sufficient that a portion of the shielding dielectric layer 151 has a thickness greater than that of the gate dielectric layer 152.
Further, a gate conductor 153 is formed in the trench 111 and on the first dielectric layer 102, as shown in fig. 3 l.
In this step, a conductive material 105 is filled in the trench 111 and on the first dielectric layer 102, for example, by a deposition process. Wherein the conductive material 105 comprises in-situ doped polysilicon, in some other embodiments undoped polysilicon may be deposited first, followed by implantation of dopant impurities, and the conductive material 105 is used in subsequent steps to form the gate conductor 153.
In the present embodiment, in the case that the bidirectional power device is a PMOS transistor, the doping type of the gate conductor 153 is P-type; in the case where the bi-directional power device is an NMOS, the doping type of the gate conductor 153 is N-type. Gate conductor 153 includes a control gate and a shield gate connected to each other, the shield gate contacting shield dielectric layer 151 and the control gate contacting gate dielectric layer 152.
Further, the conductive material 105 located above the first dielectric layer 102 is removed, as shown in fig. 3 m.
In this step, the conductive material 105 located above the epitaxial layer 110 is removed, for example, by using one or a combination of dry etching, wet etching and CMP processes, so that the first dielectric layer 102 located on the surface of the epitaxial layer 110 is exposed.
Further, the first dielectric layer 102 and the conductive material 105 over the epitaxial layer 110 are removed, as shown in fig. 3 n.
In this step, for example, one or a combination of a dry etching process, a wet etching process and a CMP process is used to remove the first dielectric layer 102 located above the epitaxial layer 110, so that the surface of the epitaxial layer 110 is exposed, the first dielectric layer 102 remaining in the trench 111 serves as a shielding dielectric layer 151, the conductive material 105 located in the trench 111 serves as a gate conductor 153, a portion located at the bottom of the trench 111 and in contact with the gate dielectric layer 152 is a control gate conductor, and a portion located at the upper half of the trench 111 and in contact with the shielding dielectric layer 151 is a shielding gate conductor.
In some embodiments, the conductive material above the epitaxial layer 110 is removed by CMP and dry etching process, or by dry etching process alone. The removal of the first dielectric layer 102 over the epitaxial layer 110 is typically performed using a CMP wetting process.
Further, a first contact region 161 is formed in the first type sub-doping region 121, a second contact region 162 is formed in the second type sub-doping region 122, and a third contact region 163 is formed in the epitaxial layer 110, as shown in fig. 3 n.
In this step, the first-type sub-doping region 121, the second-type sub-doping region 122 and the epitaxial layer 110 are doped by implantation and diffusion, for example, through a photolithography mask. Wherein the implantation energy of the doping process is 20-180 Kev, and the implantation dosage is 1E 11-1E 16cm2。
In the present embodiment, the doping types of the first contact region 161 and the second contact region 162 are the same as the doping type of the first sub-doping region 121, and the doping type of the third contact region 163 is the same as the doping type of the epitaxial layer 110. For example, when the bidirectional power device is a PMOS, the doping types of the first contact region 161 and the second contact region 162 are P-type, and the doping type of the third contact region 163 is N-type; when the bidirectional power device is an NMOS, the doping types of the first contact region 161 and the second contact region 162 are N-type, and the doping type of the third contact region 163 is P-type. The P-type contact region is doped with B +/BF2+ and the N-type contact region is doped with As + and P +.
Further, a capping dielectric layer 106 is formed on the epitaxial layer 110, and a plurality of contact holes 106a are formed through the capping dielectric layer 106, as shown in fig. 3 o.
In this step, the capping dielectric layer 106 is formed, for example, by a chemical vapor deposition process including one or a combination of LPCVD, SACVD, HTO, and SRO. The material of the capping dielectric layer 106 includes one or more of undoped silicon dioxide, boron-doped silicon dioxide, phosphorus-doped silicon dioxide, silicon dioxide doped with both boron and phosphorus, undoped polysilicon, silicon nitride, and silicon oxynitride material. Followed by forming contacts, e.g. by photolithography and etching processesA hole 106a, wherein the contact hole 106a penetrates through the capping dielectric layer 106, and the depth h5 of the bottom of the contact hole from the surface of the epitaxial layer 110 is within the range
In the present embodiment, the positions of the contact holes 106a correspond to the first contact region 161, the second contact region 162, the third contact region 163, and the trench 111d separated from the first sub-doping region 121 and the second sub-doping region 122, respectively.
Further, a substrate electrode 173, a first contact electrode 171, a second contact electrode 172, and a gate electrode 174 are formed through the capping dielectric layer 106, as shown in fig. 3 n.
In this step, for example, a metal conductive layer is first deposited on the capping dielectric layer 106, and a substrate electrode 173, a first contact electrode 171, a second contact electrode 172, and a gate electrode 174 are formed by photolithography and etching processes. The first contact electrode 171 is connected to the first contact region 161, the second contact electrode 172 is connected to the second contact region 162, the substrate electrode 173 is connected to the third contact region 163, and the gate electrode 174 is connected to the gate conductor 153. The first contact electrode 171 and the second contact electrode 172 are a source electrode and a drain electrode, and may be interchanged.
In this embodiment, the material of the metal conductive layer may be one or a combination of metals including Ti, TiN, TiSi, W, Al, AlSi, AlCu, AlSiCu, Cu, Ni, and the like. Wherein, the metal etching adopts one or more combination of wet etching and plasma etching to form the substrate electrode 173, the first contact electrode 171, the second contact electrode 172 and the gate electrode 174, and the voltage or current is applied through these 4 electrodes to realize the performance of the device.
In the present embodiment, the position of the gate electrode 174 corresponds to the trench 111d, however, the present embodiment is not limited thereto, and since the plurality of trenches 111a to 111d communicate such that the gate conductors 153 in the plurality of trenches 111a to 111d are connected to each other, the position of the gate electrode 174 may also correspond to the trench 111a and/or the trench 111b and/or the trench 111 c.
Furthermore, the first embodiment of the present invention discloses a bidirectional power device and a manufacturing method thereof, which can further optimize a wiring method and a method by increasing metal levels, so as to minimize resistance in the application process of the device and reduce signal interference to the maximum extent.
Further, the first embodiment of the present invention discloses a bidirectional power device and a method for manufacturing the same, which can be combined with the practical application of products to add structures such as passivation layers and polyimide, thereby protecting the device and enhancing the reliability.
Further, the first embodiment of the present invention discloses a bidirectional power device and a manufacturing method thereof, which can form a structure required by a product through a subsequent process such as thinning, back evaporation, and the like, thereby realizing a function.
Further, the bidirectional power device with bidirectional conduction function according to the first embodiment of the present invention can lead out the gate electrode 174, the substrate electrode 173, the first contact electrode 171, and the second contact electrode 172 from the surface of the semiconductor structure, so as to meet the packaging requirements of Chip Scale Package (CSP).
Further, the first embodiment of the present invention discloses a bidirectional power device and a method for manufacturing the same, which can be applied to products such as power MOSFET, CMOS, BCD, high-power transistor, IGBT, schottky, and the like.
According to the bidirectional power device and the manufacturing method thereof provided by the embodiment of the invention, the first doped region is formed in the epitaxial layer, the first doped region is divided into the first sub-doped region and the second sub-doped region which are alternated by the groove, and the first contact region and the second contact region are respectively formed in the first sub-doped region and the second sub-doped region, so that the two doped regions of the bidirectional power device are formed, and the two doped regions are the source region and the drain region, so that the area of the device is reduced.
More specifically, the first doped region is typically deeper, and higher diffusion temperatures and longer diffusion times are required to achieve deeper junction depths. Therefore, the first doping region is formed in the first step of the manufacturing method according to the requirements of product parameters, and the requirements of product structures and parameters can be realized by selecting proper doping conditions. Under the condition that the junction depth requirement of the first doped region is shallow, the first doped region can be formed without the first step of the manufacturing method, and the first doped region can also be annealed in the annealing process of other doped regions in the subsequent manufacturing method, so that the requirements of the junction depth and parameters required by the device structure are met.
Furthermore, the thickness of the shielding dielectric layer is set to be a structure which gradually becomes thicker from the opening of the groove to the bottom end of the groove, so that the part of the shielding dielectric layer close to the gate dielectric layer (close to the real gate oxide) is thickened, and the withstand voltage of the transverse electric field can be further improved.
Furthermore, an attachment surface of a shielding dielectric layer is provided at the upper part of the groove, an attachment surface of a gate dielectric layer is provided at the lower part of the groove, a control gate and a shielding gate are respectively formed at the lower part and the upper part of the groove, the control gate and the shielding gate are contacted with each other, the control gate, the source region, the drain region and the channel are respectively separated by the gate dielectric layer, the shielding gate, the source region and the drain region are respectively separated by the shielding dielectric layer, when the bidirectional power device is cut off, the shielding gate exhausts charges of the source region and the drain region through the shielding dielectric layer, and the voltage resistance; and under the condition that the bidirectional power device is conducted, the source region, the drain region, the second doped region and the epitaxial layer provide a low-impedance conduction path.
Further, when the bidirectional power device is conducted, the substrate electrode connected with the substrate is in short circuit with one of the first contact electrode and the second contact electrode, and bidirectional selection of the current direction is achieved. Under the condition that the substrate electrode is in short circuit with the first contact electrode, current flows to the first contact electrode from the second contact electrode through the second type sub-doping area, the channel area and the first type sub-doping area in sequence; under the condition that the substrate electrode is in short circuit with the second contact electrode, current flows to the second contact electrode from the first contact electrode through the first type sub-doping area, the channel area and the second type sub-doping area in sequence.
Further, the channel length, and thus the channel resistance, may be reduced by reducing the width of the trench.
Furthermore, the device adopts a longitudinal control grid field structure, makes full use of a charge balance mechanism, and effectively improves the conduction efficiency and reduces the chip size by making the drift region resistance small under the condition of meeting the withstand voltage requirement.
The embodiments of the present invention have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present invention. The scope of the invention is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the invention, and these alternatives and modifications are intended to fall within the scope of the invention.
Claims (31)
1. A method of manufacturing a bi-directional power device, comprising:
forming a first doped region in the semiconductor layer;
forming a plurality of grooves of a first groove area, wherein the grooves of the first groove area are positioned in the first doping area and divide the first doping area into a first sub-doping area and a second sub-doping area which are alternated;
forming a gate dielectric layer covering the lower side walls of the plurality of grooves of the first groove area;
forming a shielding medium layer covering the upper side walls of the plurality of grooves of the first groove area; and
forming gate conductors in contact with the gate dielectric layer and the shield dielectric layer respectively in the plurality of trenches of the first trench region,
the grid conductor comprises a control grid and a shielding grid which are connected, the control grid is contacted with the grid dielectric layer, the shielding grid is contacted with the shielding dielectric layer,
the thickness of the shielding dielectric layer is not consistent, and the thickness of at least part of the shielding dielectric layer is larger than that of the gate dielectric layer.
2. The manufacturing method according to claim 1, wherein in a case where one of the first type sub-doping region and the second type sub-doping region serves as a source region, the other of the first type sub-doping region and the second type sub-doping region serves as a drain region, and the source region and the drain region are interchangeable.
3. The manufacturing method according to claim 1, wherein, in the plurality of trenches in the first trench region, the thickness of the shielding dielectric layer becomes gradually thicker or thinner along a direction from an opening of the trench to a bottom.
4. The manufacturing method of claim 1, wherein the shielding dielectric layer comprises a plurality of step portions connected in sequence, and the thickness of the shielding dielectric layer is changed in a gradient manner along the direction from the opening to the bottom of the trench in the plurality of trenches of the first trench region.
5. The method of manufacturing of claim 1, further comprising forming a trench of a second trench region in the semiconductor layer and spaced apart from the first doped region,
the gate dielectric layer is further formed on the lower side wall of the trench of the second trench region, the shielding dielectric layer is further formed on the upper side wall of the trench of the second trench region, the gate conductor is further formed in the trench of the second trench region and is in contact with the gate dielectric layer and the shielding dielectric layer respectively,
the groove of the first groove region is communicated with the groove of the second groove region, and the grid conductor in the groove of the first groove region is connected with the grid conductor in the groove of the second groove region.
6. The manufacturing method according to claim 5, wherein the trenches of the first trench region are identical in structure to the trenches of the second trench region.
7. The manufacturing method according to any one of claims 1 to 6, wherein the step of forming the plurality of trenches of the first trench region includes:
forming a plurality of first recesses in the first doped region;
filling a dielectric material in the first concave part; and
removing a portion of the dielectric material in each of the first recesses and removing the first doped region and a portion of the semiconductor layer under the first recess via a bottom end of each of the first recesses to form a second recess, a bottom end of the second recess being in the semiconductor layer,
the plurality of trenches of the first trench region are constituted by the respective first concave portions and the second concave portions.
8. The manufacturing method according to claim 7, wherein a depth of the first concave portion ranges from 0.1 to 50 μm, and a distance from the bottom end of the second concave portion to the bottom end of the first concave portion ranges from 0.1 to 5 μm.
9. The method of manufacturing of claim 7, wherein forming a shield dielectric layer covering upper sidewalls of the plurality of trenches of the first trench region after forming the second recess comprises:
forming a first sacrificial layer, wherein the first sacrificial layer extends from the bottom end of the second concave part to the surface of the semiconductor layer and covers a part of the dielectric material in the first concave part;
thinning the dielectric material which is positioned in the first concave part and not covered by the first sacrificial layer, wherein the dielectric material protected by the first sacrificial layer forms a first step part;
replacing the first sacrificial layer with a second sacrificial layer, wherein the second sacrificial layer extends from the bottom end of the second concave part to the surface of the semiconductor layer and covers the first step part and the medium material partially positioned in the first concave part;
thinning the dielectric material which is positioned in the first concave part and not covered by the second sacrificial layer to form a third step part, and forming a second step part by the dielectric material which is protected by the second sacrificial layer except the first step part.
10. The manufacturing method according to claim 9, wherein a thickness range of the first step portion includes:
the thickness range of the second step portion includes:
the thickness range of the third step portion includes:
and the thickness of the gate dielectric layer is smaller than that of the first step part.
11. The manufacturing method according to claim 9, wherein a distance range from a bottom end of the first step portion to a surface of the semiconductor layer includes: 0.1-50 μm, the distance range from the bottom end of the second step part to the surface of the semiconductor layer comprises: 0-30 μm, the distance range from the bottom end of the third step part to the surface of the semiconductor layer comprises: 0 to 20 μm.
12. The manufacturing method according to any one of claims 1 to 6, further comprising:
forming a first contact region in the first type doped region;
forming a second contact region in the second type sub-doping region; and
a third contact region is formed in the semiconductor layer.
13. The manufacturing method according to any one of claims 1 to 6, further comprising forming a channel region adjacent to the control gate in the semiconductor layer.
14. The manufacturing method according to claim 12, further comprising:
forming a covering dielectric layer on the surface of the semiconductor layer; and
and forming a substrate electrode, a first contact electrode, a second contact electrode and a gate electrode which penetrate through the covering dielectric layer, wherein the substrate electrode is connected with the third contact area, the first contact electrode is connected with the first contact area, the second contact electrode is connected with the second contact area, and the gate electrode is connected with the gate conductor.
15. The manufacturing method according to any one of claims 1 to 6, wherein, in a case where the bidirectional power device is turned off, the shielding gate depletes charges of the first type sub-doped region and the second type sub-doped region through the shielding dielectric layer so as to improve a withstand voltage characteristic of the bidirectional power device.
16. A bi-directional power device comprising:
a semiconductor layer;
a first doped region in the semiconductor layer;
the plurality of grooves of the first groove area are positioned in the first doping area and divide the first doping area into a first sub-doping area and a second sub-doping area which are alternated;
the gate dielectric layer covers the lower side walls of the plurality of grooves of the first groove area;
the shielding dielectric layer covers the upper side walls of the plurality of grooves of the first groove area; and
a gate conductor in the plurality of trenches of the first trench region and in contact with the gate dielectric layer and the shield dielectric layer, respectively,
the grid conductor comprises a control grid and a shielding grid which are connected, the control grid is contacted with the grid dielectric layer, the shielding grid is contacted with the shielding dielectric layer,
the thickness of the shielding dielectric layer is not consistent, and the thickness of at least part of the shielding dielectric layer is larger than that of the gate dielectric layer.
17. The bidirectional power device of claim 16, wherein, with one of the first and second sub-doped regions being a source region, the other of the first and second sub-doped regions being a drain region, and the source and drain regions being interchangeable.
18. The bidirectional power device of claim 16, wherein the thickness of the shield dielectric layer is gradually thicker or thinner in the plurality of trenches of the first trench region in a direction from the opening to the bottom of the trench.
19. The bidirectional power device of claim 16, wherein the shielding dielectric layer comprises a plurality of step portions connected in sequence, and the thickness of the shielding dielectric layer varies in a gradient manner along a direction from the opening to the bottom of the trench in the plurality of trenches of the first trench region.
20. The bi-directional power device of claim 16, wherein said shield dielectric layer comprises a first step portion, a second step portion and a third step portion connected in sequence, said third step portion being adjacent to an opening of a trench among a plurality of trenches of said first trench region,
the thicknesses of the first step portion, the second step portion and the third step portion are sequentially decreased progressively.
21. The bi-directional power device of claim 20, wherein the range of thicknesses of the first step portion comprises:
the thickness range of the second step portion includes:
the thickness range of the third step portion includes:
and the thickness of the gate dielectric layer is smaller than that of the first step part.
22. The bidirectional power device of claim 20, wherein a range of distances from a bottom end of the first step to the trench opening comprises: 0.1-50 μm, the distance range from the bottom end of the second step part to the opening of the groove comprises: 0 ~ 30 mu m, the distance scope of the bottom of third step portion to slot opening includes: 0 to 20 μm.
23. The bi-directional power device of claim 16, further comprising a trench of a second trench region in said semiconductor layer and spaced apart from said first doped region,
the gate dielectric layer also covers the lower side wall of the groove of the second groove region, the shielding dielectric layer also covers the upper side wall of the groove of the second groove region, the gate conductor is also positioned in the groove of the second groove region and is respectively contacted with the gate dielectric layer and the shielding dielectric layer,
the groove of the first groove region is communicated with the groove of the second groove region, and the grid conductor in the groove of the first groove region is connected with the grid conductor in the groove of the second groove region.
24. The bidirectional power device of claim 23, wherein the trenches of the first trench region are identical in structure to the trenches of the second trench region.
25. The bidirectional power device of any of claims 16-24, wherein the plurality of trenches of the first trench region comprise:
a first recess in the first doped region; and
and the second concave part is positioned in the first doping region and part of the semiconductor layer, and the second concave part is positioned below the first concave part and is communicated with the first concave part.
26. The bidirectional power device of claim 25, wherein the depth of the first recess ranges from 0.1 to 50 μm, and the distance from the bottom end of the second recess to the bottom end of the first recess ranges from 0.1 to 5 μm.
27. The bi-directional power device of claim 25 wherein said shield dielectric layer is located on a sidewall of said first recess and said gate dielectric layer is located on an inner surface of said second recess.
28. The bidirectional power device of any of claims 16-24, further comprising:
the first contact region is positioned in the first-type sub-doping region;
the second contact region is positioned in the second type sub-doping region; and
a third contact region in the semiconductor layer.
29. The bidirectional power device of any of claims 16-24, further comprising a channel region in the semiconductor layer and adjacent to the control gate.
30. The bidirectional power device of claim 28, further comprising:
the covering dielectric layer is positioned on the surface of the semiconductor layer; and
the substrate electrode penetrates through the covering dielectric layer, the first contact electrode, the second contact electrode and the gate electrode, the substrate electrode is connected with the third contact area, the first contact electrode is connected with the first contact area, the second contact electrode is connected with the second contact area, and the gate electrode is connected with the gate conductor.
31. The bidirectional power device of any of claims 16-24, wherein, with the bidirectional power device turned off, the shield gate depletes the charge of the first and second sub-doped regions through the shield dielectric layer to improve the withstand voltage characteristics of the bidirectional power device.
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| CN113838918A (en) * | 2021-09-23 | 2021-12-24 | 电子科技大学 | Super-junction IGBT device structure with carrier concentration enhancement and manufacturing method |
| WO2023019694A1 (en) * | 2021-08-20 | 2023-02-23 | 长鑫存储技术有限公司 | Semiconductor structure and production method therefor |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2023019694A1 (en) * | 2021-08-20 | 2023-02-23 | 长鑫存储技术有限公司 | Semiconductor structure and production method therefor |
| CN113838918A (en) * | 2021-09-23 | 2021-12-24 | 电子科技大学 | Super-junction IGBT device structure with carrier concentration enhancement and manufacturing method |
| CN113838918B (en) * | 2021-09-23 | 2023-10-24 | 电子科技大学 | Super-junction IGBT device structure with carrier concentration enhancement and manufacturing method |
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