CN106601811B - Trench type power transistor - Google Patents

Trench type power transistor Download PDF

Info

Publication number
CN106601811B
CN106601811B CN201510680019.XA CN201510680019A CN106601811B CN 106601811 B CN106601811 B CN 106601811B CN 201510680019 A CN201510680019 A CN 201510680019A CN 106601811 B CN106601811 B CN 106601811B
Authority
CN
China
Prior art keywords
trench
dielectric layer
layer
electrode
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201510680019.XA
Other languages
Chinese (zh)
Other versions
CN106601811A (en
Inventor
李柏贤
杨国良
林家福
林伟捷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sinopower Semiconductor Inc
Original Assignee
Sinopower Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sinopower Semiconductor Inc filed Critical Sinopower Semiconductor Inc
Priority to CN201510680019.XA priority Critical patent/CN106601811B/en
Publication of CN106601811A publication Critical patent/CN106601811A/en
Application granted granted Critical
Publication of CN106601811B publication Critical patent/CN106601811B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

A trench power transistor. The trench gate structure of the trench power transistor is located in an element trench of an epitaxial layer and at least comprises a shielding electrode, a gate electrode and an insulating layer. The insulating layer comprises a first dielectric layer, a second dielectric layer and a third dielectric layer, wherein the third dielectric layer is positioned at the lower half part of the element groove, part of the second dielectric layer positioned at the lower half part of the element groove is clamped between the first dielectric layer and the third dielectric layer, and the dielectric constant of the second dielectric layer is larger than that of the first dielectric layer.

Description

Trench type power transistor
Technical Field
The present invention relates to a power transistor, and more particularly, to a trench power mosfet having a shielding electrode.
Background
Power Metal Oxide semiconductor field effect transistors (Power MOSFETs) are widely used in switching elements of Power devices, such as Power supplies, rectifiers, or low-voltage motor controllers. Most of the current power mosfets adopt a vertical structure design to increase the device density. The power metal oxide semiconductor field effect transistor adopting the vertical structure design is also called a groove type power metal oxide semiconductor field effect transistor, and has the advantage that the operation of elements can be carried out by controlling voltage under the condition of consuming low power.
The operating loss of the power mosfet can be divided into two major categories, i.e., switching loss (switching loss) and conduction loss (reducing loss), wherein the gate/drain capacitance (Cgd) is an important parameter affecting the switching loss. Too high gate/drain capacitance results in increased switching losses, which limits the switching speed of power mosfets and is not suitable for high frequency applications.
In order to improve the above problem and reduce the gate/drain capacitance, in the conventional power mosfet, a shielding electrode (shielding electrode) is additionally formed in the lower half of the gate trench.
However, in the process of manufacturing the trench power mosfet having the shielding electrode structure, after forming the shielding electrode located at the lower half of the gate trench, the dielectric layer formed on the sidewall of the upper half of the gate trench in advance is usually etched away, and a new gate dielectric layer is deposited again. However, in the process of etching the dielectric layer, it is difficult to control the etching depth of the dielectric layer, which results in a hole or gap between the subsequently formed gate dielectric layer and the dielectric layer located on the lower half sidewall of the gate trench. When a voltage is applied to the gate of the trench power mosfet, the holes or gaps may cause a leakage current between the gate and the source, which may cause the electrical performance of the trench power mosfet to be poor.
Disclosure of Invention
The invention provides a trench power transistor, which avoids generating holes or gaps (void) in a trench gate structure by forming an oxide layer and a nitride layer on the inner wall surface of a trench and the surface of an epitaxial layer in the process of the trench power transistor and then performing the subsequent process of shielding electrodes and gate electrodes without removing the nitride layer.
One embodiment of the present invention provides a trench power transistor, which includes a substrate, an epitaxial layer, a trench gate structure, a body region, and a source region. The epitaxial layer is disposed on the substrate and has at least one device trench formed therein. The trench gate structure is located in the device trench and includes a shielding electrode, a gate electrode and an insulating layer. The shielding electrode is positioned at the lower half part of the element groove, and the grid electrode is positioned at the upper half part of the element groove and is electrically insulated with the shielding electrode. The insulating layer is arranged in the element groove and has a contour matched with the inner wall surface of the element groove, the grid electrode and the shielding electrode are isolated from each other through the insulating layer and the epitaxial layer, the insulating layer at least comprises a first dielectric layer, a second dielectric layer and a third dielectric layer, the third dielectric layer is positioned at the lower half part of the element groove, part of the second dielectric layer positioned at the lower half part of the element groove is clamped between the first dielectric layer and the third dielectric layer, and the dielectric constant of the second dielectric layer is larger than that of the first dielectric layer. The substrate region is formed in the epitaxial layer and surrounds the trench gate structure. The source region is formed above the body region.
Another embodiment of the present invention provides a trench power transistor, which includes a substrate, an epitaxial layer, a trench gate structure, a first body region, a source region, a first terminal electrode structure, a second terminal electrode structure, and at least two second body regions. The epitaxial layer is located on the substrate, wherein the epitaxial layer is defined to be an active area and a rectifying area. The trench gate structure is formed in the epitaxial layer and located in the active region. The first substrate region is formed in the epitaxial layer, located in the active region and surrounding the trench gate structure. The source region is formed above the first body region. The first terminal electrode structure and the second terminal electrode structure are both formed in the epitaxial layer and located in the rectifying region, wherein the first terminal electrode structure and the second terminal electrode structure are adjacent and are arranged in parallel along a first direction. The at least two second substrate regions are located in the epitaxial layer between the first terminal electrode structure and the second terminal electrode structure and are arranged along a second direction, wherein two adjacent second substrate regions are spaced from each other by a predetermined distance to define at least one Schottky contact region.
In summary, the trench power transistor of the present invention can avoid the formation of voids or gaps in the insulating layer. Therefore, when the gate electrode is biased, the leakage current between the gate electrode and the drain can be avoided, thereby improving the electrical performance of the trench power transistor.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1 is a schematic partial cross-sectional view of a trench power transistor according to an embodiment of the invention.
Fig. 2 is a schematic partial cross-sectional view of a trench power transistor according to another embodiment of the invention.
FIG. 3 is a flow chart of a trench power transistor according to an embodiment of the present invention.
Fig. 4A to fig. 4K are schematic partial cross-sectional views illustrating steps in the process of manufacturing a trench power transistor according to an embodiment of the invention.
Fig. 5A to 5C are schematic partial cross-sectional views illustrating steps in the process of manufacturing a trench power transistor according to another embodiment of the invention.
Fig. 6 is a partially cut-away perspective view illustrating a trench power transistor according to another embodiment of the invention.
Detailed Description
Please refer to fig. 1. Fig. 1 is a schematic partial cross-sectional view illustrating a trench power transistor according to an embodiment of the invention. The trench power transistor 1 includes a substrate 100, an epitaxial layer 120, a trench gate structure 160, a body region 140, and a source region 150.
In fig. 1, a substrate 100 has a high concentration of first type conductivity impurities to form a first heavily doped region. The first heavily doped region is used as a drain (drain) of the trench power transistor and may be distributed in a local area of the substrate 100 or distributed in the entire substrate 100. The first heavily doped region in this embodiment is distributed throughout the substrate 100, but is only for illustration and not for limiting the invention. The first type conductivity impurity may be an N-type or P-type conductivity impurity. Assuming that the substrate 100 is a silicon substrate, the N-type conductivity impurity is a pentavalent ion, such as a phosphorous ion or an arsenic ion, and the P-type conductivity impurity is a trivalent ion, such as a boron ion, an aluminum ion, or a gallium ion.
If the trench power transistor is N-type, the substrate 100 is doped with N-type conductivity impurities. On the other hand, in the case of a P-type trench power transistor, the substrate 100 is doped with P-type conductivity impurities. In the embodiment of the present invention, an N-type trench power transistor is taken as an example for illustration.
An epitaxial layer (epitaxial layer)120 is on the substrate 100 and has a low concentration of first type conductivity impurities. That is, for example, for an NMOS transistor, the substrate 100 is heavily doped N + and the epitaxial layer 120 is lightly doped N-. Conversely, for a PMOS transistor, the substrate 100 is heavily doped P-type (P + doping), and the epitaxial layer 120 is lightly doped P-type (P-doping).
In the present embodiment, the trench power transistor 1 further includes a buffer layer 110 disposed between the epitaxial layer 120 and the substrate 100. The buffer layer 110 has the same conductivity type as the substrate 100 and the epitaxial layer 120, i.e., the buffer layer 110 is also doped with the first conductivity type impurities. It is noted that the doping concentration of the buffer layer 110 is between the doping concentration of the substrate 100 and the doping concentration of the epitaxial layer 120. By disposing the buffer layer 110 between the substrate 100 and the epitaxial layer 120, an on-state source/drain resistance (Rdson) can be reduced, thereby reducing power consumption of the trench power transistor 1.
In addition, the epitaxial layer 120 can be divided into a drift region 130(drift region), a body region 140(body region) and a source region 150(source region) by doping different regions with different concentrations and different types of conductive impurities. The body region 140 and the source region 150 are formed in the epitaxial layer 120 at the side of the trench gate structure 160, and the drift region 130 is located at a side of the epitaxial layer 120 close to the substrate 100. That is, the body region 140 and the source region 150 are formed on the upper half of the epitaxial layer 120, and the drift region 130 is formed on the lower half of the epitaxial layer 120.
In detail, the body region 140 is formed by doping the epitaxial layer 120 with a second type conductivity impurity, the source region 150 is formed by doping the body region 140 with a high concentration of a first type conductivity impurity, and the source region 150 is formed in the upper half of the body region 140. For example, for an NMOS transistor, the body region 140 is P-type doped (e.g., P-well), and the source region 150 is N-type doped. In addition, the body region 140 has a doping concentration less than that of the source region 150.
In addition, in the present embodiment, the epitaxial layer 120 is defined with an active region AR and a termination region TR adjacent to the active region AR. The body region 140 is formed in the active region AR and the termination region TR, and the source region 150 is formed only in the active region AR. The epitaxial layer 120 has at least one element trench 120a in the active area AR.
It is to be noted that the device trench 120a according to the embodiment of the present invention has a deep trench (deep trench) structure. That is, the element trench 120a extends from the surface of the epitaxial layer 120 down to below the body region 140, that is, into the drift region 130, and the bottom of the element trench 120a is closer to the substrate 100.
In the embodiment of the present invention, at least one trench gate structure 160 is disposed in the corresponding device trench 120a, and has a shielding electrode 165, a gate electrode 167 and an insulating layer 164.
The shielding electrode 165 is located at the lower half of the device trench 120a, and the gate electrode 167 is disposed above the shielding electrode 165 and electrically insulated from the shielding electrode 165. In detail, the trench gate structure 160 further includes an inter-electrode dielectric layer 166 disposed between the shielding electrode 165 and the gate electrode 167 to isolate the gate electrode 167 from the shielding electrode 165. The material constituting the gate electrode 167 and the shielding electrode 165 may be, but is not limited to, heavily doped polysilicon. The material forming the inter-electrode dielectric layer 166 may be an oxide (e.g., silicon oxide), a nitride (e.g., nitride), or other insulating material, but is not limited in the present invention.
It should be noted that the deep trench structure of the device trench 120a is helpful to increase the breakdown voltage of the trench power transistor 1, but increases the gate/drain capacitance (Cgd) and the source/drain on-resistance (Rdson). Accordingly, in the embodiment of the invention, the shielding electrode 165 disposed at the bottom of the device trench 120a can reduce the gate/drain capacitance (Cgd) to reduce the operating loss. In addition, the shielding electrode 165 may be electrically connected to the source electrode, so as to achieve charge balance (charge balance) in the drift region 130, thereby further increasing the breakdown voltage. Accordingly, the impurity doping concentration of the drift region 130 may be relatively increased to reduce the on-resistance in the drift region 130. It should be noted that, in the embodiment of the present invention, the lower edge of the substrate region 140 is used as a reference plane to divide the device trench 120a into an upper half and a lower half.
The insulating layer 164 is disposed on the inner wall surface of the element groove 120a in a conformal manner, and has a contour conforming to the inner wall surface of the element groove 120 a. The inner wall surface includes both side wall surfaces and a bottom surface of the element groove 120 a. The insulating layer 164 may serve to electrically isolate the gate electrode 167 and the shielding electrode 165 from the epitaxial layer 120.
In detail, the insulating layer 164 includes a first dielectric layer 161, a second dielectric layer 162 and a third dielectric layer 163. In the present embodiment, the first dielectric layer 161, the second dielectric layer 162 and the third dielectric layer 163 are sequentially formed from the inner sidewall of the device trench 120a to the direction close to the gate electrode 167 and the shielding electrode 165, wherein the third dielectric layer 163 is located at the lower half of the device trench, and part of the second dielectric layer located at the lower half of the device trench 120a is sandwiched between the first dielectric layer 161 and the third dielectric layer 163.
That is, the first dielectric layer 161 and the second dielectric layer 162 both extend from the upper portion of the device trench 120a to the lower portion and the bottom of the device trench 120a, but the third dielectric layer 163 is formed only on the lower portion and the bottom of the device trench 120 a. Therefore, in the present embodiment, the first dielectric layer 161 and the second dielectric layer 162 located on the upper half portion of the device trench 120a surround the gate electrode 167 as the gate dielectric layer. Accordingly, in the upper half of the device trench 120a, the second dielectric layer 162 is located between the gate electrode 167 and the first dielectric layer 161.
In addition, the first dielectric layer 161, the second dielectric layer 162 and the third dielectric layer 163 located at the lower half of the device trench 120a surround the shielding electrode 165 and can be used as shielding dielectric layers. Therefore, the third dielectric layer 163 is located between the second dielectric layer 162 and the shielding electrode 165. In one embodiment, the top surface of the third dielectric layer 163 is at a level below the lowermost edge of the body region 140 to ensure that an inversion channel can be created within the body region 140.
It should be noted that the structure in which the first dielectric layer 161 and the second dielectric layer 162 extend from the upper portion of the device trench 120a to the lower portion of the device trench 120a can prevent voids or holes from being formed in the device trench 120a, thereby preventing gate/source leakage current from being generated and improving poor electrical performance caused by the gate/source leakage current.
In addition, in one embodiment, the dielectric constant (dielectric constant) of the second dielectric layer 162 is greater than the dielectric constant of the first dielectric layer 161. Therefore, the materials of the first dielectric layer 161 and the second dielectric layer 162 are different, but the materials of the first dielectric layer 161 and the third dielectric layer 163 can be selected to be the same or different. For example, the material of the first dielectric layer 161 and the third dielectric layer 163 can be, but not limited to, an oxide, such as silicon oxide, and the material of the second dielectric layer 162 can be a nitride, such as silicon nitride, or other materials with high dielectric constant, such as hafnium oxide, yttrium oxide, or aluminum oxide.
Therefore, compared to using only oxide layers as the gate dielectric layer, the gate dielectric layer of the present embodiment, i.e., the first dielectric layer 161 and the second dielectric layer 162 located in the upper half of the device trench 120a, can have a higher capacitance value, also referred to as gate-to-channel capacitance (Cgs), under the same thickness. Specifically, when the gate electrode 167 is biased to form an inversion channel (inversion channel) in the body region 140, the gate/channel capacitance is inversely related to the inversion channel resistance (Rch). Accordingly, as the gate/channel capacitance increases, the inversion channel resistance decreases. Since the resistance of the inversion channel is positively correlated with the on-resistance of the source/drain, the resistance of the inversion channel is reduced, and the on-resistance of the source/drain of the trench power transistor 1 can be further reduced.
However, as long as the above-mentioned effects can be achieved, the materials of the first to third dielectric layers 161 to 163 can be different insulating materials according to practical applications, and the invention is not limited thereto.
In addition, in the present embodiment, the total thickness of the first dielectric layer 161 and the second dielectric layer 162 determines the voltage that the gate of the trench power transistor can withstand according to the total thickness of the trench power transistor, which is usually between 12V and 25V. Specifically, the thickness of the first dielectric layer is between 10 and 35nm, the thickness of the second dielectric layer is between 20 and 30nm, the thickness of the third dielectric layer 163 is between 50 and 200nm, and the thickness of the third dielectric layer determines the breakdown voltage.
Referring to fig. 1, in the present embodiment, the epitaxial layer 120 further has a termination trench 120b located in the termination region TR. Furthermore, the trench power transistor 1 further includes a terminal electrode structure 170 formed in the terminal trench 120 b. In detail, the terminal electrode structure 170 includes a terminal electrode 172 located in the terminal trench 120b and a terminal dielectric layer 171 for isolating the terminal electrode 172 and the epitaxial layer 120 from each other.
Further, the termination dielectric layer 171 is conformally disposed on the inner wall surface of the termination trench 120b, and has a contour conforming to the inner wall surface of the termination trench 120b to electrically isolate the termination electrode 172 from the epitaxial layer 120. In the present embodiment, the terminal dielectric layer 171 is a stacked structure. The laminated structure sequentially includes a first oxide layer 171a, a nitride layer 171b, and a second oxide layer 171c from the inner sidewall of the first terminal trench 120b to the terminal electrode 172. That is, the nitride layer 171b of the termination dielectric layer 171 is interposed between the first oxide layer 171a and the second oxide layer 171 c.
The trench power transistor 1 of the embodiment of the invention further includes an interlayer dielectric layer 180, at least one source conductive plug 184 and a conductive layer 190.
Referring to fig. 1, an interlayer dielectric layer 180 is formed on the epitaxial layer 120, and has a passivation layer 181 and a planarization layer 182.
In the present embodiment, the passivation layer 181 is directly formed on the surface of the epitaxial layer 120 and has a stacked structure. The passivation layer 181 at least includes a first film layer 181a formed on the surface of the epitaxial layer 120 and a second film layer 181b formed on the first film layer 181 a. The first and second film layers 181a and 181b may be made of the same material as the first and second dielectric layers 161 and 162 in the device trench 120a, respectively. That is, when the first dielectric layer 161 is an oxide layer and the second dielectric layer 162 is a nitride layer, the passivation layer 181 has a stacked structure of an oxide (the first film 181a) and a nitride (the second film 181 b). In this case, the first layer 181a and the first dielectric layer 161 may be formed in the same deposition process. Similarly, the second layer 181b and the second dielectric layer 162 can be formed in the same deposition process. The detailed process steps will be described later and will not be described herein.
In other embodiments, the materials of the first film layer 181a and the second film layer 181b may be different from the materials of the first dielectric layer 161 and the second dielectric layer 162, and the invention is not limited thereto. The planarization layer 182 is formed on the protection layer 181, and the material for the conductive layer 190 to be deposited later and constituting the planarization layer 182 may be borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), oxide, nitride or a combination thereof.
In addition, the interlayer dielectric layer 180 has at least one source contact 183. In the present embodiment, the source contact 183 extends from the upper surface of the interlayer dielectric layer 180 to a portion of the epitaxial layer 120 and is formed on one side of the source region 150. Furthermore, the epitaxial layer 120 further includes a contact doping region 121, and the contact doping region 121 is located right below the bottom of the source contact window 183. In one embodiment, the contact doping region 121 is formed by implanting boron difluoride (BF2) into the epitaxial layer 120 through the source contact 183.
However, the position of the source contact 183 may vary depending on the device design and is not limited to the embodiment of the present invention. In other embodiments, the source contact 183 may also be formed directly above the source region 150, corresponding to the position of the source region 150.
A source conductive plug 184 is formed in the source contact 183 to electrically connect to the source region 150. Specifically, the source conductive plug 184 is formed in the source contact window 183 and directly contacts the source region 150 and the contact doping region 121 in the epitaxial layer 120, thereby forming an ohmic contact (ohmic contact) between the source conductive plug 184 and the source region 150. The material constituting the source conductive plug 184 may be a metal such as, but not limited to, tungsten, copper, nickel, or aluminum.
The conductive layer 190 covers the planarization layer 182 and is electrically connected to the source region 150 through the source conductive plug 184 penetrating the interlayer dielectric layer 180. That is, the conductive layer 190 can be used as a source electrode of the trench power transistor 1 and is electrically connected to an external control circuit. The conductive layer 190 may be made of titanium (Ti), titanium nitride (TiN), tungsten (W), aluminum-silicon alloy (Al-Si), aluminum-silicon-copper alloy (Al-Si-Cu), or the like, but the present invention is not limited thereto.
Referring to fig. 2, a partial cross-sectional view of a trench power transistor according to another embodiment of the invention is shown. The same elements of the trench power transistor 1' of the present embodiment and the trench power transistor 1 of fig. 1 have the same reference numerals, and the same parts of the present embodiment and the previous embodiment are not described again.
The difference between the embodiment shown in fig. 2 and the previous embodiment is that in the trench power transistor 1 'of the present embodiment, the insulating layer 164' of the trench gate structure further includes a fourth dielectric layer 168. The fourth dielectric layer 168 is formed in the upper half of the device trench 120a and is sandwiched between the side surface of the gate electrode 167 and the second dielectric layer 162.
The first dielectric layer 161, the second dielectric layer 162 and the fourth dielectric layer 168 located on the upper half portion of the device trench 120a serve as gate dielectric layers of the trench gate structure. In one embodiment, the fourth dielectric layer 168 may be formed of the same material as the first dielectric layer 161, such as silicon oxide. In the present embodiment, the total thickness of the first dielectric layer 161, the second dielectric layer 162 and the fourth dielectric layer 168 determines the voltage that the trenched power transistor gate can withstand, which is generally between 12V and 25V. Specifically, the thickness of the first dielectric layer 161 may be thinner than that of the previous embodiment by about 10nm, the thickness of the second dielectric layer 162 is constant, between 20nm and 30nm, the thickness of the third dielectric layer 163 is between 50nm and 200nm, and the thickness of the fourth dielectric layer 168 is between 10nm and 25 nm.
In addition, the inter-electrode dielectric layer 166' of the present embodiment includes a first insulating layer 166a and a second insulating layer 166b, wherein the first insulating layer 166a and the second insulating layer 166b are sequentially stacked on the shielding electrode 165. That is, the interpoly dielectric layer 166' of the present embodiment is a stacked structure. In one embodiment, the second insulating layer 166b may be made of the same material as the fourth dielectric layer 168 and formed in the same process, but the invention is not limited thereto.
Next, the embodiment of the invention provides a manufacturing process of the trench power transistor. Referring to fig. 3, a process flow diagram of a trench power transistor according to an embodiment of the invention is shown. Fig. 4A to 4K are partial cross-sectional views illustrating steps in the manufacturing process of a trench power transistor according to an embodiment of the invention.
In step S300, a substrate is provided. Next, in step S301, an epitaxial layer (epitaxial layer) is formed on the substrate. Please refer to fig. 4A. Fig. 4A illustrates a substrate 100, and an epitaxial layer 120 has been formed on the substrate 100, wherein the substrate 100 is, for example, a silicon substrate (silicon substrate) having a first heavily doped region with a high doping concentration as a drain (drain) of the trench power transistor, and the epitaxial layer 120 has a low doping concentration.
In the present embodiment, before the step of forming the epitaxial layer 120 on the substrate 100, a buffer layer 110 is further formed on the substrate 100. As shown in fig. 4A, the buffer layer 110 is located between the substrate 100 and the epitaxial layer 120. The buffer layer 110 has the same conductivity type as the substrate 100 and the epitaxial layer 120, but the doping concentration of the buffer layer 110 is between the doping concentration of the substrate 100 and the doping concentration of the epitaxial layer 120. In addition, in the present embodiment, the epitaxial layer 120 is defined with an active region AR and a termination region TR.
Referring to fig. 3, next, in step S302, at least one device trench is formed in the epitaxial layer. The process of forming the trench power transistor provided in this embodiment may further include forming a termination trench in the epitaxial layer during the forming of the device trench.
In detail, referring to fig. 4B, the device trench 120a is formed in the active region AR, and the termination trench 120B is formed in the termination region TR. In one embodiment, the device trench 120a and the termination trench 120b are defined by a mask (not shown), and then the device trench 120a and the termination trench 120b are formed in the epitaxial layer 120 by dry etching or wet etching.
Please refer to fig. 3 again. In step S303, a trench gate structure is formed in the device trench, wherein the trench gate structure includes a shielding electrode, a gate electrode, and an insulating layer, and the insulating layer is disposed on an inner wall surface of the device trench in a conformal manner and isolates the gate electrode and the shielding electrode from the epitaxial layer. The insulating layer at least comprises a first dielectric layer, a second dielectric layer and a third dielectric layer, wherein the third dielectric layer is positioned at the lower half part of the element groove, and part of the second dielectric layer positioned at the lower half part of the element groove is clamped between the first dielectric layer and the third dielectric layer.
In addition, the method of the trench power transistor of the present embodiment further includes: a terminal electrode structure is formed in the terminal trench. Also, the steps of forming the terminal electrode structure and forming the trench gate structure may be performed simultaneously. The terminal electrode structure comprises a terminal electrode and a terminal dielectric layer, wherein the terminal dielectric layer is arranged on the inner wall surface of the first terminal groove in a shape of a straight line so as to isolate the terminal electrode from the epitaxial layer, and the terminal dielectric layer at least comprises two oxide layers and a nitride layer clamped between the oxide layers.
In detail, referring to fig. 4C to 4H, a detailed process for forming the trench gate electrode and the terminal electrode structure is shown. Please refer to fig. 4C. In fig. 4C, a first dielectric material 210, a second dielectric material 220, and a third dielectric material 230 are sequentially blanket formed on the inner wall surfaces (including both sidewall surfaces and the bottom surface) of the device trench 120a and the termination trench 120b, and on the surface of the epitaxial layer 120. The first dielectric material 210 may be an oxide layer or a nitride layer. For example, the first dielectric material 210 is silicon oxide (SiOx) and is formed by a thermal oxidation process. In other embodiments, the first dielectric material 210 may be formed by a physical vapor deposition process or a chemical vapor deposition process.
In one embodiment, the dielectric constant of the second dielectric material 220 is higher than the dielectric constant of the first dielectric material 210. For example, when the first dielectric material 210 is silicon oxide, the second dielectric material may be a nitride, such as silicon nitride, and conformally coated on the first dielectric material 210 by physical vapor deposition or chemical vapor deposition.
The third dielectric material 230 may be any one of oxide and nitride, such as silicon oxide (SiO4), and is not particularly limited. Furthermore, the process of depositing the third dielectric material 230, such as a physical vapor deposition process or a chemical vapor deposition process, may be selected according to the selected material and the actual requirements.
In one embodiment, the thickness of the first dielectric material 210 is between 20 and 30nm, the thickness of the second dielectric material 220 is between 20 and 30nm, and the thickness of the third dielectric material 230 is between 60 and 120 nm.
After the deposition of the first to third dielectric materials 210-230 is completed, a first polysilicon structure is first blanket formed on the third dielectric layer 163 and filled into the device trench 120a and the terminal trench 120 b. The first polysilicon structure may be a polysilicon structure (polysilicon poly-Si) containing conductive impurities. Then, an etch back is performed to remove the first polysilicon structure covered on the surface of the third dielectric layer 163, and leave the first polysilicon structure 240a in the device trench 120a and the first polysilicon structure 240b in the terminal trench 120b, respectively.
Next, referring to fig. 4D, a photoresist layer 3 is formed on the third dielectric material 230, wherein the photoresist layer 3 has an opening 3a to expose the device trench 120a in the active area AR. That is, the photoresist layer 3 covers the terminal trench 120b in the terminal region TR and a portion of the surface of the third dielectric material 230. Next, the first polysilicon structure 240a located in the upper half of the device trench 120a is etched, and only the first polysilicon structure 240 a' located in the lower half of the device trench 120a is left. After the etching process is completed, the photoresist layer 3 is removed.
Next, referring to fig. 4E, an oxide layer 250 is formed to cover the surface of the third dielectric material 230 and fill the device trench 120a and the terminal trench 120 b. It is noted that during the process of forming the oxide layer 250, the top of the first polysilicon structure 240 a' in the lower portion of the device trench 120a and the top of the first polysilicon structure 240b in the terminal trench 120b are slightly oxidized. After the foregoing steps are completed, the shielding electrode 165' has been formed in the lower half of the element trench 120 a.
Next, referring to fig. 4F, the oxide layer 250 on the surface of the epitaxial layer 120 and the oxide layer 250 on the upper half of the device trench 120a are removed, and only a portion of the oxide layer 250 ' on the top of the shielding electrode 165 ' is left, wherein the oxide layer 250 ' may be equivalent to the inter-electrode dielectric layer 166 shown in fig. 1.
In addition, in the step of removing the oxide layer 250, a portion of the third dielectric material 230 on the surface of the epitaxial layer 120 and in the device trench 120a and the termination trench 120b is also removed. In detail, in the device trench 120a, the third dielectric material 230 on the inner wall surface of the upper half of the device trench 120a is removed, and only the third dielectric material 230' on the inner wall surface of the lower half of the device trench 120a is left, so as to form the third dielectric layer 163 shown in fig. 1 and 2.
Please refer to fig. 4G. Next, a second polysilicon structure 260 is blanket formed overlying the surface of the epitaxial layer 120 and filling the device trenches 120a and the terminal trenches 120 b. In detail, the second polysilicon structure 260 covers the surface of the second dielectric material 220 and fills the upper portion of the device trench 120a and the remaining space of the terminal trench 120 b. The manner of forming the second polysilicon structure 260 may be the same as the manner of forming the first polysilicon structure, and will not be described herein.
Referring to fig. 4H, the second polysilicon structure 260 above the epitaxial layer 120 is etched back to form the gate electrode 167 ″ in the device trench 120a and the terminal electrode 172' in the terminal trench 120 b. Accordingly, the first dielectric material 210 and the second dielectric material 220 formed on the inner wall surface of the device trench 120a can be regarded as the first dielectric layer 161 and the second dielectric layer 162 in fig. 1, respectively.
It is to be noted that the first dielectric material 210 and the second dielectric material 220, which are initially formed in the device trench 120a and the terminal trench 120b, are not removed during the process steps for forming the trench gate structure and the terminal electrode structure. Therefore, as in the prior art, no void or hole is left in the device trench 120a, thereby preventing the generation of gate/source leakage current.
Please refer to fig. 3 again. Step S304 and step S305 are performed. In step S304, a body doping process is performed on the epitaxial layer to form a body region. In step S305, a source doping process is performed to form a source region, wherein the source region is located above the body region.
Referring to fig. 4I, after a body doping process is performed on the epitaxial layer 120, a first doped region is formed on a side of the epitaxial layer 120 away from the substrate 100. After the first doped region is formed, a source doping process is performed on the first doped region to form a source region 150 and a body region 140. It is noted that the source doping process may include performing a thermal diffusion process after the ion implantation of the first doped region to form the source region 150. In addition, as can be seen in fig. 4I, the lowest edge of the body region 140 in this embodiment is higher than the level where the top surface of the third dielectric material 230' is located.
The process of the trench power transistor according to the embodiment of the present invention may further include forming a redistribution layer on the epitaxial layer, so that the source region 150, the gate electrode 167 and the shielding electrode 165 may be electrically connected to an external control circuit. The specific steps of the redistribution layer will be described below with reference to fig. 4J to 4K, taking the formation of the source contact plug shown in fig. 1 as an example.
Referring to fig. 4J, a planarization layer 270 is formed to entirely cover the surface of the second dielectric material 220, the trench gate structure 160 'and the terminal electrode structure 170'. The material of the planarization layer 270 may be selected from borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), oxide, nitride, or a combination thereof.
Subsequently, at least one source contact 270a (2 are shown in fig. 4J as an example) is formed corresponding to the position of the source region 150. In this embodiment. The technical means for forming the source contact 270a can be realized by using the conventional steps of coating photoresist, photolithography, etching, etc.
Next, please refer to fig. 4K. Source conductive plugs 280 are formed in the corresponding source contact windows 270 a. It should be noted that the source conductive plug 280 penetrates through the planarization layer 270, the first dielectric material 210 and the second dielectric material 220, and then extends into the epitaxial layer 120 and is located at one side of the source region 150 to electrically connect with the source region 150.
It should be noted that, before forming the source conductive plugs 280 on the corresponding source contact 270a, a doping process may be performed on the epitaxial layer 120 through the source contact 270a to form a contact doped region 121 in the epitaxial layer 120 under the source contact 270 a. In one embodiment, the dopant doped in the contact doping region 121 is boron difluoride (BF 2).
In addition, after forming the source conductive plugs 280 on the corresponding source contact holes 270a, a conductive layer 290 may be further formed to cover the planarization layer 270 and electrically connect to the source conductive plugs 280. The conductive layer 290 may be made of titanium (Ti), titanium nitride (TiN), tungsten (W), aluminum-silicon alloy (Al-Si), aluminum-silicon-copper alloy (Al-Si-Cu), or the like, but the present invention is not limited thereto. Accordingly, the conductive layer 290 may be electrically connected to the source region 150 and the contact doping region 121 through the source conductive plug 280. Through the above description of the embodiments, a person skilled in the art should easily deduce other implementation details, which are not repeated herein.
It should be further noted that the effect of the portions of the first dielectric material 210 and the second dielectric material 220 on the surface of the epitaxial layer 120 is equivalent to the protection layer 181 shown in fig. 1, and the planarization layer 270 is equivalent to the planarization layer 182 shown in fig. 1. In addition, the first dielectric material 210, the second dielectric material 220 and the third dielectric material 230 sequentially disposed on the inner wall of the device trench 120a may be equivalent to the insulating layer 164 of the trench gate structure 160 shown in fig. 1.
The invention also provides a manufacturing process of the trench power transistor in another embodiment. Fig. 5A to 5B are schematic partial cross-sectional views of steps in the manufacturing process of a trench power transistor according to another embodiment.
It is noted that the process steps of fig. 5A are performed after the process steps shown in fig. 4A to 4F of the previous embodiment are completed. That is, after removing the oxide layer 250 on the surface of the epitaxial layer 120 and the oxide layer 250 on the upper half of the device trench 120a and only leaving a portion of the oxide layer 250' on the top of the shielding electrode 165, a fourth dielectric material 300 is formed to cover the surface of the second dielectric material 220 and to be formed in the device trench 120a and the termination trench 120 b. The process for forming the fourth dielectric material 300 may be a conventional deposition process, and the fourth dielectric material 300 may be an oxide or a nitride.
Next, a second polysilicon structure 260' is blanket formed over the fourth dielectric material 300. The process for forming the second polysilicon structure 260' may refer to the process described in fig. 4G, and will not be described herein.
Subsequently, referring to fig. 5B, the second polysilicon structure 260 is etched back to remove the second polysilicon structure 260 above the epitaxial layer 120 and covering the terminal trench 120B, and the second polysilicon structure is left in the device trench 120a to form the gate electrode 167 a. Accordingly, the first to fourth dielectric materials 210, 220, 230 ', 300 formed on the inner wall surface of the element trench 120a may be equivalent to the insulating layer 164' shown in fig. 2. In addition, in the device trench 120a, the oxide layer 250 ' and the fourth dielectric layer 300a between the first polysilicon structure 165 ' and the second polysilicon structure 260 ' may be the first film 181a and the second film 181b shown in fig. 2, respectively.
Please refer to fig. 5C. Body region 140 and source region 150 are then formed in epitaxial layer 120, respectively, and a redistribution layer is formed on epitaxial layer 120, i.e., on fourth dielectric layer 300. The detailed process steps for forming the redistribution layer are similar to those shown in fig. 4J to 4K, and include: forming a planarization layer 270 to completely cover the surface of the second dielectric material 220, the trench gate structure and the terminal electrode structure; performing a doping process on the epitaxial layer 120 through the source contact 270a to form a contact doped region 121 in the epitaxial layer 120 under the source contact 270 a; forming source conductive plugs 280 in the corresponding source contact windows 280; and forming a conductive layer 290 overlying the planarization layer 270 and electrically connected to the source conductive plug 280. By the above process, the trench power transistor shown in fig. 2 can be formed.
Please refer to fig. 6. Fig. 6 is a partially cut-away perspective view illustrating a trench power transistor according to another embodiment of the invention.
The trench power transistor 3 of the present embodiment can be applied to a voltage conversion circuit as a low side power transistor. In detail, the trench power transistor 3 of the present embodiment includes a substrate 310, an epitaxial layer 330, a trench gate structure 360, a terminal electrode structure 370, first to third terminal electrode structures 380a to 380c, a plurality of first body regions 340a, a plurality of second body regions 340b, and a source region 350. In addition, similar to the embodiment of fig. 1 and 2, a buffer layer 320 is further disposed between the substrate 310 and the epitaxial layer 330. It should be noted that the same elements in the present embodiment as those in the embodiment of fig. 1 and 2 will not be described in detail.
In the present embodiment, the epitaxial layer 330 defines an active region AR, a termination region TR and a rectifying region SR. The epitaxial layer 330 has at least one device trench 360h in the active region AR, a termination trench 370h in the termination region TR, and a first termination trench 381, a second termination trench 382, and a third termination trench 383 in the rectifying region SR.
Element trench 360h, termination trench 370h, first termination trench 381, second termination trench 382, and third termination trench 383 are formed in epitaxial layer 330 in parallel along a first direction D1. In the present embodiment, the device trench 360h is adjacent to the first terminal trench 381, and has a first pitch P1. In addition, in the rectifying region SR, the first to third terminal trenches 381-383 are separated from each other by a second pitch P2, wherein the second pitch P2 is slightly smaller than the first pitch P1, and the difference between the first pitch P1 and the second pitch P2 is between 0.1 μm and 0.3 μm.
In this embodiment, the trench gate structure 360 may have the same structure as the trench gate structure 160 shown in fig. 1 or fig. 2 and is located in the device trench (not numbered), wherein the device trench is located in the active area AR. In addition, the first body region 340a and the source region 350 are located in the active region AR and are formed in the epitaxial layer 330 on both sides of the trench gate structure 360.
Termination electrode structure 370 may be the same as termination electrode structure 170 shown in fig. 1 or 2 and is located in a termination trench (not numbered) that is located in termination region TR. Similarly, the first to third terminal electrode structures 380a to 380c may have the same structure as the terminal electrode structure 170 shown in fig. 1 or 2. The first to third terminal electrode structures 380a to 380c are respectively located in the first terminal trench 381, the second terminal trench 382 and the third terminal trench 383.
Specifically, a plurality of second body regions 340b are formed in the epitaxial layer 330 between two adjacent first and second terminal electrode structures 380a, 380b or between two adjacent second and third terminal electrode structures 380b, 380 c.
Further, a plurality of second body regions 340b located between two adjacent first and second terminal electrode structures 380a, 380b are arranged along a second direction D2, wherein any two adjacent second body regions 340b are spaced apart from each other by a predetermined distance, thereby defining at least one schottky contact region 330 s. In other words, the distance between two adjacent second substrate regions 340b arranged along the second direction D2 is the length L of the schottky contact region 330s in the second direction D2. In one embodiment, the length L of the schottky contact region 330s in the second direction D2 is between 0.6 μm and 1.2 μm. In the embodiment of the present invention, the trench power transistor 3 may further include an interlayer dielectric layer (not shown) formed on the epitaxial layer and at least one conductive plug (not shown) penetrating the interlayer dielectric layer.
In detail, the interlayer dielectric layer may have at least one contact window (not shown) corresponding to the schottky contact region 330s, and the conductive plug contacts the epitaxial layer at the schottky contact region through the contact window to form a schottky diode.
Since the forward voltage drop for turning on the schottky diode is lower than the forward voltage drop of the body diode, the schottky diode is constructed in the trench power transistor 3, so that the switching loss can be reduced. In addition, the reverse recovery characteristic of the schottky diode is better, and when the trench power transistor 3 is applied to a higher frequency circuit, the switching loss can be more effectively reduced.
In summary, in the trench power transistor and the manufacturing process thereof provided by the embodiments of the invention, after the step of forming the oxide layer and the nitride layer on the inner wall surface of the device trench and the surface of the epitaxial layer, the oxide layer contacting the epitaxial layer and the nitride layer covering the oxide layer are not removed. In addition, under the condition of not removing the nitride layer, the subsequent processes of the shielding electrode and the grid electrode are directly carried out, so that the trench grid structure which can avoid generating holes or gaps (void) in the trench grid structure can avoid generating holes or gaps in the insulating layer. Therefore, when the gate electrode is biased, the leakage current between the gate electrode and the drain can be avoided, thereby improving the electrical performance of the trench power transistor.
Although the present invention has been described with reference to the above embodiments, it should be understood that the invention is not limited to the above embodiments, and various changes and modifications can be made by one skilled in the art without departing from the scope of the invention as defined in the appended claims.
[ notation ] to show
Trench power transistor 1, 1', 3
Substrate 100, 310
Buffer layers 110, 320
Epitaxial layers 120, 330
Drift region 130
Land region 140
First substrate region 340a
Second substrate region 340b
Source regions 150, 350
Trench gate structures 160, 160', 360
Schottky contact region 330s
Active area AR
Terminal region TR
Rectifying region SR
Element trenches 120a, 360h
Termination trenches 120b, 370h
First termination trench 381
Second termination trench 382
Third termination trench 383
Shield electrodes 165, 165'
Gate electrodes 167, 167', 167a
Insulating layers 164, 164'
Inter-electrode dielectric layers 166 and 166'
First insulating layer 166a
Second insulating layer 166b
First dielectric layer 161
Second dielectric layer 162
Third dielectric layer 163
Terminal electrode structures 170, 170', 370
First terminal electrode structure 380a
Second terminal electrode structure 380b
Third terminal electrode structure 380c
Terminal electrodes 172, 172'
Termination dielectric layer 171
First oxide layer 171a
Nitride layer 171b
Second oxide layer 171c
Interlayer dielectric layer 180
Source conductive plugs 184, 280
Source contact 183, 270a
Conductive layers 190, 290
Protective layer 181
First film layer 181a
Second film layer 181b
Planarization layer 182, 270
Contact doping region 121
Fourth dielectric layer 168
First dielectric material 210
Second dielectric material 220
Third dielectric Material 230, 230'
First polysilicon structure 240a, 240b, 240a ', 240 b'
A photoresist layer 3
Opening 3a
Oxide layer 250, 250'
Second polysilicon structures 260, 260'
Fourth dielectric material 300, 300a
First direction D1
Second direction D2
First pitch P1
Second pitch P2
Length L
The flow steps S300 to S305.

Claims (9)

1. A trench power transistor, comprising:
a substrate;
an epitaxial layer on the substrate, wherein the epitaxial layer has at least one device trench formed therein;
a trench gate structure in the device trench, wherein the trench gate structure comprises:
a shielding electrode located at the lower half part of the element groove;
a gate electrode located at the upper half part of the element groove and electrically insulated with the shielding electrode;
an insulating layer disposed in the device trench and having a profile corresponding to an inner wall surface of the device trench, wherein the gate electrode and the shielding electrode are isolated from each other by the insulating layer, wherein the insulating layer at least includes a first dielectric layer, a second dielectric layer and a third dielectric layer, wherein the third dielectric layer is located at a lower half portion of the device trench, and a part of the second dielectric layer located at the lower half portion of the device trench is sandwiched between the first dielectric layer and the third dielectric layer, wherein a dielectric constant of the second dielectric layer is greater than a dielectric constant of the first dielectric layer; and
an inter-electrode dielectric layer between the gate electrode and the shield electrode;
a substrate region formed in the epitaxial layer and surrounding the trench gate structure; and
a source region formed above the body region,
the width of the inter-electrode dielectric layer is the same as that of the shielding electrode, and the first dielectric layer and the second dielectric layer extend from the upper half part of the element groove to the lower half part of the element groove.
2. The trench power transistor of claim 1, wherein the epitaxial layer further comprises at least one termination trench formed in the epitaxial layer, and the trench power transistor further comprises at least one termination electrode structure formed in the termination trench, wherein the termination electrode structure comprises:
a terminal electrode in the terminal trench; and
and a terminal dielectric layer disposed on the inner wall surface of the terminal trench and having a profile corresponding to the inner wall surface of the terminal trench to isolate the terminal electrode from the epitaxial layer, wherein the terminal dielectric layer comprises at least two oxide layers and a nitride layer sandwiched between the oxide layers.
3. The trench power transistor of claim 1 wherein the thickness of the first dielectric layer is between 10nm and 35nm, the thickness of the second dielectric layer is between 20nm and 30nm, and the thickness of the third dielectric layer is between 50nm and 200 nm.
4. The trench power transistor of claim 1, wherein the insulating layer further comprises a fourth dielectric layer formed on the upper half of the device trench, the fourth dielectric layer being sandwiched between the second dielectric layer and the gate electrode.
5. The trench power transistor of claim 4 wherein the thickness of the first dielectric layer is 10nm, the thickness of the second dielectric layer is between 20nm and 30nm, the thickness of the third dielectric layer is between 50nm and 200nm, and the thickness of the fourth dielectric layer is between 10nm and 25 nm.
6. The trench power transistor of claim 1, further comprising:
an interlayer dielectric layer formed on the epitaxial layer, wherein the interlayer dielectric layer has at least one source contact window; and
at least one source conductive plug formed in the source contact window to electrically connect to the source region.
7. The trench power transistor of claim 6 wherein the interlayer dielectric layer comprises a passivation layer directly formed on the surface of the epitaxial layer, wherein the passivation layer is a stack of oxide and nitride layers.
8. A trench power transistor, comprising:
a substrate;
an epitaxial layer located on the substrate, wherein the epitaxial layer is defined to have an active region and a rectifying region, and the epitaxial layer has at least one device trench located in the active region, and a first terminal trench and a second terminal trench located in the rectifying region;
a trench gate structure formed in the device trench, wherein the trench gate structure comprises:
a shielding electrode located at the lower half part of the element groove;
a gate electrode located at the upper half part of the element groove and electrically insulated with the shielding electrode; and
an insulating layer disposed in the device trench, wherein the gate electrode and the shielding electrode are isolated from the epitaxial layer by the insulating layer, the insulating layer at least includes a first dielectric layer, a second dielectric layer and a third dielectric layer, the first dielectric layer and the second dielectric layer extend from the upper half of the device trench to the lower half of the device trench, and the third dielectric layer is located at the lower half of the device trench;
a first substrate region formed in the epitaxial layer, located in the active region and surrounding the trench gate structure;
a source region formed above the first body region;
a first terminal electrode structure formed in the first terminal trench;
a second terminal electrode structure formed in the second terminal trench, wherein the trench gate structure, the first terminal electrode structure and the second terminal electrode structure are adjacent and parallel along a first direction; and
and at least two second substrate regions located in the epitaxial layer between the first terminal electrode structure and the second terminal electrode structure and arranged along a second direction, wherein two adjacent second substrate regions are spaced apart from each other by a predetermined distance to define at least one Schottky contact region.
9. The trench power transistor of claim 8 wherein the device trench is adjacent to the first termination trench and separated by a first pitch, the first termination trench is adjacent to the second termination trench and has a second pitch, wherein the second pitch is smaller than the first pitch, and the difference between the first pitch and the second pitch is between 0.1 μm and 0.3 μm.
CN201510680019.XA 2015-10-19 2015-10-19 Trench type power transistor Active CN106601811B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201510680019.XA CN106601811B (en) 2015-10-19 2015-10-19 Trench type power transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201510680019.XA CN106601811B (en) 2015-10-19 2015-10-19 Trench type power transistor

Publications (2)

Publication Number Publication Date
CN106601811A CN106601811A (en) 2017-04-26
CN106601811B true CN106601811B (en) 2020-03-03

Family

ID=58554701

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201510680019.XA Active CN106601811B (en) 2015-10-19 2015-10-19 Trench type power transistor

Country Status (1)

Country Link
CN (1) CN106601811B (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110838486B (en) * 2018-08-17 2023-04-07 力智电子股份有限公司 Power transistor element
CN112201685B (en) * 2020-09-08 2022-02-11 浙江大学 Super junction device and dielectric combined terminal

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006108011A2 (en) * 2005-04-06 2006-10-12 Fairchild Semiconductor Corporation Trenched-gate field effect transistors and methods of forming the same
US7492005B2 (en) * 2005-12-28 2009-02-17 Alpha & Omega Semiconductor, Ltd. Excessive round-hole shielded gate trench (SGT) MOSFET devices and manufacturing processes
US8497549B2 (en) * 2007-08-21 2013-07-30 Fairchild Semiconductor Corporation Method and structure for shielded gate trench FET
US8525255B2 (en) * 2009-11-20 2013-09-03 Force Mos Technology Co., Ltd. Trench MOSFET with trenched floating gates having thick trench bottom oxide as termination
JP5511019B2 (en) * 2011-11-04 2014-06-04 ルネサスエレクトロニクス株式会社 Semiconductor device
US8680614B2 (en) * 2012-06-12 2014-03-25 Monolithic Power Systems, Inc. Split trench-gate MOSFET with integrated Schottky diode
CN104425628B (en) * 2013-08-22 2017-11-07 大中积体电路股份有限公司 Power semiconductor component and its semiconductor structure

Also Published As

Publication number Publication date
CN106601811A (en) 2017-04-26

Similar Documents

Publication Publication Date Title
US9799743B1 (en) Trenched power semiconductor element
US9722071B1 (en) Trench power transistor
US7504303B2 (en) Trench-gate field effect transistors and methods of forming the same
US20130134505A1 (en) Semiconductor device for power and method of manufacture thereof
US20140159144A1 (en) Trench gate mosfet and method of forming the same
US7494876B1 (en) Trench-gated MIS device having thick polysilicon insulation layer at trench bottom and method of fabricating the same
US8471331B2 (en) Method of making an insulated gate semiconductor device with source-substrate connection and structure
CN107910267B (en) Power semiconductor device and method of manufacturing the same
US9991378B2 (en) Trench power semiconductor device
US11855184B2 (en) Method of manufacturing a power semiconductor device having source region and body contact region formed between trench-type gate electrodes
US10128368B2 (en) Double gate trench power transistor and manufacturing method thereof
US10497782B2 (en) Trench power semiconductor component and method of manufacturing the same
CN107910269B (en) Power semiconductor device and method of manufacturing the same
US10529847B2 (en) Trench power semiconductor component and method of manufacturing the same
CN106601811B (en) Trench type power transistor
TWI622124B (en) Manufacturing method of trench power semiconductor device
TWI588991B (en) Trench power semiconductor device
US20230290815A1 (en) Trench-gate transistor device
CN108962972B (en) Trench type power semiconductor element and manufacturing method thereof
CN107910271B (en) Power semiconductor device and method of manufacturing the same
CN107910268B (en) Power semiconductor device and method of manufacturing the same
CN113809148B (en) Power element and manufacturing method thereof
US20220045184A1 (en) Shielded gate trench mosfet with esd diode manufactured using two poly-silicon layers process
US20220216336A1 (en) Methods and structures for contacting shield conductor in a semiconductor device
TW202209676A (en) Trench mos transistor device and method of manufacturing the same

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant