CN106601811A - Trench type power transistor - Google Patents
Trench type power transistor Download PDFInfo
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- CN106601811A CN106601811A CN201510680019.XA CN201510680019A CN106601811A CN 106601811 A CN106601811 A CN 106601811A CN 201510680019 A CN201510680019 A CN 201510680019A CN 106601811 A CN106601811 A CN 106601811A
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- power transistor
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Provided is a trench type power transistor. A trench grid structure of the trench type power transistor is positioned in a component trench of an epitaxial layer, and a shielding electrode, a grid electrode and an insulating layer are included at least. The insulating layer comprises first, second and third dielectric layers, the third dielectric layer is positioned in the lower half portion of the component trench, the second dielectric layer which is partially positioned in the lower half portion of the component trench is clamped between the first and third dielectric layers, and the dielectric constant of the second dielectric layer is greater than that of the first dielectric layer.
Description
Technical field
The present invention relates to a kind of power transistor, and more particularly to a kind of plough groove type with cover electrode (maskingelectrode)
Power metal oxide semiconductor field-effect transistor.
Background technology
Power metal oxide semiconductor field-effect transistor (Power Metal Oxide
Semiconductor Field Transistor, Power MOSFET) it is widely used in electric device
Switching device, e.g. power supply unit, commutator or low voltage motor controller etc..Now
The design of vertical stratification being taken power metal oxide semiconductor field-effect transistor, with lift elements more
Density.This kind of power metal oxide semiconductor field-effect transistor for adopting vertical stratification design is also claimed
For groove-type power type metal oxide semiconductor field-effect transistor, its advantage can be to expend low
Under the situation of power, control voltage enters the operation of units.
The work-loss costs of power metal oxide thing semiconductor field effect transistor are divided into switch cost
(switching loss) and conduction losses (conducting loss) two big class, the wherein electric capacity of gate/drain
Value (Cgd) is the important parameter for affecting switch cost.Gate/drain capacitance is too high to cause switching to damage
Losing increases, and then limits the switch speed of power metal oxide thing semiconductor field effect transistor, no
Beneficial to using in high-frequency circuit.
In order to improve the problems referred to above, gate/drain capacitance is reduced, in known power metal oxygen
In compound semiconductor field effect transistor, masking electricity can be additionally formed in the lower half of gate trench
Pole (shielding electrode).
However, making the groove-type power type metal oxide semiconductor field with cover electrode (maskingelectrode) structure
During effect transistor, in formation after the cover electrode (maskingelectrode) of gate trench lower half, generally
The dielectric layer etch that can be previously formed on the side wall of the gate trench first half is fallen, then redeposited
New gate dielectric.However, during etching dielectric layer, it is more difficult to control the etching of dielectric layer
Depth, cause the gate dielectric that is subsequently formed with the dielectric layer for being located at gate trench lower half side wall it
Between produce hole or gap.When the grid of groove-type power type metal oxide semiconductor field-effect transistor
In applied voltage, these holes or gap are likely to result in the leakage current between gate/source for pole, and
Make the electrical performance of groove-type power type metal oxide semiconductor field-effect transistor not good.
The content of the invention
The present invention provides a kind of groove-type power transistor, and which is by the system in groove-type power transistor
Cheng Zhong, the surface of the internal face and epitaxial layer of groove form oxide skin(coating) and the step of nitride layer it
Afterwards, in the case where nitride layer is not removed, carry out the system of follow-up cover electrode (maskingelectrode) and gate electrode
Journey, to avoid hole or space (void) are produced in channel grid structure.
A wherein embodiment of the invention provides a kind of groove-type power transistor, including base material, epitaxial layer,
Trench gate structure, matrix area and source area.Epitaxial layer is located on base material, and has an at least element
Groove is formed at wherein.Trench gate structure is located in element groove, and trench gate structure includes hiding
Cover electrode, gate electrode and insulating barrier.Cover electrode (maskingelectrode) is located at the lower half of element groove, and grid is electric
Pole is located at the first half of element groove, and is electrically insulated with cover electrode (maskingelectrode).Insulating barrier is arranged at element ditch
The profile being consistent in groove and with the internal face with element groove, wherein gate electrode and cover electrode (maskingelectrode) are logical
Cross insulating barrier to be isolated from each other with epitaxial layer, wherein insulating barrier at least includes the first dielectric layer, the second dielectric
Layer and the 3rd dielectric layer, wherein the 3rd dielectric layer is located at the lower half of element groove, and part is located at unit
Second dielectric layer of the lower half of part groove is located between the first dielectric layer and the 3rd dielectric layer, its
In the second dielectric layer dielectric constant more than the first dielectric layer dielectric constant.Matrix area is formed at extension
In layer, and around trench gate structure.Source area is then formed above matrix area.
Another embodiment of the present invention provides a kind of groove-type power transistor, including base material, epitaxial layer,
Trench gate structure, the first matrix area, source area, first terminal electrode structure, second terminal electrode
Structure and at least two second matrix areas.Epitaxial layer is located on base material, and its epitaxial layers is defined out
Source region and rectifying section.Trench gate structure is formed in epitaxial layer, and is located at active region.The
One matrix area is formed in epitaxial layer, and is located in active region and around trench gate structure.Source electrode
Area is formed at the top of the first matrix area.First terminal electrode structure and second terminal electrode structure all shapes
Into in epitaxial layer, and it is located in rectifying section, wherein first terminal electrode structure and second terminal electricity
Pole structure is arranged side by side adjacent and along a first direction.At least two second matrix areas are located at first terminal electricity
In epitaxial layer between pole structure and second terminal electrode structure, and arrange along a second direction, its
In two the second adjacent matrix areas be spaced a preset distance, to define at least one schottky junctions
Tactile area.
In sum, groove-type power transistor of the invention can avoid producing in insulating barrier hole or
Space.Therefore, when gate electrode is applied in bias, can avoid producing between gate electrode and drain electrode
Leakage current, so as to the electrical performance of groove-type power transistor can be improved.
It is that the features described above and advantage of the present invention can be become apparent, preferred embodiment cited below particularly,
And coordinate institute's accompanying drawings, it is described in detail below.
Description of the drawings
Fig. 1 illustrates the partial cutaway schematic of the groove-type power transistor of one embodiment of the invention.
Fig. 2 illustrates the partial cutaway schematic of the groove-type power transistor of another embodiment of the present invention.
Fig. 3 shows the processing flow figure of the groove-type power transistor of one embodiment of the invention.
Fig. 4 A to Fig. 4 K illustrate the processing procedure of the groove-type power transistor of one embodiment of the invention respectively
In each step partial cutaway schematic.
Fig. 5 A to Fig. 5 C illustrate the system of the groove-type power transistor of another embodiment of the present invention respectively
The partial cutaway schematic of each step in journey.
Fig. 6 illustrates the part section solid of the groove-type power transistor of another embodiment of the present invention and shows
It is intended to.
Specific embodiment
Refer to Fig. 1.Fig. 1 illustrates the partial cutaway of the groove-type power transistor of one embodiment of the invention
Face structural representation.Groove-type power transistor 1 includes base material 100, epitaxial layer 120, trench gate
Pole structure 160, matrix area 140 and source area 150.
In FIG, base material 100 has the first type conductive impurities of high concentration, and forms the first weight
Doped region.First heavily doped region is intended for the drain electrode (drain) of groove-type power transistor, and can
It is distributed in the regional area of base material 100 or is distributed in whole base material 100.The of the present embodiment
One heavily doped region is distributed across in whole base material 100, but is only used for illustrating and being not used to limit the present invention.
Aforesaid first type conductive impurities can be N-type or P-type conductivity impurity.Assume base material 100
For silicon substrate, N-type conductivity impurity is pentad ion, such as phosphonium ion or arsenic ion, and P
Type conductive impurities be trivalent element ion, such as boron ion, aluminium ion or gallium ion.
If groove-type power transistor is N-type, 100 doped N-type conductive impurities of base material.It is another
Aspect, if p-type groove-type power transistor, then 100 doped p-type conductive impurities of base material.This
In inventive embodiments, it is the explanation by taking N-type groove-type power transistor as an example.
Epitaxial layer (epitaxial layer) 120 is located on base material 100, and the first type with low concentration
Conductive impurities.That is, by taking nmos pass transistor as an example, N of the base material 100 for high concentration
Type adulterates (N+), and the n-type doping (N-) then for low concentration of epitaxial layer 120.Conversely, with PMOS
As a example by transistor, p-type doping (P+doping) of the base material 100 for high concentration, and epitaxial layer 120 is then
For p-type doping (P-doping) of low concentration.
In the present embodiment, groove-type power transistor 1 further includes one and is arranged at epitaxial layer 120 and base
Cushion 110 between material 100.Cushion 110 has identical with base material 100 and epitaxial layer 120
Conductivity type, the first type conductive impurities are also doped in implying that cushion 110.To be illustrated
It is that the doping content of cushion 110 is between the doping content of base material 100 and mixing for epitaxial layer 120
Between miscellaneous concentration.By cushion 110 is arranged between base material 100 and epitaxial layer 120, can be with
Source/drain conducting resistance (on-state source/drain resistance, Rdson) is reduced, so as to reduce
The power consumption of groove-type power transistor 1.
In addition, by zones of different doping variable concentrations and different types of conductive impurities, extension
Layer 120 can be divided into drift region 130 (drift region), matrix area 140 (body region) and source electrode
Area 150 (source region).Matrix area 140 is formed at trench gate structure 160 with source area 150
In the epitaxial layer 120 of side, and drift region 130 is then in epitaxial layer 120 near base material 100
Side.That is, matrix area 140 is formed at the first half of epitaxial layer 120 with source area 150,
Drift region 130 is then formed at the lower half of epitaxial layer 120.
Specifically, matrix area 140 is by Second-Type conductive impurities of adulterating in epitaxial layer 120
And formed, and source area 150 is then the first type electric conductivity by high concentration of adulterating in matrix area 140
Impurity and formed, and source area 150 is formed at the first half of matrix area 140.For example, it is right
For nmos pass transistor, matrix area 140 is that p-type is adulterated (such as p type wellses, P-well), and source electrode
Area 150 is n-type doping.Additionally, doping of the doping content of matrix area 140 less than source area 150
Concentration.
In addition, in the present embodiment, epitaxial layer 120 be defined out an active region AR and with
Active region AR adjacent terminal area TR.Aforesaid matrix area 140 is formed at active region AR
In the TR of terminal area, and source area 150 is then formed only in active region AR.Epitaxial layer 120
And with least one element groove 120a in active region AR.
To be illustrated, the element groove 120a of the embodiment of the present invention has deep trench (deep
Trench) structure.That is, element groove 120a extends downward base by the surface of epitaxial layer 120
Body area is below 140, that is, extends in drift region 130, and the bottom of element groove 120a
Closer base material 100.
In the embodiment of the present invention, at least one trench gate structure 160 is arranged at corresponding element groove
In 120a, and there is cover electrode (maskingelectrode) 165, gate electrode 167 and insulating barrier 164.
Cover electrode (maskingelectrode) 165 is then arranged at positioned at the lower half of element groove 120a, gate electrode 167
Above cover electrode (maskingelectrode) 165, and it is electrically insulated with cover electrode (maskingelectrode) 165.Specifically, trench-gate knot
Structure 160 further includes an interpolar dielectric layer 166, be arranged at cover electrode (maskingelectrode) 165 and gate electrode 167 it
Between, gate electrode 167 is isolated with cover electrode (maskingelectrode) 165.Constitute gate electrode 167 and masking electricity
The material of pole 165 can be but be not limited to heavily doped polysilicon.Constitute the material of interpolar dielectric layer 166
Material can be oxide (such as silicon oxide), nitride (such as nitride) or other insulant, this
It is not intended to limit in invention.
It should be noted that, element groove 120a contributes to increasing groove-type power crystalline substance for deep groove structure
The breakdown voltage of body pipe 1, but the electric capacity (Cgd) and source/drain that can but increase gate/drain are led
Be powered resistance (Rdson).Accordingly, in embodiments of the present invention, arrange in element groove 120a bottoms and hide
Covering electrode 165 can reduce the electric capacity (Cgd) of gate/drain, to reduce work-loss costs.In addition,
Cover electrode (maskingelectrode) 165 can be electrically connected at source electrode, so that drift region 130 reaches charge balance (charge
Balance), and further improve breakdown voltage.Therefore, the impurity doping concentration of drift region 130 can
Relatively improve, to reduce the conducting resistance in drift region 130.Should be noted that in addition, at this
In inventive embodiments, it is the face on the basis of the lower edge of matrix area 140, by element groove 120a substantially
Divide into the first half and lower half.
Insulating barrier 164 is arranged at the internal face of element groove 120a conformally, and with element ditch
The profile that the internal face of groove 120a is consistent.Aforesaid internal face includes the two side of element groove 120a
Face and bottom surface.Insulating barrier 164 is available so that gate electrode 167 and cover electrode (maskingelectrode) 165 and epitaxial layer
120 electrically isolate.
Specifically, insulating barrier 164 include one first dielectric layer 161, one second dielectric layer 162 and
One the 3rd dielectric layer 163.In the present embodiment, by near the medial wall of element groove 120a to close
Gate electrode 167 is sequentially the first dielectric layer 161, the second dielectric layer with the direction of cover electrode (maskingelectrode) 165
162 and the 3rd dielectric layer 163, wherein the 3rd dielectric layer 163 is positioned at element groove lower half, and
And second dielectric layer of the part positioned at element groove 120a lower half is located in the first dielectric layer 161
Between the 3rd dielectric layer 163.
That is, the first dielectric layer 161 and the second dielectric layer 162 are all by element groove 120a's
The first half extends to the lower half and bottom of element groove 120a, but a 3rd dielectric layer 163 then shape
Into in the lower half and bottom of element groove 120a.Therefore, in the present embodiment, positioned at element ditch
First dielectric layer 161 of the groove 120a first halves and the second dielectric layer 162 surround gate electrode 167, and
As gate dielectric.Accordingly, in the first half of element groove 120a, the second dielectric layer 162 is
Between gate electrode 167 and the first dielectric layer 161.
In addition, the first dielectric layer 161, the second dielectric layer 162 positioned at element groove 120a lower half
And the 3rd dielectric layer 163 then surround cover electrode (maskingelectrode) 165 and can as masking dielectric layer.Therefore, the 3rd
Dielectric layer 163 is between the second dielectric layer 162 and cover electrode (maskingelectrode) 165.In one embodiment,
The horizontal plane that the top surface of the 3rd dielectric layer 163 is located is less than the bottom edge of matrix area 140, with
Ensure to produce inverting channel in matrix area 140.
In addition it is noted that the first dielectric layer 161 and the second dielectric layer 162 are by element groove 120a
The first half extends to the structure of element groove 120a lower half, can avoid in element groove 120a
Space or hole are formed, so as to avoid producing gate/source leakage current, and can be improved because of grid/source
The not good situation of electrical performance caused by the leakage current of pole.
In addition, in one embodiment, the dielectric constant (dielectric constant) of the second dielectric layer 162
More than the dielectric constant of the first dielectric layer 161.Therefore, the first dielectric layer 161 and the second dielectric are constituted
The material of layer 162 is different, but constitute the material of the first dielectric layer 161 and the 3rd dielectric layer 163 can be with
Select identical or different material.For example, the first dielectric layer 161 and the 3rd dielectric layer are constituted
163 material can be, but not limited to be oxide, e.g. silicon oxide, and constitute the second dielectric layer 162
Material be nitride, e.g. silicon nitride, or other have the material of high-k, for example
Hafnium oxide, yittrium oxide or aluminium oxide etc..
Therefore, for compared to oxide skin(coating) is only used as gate dielectric, under same thickness,
The gate dielectric of the present embodiment, that is, positioned at the first dielectric layer of the element groove 120a first halves
161 and second dielectric layer 162, can have higher capacitance, also known as grid/channel capacitor value
(gate-to-channel capacitance,Cgs).It is to be illustrated, when gate electrode 167 is applied
Biasing, and when making to form inverting channel (inversion channel) in matrix area 140, grid/passage
Capacitance can be with inverting channel resistance (Rch) into negative correlation.Accordingly, when grid/channel capacitor value increases
When, inverting channel resistance can decline.As inverting channel resistance and source/drain conducting resistance are into positive
Close, therefore inverting channel resistance decrease, further can reduce the source electrode of groove-type power transistor 1/
Drain electrode conducting resistance.
As long as however, can reach the effect above, the material of the first to the 3rd dielectric layer 161～163 also may be used
To be selected different insulant, the present invention to be not limited according to practical application.
In addition, in the present embodiment, the gross thickness root of the first dielectric layer 161 and the second dielectric layer 162
The voltage that groove-type power transistor gate can bear is determined according to groove-type power transistor gross thickness, is led to
It is often between 12V to 25V.Specifically, the thickness of the first dielectric layer is between 10 to 35nm
Between, the thickness of the second dielectric layer is between 20 to 30nm, and the thickness of the 3rd dielectric layer 163
Degree is between 50 to 200nm, and third layer thickness can determine breakdown voltage.
Fig. 1 is continued referring to, in the present embodiment, epitaxial layer 120 is located at terminal area with more one
Terminal trenches 120b in TR.Also, groove-type power transistor 1 is further included and is formed at terminal ditch
Terminal electrode structure 170 in groove 120b.Specifically, terminal electrode structure 170 was included positioned at end
Terminal electrode 172 in the groove 120b of end and to by terminal electrode 172 and epitaxial layer 120 that
The terminal dielectric layer 171 of this isolation.
Furthermore, terminal dielectric layer 171 is the inwall for being arranged at terminal trenches 120b conformally
Face, and the profile being consistent with the internal face with terminal trenches 120b, to electrically isolate terminal electrode
172 with epitaxial layer 120.In the present embodiment, terminal dielectric layer 171 is a layered structure.It is aforementioned
Layered structure be sequentially by first terminal groove 120b medial walls to the direction of terminal electrode 172
Monoxide layer 171a, nitride layer 171b and the second oxide skin(coating) 171c.That is, terminal
The nitride layer 171b of dielectric layer 171 is located in aforementioned first oxide skin(coating) 171a and the second oxide
Between layer 171c.
The groove-type power transistor 1 of the embodiment of the present invention further includes an interlayer dielectric layer 180, at least
One source conductive connector 184 and a conductive layer 190.
Fig. 1 is refer to, interlayer dielectric layer 180 is formed on epitaxial layer 120, and there is a protective layer
181 and a flatness layer 182.
In the present embodiment, protective layer 181 is formed directly on 120 surface of epitaxial layer, and is had repeatedly
Rotating fields.Protective layer 181 is at least including first film layer 181a for being formed at 120 surface of epitaxial layer
The second film layer 181b being formed at one in first film layer 181a.First film layer 181a and the second film layer
The material of 181b can be respectively and in element groove 120a the first dielectric layer 161 and the second dielectric
Layer 162 is identical.That is, when the first dielectric layer 161 is oxide skin(coating), and the second dielectric layer 162
For nitride layer when, protective layer 181 has oxide (the first film layer 181a) and nitride (the second film layer
Layered structure 181b).In that case, the first film layer 181a and the first dielectric layer 161 can be
Formed in same deposition manufacture process.Similarly, the second film layer 181b and the second dielectric layer 162 also can be
Formed in same deposition manufacture process.Detailed fabrication steps will be in being described hereinafter, and here is not repeated.
In other embodiments, constitute the first film layer 181a and the material of the second film layer 181b can also
Different from the second dielectric layer 162 with the first dielectric layer 161, the present invention is not intended to limit.Flatness layer 182
Be formed on protective layer 181, to as subsequent deposition conductive layer 190 and constitute flatness layer 182
Material can be boron-phosphorosilicate glass (BPSG), phosphorosilicate glass (PSG), oxide, nitride or its
Combination.
In addition, interlayer dielectric layer 180 and have an at least source contacts 183.In the present embodiment,
Source contacts 183 are extended in part epitaxial layer 120 by the upper surface of interlayer dielectric layer 180, and
It is formed at the side of source area 150.Also, epitaxial layer 120 further includes a contact doping area 121,
And contact doping area 121 is immediately below the bottom of source contacts 183.In one embodiment,
It is implant boron difluoride (BF2) in epitaxial layer 120 by source contacts 183, to form contact
Doped region 121.
However, the position of source contacts 183 can change according to the design of element, however it is not limited to this
Inventive embodiment.In other embodiments, source contacts 183 can also correspond directly to source electrode
The position in area 150, and be formed at directly over source area 150.
Source conductive connector 184 is formed in source contacts 183, to be electrically connected at source area
150.Specifically, source conductive connector 184 is formed in source contacts 183, and is directly connect
The source area 150 in epitaxial layer 120 and contact doping area 121 are touched, thereby in source conductive
Nurse difficult to understand is formed between connector 184 and source area 150 and contacts (ohmic contact).Constitute source conductive
The material of connector 184 can be metal, such as, but not limited to being, tungsten, copper, nickel or aluminum.
Conductive layer 190 is covered on flatness layer 182, and by being arranged in the source of interlayer dielectric layer 180
Pole conductive plunger 184 is electrically connected at source area 150.That is, conductive layer 190 can be used as ditch
The source electrode of slot type power transistor 1, and it is electrically connected to an external control circuit.It is conductive
The material of layer 190 can be titanium (Ti), titanium nitride (TiN), tungsten (W), alusil alloy (Al-Si)
Or Al-Si-Cu alloy (Al-Si-Cu) etc., but the present invention is not restricted to this.
Fig. 2 is refer to, the part section of the groove-type power transistor of another embodiment of the present invention is shown
Schematic diagram.The groove-type power transistor 1 ' and 1 phase of groove-type power transistor of Fig. 1 of the present embodiment
Same element has identical label, and the present embodiment and previous embodiment identical part are no longer gone to live in the household of one's in-laws on getting married
State.
Where embodiment shown in Fig. 2 is different with previous embodiment it is, in the groove of the present embodiment
In formula power transistor 1 ', the insulating barrier 164 ' of trench gate structure further includes one the 4th dielectric layer 168.
4th dielectric layer 168 is formed at the first half of element groove 120a, and is located in gate electrode 167
Side and the second dielectric layer 162 between.
The first dielectric layer 161, the second dielectric layer 162 positioned at the element groove 120a first halves and
Gate dielectric of 4th dielectric layer 168 as trench gate structure.In one embodiment, constitute the
The material of four dielectric layers 168 can be identical with the first dielectric layer 161, for example, be all silicon oxide.Also,
In the present embodiment, the first dielectric layer 161, the second dielectric layer 162 are total with the 4th dielectric layer 168
Thickness determines the voltage that groove-type power transistor gate can bear, typically between 12V to 25V
Between.Specifically, compared to previous embodiment, the thickness of the first dielectric layer 161 can be relatively thin, greatly
About 10nm, the thickness of the second dielectric layer 162 are constant, between 20nm to 30nm, the 3rd
The thickness of dielectric layer 163 between 50 to 200nm, and the thickness of the 4th dielectric layer 168 between
Between 10nm to 25nm.
In addition, the interpolar dielectric layer 166 ' of the present embodiment includes one first insulating barrier 166a and one second
Insulating barrier 166b, wherein the first insulating barrier 166a and the second insulating barrier 166b are sequentially stacked over masking electricity
On pole 165.That is, the interpolar dielectric layer 166 ' of the present embodiment is layered structure.Implement one
In example, the second insulating barrier 166b can be identical with the material of the 4th dielectric layer 168, and in same system
Formed in journey, but the present invention is not limited.
Then, the embodiment of the present invention provide the processing procedure of groove-type power transistor.Refer to Fig. 3,
Show the processing flow figure of the groove-type power transistor of one embodiment of the invention.In addition, refer to figure
4A to Fig. 4 K, each step in the processing procedure of the groove-type power transistor for illustrating one embodiment of the invention
Partial cutaway schematic.
In step S300, there is provided a base material.Then, in step S301, form epitaxial layer
(epitaxial layer) is on base material.Reference please be coordinate to coordinate reference picture 4A.Base is illustrated in Fig. 4 A
Material 100, and an epitaxial layer (epitaxial layer) 120, wherein base material have been formed on base material 100
100 is, for example, silicon substrate (silicon substrate), its there is the first heavily doped region of high-dopant concentration with
Drain electrode (drain) as groove-type power transistor, epitaxial layer 120 are then low doping concentration.
In the present embodiment, epitaxial layer 120 was being formed before the step on base material 100, further including
A cushion 110 is formed on base material 100.As shown in Figure 4 A, cushion 110 is positioned at base material
Between 100 and epitaxial layer 120.In addition, cushion 110 having and base material 100 and epitaxial layer 120
Identical conductivity type, but the doping content of cushion 110 be between base material 100 doping content with it is outer
Prolong between the doping content of layer 120.In addition, in the present embodiment, epitaxial layer 120 is defined out one
An active region AR and terminal area TR.
Referring again to Fig. 3, then, in step s 302, an at least element groove is formed in extension
In layer.The processing procedure of the groove-type power transistor provided by the present embodiment can be further included, and form element
During groove, terminal trenches are formed in the lump in the epitaxial layer.
Specifically, reference picture 4B, element groove 120a please be coordinate to be formed at active region AR
In, and terminal trenches 120b are formed in the TR of terminal area.Also, in one embodiment, first
First defined behind positions of the element groove 120a with terminal trenches 120b using light shield (non-icon), then
Element groove 120a and terminal ditch are produced in epitaxial layer 120 in the way of dry ecthing or wet etching
Groove 120b.
Then, referring again to Fig. 3.In step S303, trench gate structure is formed in element ditch
In groove, wherein trench gate structure includes cover electrode (maskingelectrode), gate electrode and insulating barrier, wherein insulating barrier
Be arranged at the internal face of element groove conformally, and make gate electrode and masking electricity and epitaxial layer each other every
From.Insulating barrier at least includes the first dielectric layer, the second dielectric layer and the 3rd dielectric layer, wherein the 3rd is situated between
Electric layer is located at element groove lower half, and second dielectric layer of the part positioned at element groove lower half is pressed from both sides
Between the first dielectric layer and the 3rd dielectric layer.
In addition, the method for the groove-type power transistor of the present embodiment is further included：Form terminal electrode knot
Structure is in terminal trenches.Also, forming terminal electrode structure can with the step of forming trench gate structure
Synchronously carry out.Terminal electrode structure includes terminal electrode and terminal dielectric layer, and wherein terminal dielectric layer is suitable
The internal face of first terminal groove is arranged at shape, to isolate terminal electrode and epitaxial layer, wherein terminal
Dielectric layer is at least located in the nitride layer between these oxide skin(coating)s including two-layer oxide skin(coating) and one.
Specifically, Fig. 4 C to Fig. 4 H are refer to, display forms trench gate electrode with terminal electricity
The detailed process of pole structure.Please also refer to Fig. 4 C.In figure 4 c, first is sequentially formed blanket-like
Dielectric material 210, the second dielectric material 220 and the 3rd dielectric material 230 are in element groove 120a
And the internal face (including two side walls and bottom surface) of terminal trenches 120b, and the surface of epitaxial layer 120.
First dielectric material 210 can be oxide skin(coating) or nitride layer.For example, the first dielectric material 210
For silicon oxide (SiOx), and using thermal oxidation process being formed.In other embodiments, it is also possible to profit
The first dielectric material 210 is formed with physical vapour deposition (PVD) or chemical vapor deposition process.
In one embodiment, the dielectric constant of the second dielectric material 220 is above the first dielectric material
210 dielectric constant.For example, when the first dielectric material 210 is silicon oxide, the second dielectric
Material can be nitride, such as silicon nitride, and with physical vapour deposition (PVD) or chemical vapor deposition manner
It is covered on the first dielectric material 210 conformally.
3rd dielectric material 230 can arbitrarily selective oxidation thing or nitride one of which, e.g. oxygen
SiClx (SiO4), is not particularly limited.And it is possible to according to selected material and reality
Demand is selecting to deposit the processing procedure of the 3rd dielectric material 230, e.g. physical vapour deposition (PVD) or chemical gas
Phase deposition manufacture process.
In one embodiment, the thickness of the first dielectric material 210 is between 20 to 30nm, the second dielectric
The thickness of material 220 is between 20 to 30nm, and the thickness of the 3rd dielectric material 230 is between 60
To 120nm.
After the deposition for completing the first to the 3rd dielectric material 210～230, the is first formed blanket-like
One polysilicon structure is on the 3rd dielectric layer 163, and inserts element groove 120a and terminal trenches 120b
In.First polysilicon structure can be the polysilicon structure containing conductive impurities (doped poly-Si).
Then, it is etched back (etch back) and removes the first polysilicon knot covered on 163 surface of the 3rd dielectric layer
Structure, and the first polysilicon structure 240a and terminal trenches positioned at element groove 120a are left respectively
The first polysilicon structure 240b in 120b.
Then, Fig. 4 D are refer to, and a photoresist layer 3 are formed on the 3rd dielectric material 230, wherein
Photoresist layer 3 has an opening 3a, to expose the element groove 120a in active region AR.
That is, photoresist layer 3 covers terminal trenches 120b and the 3rd dielectric material positioned at terminal area TR
The part surface of material 230.Then, first polysilicon of the etching positioned at the element groove 120a first halves
Structure 240a, and leave behind the first polysilicon structure 240a ' positioned at element groove 120a lower half.
After aforementioned etch process is completed, removing photoresistance layer 3 is removed.
Then, Fig. 4 E are refer to, an oxide layer 250 are formed and is covered 230 surface of the 3rd dielectric material,
And insert in element groove 120a and terminal trenches 120b.It is noted that forming oxide layer 250
Processing procedure in, positioned at the top of the first polysilicon structure 240a ' of element groove 120a lower half, with
And the top of the first polysilicon structure 240b in terminal trenches 120b all can be aoxidized by micro-.
After abovementioned steps are completed, in the lower half of element groove 120a, cover electrode (maskingelectrode) 165 ' has been formed.
Then, refer to Fig. 4 F, remove oxide layer 250 positioned at 120 surface of epitaxial layer, and
Positioned at the oxide layer 250 of the element groove 120a first halves, and leave behind part and be located at cover electrode (maskingelectrode) 165 '
The oxide layer 250 ' at top, wherein oxide layer 250 ' can be equivalent to interpolar dielectric layer as shown in Figure 1
166。
In addition, in the step of going to removing oxide layer 250, also can remove in the lump positioned at epitaxial layer 120
Surface and the 3rd dielectric material 230 of part in element groove 120a with terminal trenches 120b.
Specifically, in element groove 120a, positioned at the of the internal face of the element groove 120a first halves
Three dielectric materials 230 can be removed, and leave behind the internal face positioned at element groove 120a lower half
The 3rd dielectric material 230 ', so as to form the 3rd dielectric layer 163 as shown in Fig. 1 and Fig. 2.
Refer to Fig. 4 G.Then, the second polysilicon structure 260 is formed blanket-like is covered in extension
On 120 surface of layer, and insert in element groove 120a and terminal trenches 120b.Specifically,
Two polysilicon structures 260 are the surfaces for being covered in the second dielectric material 220, and insert element groove
In the remaining space of the first half and terminal trenches 120b of 120a.Form the second polysilicon structure 260
Mode can with formed the first polysilicon structure mode it is identical, will not be described here.
Fig. 4 H are refer to, the second polysilicon structure 260 gone above epitaxial layers 120 is etched back, with
Gate electrode 167 is formed in element groove 120a ", and terminal is formed in terminal trenches 120b
Electrode 172 '.Accordingly, it is formed at first dielectric material 210 and of element groove 120a internal faces
Two dielectric materials 220 can be considered separately as the first dielectric layer 161 and the second dielectric layer in Fig. 1
162。
It is to be illustrated, in the fabrication steps for forming trench gate structure and terminal electrode structure
In, all will not initially form the first dielectric in element groove 120a with terminal trenches 120b
Material 210 is removed with the second dielectric material 220.Therefore, will not be as known techniques, in unit
Leave a void or hole in part groove 120a, and gate/source leakage current can be avoided to produce.
Referring again to Fig. 3.Carry out step S304 and step S305.In step s 304, externally
Prolonging layer carries out a body dopant processing procedure, to form a matrix area.In step S305, a source is carried out
To form source region, wherein source area is located above matrix area pole dopping process.
Fig. 4 I are refer to, epitaxial layer 120 is carried out after a body dopant processing procedure, in epitaxial layer 120
The first doped region is formed away from the side of base material 100.After the first doped region is formed, mix to first
Miscellaneous area carries out a source dopant processing procedure to form source area 150 and matrix area 140.It is noted that
Source dopant processing procedure is may include after ion implant is carried out to the first doped region, then carries out a thermal diffusion
Processing procedure, to form source area 150.In addition, can be seen that by Fig. 4 I, the matrix area in the present embodiment
Horizontal level of 140 lowest edge higher than the top surface place of the 3rd dielectric material 230 '.
The processing procedure of the groove-type power transistor provided by the embodiment of the present invention can further include to be formed
Circuit redistribution layer is on epitaxial layer, so that source area 150, gate electrode 167 and cover electrode (maskingelectrode) 165
The control circuit of outside can be electrically connected to.To form the source contact connector shown in Fig. 1 will be below
Example, and coordinate Fig. 4 J to Fig. 4 K, illustrate the concrete steps of circuit redistribution layer.
Refer to Fig. 4 J, formed a flatness layer 270 comprehensively cover 220 surface of the second dielectric material,
Trench gate structure 160 ' and terminal electrode structure 170 '.The material for constituting flatness layer 270 can be selected
Select boron-phosphorosilicate glass (BPSG), phosphorosilicate glass (PSG), oxide, nitride or its combination.
Subsequently, corresponding to the position of source area 150, at least one source contacts 270a (figures are formed
Illustrate in 4J as a example by 2).In the present embodiment.The technological means for forming source contacts 270a can
Realized using steps such as known coating photoresistance, lithographic, etchings.
Then, Fig. 4 K be refer to.Source conductive connector 280 is formed in corresponding source contacts 270a
It is interior.It should be noted that, source conductive connector 280 runs through flatness layer 270, the first dielectric material 210
After the second dielectric material 220, extend in epitaxial layer 120, and positioned at source area 150 its
Middle side, to be electrically connected with source area 150.
It should be noted that, formed source conductive connector 280 in corresponding source contacts 270a it
Before, can first pass through source contacts 270a carries out a dopping process to epitaxial layer 120, with source electrode
A contact doping area 121 is formed in epitaxial layer 120 below contact hole 270a.In one embodiment,
The impurity adulterated by contact doping area 121 is boron difluoride (BF2).
In addition, in formation source conductive connector 280 after corresponding source contacts 270a, can
Further include and to form a conductive layer 290 and be covered on flatness layer 270, and be electrically connected at source conductive and insert
Plug 280.The material of conductive layer 290 can be titanium (Ti), titanium nitride (TiN), tungsten (W), alusil alloy (Al-Si)
Or Al-Si-Cu alloy (Al-Si-Cu) etc., but the present invention is not restricted to this.Accordingly, conductive layer 290
Source area 150 and contact doping area 121 can be electrically connected at by source conductive connector 280.Via
The explanation of above-described embodiment, the art tool usually intellectual should deduce other realities easily
CONSTRUCTED SPECIFICATION is applied, here is not added with repeating.
Further need to illustrate, positioned at first dielectric material of part 210 on 120 surface of epitaxial layer
Protective layer 181 as shown in Figure 1 is equivalent to effect of the second dielectric material 220, and flatness layer 270
The flatness layer 182 being then equivalent to shown in Fig. 1.In addition, being sequentially located on element groove 120a internal faces
First dielectric material 210, the second dielectric material 220 and the 3rd dielectric material 230 can be equivalent to Fig. 1
The insulating barrier 164 of shown trench gate structure 160.
In the present invention and provide another embodiment groove-type power transistor processing procedure.Refer to figure
5A to Fig. 5 B, each step in the processing procedure of the groove-type power transistor for illustrating another embodiment respectively
Partial cutaway schematic.
To be illustrated, the fabrication steps of Fig. 5 A are that Fig. 4 A are extremely in previous embodiment is completed
Perform after fabrication steps shown in 4F.That is, removing positioned at 120 surface of epitaxial layer
Oxide layer 250, and positioned at the oxide layer 250 of the element groove 120a first halves, and leave behind part
After the oxide layer 250 ' at the top of cover electrode (maskingelectrode) 165, one the 4th dielectric material 300 is formed conformal
Be covered in the surface of the second dielectric material 220, and be formed at element groove 120a and terminal trenches
In 120b.The processing procedure for forming the 4th dielectric material 300 can select known deposition manufacture process, and the 4th
Dielectric material 300 can be oxide or nitride.
Then one second polysilicon structure 260 ' is formed, then blanket-like in the 4th dielectric material 300
On.The processing procedure for forming the second polysilicon structure 260 ' may be referred to previously correspond to the system described in Fig. 4 G
Journey, will not be described here.
Subsequently, Fig. 5 B are refer to, eat-back is gone above epitaxial layers 120 and is covered in terminal trenches
The second polysilicon structure 260 on 120b, and leave the second polysilicon in element groove 120a
Structure, to form gate electrode 167a.Accordingly, formed on the internal face of element groove 120a
First to fourth dielectric material 210,220,230 ', 300, can be equivalent to shown in Fig. 2
Insulating barrier 164 '.In addition, in element groove 120a, positioned at the first polysilicon structure 165 ' and
Oxide layer 250 ' and the 4th dielectric layer 300a between two polysilicon structures 260 ' respectively can be schemed
The first film layer 181a and the second film layer 181b shown in 2.
Refer to Fig. 5 C.Matrix area 140 and source area 150 are formed in epitaxial layer 120 respectively subsequently,
And on epitaxial layer 120, be i.e., on the 4th dielectric layer 300, form circuit and reassign layer.Form circuit
The detailed fabrication steps for reassigning layer are similar with the step shown in Fig. 4 J to Fig. 4 K, including：Form one
Flatness layer 270 comprehensively covers 220 surface of the second dielectric material, trench gate structure and terminal electricity
Pole structure；One dopping process is carried out to epitaxial layer 120 by source contacts 270a, with source electrode
A contact doping area 121 is formed in epitaxial layer 120 below contact hole 270a；Form source conductive to insert
Plug 280 is in corresponding source contacts 280；And one conductive layer 290 of formation is covered in flatness layer
On 270, and it is electrically connected at source conductive connector 280.By above-mentioned processing procedure, can be formed such as Fig. 2
Shown groove-type power transistor.
Refer to Fig. 6.Fig. 6 illustrates the local of the groove-type power transistor of another embodiment of the present invention
Broken isometric schematic diagram.
The groove-type power transistor 3 of the present embodiment is can be applicable in voltage conversion circuit, used as downside
The power transistor of (low side).Specifically, the groove-type power transistor 3 of the present embodiment includes
Base material 310, epitaxial layer 330, trench gate structure 360, terminal electrode structure 370, first are to
Three terminal electrode structures 380a～380c, multiple first matrix area 340a, multiple second matrix area 340b
And source area 350.In addition, similar to the embodiment of Fig. 2 with Fig. 1, base material 310 and epitaxial layer
A cushion 320 is had more between 330.First to illustrate, in the present embodiment and Fig. 1 and Fig. 2
Embodiment identical element, no longer especially describe.
In the present embodiment, epitaxial layer 330 is defined out an active region AR, a terminal area TR
And a rectifying section SR.Epitaxial layer 330 is simultaneously located at the unit in active region AR with least one
Part groove 360h, positioned at terminal trenches 370h of terminal area TR, and be located at rectifying section SR
In first terminal groove 381, second terminal groove 382 and third terminal groove 383.
Element groove 360h, terminal trenches 370h, first terminal groove 381, second terminal groove
382 is to be formed in epitaxial layer 330 side by side along a first direction D1 with third terminal groove 383.
In the present embodiment, element groove 360h is adjacent with first terminal groove 381, and has one first
Spacing P1.In addition, in the SR of rectifying section, the first to third terminal groove 381～383 each other it
Between be separated by one second spacing P2, wherein the second spacing P2 is slightly less than the first spacing P1, and the first spacing
Difference between P1 and the second spacing P2 is between 0.1 μm to 0.3 μm.
In the present embodiment, the structure of trench gate structure 360 can be with the ditch shown in Fig. 1 or Fig. 2
Groove grid structure 160 is identical, and in bit unit groove (non-label), wherein element groove is to be located to have
In source region AR.In addition, the first matrix area 340a and source area 350 are positioned at active region AR
In, and be formed in the epitaxial layer 330 of 360 both sides of trench gate structure.
Terminal electrode structure 370 can be identical with the terminal electrode structure 170 shown in Fig. 1 or Fig. 2,
And be located in terminal trenches (non-label), wherein terminal trenches are in the TR of terminal area.It is similar
Ground, the first to third terminal electrode structure 380a～380c can be with the electricity of the terminal shown in Fig. 1 or Fig. 2
Pole structure 170 has identical structure.The first to third terminal electrode structure 380a～380c difference position
In first terminal groove 381, second terminal groove 382 and third terminal groove 383.
To be illustrated, multiple second matrix area 340b are formed at two adjacent first and second
Between terminal electrode structure 380a, 380b, or two second and third adjacent terminal electrode structure
In epitaxial layer 330 between 380b, 380c.
Furthermore, positioned at two first and second adjacent terminal electrode structure 380a, 380b it
Between multiple second matrix area 340b be along second direction D2 arrange, wherein any two are adjacent
Second matrix area 340b is spaced a preset distance, so as to define at least one Schottky contacts
Area 330s.In other words, along two the second adjacent matrix area 340b of second direction D2 arrangement
Between spacing, as length L of the Schottky contact region 330s in second direction D2.Implement one
In example, Schottky contact region 330s is between 0.6 μm to 1.2 μm in length L of second direction D2
Between.In embodiments of the present invention, groove-type power transistor 3 can further include one and be formed at epitaxial layer
On interlayer dielectric layer (not shown) and one be arranged in interlayer dielectric layer an at least conductive plunger (figure
Do not show).
Specifically, interlayer dielectric layer can have at least one corresponding to Schottky contact region 330s's
Contact hole (not shown), and conductive plunger is then located at the extension of Schottky contact region by contact hole contact
Layer, to form a Schottky diode.
Due to making the forward voltage drop of Schottky diode conducting less than the forward voltage drop of body diode, because
This, Schottky diode is established in groove-type power transistor 3, switch cost can be reduced.
In addition, the reverse recovery characteristic of Schottky diode is preferably, when groove-type power transistor 3 is applied
During the circuit of higher frequency, switch cost can be more effectively reduced.
In sum, in the embodiment of the present invention is provided groove-type power transistor and its processing procedure,
After the step of surface of the internal face and epitaxial layer of element groove forms oxide skin(coating) and nitride layer,
Again the oxide layer for being contacted with epitaxial layer and the nitration case for being covered in aforementioned oxidation layer are not removed.
Also, in the case where nitride layer is not removed, follow-up cover electrode (maskingelectrode) is directly carried out with grid electricity
The processing procedure of pole, can avoid the trench-gate of hole or space (void) is produced in channel grid structure
Structure can avoid hole or space are produced in insulating barrier.Therefore, when gate electrode is applied in bias,
Can avoid producing leakage current between gate electrode and drain electrode, so as to groove-type power transistor can be improved
Electrical performance.
Although embodiments of the invention are disclosed as above, the right present invention is not limited to above-described embodiment,
Any art those of ordinary skill, in without departing from scope disclosed in this invention, when can
Make a little change to be defined with claims with adjustment, therefore protection scope of the present invention
Person is defined.
【Symbol description】
Groove-type power transistor 1,1 ', 3
Base material 100,310
Cushion 110,320
Epitaxial layer 120,330
Drift region 130
Matrix area 140
First matrix area 340a
Second matrix area 340b
Source area 150,350
Trench gate structure 160,160 ', 360
Schottky contact region 330s
Active region AR
Terminal area TR
Rectifying section SR
Element groove 120a, 360h
Terminal trenches 120b, 370h
First terminal groove 381
Second terminal groove 382
Third terminal groove 383
Cover electrode (maskingelectrode) 165,165 '
Gate electrode 167,167 ', 167 ", 167a
Insulating barrier 164,164 '
Interpolar dielectric layer 166,166 '
First insulating barrier 166a
Second insulating barrier 166b
First dielectric layer 161
Second dielectric layer 162
3rd dielectric layer 163
Terminal electrode structure 170,170 ', 370
First terminal electrode structure 380a
Second terminal electrode structure 380b
Third terminal electrode structure 380c
Terminal electrode 172,172 '
Terminal dielectric layer 171
First oxide skin(coating) 171a
Nitride layer 171b
Second oxide skin(coating) 171c
Interlayer dielectric layer 180
Source conductive connector 184,280
Source contacts 183,270a
Conductive layer 190,290
Protective layer 181
First film layer 181a
Second film layer 181b
Flatness layer 182,270
Contact doping area 121
4th dielectric layer 168
First dielectric material 210
Second dielectric material 220
3rd dielectric material 230,230 '
First polysilicon structure 240a, 240b, 240a ', 240b '
Photoresist layer 3
Opening 3a
Oxide layer 250,250 '
Second polysilicon structure 260,260 '
4th dielectric material 300,300a
First direction D1
Second direction D2
First spacing P1
Second spacing P2
Length L
Process step S300～S305.
Claims (10)
1. a kind of groove-type power transistor, it is characterised in that the groove-type power transistor includes：
One base material；
One epitaxial layer, on the base material, wherein, the epitaxial layer has an at least element ditch
Groove is formed at wherein；
One trench gate structure, in the element groove, wherein, the trench gate structure
Including：
One cover electrode (maskingelectrode), positioned at the lower half of the element groove；
One gate electrode, positioned at the first half of the element groove, and with the cover electrode (maskingelectrode)
It is electrically insulated；And
One insulating barrier, be arranged in the element groove and with the element groove in
The profile that wall is consistent, wherein, the gate electrode and the cover electrode (maskingelectrode) pass through the insulation
Layer is isolated from each other with the epitaxial layer, wherein, the insulating barrier at least includes one first dielectric
Layer, one second dielectric layer and one the 3rd dielectric layer, wherein, the 3rd dielectric layer is located at
The lower half of the element groove, and part be located at the lower half of the element groove this
Two dielectric layers are located between first dielectric layer and the 3rd dielectric layer, wherein,
Dielectric constant of the dielectric constant of second dielectric layer more than first dielectric layer；
One matrix area, is formed in the epitaxial layer, and around the trench gate structure；And
Source region, is formed at the top of the matrix area.
2. groove-type power transistor according to claim 1, wherein, the epitaxial layer is further included
At least one is formed at the terminal trenches in the epitaxial layer, and the groove-type power transistor is more wrapped
At least one terminal electrode structure being formed in the terminal trenches is included, wherein, the terminal electrode
Structure includes：
One terminal electrode, in the terminal trenches；And
One terminal dielectric layer, is arranged at the internal face of the terminal trenches, and with the terminal
The profile that the internal face of groove is consistent to isolate the terminal electrode and the epitaxial layer, wherein, should
Terminal dielectric layer is at least located between those oxide skin(coating)s including two-layer oxide skin(coating) and one
Nitride layer.
3. groove-type power transistor according to claim 1, wherein, the trench gate structure
An interpolar dielectric layer is further included, is formed between the gate electrode and the cover electrode (maskingelectrode).
4. groove-type power transistor according to claim 1, wherein, first dielectric layer
, between 10nm to 35nm, the thickness of second dielectric layer is between 20nm to 30 for thickness
Between nm, the thickness of the 3rd dielectric layer is between 50nm to 200nm.
5. groove-type power transistor according to claim 1, wherein, the insulating barrier is further included
One the 4th dielectric layer, is formed at the first half of the element groove, and the 4th dielectric layer sandwiched
Between second dielectric layer and the gate electrode.
6. groove-type power transistor according to claim 5, wherein, first dielectric layer
Thickness is 10nm, and, between 20nm to 30nm, this for the thickness of second dielectric layer
Between 50nm to 200nm, the thickness of the 4th dielectric layer is situated between the thickness of three dielectric layers
Between 10nm to 25nm.
7. groove-type power transistor according to claim 1, further includes：
One interlayer dielectric layer, is formed on the epitaxial layer, wherein, the interlayer dielectric layer has
At least one source contacts；And
An at least source conductive connector, is formed in the source contacts, to be electrically connected at
The source area.
8. groove-type power transistor according to claim 7, wherein, the interlayer dielectric layer bag
A protective layer for being formed directly into the epi-layer surface is included, wherein, the protective layer is oxidation
Thing and nitride stack structure.
9. a kind of groove-type power transistor, it is characterised in that the groove-type power transistor includes：
One base material；
One epitaxial layer, on the base material, wherein, the epitaxial layer is defined out an active area
The unit in the active region is located at at least one in domain and a rectifying section, and the epitaxial layer
Part groove, and the first terminal groove and a second terminal ditch in the rectifying section
Groove；
One trench gate structure, is formed in the element groove；
One first matrix area, is formed in the epitaxial layer, and is located in the active region and ring
Around the trench gate structure；
Source region, is formed at the top of first matrix area；
One first terminal electrode structure, is formed in the first terminal groove；
One second terminal electrode structure, is formed in the second terminal groove, wherein, the ditch
Groove grid structure, the first terminal electrode structure be adjacent with the second terminal electrode structure and edge
A first direction arranged side by side；And
At least two second matrix areas, positioned at the first terminal electrode structure and the second terminal
In epitaxial layer between electrode structure, and arrange along a second direction, wherein, two is adjacent
Those second matrix areas be spaced a preset distance, to define at least one Schottky
Contact area.
10. groove-type power transistor according to claim 9, wherein, the element groove with should
First terminal groove is adjacent, and is separated by one first spacing, the first terminal groove with this second
Terminal trenches are adjacent and have one second spacing, wherein, this second is smaller than this between first
Away from, and the difference between first spacing and second spacing between 0.1 μm to 0.3 μm it
Between.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110838486A (en) * | 2018-08-17 | 2020-02-25 | 力智电子股份有限公司 | Power transistor element |
| CN112201685A (en) * | 2020-09-08 | 2021-01-08 | 浙江大学 | Super junction device and dielectric combined terminal |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101785091A (en) * | 2007-08-21 | 2010-07-21 | 飞兆半导体公司 | Method and structure for shielded gate trench FET |
| CN101950720A (en) * | 2005-12-28 | 2011-01-19 | 万国半导体股份有限公司 | Circular hole masked grating groove MOSFET device and production technology thereof |
| JP2012049562A (en) * | 2011-11-04 | 2012-03-08 | Renesas Electronics Corp | Semiconductor device |
| CN103346166A (en) * | 2012-06-12 | 2013-10-09 | 成都芯源系统有限公司 | Semiconductor device and method for manufacturing the same |
| US20130330892A1 (en) * | 2009-11-20 | 2013-12-12 | Force Mos Technology Co., Ltd. | Trench mosfet with trenched floating gates having thick trench bottom oxide as termination |
| US20140203355A1 (en) * | 2005-04-06 | 2014-07-24 | Fairchild Semiconductor Corporation | Field effect transistor and schottky diode structures |
| CN104425628A (en) * | 2013-08-22 | 2015-03-18 | 大中积体电路股份有限公司 | Semiconductor power component and semiconductor structure thereof |
-
2015
- 2015-10-19 CN CN201510680019.XA patent/CN106601811B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20140203355A1 (en) * | 2005-04-06 | 2014-07-24 | Fairchild Semiconductor Corporation | Field effect transistor and schottky diode structures |
| CN101950720A (en) * | 2005-12-28 | 2011-01-19 | 万国半导体股份有限公司 | Circular hole masked grating groove MOSFET device and production technology thereof |
| CN101785091A (en) * | 2007-08-21 | 2010-07-21 | 飞兆半导体公司 | Method and structure for shielded gate trench FET |
| US20130330892A1 (en) * | 2009-11-20 | 2013-12-12 | Force Mos Technology Co., Ltd. | Trench mosfet with trenched floating gates having thick trench bottom oxide as termination |
| JP2012049562A (en) * | 2011-11-04 | 2012-03-08 | Renesas Electronics Corp | Semiconductor device |
| CN103346166A (en) * | 2012-06-12 | 2013-10-09 | 成都芯源系统有限公司 | Semiconductor device and method for manufacturing the same |
| CN104425628A (en) * | 2013-08-22 | 2015-03-18 | 大中积体电路股份有限公司 | Semiconductor power component and semiconductor structure thereof |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110838486A (en) * | 2018-08-17 | 2020-02-25 | 力智电子股份有限公司 | Power transistor element |
| CN110838486B (en) * | 2018-08-17 | 2023-04-07 | 力智电子股份有限公司 | Power transistor element |
| CN112201685A (en) * | 2020-09-08 | 2021-01-08 | 浙江大学 | Super junction device and dielectric combined terminal |
| CN112201685B (en) * | 2020-09-08 | 2022-02-11 | 浙江大学 | Super junction device and dielectric combined terminal |
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