CN106549056B - Bigrid groove-type power transistor and its manufacturing method - Google Patents
Bigrid groove-type power transistor and its manufacturing method Download PDFInfo
- Publication number
- CN106549056B CN106549056B CN201510607082.0A CN201510607082A CN106549056B CN 106549056 B CN106549056 B CN 106549056B CN 201510607082 A CN201510607082 A CN 201510607082A CN 106549056 B CN106549056 B CN 106549056B
- Authority
- CN
- China
- Prior art keywords
- dielectric layer
- layer
- electrode
- terminal
- maskingelectrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 25
- 230000000873 masking effect Effects 0.000 claims abstract description 22
- 239000010410 layer Substances 0.000 claims description 352
- 239000000758 substrate Substances 0.000 claims description 41
- 239000011159 matrix material Substances 0.000 claims description 28
- 238000000034 method Methods 0.000 claims description 26
- 239000011229 interlayer Substances 0.000 claims description 23
- 239000000463 material Substances 0.000 claims description 21
- 150000004767 nitrides Chemical class 0.000 claims description 11
- 239000002019 doping agent Substances 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 9
- 230000005611 electricity Effects 0.000 claims description 6
- 238000000407 epitaxy Methods 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 13
- 239000012535 impurity Substances 0.000 description 12
- 229920005591 polysilicon Polymers 0.000 description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 239000013078 crystal Substances 0.000 description 8
- 238000005240 physical vapour deposition Methods 0.000 description 8
- 230000015556 catabolic process Effects 0.000 description 7
- 239000003990 capacitor Substances 0.000 description 6
- 230000000875 corresponding effect Effects 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 229910045601 alloy Inorganic materials 0.000 description 4
- 239000000956 alloy Substances 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 230000012447 hatching Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- OKZIUSOJQLYFSE-UHFFFAOYSA-N difluoroboron Chemical compound F[B]F OKZIUSOJQLYFSE-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- -1 phosphonium ion Chemical class 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 239000004575 stone Substances 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical group [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- 229910000632 Alusil Inorganic materials 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- KZNMRPQBBZBTSW-UHFFFAOYSA-N [Au]=O Chemical compound [Au]=O KZNMRPQBBZBTSW-UHFFFAOYSA-N 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- REDXJYDRNCIFBQ-UHFFFAOYSA-N aluminium(3+) Chemical compound [Al+3] REDXJYDRNCIFBQ-UHFFFAOYSA-N 0.000 description 1
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 210000000746 body region Anatomy 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000002596 correlated effect Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- CKHJYUSOUQDYEN-UHFFFAOYSA-N gallium(3+) Chemical compound [Ga+3] CKHJYUSOUQDYEN-UHFFFAOYSA-N 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 229910052909 inorganic silicate Inorganic materials 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 1
- 238000012216 screening Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000012144 step-by-step procedure Methods 0.000 description 1
Classifications
-
- H01L29/78—
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H01L29/4232—
-
- H01L29/66477—
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The present invention provides a kind of bigrid groove-type power transistor and its manufacturing method.The groove structure of bigrid groove-type power transistor is located in an epitaxial layer, and it is adjacent to the shallow channel section of two opposite sides of deep trench respectively including at least deep trench and two, it is wherein equipped with gate structure in each shallow channel section, is equipped with cover electrode (maskingelectrode) structure in deep trench.The gate insulating layer of gate structure includes at least one first dielectric layer, one second dielectric layer and a third dielectric layer, wherein the second dielectric layer is located between the first dielectric layer and third dielectric layer, and part of grid pole insulating layer is contacted with the masking dielectric layer of cover electrode (maskingelectrode) structure.
Description
Technical field
The present invention relates to a kind of power MOSFET transistors, and in particular to a kind of bigrid groove-type power crystal
Pipe.
Background technique
Power MOSFET transistor (Power Metal Oxide Semiconductor Field
Transistor, Power MOSFET) it is widely used in the switching element of electric device, e.g. power supply unit, whole
Flow device or low voltage motor controller etc..Power MOSFET transistor now takes the design of vertical structure more, to mention
Rise component density.Such power MOSFET transistor for adopting vertical structure design is also referred to as groove-type power type gold oxygen half
Field-effect transistor, its advantage is that can be under the situation for expending low-power, control voltage carries out the operation of element.
Influence power MOSFET transistor element characteristic parameter include source/drain conducting resistance (Rdson),
Breakdown voltage (breakdown voltage) and switch speed (switching speed) etc..However, for power gold oxygen
For half field effect transistor, it is positively correlated between source/drain conducting resistance (Rdson) and breakdown voltage.That is, for
While reducing source/drain conducting resistance and improve the doping concentration of drift region and either reduce drift region thickness, also can
Breakdown voltage is caused to reduce.
Therefore, in order to maintain power MOSFET transistor still under relatively low source/drain conducting resistance
Higher breakdown voltage can form the cover electrode (maskingelectrode) structure extended in drift region in gate trench.
In the structure of Partial Power metal-oxide half field effect transistor, two gate electrodes and cover electrode (maskingelectrode) are juxtaposed on together
In one groove, and it is electrically insulated by oxide layer.Furthermore, cover electrode (maskingelectrode) be located between two gate electrodes, and by
Epitaxy layer surface extends in drift region.
However, when making such power MOSFET transistor, the step of forming grid oxic horizon, it is used to formation
The step of insulating layer between isolated gate electrode and cover electrode (maskingelectrode), is formed in technique with along with, this will cause gate electrode
Thickness of insulating layer between cover electrode (maskingelectrode) is relatively low, and causes the capacitor between grid and source electrode higher.
In addition, due to the limitation in process conditions, because bottom oxidization layer is not easy to deposit, thus it is relatively thin, especially in grid
Electrode bottom end is more likely formed point effect close to the side of cover electrode (maskingelectrode), so that the resistance to drops that grid can be born, this is in high temperature
When be easier deteriorate, occur reliability issues, influence the component life of power MOSFET transistor.
Summary of the invention
The present invention provides a kind of bigrid groove-type power transistor and its manufacturing method, wherein completing to be located at shallow trench
The manufacturing process of the gate electrode in portion and then step is etched to form deep trench.In addition, forming deep trench
In the process, by the nitride layer in gate insulating layer as lateral hard cover power, it can avoid the grid electricity positioned at shallow channel section
Pole is etched.
Wherein an embodiment provides a kind of bigrid groove-type power transistor, including substrate, epitaxial layer, two to the present invention
Gate structure, cover electrode (maskingelectrode) structure, matrix area and source area.Epitaxial layer is located on substrate, wherein epitaxial layer definition at least unitary
Part region, and epitaxial layer has a groove structure being located in element area, wherein groove structure includes a deep trench and two
The shallow channel section of a two opposite sides for being adjacent to deep trench respectively.Two gate structures are respectively arranged at two shallow channel sections
Interior, wherein each gate structure includes a gate insulating layer and a gate electrode, and wherein gate insulating layer covers conformally
In the inner wall of corresponding shallow channel section, so that gate electrode is electrically insulated with epitaxial layer, and gate insulating layer includes first
Dielectric layer, the second dielectric layer and third dielectric layer, wherein the second dielectric layer be located in the first dielectric layer and third dielectric layer it
Between.Cover electrode (maskingelectrode) structure is located in deep trench, and wherein cover electrode (maskingelectrode) structure includes masking dielectric layer and a cover electrode (maskingelectrode), the screening
The inner wall that dielectric layer covers the deep trench conformally is covered, so that cover electrode (maskingelectrode) is electrically insulated with epitaxial layer, and is located at and hides
The part masking dielectric layer for covering two opposite sides of electrode is contacted with the gate insulating layer being located in two shallow channel sections.In epitaxy
Matrix area is formed in layer, and around two gate structures.Source area is formed in above matrix area.
In an alternative embodiment of the invention, a kind of manufacturing method of bigrid groove-type power transistor is provided comprising
The following steps.One substrate is provided first, forms an epitaxial layer on substrate, wherein epitaxial layer defines an element area.Then, exist
Multiple shallow trench are formed in epitaxial layer, and these shallow trench are located in element area.Then, it is formed respectively in these shallow trench
First insulating layer and gate electrode, wherein the first insulating layer covers the inner wall of shallow trench conformally, and insulating layer includes first
Dielectric layer, the second dielectric layer and third dielectric layer, wherein the second dielectric layer is located between the first dielectric layer and third dielectric layer.
Then, an etching step is executed, to form multiple deep trench in epitaxial layer, wherein each deep trench is in close proximity to these shallow ridges
At least one shallow trench in slot, and when executing etching step is as a side by the second dielectric layer to hard cover power.It
Afterwards, second insulating layer and cover electrode (maskingelectrode) are formed in each deep trench, wherein second insulating layer covers each depth conformally
The inner wall of groove, and keep cover electrode (maskingelectrode) and the epitaxial layer mutually isolated, and second insulating layer contacts the second dielectric layer.Later,
Body dopant process and source dopant process are carried out to epitaxial layer, to form matrix area and source area in element area, wherein
Source area is located above matrix area.
In conclusion bigrid groove-type power transistor provided by the present invention and its manufacturing process method, grid electricity
Be between pole and cover electrode (maskingelectrode) it is mutually isolated by thicker masking dielectric layer and part of grid pole insulating layer, can relative reduction grid
Generated capacitor between electrode and cover electrode (maskingelectrode).In addition, in the manufacturing process provided by the embodiment of the present invention, gate electrode
It will form the point of stored charge, less so as to make bigrid groove-type power transistor have preferable electrical performance.
To make the foregoing features and advantages of the present invention clearer and more comprehensible, preferred embodiment is cited below particularly, and appended by cooperation
Schema is described in detail below.
Detailed description of the invention
Figure 1A is painted the schematic top plan view of the bigrid groove-type power transistor of one embodiment of the invention.
Figure 1B is painted Figure 1A along the diagrammatic cross-section of H-H hatching.
Fig. 1 C is painted Figure 1A along the diagrammatic cross-section of I-I hatching.
Fig. 2 shows the fabrication process flow figure of the bigrid groove-type power transistor of one embodiment of the invention.
Fig. 3 A to Fig. 3 H is painted respectively in the manufacturing process of bigrid groove-type power transistor of one embodiment of the invention
The partial cutaway schematic of each step.
[symbol description]
Bigrid groove-type power transistor 1
Substrate 100
Buffer layer 110
Epitaxial layer 120
Drift region 130
Matrix area 140
Source area 150
Groove structure 160
Shallow trench 160a '
Shallow channel section 160a
Deep trench 160b '
Deep trench 160b
Gate structure 170
Gate insulating layer 171
Gate electrode 172
First dielectric layer 171a, 171a '
Second dielectric layer 171b
Third dielectric layer 171c
Cover electrode (maskingelectrode) structure 180
Cover dielectric layer 181
Cover electrode (maskingelectrode) 182
Terminal trenches 160c
Terminal electrode structure 185
Terminal dielectric layer 183
Terminal electrode 184
Element area AR
Terminal area TR
Interlayer dielectric layer 190
First contact hole 191a~191c
Second contact hole 193
First conductive plunger 192a~192c
Second conductive plunger 194
Source conductive layer 200S
Grid conducting layer 200G
Insulating layer 171 '
Contact doping area 121
Photoresist layer 300
Be open 300a
First side S1
Second side S2
Thickness T1, T2
Process step S200~S207
Specific embodiment
Please refer to Figure 1A to Fig. 1 C.Figure 1A is painted the part of the bigrid groove-type power transistor of one embodiment of the invention
The schematic diagram of the section structure.Figure 1B is painted Figure 1A along the diagrammatic cross-section of H-H hatching.Fig. 1 C is painted Figure 1A along I-I hatching
Diagrammatic cross-section.
Please also refer to Figure 1B, bigrid groove-type power transistor 1 includes substrate 100, epitaxial layer 120, at least two grid
Pole structure 170, cover electrode (maskingelectrode) structure 180, matrix area 140 and source area 150.
In Figure 1A to Fig. 1 C, substrate 100 has the first type conductive impurities of high concentration, and forms the first heavy doping
Area.First heavily doped region is intended for the drain electrode (drain) of groove-type power transistor, and can be distributed in the office of substrate 100
It portion region or is distributed in entire substrate 100.It is distributed across in entire substrate 100 in first heavily doped region of the present embodiment,
But it is only used for citing rather than to limit the present invention.First type conductive impurities above-mentioned can be N-type or P-type conductivity is miscellaneous
Matter.Assuming that substrate 100 is silicon substrate, N-type conductivity impurity is pentad ion, such as phosphonium ion or arsenic ion, and p-type is led
Electrical impurity is triad ion, such as boron ion, aluminium ion or gallium ion.
If groove-type power transistor is N-type, 100 doped N-type conductive impurities of substrate.On the other hand, if p-type groove
Formula power transistor, then 100 doped p-type conductive impurities of substrate.It is with N-type groove-type power crystal in the embodiment of the present invention
Illustrate for pipe.
Epitaxial layer (epitaxial layer) 120 is located on substrate 100, and the first type electric conductivity with low concentration is miscellaneous
Matter.That is, substrate 100 is the n-type doping (N+) of high concentration, and epitaxial layer 120 is then low dense by taking NMOS transistor as an example
The n-type doping (N-) of degree.Conversely, substrate 100 is that the p-type of high concentration adulterates (P+doping), and builds by taking PMOS transistor as an example
Crystal layer 120 then adulterates (P-doping) for the p-type of low concentration.
In the present embodiment, bigrid groove-type power transistor 1 further includes one being set to epitaxial layer 120 and substrate 100
Between buffer layer 110.Buffer layer 110 and substrate 100 and the conductivity type having the same of epitaxial layer 120, imply that in buffer layer 110
Also the first type conductive impurities are doped.It should be particularly noted that, the doping concentration of buffer layer 110 is mixing between substrate 100
Between miscellaneous concentration and the doping concentration of epitaxial layer 120.By the way that buffer layer 110 is set between substrate 100 and epitaxial layer 120,
Source/drain conducting resistance (on-state source/drain resistance, Rdson) can be reduced, to reduce double
The power consumption of gate trench formula power transistor 1.
In addition, by can be by area in different zones doping various concentration and different types of conductive impurities, epitaxial layer 120
It is divided into drift region 130 (drift region), matrix area 140 (body region) and source area 150 (source region).
Matrix area 140 and source area 150 are formed in the epitaxial layer 120 of 160 side of groove structure, and drift region 130 is then positioned at of heap of stone
Close to the side of substrate 100 in crystal layer 120.That is, matrix area 140 is formed at the upper of epitaxial layer 120 with source area 150
Half portion, drift region 130 are then formed in the lower half of epitaxial layer 120.
Specifically, matrix area 140 is formed and adulterating second type conductive impurities in epitaxial layer 120, and source
Polar region 150 be then by matrix area 140 adulterate high concentration first type conductive impurities and formed, and source area 150 is shape
At in the upper half of matrix area 140.For example, for pair nmos transistor, matrix area 140 is that p-type adulterates (such as p type wells, P-
Well), and source area 150 be n-type doping.In addition, the doping concentration of matrix area 140 is less than the doping concentration of source area 150.
Please refer to Figure 1A and Figure 1B.In the present embodiment, epitaxial layer 120 is defined out an element area AR and around member
The terminal area TR of part region AR.Matrix area 140 above-mentioned is formed in element area AR and terminal area TR, and source area
150 are formed only in element area AR.There is epitaxial layer 120 at least one to be located at the groove structure 160 in element area AR,
An and terminal trenches 160c being located in the TR of terminal area.Figure 1A is please referred to, it is seen by top view, terminal trenches 160c ring
Generally in a ring around element area AR.
In addition, please referring to the groove structure 160 of Figure 1B embodiment of the present invention has the portion a deep trench (deep trench)
The shallow channel section 160a of 160b and two two opposite side for being adjacent to deep trench 160b respectively.That is, deep trench
160b is to be located between two shallow channel section 160a, also, deep trench 160b extends downward into base by the surface of epitaxial layer 120
Body area 140 is hereinafter, namely extend in drift region 130, and the closer substrate 100 in bottom of deep trench 160b.Shallow ridges
Groove portion 160a matrix area 140 is equally extended downward by the surface of epitaxial layer 120 hereinafter, but shallow channel section 160a bottom then compared with
Far from substrate 100.
In the embodiment of the present invention, at least two gate structures 170, which respectively correspond, to be set in these shallow channel sections 160a.Grid
Pole structure 170 has gate insulating layer 171 and gate electrode 172, and wherein gate insulating layer 171 covers corresponding conformally
The inner wall of shallow channel section 160a, so that gate electrode 172 is electrically insulated with epitaxial layer 120.Inner wall above-mentioned includes shallow ridges
The side wall surface of the bottom surface of groove portion 160a and the wherein side far from deep trench 160b.
Gate electrode 172 is located in the groove that gate insulating layer 171 is defined in shallow channel section 160a.Implement one
In example, the material for constituting gate electrode 172 be may be, but not limited to, the polysilicon of heavy doping.
Furthermore, gate insulating layer 171 includes one first dielectric layer 171a, one second dielectric layer 171b and a third
Dielectric layer 171c.In the present embodiment, sequentially by the inner wall close to shallow channel section 160a to the direction of close gate electrode 172
For the first dielectric layer 171a, the second dielectric layer 171b and third dielectric layer 171c, wherein at least the second dielectric layer of part 171b quilt
It is located between the first dielectric layer 171a and third dielectric layer 171c.
In one embodiment, the dielectric constant (dielectric constant) of the second dielectric layer 171b is greater than first and is situated between
The dielectric constant of electric layer 171a.Therefore, it is different from the material of the second dielectric layer 171b to constitute the first dielectric layer 171a, but composition the
The material of one dielectric layer 171a and third dielectric layer 171c can choose identical or is different material.For example, the is constituted
The material of one dielectric layer 171a and third dielectric layer 171c can be, but not limited to be oxide, e.g. silica, and constitute the
The material of two dielectric layer 171b is nitride, e.g. silicon nitride or other materials with high dielectric constant, such as is aoxidized
Hafnium, yttrium oxide or aluminium oxide etc..
Therefore, for compared to oxide skin(coating) is only used as gate insulating layer, under same thickness, the grid of the present embodiment
Pole insulating layer, including being namely located at the first of side of the shallow channel section 160a far from deep trench 160b to third dielectric layer
171a~171c can have higher capacitance, also known as grid/channel capacitor value (gate-to-channel
capacitance,Cgs).It should be particularly noted that, when gate electrode 172 is applied bias, and make to be formed in matrix area 140 anti-
When turning channel (inversion channel), grid/channel capacitor value can be inversely proportional with inverting channel resistance value (Rch).Accordingly,
When grid/channel capacitor value increases, inverting channel resistance value can decline.Due to inverting channel resistance value and source/drain electric conduction
Directly proportional, therefore inverting channel resistance decrease is hindered, the source/drain of bigrid groove-type power transistor 1 can be further decreased
Conducting resistance.
In addition, in one embodiment, the second dielectric layer 171b is nitride layer, it can be in the mistake for forming deep trench 160b
Cheng Zhong is etched as lateral hard cover power to avoid gate electrode 172.As long as however, can reach said effect, first to
The material of third dielectric layer 161~163 can also select different insulating materials according to practical application, the present invention not as
Limit.
It is noted that the part of first dielectric layer 171a close to deep trench 160b may form deep trench
It is partly removed during 160b.Form the process and the first dielectric layer 171a and the of bigrid plough groove type transistor 1
The effect of two dielectric layer 171b, will be in being hereinafter described in detail.
Accordingly, if the side of the closer deep trench 160b of gate electrode 172 is defined as the first side S1, and grid is electric
Pole 172 is defined as second side S2 further away from the side of deep trench 160b, then contacts gate insulating layer 171 packets of the first side S1
Include the second dielectric layer 171b and third dielectric layer 171c.That is, the thickness t1 of the gate insulating layer 171 of the first side S1 of contact
The thickness t2 of the gate insulating layer 171 of contact second side S2 can be less than.
In the present embodiment, the overall thickness of the first dielectric layer 161 and the second dielectric layer 162 is according to bigrid groove-type power
The voltage to be born of transistor 1 (about 20 to 25V) and set.In one embodiment, the first dielectric layer 161 and the second dielectric layer
162 overall thickness is about between 30nm between 65nm.Specifically, the thickness of the first dielectric layer 171a between 10nm extremely
Between 35nm, the thickness of the second dielectric layer 171b between 20nm between 30nm, the thickness of third dielectric layer 171c between 7nm extremely
Between 10nm.
Cover electrode (maskingelectrode) structure 180 is located in deep trench 160b, and including masking dielectric layer 181 and a cover electrode (maskingelectrode) 182.
Cover electrode (maskingelectrode) 182 positioned at deep trench 160b is by extending downwardly close to the position on 120 surface of epitaxial layer and being more than grid electricity
Horizontal position where the bottom of pole 172.
Masking dielectric layer 181 covers the inner wall of deep trench 160b then conformally, so that cover electrode (maskingelectrode) 182 and epitaxial layer
120 are electrically insulated.In addition, the part for being located at two opposite sides of cover electrode (maskingelectrode) 182 covers the meeting of dielectric layer 181 and is located at shallow trench
Gate insulating layer 171 in portion 160a contacts.Still further, part masking dielectric layer 181 can be with the second dielectric layer 171b
Directly contact.
That is, in embodiments of the present invention, cover electrode (maskingelectrode) 182 and gate electrode 172 are by covering dielectric layer 181
It is mutually isolated with the gate insulating layer 171 for the first side for being located at gate electrode 172, to can guarantee cover electrode (maskingelectrode) 182 and grid
Electrode 172 is separated farther out.Grid are formed by between cover electrode (maskingelectrode) 182 and gate electrode 172 in this way, can further decrease
Pole/source capacitance (Cgs), and switch cost can be reduced.
In one embodiment, the material for constituting masking dielectric layer 181 can be either other insulation of oxide, nitride
Material, and the material for constituting cover electrode (maskingelectrode) 182 can be the polysilicon of heavy doping, but cover dielectric layer 181 and cover electrode (maskingelectrode) 182
Material be not restricted to previous embodiment in the present invention.
In addition, it should be noted that, in embodiments of the present invention, setting is electrically connected at source electrode in deep trench 160b
Cover electrode (maskingelectrode) 182 can make drift region 130 reach charge balance (charge balance), and further increase breakdown voltage.Cause
This, the impurity doping concentration of drift region 130 can relatively improve, to reduce source/drain conducting resistance.
Please with reference to Figure 1A and Figure 1B.The bigrid groove-type power transistor 1 of the embodiment of the present invention further includes at least
One is formed in the terminal electrode structure 185 in terminal trenches 160c, and wherein terminal electrode structure 185 includes a terminal electrode 184
An and terminal dielectric layer 183.Terminal electrode 184 is located in terminal trenches 160c, and around element area AR.Terminal dielectric layer
183 cover the inner wall of terminal trenches 160c conformally, so that terminal electrode 184 is electrically insulated with epitaxial layer 120.
In one embodiment, the material for constituting terminal dielectric layer 183 can choose oxide or nitride, the present invention not with
This is limited.In the present embodiment, terminal electrode 184 can be electrically connected to source electrode, and can increase bigrid groove-type power crystal
The breakdown voltage of 1 element of pipe.
Figure 1A to Fig. 1 C is please referred to, the bigrid groove-type power transistor 1 of the embodiment of the present invention further includes interlayer dielectric
Layer 190, multiple first conductive plunger 191a~191c, multiple second conductive plungers 194, source conductive layer 200S and Gate Electrode Conductive
Layer 200G.
Interlayer dielectric layer 190 is located on epitaxial layer 120, and the material for constituting interlayer dielectric layer 190 can be boron-phosphorosilicate glass
(BPSG), phosphorosilicate glass (PSG), oxide, nitride or combinations thereof.In addition, interlayer dielectric layer 190 and having multiple first connects
Touch window 191a~191c (as shown in Figure 1B) and multiple second contact holes 193 (as shown in Figure 1 C).
Figure 1A and Figure 1B are please referred to, in the present embodiment, a portion the first contact hole 191a is by interlayer dielectric layer 190
Upper surface extend to the terminal electrode 184 in the TR of terminal area.
The first contact hole 191b of another part is extended to the part epitaxial layer in element area AR by interlayer dielectric layer 190
In 120, and it is formed in the side of source area 150.Also, epitaxial layer 120 further includes a contact doping area 121, and contact doping
Area 121 is immediately below the bottom of these first contact holes 191b.In one embodiment, be by the first contact hole 191b,
Implant boron difluoride (the BF in epitaxial layer 1202), to form contact doping area 121.
However, the position of the first contact hole 191b can according to element design and change, however it is not limited to implementation of the invention
Example.In other embodiments, these first contact holes 191b can also correspond directly to the position of source area 150, and be formed in
Right above source area 150.In addition some first contact hole 191c, which is then extended to by the upper surface of interlayer dielectric layer 190, is located at
In cover electrode (maskingelectrode) 182 in element area AR.
Multiple first conductive plunger 192a~192c are respectively formed, in first contact hole 191a~191c with electrical respectively
It is connected to terminal electrode 184, source area 150 and cover electrode (maskingelectrode) 182.Specifically, forming in the first contact hole 191a
One conductive plunger 192a, and Ohmic contact is formed between terminal electrode 184.Similarly, it is formed in the first contact hole 191c
First conductive plunger 192c, to form Ohmic contact between cover electrode (maskingelectrode) 182.In addition, being formed in the first contact hole 191b
First conductive plunger 192b, and directly contact is located at source area 150 and contact doping area 121 in epitaxial layer 120, exists whereby
Ohmic contact (ohmic contact) is formed between first conductive plunger 191b and source area 150.
Fig. 1 C is please referred to, multiple second contact holes 193 are then extended to by the surface of interlayer dielectric layer 190 positioned at element area
In the gate electrode 172 of AR.Multiple second conductive plungers 194 are then respectively formed in these second contact holes 193, with respectively and
Ohmic contact is formed between multiple gate electrodes 172.Constitute aforementioned first conductive plunger 191a~191c and the second conductive plunger
194 material can be metal, such as, but not limited to, it is tungsten, copper, nickel or aluminium.
Figure 1A to Fig. 1 C, source conductive layer 200S and grid conducting layer 200G is please referred to be covered on interlayer dielectric layer 190,
Wherein source conductive layer 200S is electrically connected by being arranged in first conductive plunger 192a~192c of interlayer dielectric layer 190
In terminal electrode 184, source area 150 and cover electrode (maskingelectrode) 182, and grid conducting layer 200G is then by being arranged in interlayer dielectric layer
190 multiple second conductive plungers 194 are electrically connected to gate electrode 172.
That is, source conductive layer 200S and grid conducting layer 200G can be respectively as bigrid groove-type power crystal
The source electrode connection pad and grid connection pad of pipe 1, and be electrically connected to an outside and control route.Source conductive layer 200S is led with grid
The material of electric layer 200G can be titanium (Ti), titanium nitride (TiN), tungsten (W), alusil alloy (Al-Si) or Al-Si-Cu alloy (Al-Si-
Cu) etc., but the present invention is not restricted to this.
Then, the embodiment of the present invention and the manufacturing process of bigrid groove-type power transistor is provided.Referring to figure 2., it shows
Show the fabrication process flow figure of the bigrid groove-type power transistor of one embodiment of the invention.In addition, A extremely schemes referring to figure 3.
3H is painted the part section signal of each step in the manufacturing process of the bigrid groove-type power transistor of one embodiment of the invention
Figure.
Please also refer to Fig. 2, in step s 200, a substrate is provided.Then, in step s 201, formed on substrate of heap of stone
Crystal layer (epitaxial layer), wherein epitaxial layer defines an element area.It please cooperate referring to Fig. 3 A.Substrate is painted in Fig. 3 A
100, and in having formed an epitaxial layer (epitaxial layer) 120 on substrate 100, wherein substrate 100 is, for example, silicon substrate
(silicon substrate), the first heavily doped region with high-dopant concentration is using the leakage as groove-type power transistor
Pole (drain), epitaxial layer 120 are then low doping concentration.
It in the present embodiment, further include forming a buffer layer 110 before the step of forming epitaxial layer 120 on substrate 100
In on substrate 100.As shown in Figure 3A, buffer layer 110 is between substrate 100 and epitaxial layer 120.In addition, buffer layer 110 is simultaneously
With conductivity type identical with epitaxial layer 120 with substrate 100, but the doping concentration of buffer layer 110 is the doping between substrate 100
Between concentration and the doping concentration of epitaxial layer 120.In addition, in the present embodiment, epitaxial layer 120 is defined out an element area AR
An and terminal area TR.
Referring again to Fig. 2, then, in step S202, multiple shallow trench, and these shallow trench are formed in the epitaxial layer
In element area.It please cooperate referring to Fig. 3 B.Multiple shallow trench 160a ', and shallow trench 160a ' are formed in epitaxial layer 120
About 0.8 μm to 1.3 μm of depth between.
In one embodiment, behind the position that multiple shallow trench 160a ' are defined first with light shield (not shown), then with dry corrosion
It carves or the mode of wet etching produces multiple shallow trench 160a ' in epitaxial layer 120.
Then, referring again to Fig. 2, in step S203, insulating layer and gate electrode are formed in each shallow trench,
Middle insulating layer covers the inner sidewall of shallow trench conformally, and including one first dielectric layer, one second dielectric layer and a third dielectric
Layer, wherein second dielectric layer is located between the first dielectric layer and third dielectric layer.
It please cooperate referring to Fig. 3 C.It specifically, is in inner wall (including the two side walls face of each shallow trench 160a '
And bottom surface) sequentially form the first dielectric layer 171a ', the second dielectric layer 171b and third dielectric layer 171c.First dielectric layer
The material of 171a ' can be oxide skin(coating) or nitride layer.For example, the first dielectric layer 171a ' is silicon oxide layer (SiOx), and
It is formed using thermal oxidation process.In other embodiments, physical vapour deposition (PVD) or chemical vapor deposition processes also be can use
To form the first dielectric layer 171a '.
In one embodiment, the dielectric constant of the second dielectric layer 171b is above the dielectric constant of the first dielectric layer 171a ',
And to be used as a side to hard cover power in subsequent manufacturing processes.For example, when the first dielectric layer 171a ' is silica
When, the second dielectric layer 171b can be nitride, such as silicon nitride, and suitable with physical vapour deposition (PVD) or chemical vapor deposition manner
It is covered in shape on the first dielectric layer 171a '.
Third dielectric layer 171c can any selective oxidation object or nitride it is one of, e.g. silica (SiO4),
It is not particularly limited.And it is possible to select deposition third dielectric layer according to selected material and actual demand
The process of 171c, e.g. physical vapour deposition (PVD) or chemical vapor deposition processes.
In one embodiment, thickness of the thickness of the first dielectric layer 171a ' between 10nm to 35nm, the second dielectric layer 171b
Between 20nm to 30nm, and the thickness of third dielectric layer 171c is between 7nm to 10nm.
After the deposition for completing first to third dielectric layer 171a ', 171b, 171c, insulating layer 171 ' is shallow at each
Groove (not labeled) is defined in groove 160a '.Then the first polysilicon structure, then is blanket-like formed in third dielectric layer
On 171c, and insert in groove (not labeled) defined in insulating layer 171 '.First polysilicon structure can be miscellaneous containing electric conductivity
The polysilicon structure (doped poly-Si) of matter.Then, first covered on eatch-back (etch back) removal epitaxial layer 120
Polysilicon structure and small part are located at the first polysilicon structure in shallow trench 160a ', and are formed in shallow trench 160a '
Gate electrode 172.
Then, referring to figure 2..In step S204, an etching step is executed, to form multiple zanjons in epitaxial layer
Slot, wherein each deep trench is in close proximity at least one of these shallow trench, and the second dielectric layer as a side to hard cover
Power.The manufacturing process of bigrid groove-type power transistor provided by the present embodiment can further include, when forming deep trench, one
And terminal trenches are formed in epitaxial layer.
Detailed step D to Fig. 3 E referring to figure 3..As shown in Figure 3D, a photoresist layer 300 is first formed on epitaxial layer 120,
The middle covering of photoresist layer 300 is located at the shallow trench 160a ' in element area AR.In addition, photoresist layer 300 has multiple opening 300a,
To define the predetermined position for forming deep trench 160b ' in element area AR respectively, and define in the TR of terminal area
The predetermined position for forming terminal trenches 160c.
Then, please continue to refer to Fig. 3 E, deep trench is formed in epitaxial layer 120 in a manner of dry ecthing or wet etching
160b ' and terminal trenches 160c.As shown in FIGURE 3 E, deep trench 160b ' is formed in element area AR, and terminal trenches
160c is formed in the TR of terminal area.
It should be particularly noted that, the depth of deep trench 160b ' and terminal trenches 160c are between 3 μm to 5 μm.Due to depth
Groove 160b ' and terminal trenches 160c can be at least one shallow trench 160a ' close to therefore, being etched to epitaxial layer 120
When forming deep trench 160b ', partial insulative layer 171 ' established in shallow trench 160a ' can also be removed.Specifically, portion
Quartile is in the shallow trench 160a ', and the first dielectric layer 171a of closer deep trench 160b ' is because of thinner thickness, and is possible to
It is completely removed in etching step.
However, the second dielectric layer 171b in insulating layer 171 ' can be used as lateral hard cover power in an etching step, with
During forming deep trench 160b ', gate electrode 172 and third dielectric layer 171c is protected not to be etched, and can ensure that depth
Groove 160b ' can be located between two shallow trench 160a ', to keep groove structure more symmetrical.
Accordingly, the first side S1 (side of the closer deep trench 160b ' of finger grid electrode 172) of gate electrode 172 is contacted
Gate insulating layer 171 thickness t1, can be less than contact gate electrode 172 second side S2 (finger grid electrode 172 is further away from depth
The side of groove 160b ') gate insulating layer 171 thickness.
Then, referring again to Fig. 2, in step S205, masking dielectric layer and masking electricity are formed in each deep trench
Pole wherein masking dielectric layer covers the inner wall of each deep trench conformally, and keeps cover electrode (maskingelectrode) mutually isolated with epitaxial layer, and
Masking dielectric layer contacts second dielectric layer.
In embodiments of the present invention, in forming the step of covering dielectric layer, terminal can be formed in terminal trenches together
Dielectric layer, and in the step of forming cover electrode (maskingelectrode), terminal electrode can be formed in terminal trenches together.
Specifically, please cooperate referring to Fig. 3 F.In one embodiment, cover electrode (maskingelectrode) structure 180 and terminal electrode knot are formed
The step-by-step procedures of structure 185 is as follows.Firstly, passing through thermal oxidation process, chemical vapor deposition processes or physical vapour deposition (PVD) mistake
Insulating materials is formed on the inner wall of deep trench 160b ' and terminal trenches 160c by journey, with respectively deep trench 160b ' with
Terminal trenches 160c forms masking dielectric layer 181 and terminal dielectric layer 183.
It should be noted that being partially located at due in previous etching step in shallow trench 160a ' and close to deep trench
First dielectric layer 171a of the side of 160b ' has been removed, therefore masking dielectric layer 181 can directly contact the second dielectric layer
171b。
Then, then on the surface of epitaxial layer 120 one second polysilicon structure is formed, and inserts deep trench 160b ' and end
It holds in groove 160c.Then, eatch-back removal be located at 120 surface of epitaxial layer the second polysilicon structure, leave deep trench 160b ' with
The second polysilicon structure in terminal trenches 160c, to form cover electrode (maskingelectrode) 182 and terminal electrode in deep trench 160b ' respectively
184.The mode for forming the second polysilicon structure can be identical with the mode of the first polysilicon structure is formed, and details are not described herein.
Referring again to Fig. 2.Carry out step S206 and step S207.In step S206, a matrix is carried out to epitaxial layer and is mixed
Miscellaneous process, to form a matrix area.In step S207, a source dopant process is carried out to form source region, wherein source electrode
Area is located above matrix area.
G referring to figure 3., to epitaxial layer 120 carry out a body dopant process after, epitaxial layer 120 far from substrate 100 one
Side forms the first doped region.After forming the first doped region, a source dopant process is carried out to form source to the first doped region
Polar region 150 and matrix area 140.It is noted that source dopant process may include to the first doped region carry out ion implant it
Afterwards, then a thermal diffusion process is carried out, to form source area 150.In addition, can be seen that by Fig. 3 G, the matrix area 140 in the present embodiment
Lowest edge be higher than gate electrode 172 bottom surface where horizontal position.
The manufacturing process of bigrid groove-type power transistor provided by the embodiment of the present invention can further comprise of heap of stone
Route redistribution layer is formed on crystal layer, so that source area 150, gate electrode 172, cover electrode (maskingelectrode) 182 and terminal electrode 184 can electricity
Property be connected to external control circuit.It will be led below with forming first contact plunger 192a~192c and source electrode shown in Figure 1B
For electric layer 200S, the specific steps of route redistribution layer are described in detail.
H referring to figure 3. forms an interlayer dielectric layer 190 and comprehensively covers 120 surface of epitaxial layer, gate structure 170, hides
Cover electrode structure 180 and terminal electrode structure 185.The material for constituting interlayer dielectric layer 190 can choose boron-phosphorosilicate glass
(BPSG), phosphorosilicate glass (PSG), oxide, nitride or combinations thereof.
Then, it corresponds respectively to the position of terminal electrode 184, source area 150 and cover electrode (maskingelectrode) 182, forms multiple the
One contact hole 191a~191c.In the present embodiment.Formed first contact hole 191a~191c technological means can be used it is known
Coating photoresist, lithographic, etching and etc. realize.
Then, multiple first conductive plunger 192a~192c are formed in corresponding first contact hole 191a~191c.Palpus
Illustrate, first conductive plunger 192a~192c runs through after interlayer dielectric layer 190, extends to terminal electrode 184, epitaxial layer
120 and cover electrode (maskingelectrode) 182 in, terminal electrode 184, source area 150 and cover electrode (maskingelectrode) 182 is electrically connected.
It should be noted that the first contact hole can be first passed through before forming multiple first conductive plunger 192a~192c
191b carries out a doping process to epitaxial layer 120, to form a contact in the epitaxial layer 120 of the lower section of the first contact hole 191b
Doped region 121.In one embodiment, the impurity that contact doping area 121 is adulterated is boron difluoride (BF2)。
In addition, forming first conductive plunger 192a~192c after corresponding first contact hole 191a~191c, it can
It further include forming a source conductive layer 200S to be covered on interlayer dielectric layer 190.Source conductive layer 200S can pass through first respectively
Conductive plunger 192a~192c is electrically connected to terminal electrode 184, source area 150 and cover electrode (maskingelectrode) 182.Source conductive layer
The material of 200S can be titanium (Ti), titanium nitride (TiN), tungsten (W), alusil alloy (Al-Si) or Al-Si-Cu alloy (Al-Si-Cu)
Deng, but the present invention is not restricted to this.
Via the explanation of above-described embodiment, the art tool usually intellectual can should deduce easily other implementations
CONSTRUCTED SPECIFICATION is not added repeats herein.In addition, forming the second contact plunger 194 and grid conducting layer 200G's shown in Fig. 1 C
Step is similar to previous embodiment.Specifically, form multiple first contact hole 191a~191c's in interlayer dielectric layer 190
In step, multiple second contact holes 193 can be formed together.And the step of forming multiple first conductive plunger 192a~192c
In, can corresponding second conductive plunger 194 be formed in each second contact hole 193 together.In addition, forming source conductive
In the step of layer 200S, grid conducting layer 200G can be formed together.
In conclusion bigrid groove-type power transistor and its manufacturing process method provided by the embodiment of the present invention
In, be between gate electrode and cover electrode (maskingelectrode) it is mutually isolated by thicker masking dielectric layer and part of grid pole insulating layer, can phase
To generated capacitor between reduction gate electrode and cover electrode (maskingelectrode).In addition, the manufacturing process provided by the embodiment of the present invention
In, gate electrode less will form the point of stored charge, so as to there is bigrid groove-type power transistor preferably
Electrical performance.
In addition to this, it is being etched step, the second dielectric layer during forming deep trench, in gate insulating layer
It can be used as the lateral hard cover power in etching step, during forming deep trench, to protect gate electrode and third to be situated between
Electric layer is not etched, and can ensure that deep trench can be located between two shallow trench, to form more symmetrical groove structure.
Although the embodiment of the present invention has disclosed as above, the right present invention is not limited to above-described embodiment, any affiliated skill
Art has usually intellectual in field, is not departing from presently disclosed range, when can make a little change and adjustment, because
This protection scope of the present invention should be subject to appended claim institute defender.
Claims (11)
1. a kind of bigrid groove-type power transistor, which is characterized in that the bigrid groove-type power transistor includes:
One substrate；
One epitaxial layer, the epitaxial layer are located on the substrate, wherein the epitaxial layer defines an at least element area, and described
Epitaxial layer has a groove structure being located in the element area, wherein the groove structure includes a deep trench and two
It is adjacent to the shallow channel section of two opposite sides of the deep trench respectively；
Two gate structures, described two gate structures are respectively arranged in two shallow channel sections, wherein each grid
Pole structure includes a gate insulating layer and a gate electrode, wherein the gate insulating layer is covered in corresponding institute conformally
The inner wall of shallow channel section is stated, so that the gate electrode is electrically insulated with the epitaxial layer, and the gate insulating layer includes
One first dielectric layer, one second dielectric layer and a third dielectric layer are situated between wherein second dielectric layer is located in described first
Between electric layer and the third dielectric layer；
One cover electrode (maskingelectrode) structure, the cover electrode (maskingelectrode) structure is located in the deep trench, wherein the cover electrode (maskingelectrode) structure packet
A masking dielectric layer and a cover electrode (maskingelectrode) are included, wherein the masking dielectric layer covers the inner wall of the deep trench conformally,
So that the cover electrode (maskingelectrode) is electrically insulated with the epitaxial layer, and it is located at the part institute of two opposite sides of the cover electrode (maskingelectrode)
It states masking dielectric layer and is contacted with the multiple gate insulating layers being located in two shallow channel sections；
One matrix area forms described matrix area in the epitaxial layer, and around two gate structures；And
Source region forms the source area in the top in described matrix area,
Wherein, the gate electrode is with close to one first side of the cover electrode (maskingelectrode) and with opposite with first side one
Second side, wherein the thickness for contacting the gate insulating layer of first side is less than the thickness for contacting the gate insulating layer of described second side
Degree.
2. bigrid groove-type power transistor according to claim 1, which is characterized in that the epitaxial layer defines one eventually
End regions, and the epitaxial layer includes at least one terminal trenches being located in the terminal area, and the bigrid plough groove type
Power transistor further includes at least one terminal electrode structure being formed in the terminal trenches, wherein the terminal electrode structure
Include:
One terminal electrode, the terminal electrode are located in the terminal trenches；And
One terminal dielectric layer, the terminal dielectric layer cover the inner wall of the terminal trenches conformally, the terminal is isolated
Electrode and the epitaxial layer.
3. bigrid groove-type power transistor according to claim 2, which is characterized in that the terminal electrode is around institute
State element area.
4. bigrid groove-type power transistor according to claim 1, which is characterized in that the part masking dielectric layer
It is directly contacted with second dielectric layer of each gate insulating layer.
5. bigrid groove-type power transistor according to claim 1, which is characterized in that the thickness of first dielectric layer
Degree between 10nm between 35nm, the thickness of second dielectric layer between 20nm between 30nm, the third dielectric layer
Thickness is between 7nm between 10nm.
6. bigrid groove-type power transistor according to claim 1, which is characterized in that constitute second dielectric layer
Material be nitride layer.
7. bigrid groove-type power transistor according to claim 1, which is characterized in that the bigrid plough groove type function
Rate transistor further include:
One interlayer dielectric layer, the interlayer dielectric layer are located on the epitaxial layer, wherein the interlayer dielectric layer has multiple the
One contact hole and multiple second contact holes, wherein the multiple first contact hole exposure source area and the cover electrode (maskingelectrode),
The multiple second contact hole exposes multiple gate electrodes respectively；
Multiple first conductive plungers are respectively formed the multiple first conductive plunger, in the multiple first contact hole with electricity
Property is connected to the source area and the cover electrode (maskingelectrode)；And
Multiple second conductive plungers form the multiple second conductive plunger in second contact hole, electrically to connect respectively
It is connected to multiple gate electrodes.
8. a kind of manufacturing method of bigrid groove-type power transistor, which is characterized in that the bigrid groove-type power is brilliant
The manufacturing method of body pipe includes:
One substrate is provided；
An epitaxial layer is formed on the substrate, wherein the epitaxial layer defines an element area；
Multiple shallow trench are formed in the epitaxial layer, and the multiple shallow trench is located in the element area；
An insulating layer and a gate electrode are formed in each shallow trench, wherein the insulating layer cover conformally it is described shallow
The inner wall of groove, and the insulating layer includes one first dielectric layer, one second dielectric layer and a third dielectric layer, wherein described
Second dielectric layer is located between first dielectric layer and the third dielectric layer；
An etching step is executed, to form multiple deep trench in the epitaxial layer, wherein each deep trench is in close proximity to institute
State at least one shallow trench in multiple shallow trench, and second dielectric layer as a side to hard cover power；
A masking dielectric layer and a cover electrode (maskingelectrode) are formed in each deep trench, wherein the masking dielectric layer covers conformally
The inner wall of the corresponding deep trench is covered, and keeps the cover electrode (maskingelectrode) and the epitaxial layer mutually isolated, and the masking
Dielectric layer contacts second dielectric layer；And
One body dopant process is carried out to the epitaxial layer, to form a matrix area；And
A source dopant process is carried out to form source region, wherein the source area is located at the top in described matrix area.
9. the manufacturing method of bigrid groove-type power transistor according to claim 8, which is characterized in that the epitaxy
Layer defines a terminal area, wherein the terminal area surrounds the element area.
10. the manufacturing method of bigrid groove-type power transistor according to claim 9, which is characterized in that described double
The manufacturing method of gate trench formula power transistor further include:
The terminal trenches being located in the terminal area are formed in the epitaxial layer, wherein the terminal trenches are around described
Element area；And
A terminal dielectric layer and a terminal electrode are formed in the terminal trenches, wherein the terminal dielectric layer covers conformally
The inner wall of the terminal trenches, so that the terminal electrode and the epitaxial layer electrically completely cut off.
11. the manufacturing method of bigrid groove-type power transistor according to claim 10, which is characterized in that described double
The manufacturing method of gate trench formula power transistor further include:
An interlayer dielectric layer is formed on the epitaxial layer；
Multiple first contact holes and multiple second contact holes are formed in the interlayer dielectric layer, wherein the multiple first connects
Touching window exposes the source area, multiple cover electrode (maskingelectrode)s and the terminal electrode, and the multiple second contact hole point respectively
Multiple gate electrodes are not exposed；
Multiple source conductive plugs are respectively formed in the multiple first contact hole, be electrically connected the source area,
Multiple cover electrode (maskingelectrode)s and the terminal electrode；
Multiple Gate Electrode Conductive plugs are respectively formed, in the multiple second contact hole to be electrically connected the gate electrode；With
And
A source conductive layer and a grid conducting layer are formed on the interlayer dielectric layer, wherein the source conductive layer with it is described
Grid conducting layer is electrically insulated, and the source conductive layer is connected to the multiple source conductive plug, and the grid conducting layer
It is connected to the multiple Gate Electrode Conductive plug.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510607082.0A CN106549056B (en) | 2015-09-22 | 2015-09-22 | Bigrid groove-type power transistor and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510607082.0A CN106549056B (en) | 2015-09-22 | 2015-09-22 | Bigrid groove-type power transistor and its manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106549056A CN106549056A (en) | 2017-03-29 |
| CN106549056B true CN106549056B (en) | 2019-07-30 |
Family
ID=58364932
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510607082.0A Expired - Fee Related CN106549056B (en) | 2015-09-22 | 2015-09-22 | Bigrid groove-type power transistor and its manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106549056B (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102104068A (en) * | 2009-12-18 | 2011-06-22 | 上海华虹Nec电子有限公司 | Structure of power MOS (Metal Oxide Semiconductor) transistor and preparation method thereof |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4760081B2 (en) * | 2004-04-21 | 2011-08-31 | 株式会社デンソー | Semiconductor device and manufacturing method thereof |
| JP4817827B2 (en) * | 2005-12-09 | 2011-11-16 | 株式会社東芝 | Semiconductor device |
-
2015
- 2015-09-22 CN CN201510607082.0A patent/CN106549056B/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102104068A (en) * | 2009-12-18 | 2011-06-22 | 上海华虹Nec电子有限公司 | Structure of power MOS (Metal Oxide Semiconductor) transistor and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106549056A (en) | 2017-03-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10121892B2 (en) | Semiconductor device | |
| US9741808B2 (en) | Split-gate trench power MOSFET with protected shield oxide | |
| TWI567979B (en) | Trench power transistor | |
| CN104518010B (en) | The method of integrated circuit and manufacture integrated circuit | |
| US10636883B2 (en) | Semiconductor device including a gate trench and a source trench | |
| KR102614549B1 (en) | Trench field effect transistor structure and manufacturing method | |
| TW200524085A (en) | Closed cell trench metal-oxide-semiconductor field effect transistor | |
| US20160027913A1 (en) | Trench mosfet and manufacturing method thereof | |
| CN109817702A (en) | Semiconductor device with vertical-channel | |
| US10128368B2 (en) | Double gate trench power transistor and manufacturing method thereof | |
| US20100163988A1 (en) | High voltage (>100v) lateral trench power mosfet with low specific-on-resistance | |
| US20090166731A1 (en) | Vertical-type field-effect transistor and manufacturing method thereof | |
| US9299616B1 (en) | Integrated circuits with separate workfunction material layers and methods for fabricating the same | |
| CN111508843B (en) | Semiconductor device and method of forming the same | |
| JP2002026323A (en) | Method of manufacturing trench gate type mis device having thick polysilicon insulating layer at bottom of trench | |
| CN107393871A (en) | Integrated circuit and its manufacture method and semiconductor devices | |
| US10211339B2 (en) | Vertical transistor having a semiconductor pillar penetrating a silicide formed on the substrate surface | |
| TWI588991B (en) | Trench power semiconductor device | |
| CN106601811A (en) | Trench type power transistor | |
| CN106549056B (en) | Bigrid groove-type power transistor and its manufacturing method | |
| KR102350485B1 (en) | Semiconductor device | |
| US11575004B2 (en) | Semiconductor structure and formation method thereof | |
| TWI702724B (en) | Using source/drain contact cap during gate cut | |
| CN104425609B (en) | Semiconductor device | |
| TW201714304A (en) | Semiconductor devices and methods for forming the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20190730 |