CN213660381U - Bidirectional power device - Google Patents

Bidirectional power device Download PDF

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CN213660381U
CN213660381U CN202022417338.0U CN202022417338U CN213660381U CN 213660381 U CN213660381 U CN 213660381U CN 202022417338 U CN202022417338 U CN 202022417338U CN 213660381 U CN213660381 U CN 213660381U
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power device
gate
dielectric layer
trench
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杨彦涛
张邵华
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Hangzhou Silan Microelectronics Co Ltd
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Hangzhou Silan Microelectronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1087—Substrate region of field-effect devices of field-effect transistors with insulated gate characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

The application discloses two-way power device includes: a substrate; an epitaxial layer on the substrate; the first doping area is positioned in the epitaxial layer; a conductive channel extending from the surface of the epitaxial layer toward the substrate and contacting the substrate; the plurality of grooves of the first groove area are positioned in the first doping area and divide the first doping area into a first sub-doping area and a second sub-doping area which are alternated; the gate dielectric layer covers the lower side walls of the plurality of grooves of the first groove area; the control grid is positioned at the lower parts of the plurality of grooves of the first groove area and is in contact with the grid dielectric layer; the shielding dielectric layer covers the upper side walls of the plurality of grooves in the first groove region and is positioned on the surface of the control gate; and the shielding grid is positioned at the upper parts of the plurality of trenches in the first trench region and is in contact with the shielding dielectric layer, wherein the shielding dielectric layer separates the control grid from the shielding grid. The bidirectional power device reduces the body resistance of the device through the conductive channel connected with the substrate, and improves the performance of the bidirectional power device.

Description

Bidirectional power device
Technical Field
The present application relates to the field of semiconductor manufacturing technologies, and more particularly, to a bidirectional power device.
Background
Bidirectional power devices are widely used in charging devices having a secondary charging function. Taking the lithium battery charging and discharging device as an example, when the lithium battery charging and discharging device continuously supplies power to the terminal device to a certain extent, the lithium battery charging and discharging device needs to be prevented from over-discharging so as to prevent the terminal device from stopping running, and the lithium battery needs to be charged in time. In the process of charging the lithium battery, the lithium battery also needs to supply power to the terminal equipment, and meanwhile, the lithium battery is prevented from being overcharged. Therefore, in order to manage and control the charge/discharge state of the lithium battery, a charge/discharge protection circuit having a bidirectional switch for controlling current conduction is generally used.
As shown in fig. 1, in the first charge/discharge protection circuit, two drain-connected single planar gate NMOS transistors M1 and M2 were used as bidirectional switches. When charging is performed, a high voltage is applied to the gate G1 of M1 to turn on M1, and a low voltage is applied to the gate G2 of M2 to turn off M2, and at this time, current flows from the source S2 of M2 to the drain of M2 through the parasitic diode D2 of M2, and then flows from the drain of M1 to the source S1 of M1. When discharging, a low voltage is applied to gate G1 of M1, turning off M1, and a high voltage is applied to gate G2 of M2, turning on M2. At this time, the current flows from the source S1 of M1 to the drain of M1 through the parasitic diode D1 of M1, and then flows from the drain of M2 to the source S2 of M2. However, the MOS process using the planar gate structure requires a sufficient area to meet the requirement of higher withstand voltage, and the device has low on-state efficiency and large power consumption.
Therefore, it is desirable to further optimize the structure of the bidirectional power device, so that the bidirectional power device has smaller area and higher performance.
SUMMERY OF THE UTILITY MODEL
In view of the above problem, an object of the present invention is to provide a bidirectional power device, which uses a plurality of trenches in a first trench region to separate a first doped region into a first sub-doped region and a second sub-doped region, so as to form a source region and a drain region of the bidirectional power device, thereby reducing the area of the device.
According to the utility model provides a two-way power device, include: a substrate; an epitaxial layer on the substrate; the first doping area is positioned in the epitaxial layer; a conductive channel extending from the epitaxial layer surface toward the substrate and in contact with the substrate; the plurality of grooves of the first groove area are positioned in the first doping area and divide the first doping area into a first sub-doping area and a second sub-doping area which are alternated; the gate dielectric layer covers the lower side walls of the plurality of grooves of the first groove area; the control gate is positioned at the lower parts of the plurality of trenches of the first trench region and is in contact with the gate dielectric layer; the shielding dielectric layer covers the upper side walls of the plurality of trenches in the first trench region and is positioned on the surface of the control gate; and the shielding grid is positioned at the upper parts of the plurality of grooves of the first groove region and is in contact with the shielding dielectric layer, wherein the control grid and the shielding grid are separated by the shielding dielectric layer.
Optionally, in a case where one of the first type sub-doping region and the second type sub-doping region serves as a source region, the other of the first type sub-doping region and the second type sub-doping region serves as a drain region, and the source region and the drain region may be interchanged.
Optionally, the conductive channel includes a doped region located in the epitaxial layer, and the doping type of the doped region is the same as that of the epitaxial layer.
Optionally, the conductive via comprises a polysilicon conductive via.
Optionally, the device further includes a trench of a second trench region, the trench is located in the epitaxial layer and is separated from the first doped region, the gate dielectric layer further covers a sidewall of the trench of the second trench region, the control gate is further located in the trench of the second trench region, the trench of the first trench region is communicated with the trench of the second trench region, and the control gate located in the trench of the first trench region is connected to the control gate located in the trench of the second trench region.
Optionally, the method further comprises: the first contact region is positioned in the first-type sub-doping region; the second contact region is positioned in the second type sub-doping region; and a third contact region in the epitaxial layer.
Optionally, a channel region is further included in the epitaxial layer and adjacent to the control gate.
Optionally, the method further comprises: the covering dielectric layer is positioned on the surface of the epitaxial layer; and the substrate electrode, the first contact electrode, the second contact electrode, the first gate electrode and the second gate electrode penetrate through the covering dielectric layer, the substrate electrode is connected with the third contact area, the first contact electrode is connected with the first contact area, the second contact electrode is connected with the second contact area, the first gate electrode is connected with the control grid, and the second gate electrode is connected with the shielding grid.
Optionally, the first gate electrode is connected to the second gate electrode to receive the same control voltage.
Optionally, the first gate electrode is electrically isolated from the second gate electrode to receive different control voltages.
Optionally, the thickness of the shielding dielectric layer is greater than the thickness of the gate dielectric layer.
Optionally, the thickness of the shielding dielectric layer on the surface of the control gate is greater than the thickness of the shielding dielectric layer covering the sidewalls of the upper portions of the trenches of the first trench region.
Optionally, the thickness range of the gate dielectric layer includes
Figure BDA0002745151780000031
Optionally, the thickness range of the shielding dielectric layer on the control gate surface includes:
Figure BDA0002745151780000032
optionally, the thickness range of the shielding dielectric layer covering the upper sidewalls of the plurality of trenches of the first trench region includes
Figure BDA0002745151780000033
Optionally, the depth of the plurality of trenches in the first trench region and the second trench region ranges from 0.1 μm to 50 μm.
Optionally, the distance from the surface of the control gate located in the first trench region to the surface of the epitaxial layer includes 0.1-49 μm.
Optionally, when the bidirectional power device is turned off, the shield gate depletes charges in the first sub-doped region and the second sub-doped region through the shield dielectric layer, so as to improve a withstand voltage characteristic of the bidirectional power device.
According to the utility model provides a two-way power device forms first doped region in the epitaxial layer to make first doped region be separated for first class of alternative sub-doped region and second class sub-doped region by the slot, and form first contact zone and second contact zone in first class of sub-doped region and second class sub-doped region respectively, thereby two doped regions of two-way power device have been constituted, these two doped regions are each other source region and drain region, the area of device has been reduced. Furthermore, the body resistance of the device is reduced through the conductive channel connected with the substrate, and the performance of the bidirectional power device is improved.
More specifically, the first doped region is typically deeper, and higher diffusion temperatures and longer diffusion times are required to achieve deeper junction depths. Therefore, the first doping region is formed in the first step of the manufacturing method according to the requirements of product parameters, and the requirements of product structures and parameters can be realized by selecting proper doping conditions. Under the condition that the junction depth requirement of the first doped region is shallow, the first doped region can be formed without the first step of the manufacturing method, and the first doped region can also be annealed in the annealing process of other doped regions in the subsequent manufacturing method, so that the requirements of the junction depth and parameters required by the device structure are met.
Furthermore, by forming the control gates and the shielding gates in the plurality of grooves, when the bidirectional power device is cut off, the shielding gates deplete charges in the source region and the drain region through the shielding dielectric layer, and the voltage resistance of the device is improved; in the case of conduction of the bidirectional power device, the source region and/or the drain region and the channel region provide a low-impedance conduction path.
Furthermore, the control gate and the shielding gate in the device structure are separated from each other, the control gate in the first groove region and the control gate in the second groove region are connected and are led out through the electrodes, the shielding gate in the first groove region is led out through the electrodes, the connection between the shielding gate and the control gate can be realized through the leading-out electrodes (a structure similar to single polycrystal is formed), the shielding gate and the control gate can be isolated through the leading-out electrodes for separating the shielding gate from the control gate (namely, the upper section of polycrystal is independently connected), the electric field of the upper section is controlled, the independent control of the shielding gate is realized, and the shielding effect can be flexibly adjusted according to needs.
Further, when the bidirectional power device is conducted, the substrate electrode connected with the substrate is in short circuit with one of the first contact electrode and the second contact electrode, and bidirectional selection of the current direction is achieved. Under the condition that the substrate electrode is in short circuit with the first contact electrode, current flows to the first contact electrode from the second contact electrode through the second type sub-doping area, the channel area and the first type sub-doping area in sequence; under the condition that the substrate electrode is in short circuit with the second contact electrode, current flows to the second contact electrode from the first contact electrode through the first type sub-doping area, the channel area and the second type sub-doping area in sequence.
Further, the channel length, and thus the channel resistance, may be reduced by reducing the width of the trench.
Furthermore, the device adopts a longitudinal control grid field structure, makes full use of a charge balance mechanism, and effectively improves the conduction efficiency and reduces the chip size by making the drift region resistance small under the condition of meeting the withstand voltage requirement.
Further, in the case that the control gate and the shield gate are located in the same trench, for example, in the first trench region, since the vertical depth of the entire trench is implemented at one time, the vertical distance from the central line of the control gate extending in the substrate thickness direction to the inner boundaries of the shield dielectric layers located on the two side walls of the trench is the same, and the vertical distance from the central line of the control gate extending in the substrate thickness direction to the outer boundaries of the shield dielectric layers located on the two side walls of the trench is the same, that is, the control gate is located right below the shield gate.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description only relate to some embodiments of the present application and are not limiting on the present application.
Fig. 1 shows a circuit schematic of a prior art bi-directional power device.
Fig. 2 shows a schematic circuit diagram of a bidirectional power device according to an embodiment of the present invention.
Fig. 3a to 3l show a block diagram of a method of manufacturing a bidirectional power device according to an embodiment of the present invention at some stages.
Detailed Description
The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, certain well known components may not be shown. For simplicity, the semiconductor structure obtained after several steps can be described in one figure.
It will be understood that when a layer or region is referred to as being "on" or "over" another layer or region in describing the structure of the device, it can be directly on the other layer or region or intervening layers or regions may also be present. And, if the device is turned over, that layer, region, or regions would be "under" or "beneath" another layer, region, or regions.
If for the purpose of describing the situation directly on another layer, another area, the expressions "directly on … …" or "on … … and adjacent thereto" will be used herein.
Numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of the devices are described below in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.
The present invention may be presented in a variety of forms, some of which are described below.
Fig. 2 shows a schematic circuit diagram of a bidirectional power device according to an embodiment of the present invention.
The utility model discloses two-way power device is formed by a transistor, has two-way conduction function. As shown in fig. 2, the bidirectional power device includes: a substrate Sub, two output poles S1 and S2 located on the substrate Sub, and two parasitic body diodes D1 and D2. When the output electrode S2 and the substrate Sub are in short circuit, a high voltage is applied to the grid G, the voltage is higher than the threshold voltage of the bidirectional power device, the bidirectional power device is conducted, and current flows from the output electrode S1 to the output electrode S2; when the output electrode S1 and the substrate Sub are in short circuit, a high voltage is applied to the grid G, the voltage is higher than the threshold voltage of the bidirectional power device, the bidirectional power device is conducted, and current flows from the output electrode S2 to the output electrode S1; when the substrate Sub is connected to zero voltage, a low voltage is applied to the gate G, and the voltage is lower than the threshold voltage, so that the bidirectional power device is turned off. In the embodiment of the present invention, the bidirectional power device is a trench type device, and may be a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), an IGBT device, or a diode. However, the present invention is not limited thereto.
Fig. 3a to 3l show a block diagram of the method of the present invention for manufacturing a bidirectional power device at some stages. It should be noted that the structure of each step of the structure diagram disclosed in this embodiment is not necessarily in a cross section, and may be placed in different regions and directions of a product through a specific design according to the requirements of a product layout, where the illustration diagram only includes 4 trenches, a source region and a drain region, and in an actual product, the number of the trenches, the source region and the drain region may be changed, and when one of the first-type sub-doped region and the second-type sub-doped region is used as a source region, the other is used as a drain region, that is, through different working and application occasions, the source region and the drain region of the structure may be interchanged. In the embodiment of the present invention, in order to facilitate understanding of the forming process of the device structure in each step in the embodiment process, the main structure of the device is shown in a cross section in the embodiment of the present disclosure, but it is not intended to limit the claims, and any person skilled in the art may make possible changes and modifications without departing from the spirit and scope of the embodiment, so the scope of the embodiment should be determined by the scope defined by the claims of the present invention.
In the present embodiment, the manufacturing process starts with a semiconductor layer having a specific doping type, as shown in fig. 3a, the semiconductor layer includes a substrate 101 and an epitaxial layer 110 located on the substrate 101, wherein the substrate 101 includes a silicon substrate, a silicon germanium substrate, a group iii-v compound substrate or other semiconductor material substrates known to those skilled in the art, and a silicon substrate is used in the present embodiment. More specifically, the silicon substrate employed in the present embodiment may be formed with semiconductor devices such as MOS field effect transistors, IGBT insulated gate field effect transistors, schottky, and the like.
The semiconductor layer having a specific doping type refers to an N-type or P-type substrate 101 doped with a certain amount of impurities according to product characteristics and an N-type or P-type epitaxial layer 110 having a certain resistivity and thickness. For example, in the case that the bidirectional power device is an NMOS transistor, the doping types of the substrate 101 and the epitaxial layer 110 are P-type; in the case where the bidirectional power device is a PMOS, the doping types of the substrate 101 and the epitaxial layer 110 are N-type.
Further, a first doped region 120 is formed in the epitaxial layer 110, as shown in fig. 3 a.
In this step, the first doped region 120 is formed by one or more of implantation doping, diffusion source doping and coating doping, wherein the implantation energy is 20 to 800KeV and the implantation dose is 1E11 to 1E16cm2The annealing temperature is 600-1200 ℃.
In this embodiment, the bidirectional power device has a first trench region 103 and a second trench region 104, the first doped region 120 is located in the first trench region 103, and the doping type is opposite to that of the epitaxial layer 110, for example, in the case that the bidirectional power device is a PMOS transistor, the doping type of the first doped region 120 is P-type, and the doping impurities generally adopt B +; in the case where the bidirectional power device is an NMOS, the doping type of the first doped region 120 is an N type, and the doping impurity is usually As + or P +. The first trench region 103 is separated from the second trench region 104, and the second trench region 104 is located in the epitaxial layer 110.
Further, conductive vias 170 are formed in the epitaxial layer 110, the conductive vias 170 being in contact with the substrate, as shown in fig. 3 a.
In this embodiment, the conductive vias 170 may be implemented in two ways.
The first embodiment of the conductive via 170 forms a doped region in the epitaxial layer 110 by one or more of implantation doping, diffusion source doping, and coating doping, and anneals the doped region to contact the doped region with the substrate 101, wherein the implantation energy is 50 to 10000Kev, and the implantation dose is 1E11 to 1E16cm2The annealing temperature is 600-1200 ℃. In a subsequent step, the formed third contact region 153 is contacted with the conductive via 170.
Conductive via 170 in the first embodiment, the doping type of the doped region (conductive via 170) is the same as that of the epitaxial layer 110. For example, in the case that the bidirectional power device is an NMOS transistor, the doping type of the doped region is P-type, and the doping impurities generally adopt B +; in the case where the bidirectional power device is a PMOS transistor, the doping type of the doped region is N type, and the doping impurity is usually As + or P +.
In the first embodiment of the conductive via 170, the doped region is usually implanted with high energy, so as to reduce the process difficulty of the annealing process and reduce the area occupied by the impurity laterally diffused on the chip during the annealing process of the doped region. The doped regions extend through the epitaxial layer 110 to the substrate 101 such that the third contact regions 153 of the final device structure are connected to the substrate electrode 163 and the conductive vias 170, respectively.
A second embodiment of the conductive via 170 is formed by filling a conductive material by etching from the surface of the epitaxial layer 110 and extending towards the substrate 101, for example, using a notching process.
In the second embodiment of the conductive via 170, the in-situ doped polysilicon may be directly filled, and in some other embodiments, the polysilicon without impurity may be filled first, and then the impurity may be implanted.
Further, a plurality of trenches 111a to 111d are formed as shown in fig. 3 b.
In this step, for example, a barrier layer 10 is formed on the surface of the epitaxial layer 110 by using thermal oxidation or deposition, the barrier layer 10 is selectively removed by photolithography and etching processes to form an opening 11, and then the semiconductor layer is etched through the opening 11 to form a trench, and the region reserved in the barrier layer 10 is not formed with a trench.
Fig. 3b is a cross-sectional view showing a total of 4 grooves, including the groove 111a, the groove 111b, the groove 111c, and the groove 111 d. The trenches 111a, 111c, and 111d are located in the first trench region 103, the bottoms of the trenches 111a, 111c, and 111d are located in the epitaxial layer 110, and the trench 111b is located in the second trench region 104. Specifically, the trench 111a is located in the first doping region 120, and the trench 111d and the trench 111c are located at the boundary of the first doping region 120, and the three trenches divide the first doping region 120 into a first sub-doping region 121 and a second sub-doping region 122. The trench 111b is located in the epitaxial layer 110 and is separated from the first doped region 120. The trench 111c and the trench 111d are respectively located at two sides of the first doped region 120 and are in contact with the first doped region 120, for example, the trench 111c is in contact with the second-type sub-doped region 122, and the trench 111d is in contact with the first-type sub-doped region 121. The groove 111c is located between the grooves 111a and 111 b. On a plane perpendicular to the thickness direction of the substrate 101, the trench 111a, the trench 111d, the trench 111c in the first trench region 103 and the trench 111b in the second trench region are communicated, for example, in an "S" shape in turn, however, the present invention is not limited thereto, and one skilled in the art can separate at least two trenches as required.
In the present embodiment, the widths of the plurality of trenches 111a to 111d are determined according to the product structure and the process capability, and the depths h1 of the plurality of trenches 111a to 111d are determined according to the withstand voltage of the product and the like. Specifically, the width of the plurality of grooves 111a to 111d ranges from 0.05 to 5 μm, and the depth h1 ranges from 0.1 to 50 μm. However, the embodiments of the present invention are not limited thereto, and those skilled in the art may match the depth h1 and the width of the trenches 111a to 111d according to the requirements of the product, such as epitaxy, voltage resistance, doping, gate oxide thickness, etc. Those skilled in the art can make other arrangements to the number of trenches in the first trench region 103 as required, so that the plurality of trenches separate the first doped region 120 into the alternating first-type sub-doped regions 121 and second-type sub-doped regions 122.
Further, a channel region 130 is formed in the epitaxial layer 110 through the bottom of the plurality of trenches 111a to 111d, as shown in fig. 3 c.
In this step, for example, the bottom of the plurality of trenches 111a to 111d is first doped through the opening 11 of the barrier layer 10 to form the channel region 130 in the epitaxial layer 110, and then the barrier layer 10 is removed. For example, a zero angle implantation process is used to form a channel region 130 at the bottom of the trenches 111a to 111d for adjusting the threshold voltage of the device, wherein the implantation energy is 20 to 800KeV and the implantation dose is 1E11 to 1E16cm2The annealing temperature is 600-1200 ℃.
In the present embodiment, the channel region 130 is in contact with the first-type sub-doping region 121 and the second-type sub-doping region 122, respectively, and the doping types of the channel region 130 and the first-type sub-doping region 121 and the second-type sub-doping region 122 are the same. For example, in the case that the bidirectional power device is a PMOS transistor, the doping type of the channel region 130 is P-type, and the doping impurities generally adopt B +; in the case where the bidirectional power device is an NMOS, the doping type of the channel region 130 is an N type, and the doping impurity is usually As + or P +.
Further, a first dielectric layer 141a is formed on the inner surfaces of the trenches 111a to 111d, the surface of the epitaxial layer 110, the surface of the first type sub-doping region 121 and the surface of the second type sub-doping region 122, as shown in fig. 3 d.
In this step, the first dielectric layer 141a is formed, for example, by using one or a combination of various processes such as an oxide growth process, a chemical vapor deposition process, LPCVD, SACVD, HTO, and SRO. In some preferred embodiments, the first dielectric layer 141a is formed by an oxidation growth process, and in the subsequent steps, the first dielectric layerLayer 141a will form gate dielectric layer 141. The thickness T1 of the first dielectric layer 141a should be considered in combination with the threshold voltage required by the product, the depth of the trench in the device structure, the doping concentration of the first doped region 120 and the junction depth, and the range of T1 includes
Figure BDA0002745151780000091
Further, a first conductive layer 142a is formed on the first dielectric layer 141a on the surface of the epitaxial layer 110 and in the plurality of trenches 111a to 111d, as shown in fig. 3 e.
In this step, the first conductive layer 142a is formed, for example, using a deposition process such that the first conductive layer 142a fills the plurality of trenches 111a to 111d, and the first conductive layer 142a and the first dielectric layer 141a are in contact with each other. The material of the first conductive layer 142a includes in-situ doped polysilicon. In some other embodiments, polysilicon that is not doped with impurities may be deposited first, followed by implantation of doped impurities. In the subsequent steps, the first conductive layer 142a will form the control gate 142.
In this embodiment, in the case that the bidirectional power device is a PMOS transistor, the doping type of the first conductive layer 142a is P-type; in the case that the bidirectional power device is an NMOS, the doping type of the first conductive layer 142a is an N type.
Further, the first conductive layer 142a on the surface of the first dielectric layer 141a is removed, and the first conductive layer 142a in the trench of the first trench region 103 is selectively removed, and the remaining first conductive layer 142a forms the control gate 142, as shown in fig. 3 f.
In this step, for example, a combination of one or more of dry etching, wet etching and CMP processes is firstly used to remove the first conductive layer 142a outside the trenches 111a to 111d, so that the first dielectric layer 141a on the surface of the epitaxial layer 110 is exposed, and the first conductive layer 142a in the trenches 111a to 111d is flush with the first dielectric layer 141a on the surface of the epitaxial layer 110. Then, by photolithography and etching processes, the first conductive layer 142a in the trenches 111a, 111c, and 111d of the first trench region 103 is selectively removed, so that the depth of the first conductive layer 142a in the trenches 111a, 111c, and 111d of the first trench region 103 from the surface of the epitaxial layer 110 is h 2. The remaining first conductive layer 142a forms the control gate 142 such that the control gate 142 is located in the lower portions of the trenches 111a, 111c, and 111d of the first trench region 103 and the trench 111b of the second trench region 104, respectively. Wherein the control gate in the trench of the first trench region 103 is connected to the control gate in the trench of the second trench region 104.
In the present embodiment, the depth h2 of the control gate 142 in the trench 111a, the trenches 111c and 111d of the first trench region 103 from the surface of the epitaxial layer 110 needs to be matched in combination with the epitaxy, the withstand voltage, the doping, the gate oxide thickness, etc. of the product, and the depth h2 ranges from 0.1 μm to 49 μm. In this embodiment, the first dielectric layer 141a is remained after the formation of the control gate 142, so that the whole process is simple.
In some other embodiments, after forming the control gate 142, a wet process or the like may be further employed to remove the first dielectric layer 141a on the sidewalls of the trenches 111a, 111c and 111d of the first trench region 103 and the surface of the epitaxial layer 110.
Further, a second dielectric layer 143a is formed on the sidewalls of the trenches 111a, 111c and 111d in the first trench region 103, the surface of the control gate 142, and the first dielectric layer 141a on the surface of the epitaxial layer 110, as shown in fig. 3 g.
In this step, for example, an oxide growth process, a chemical vapor deposition process: one or more of LPCVD, SACVD, HTO, and SRO processes may be combined to form second dielectric layer 143 a. In some preferred embodiments, the second dielectric layer 143a is formed using an oxide growth process. The thickness of the second dielectric layer 143a grown on the surface of the control gate 142 is T2, and the thickness of the second dielectric layer 143a grown on the sidewalls of the upper portions of the trenches 111a, 111c, and 111d is T3. Under the same oxidation growth conditions, T2 is common>T3. Wherein the range of T2 includes
Figure BDA0002745151780000111
The range of T3 should be considered in combination with the voltage required for the product, the depth of the trench in the device structure, the doping concentration of the first doped region, and the junction depth, and the range of T3 includes
Figure BDA0002745151780000112
And T3>T1。
In the present embodiment, an oxidation growth process is used to form the second dielectric layer 143a, in which a portion of the exposed control gate 142 is oxidized to form a portion of the second dielectric layer 143a, and in the subsequent steps, the second dielectric layer 143a on the surface of the control gate 142 and on the sidewalls of the upper portions of the trenches 111a, 111c, and 111d forms the shielding dielectric layer 143.
Further, a second conductive layer 144a covering the second dielectric layer 143a and filling the trench 111a, the trench 111c and the trench 111d of the first trench region 103 is formed, as shown in fig. 3 h.
In this step, the second conductive layer 144a is formed, for example, using a deposition process. The material of the second conductive layer 144a includes in-situ doped polysilicon, and in some other embodiments, the polysilicon without doping impurities may be deposited first, and then the doping impurities may be implanted. In a subsequent step, the second conductive layer 144a will form the shield gate 144.
In this embodiment, the doping type of the second conductive layer 144a is P-type in the case that the bidirectional power device is a PMOS transistor; in the case that the bidirectional power device is an NMOS, the doping type of the second conductive layer 144a is an N type.
Further, the second conductive layer 144a, the second dielectric layer 143a and the first dielectric layer 141a on the surface of the epitaxial layer 110 are removed, so as to form the shielding gate 144, the shielding dielectric layer 143 and the gate dielectric layer 141, as shown in fig. 3 i.
In this step, for example, one or a combination of a dry etching process, a wet etching process and a CMP process is used to remove the second conductive layer 144a, the second dielectric layer 143a and the first dielectric layer 141a outside the trenches 111a to 111d, so that the surfaces of the epitaxial layer 110, the first type sub-doping region 121 and the second type sub-doping region 122 are exposed, the remaining second dielectric layer 143a in the trenches 111a, 111c and 111d of the first trench region 103 is used as the shielding dielectric layer 143, and the remaining second conductive layer 144a is used as the shielding gate 144, where the remaining second dielectric layer 143a is also left at the top of the trench 111 d. The remaining first dielectric layer 141a in the trenches 111a to 111d serves as a gate dielectric layer 141. The gate dielectric layer 141 is located on the inner surface of the lower portion of the trenches 111a, 111c, 111d of the first trench region 103 and the entire inner surface of the trench 111b of the second trench region 104. The shielding dielectric layer 143 is located on sidewalls of upper portions of the trenches 111a, 111c, and 111d of the first trench region 103, and covers a surface of the control gate 142, and the shielding gate 144 is filled on the upper portions of the trenches 111a, 111c, and 111d, wherein the control gate 142 and the shielding gate 144 are separated by the shielding dielectric layer 143.
In some embodiments, the second conductive layer 144a above the epitaxial layer 110 is removed by CMP and dry etching, or by dry etching. The second dielectric layer 143a above the epitaxial layer 110 is removed by a CMP wetting process. The thickness T2 of the shielding dielectric layer 143 on the surface of the control gate 142 and the thickness T3 of the shielding dielectric layer 143 on the upper sidewall of the trench are both greater than the thickness T1 of the gate dielectric layer 141.
In the case where the control gate 142 and the shield gate 144 are located in the same trench, for example, in the first trench region 103, since the vertical depth of the entire trench is implemented at one time, the control gate 142 is located directly below the shield gate 144, and the vertical distance from the central line of the control gate 142 extending along the thickness direction of the substrate 101 to the inner boundary of the shield dielectric layer 143 located on the two side walls of the trench is the same, that is, d1 is d2, and the vertical distance from the central line of the control gate 142 extending along the thickness direction of the substrate 101 to the outer boundary of the shield dielectric layer 143 located on the two side walls of the trench is the same, that is, d3 is d 4.
Further, a first contact region 151 is formed in the first type sub-doping region 121, a second contact region 152 is formed in the second type sub-doping region 122, and a third contact region 153 is formed in the epitaxial layer 110, as shown in fig. 3 j.
In this step, the first-type sub-doping region 121, the second-type sub-doping region 122 and the epitaxial layer 110 are doped by implantation and diffusion, for example, through a photolithography mask. Wherein the implantation energy of the doping process is 20-180 Kev, and the implantation dosage is 1E 11-1E 16cm2。
In the present embodiment, the doping types of the first contact region 151 and the second contact region 152 are the same as the doping type of the first sub-doping region 121, and the doping type of the third contact region 153 is the same as the doping type of the epitaxial layer 110. For example, when the bidirectional power device is a PMOS, the doping types of the first contact region 151 and the second contact region 152 are P-type, and the doping type of the third contact region 153 is N-type; when the bidirectional power device is an NMOS, the doping types of the first contact region 151 and the second contact region 152 are N-type, and the doping type of the third contact region 153 is P-type. The P-type contact region is doped with B +/BF2+ and the N-type contact region is doped with As + and P +.
Further, a capping dielectric layer 102 is formed on the epitaxial layer 110, and a plurality of contact holes 102a extending from the surface of the capping dielectric layer 102 toward the substrate direction 101 are formed, as shown in fig. 3 k.
In this step, the capping dielectric layer 102 is formed by, for example, a chemical vapor deposition process, which may include one or a combination of LPCVD, SACVD, HTO, and SRO. The material of the cover dielectric layer 102 includes one or more of undoped silicon dioxide, boron-doped silicon dioxide, phosphorus-doped silicon dioxide, silicon dioxide doped with both boron and phosphorus, undoped polysilicon, silicon nitride, and silicon oxynitride material. Then, for example, photolithography and etching processes are used to form a plurality of contact holes 102a, the plurality of contact holes 102a respectively extend into the first contact region 151, the second contact region 152, the third contact region 153, the control gate 142 and the shield gate 144 to a depth h3, which includes
Figure BDA0002745151780000131
Further, a substrate electrode 163, a first contact electrode 161, a second contact electrode 162, a first gate electrode 164, and a second gate electrode 165 are formed in the plurality of contact holes, respectively, as shown in fig. 3 l.
In this step, for example, a metal conductive layer is deposited on the capping dielectric layer 102, the metal conductive layer extending from the surface of the capping dielectric layer 102 into the contact hole. Finally, photolithography and etching processes are used to form the first contact electrode 161, the second contact electrode 162, the substrate electrode 163, the first gate electrode 164, and the second gate electrode 165. The first contact electrode 161 and the second contact electrode 162 are a source electrode and a drain electrode, and may be interchanged.
The first contact electrode 161 is connected to the first contact region 151, the second contact electrode 162 is connected to the second contact region 152, the substrate electrode 163 is connected to the third contact region 153, the first gate electrode 164 is connected to the control gate 142, and the second gate electrode 165 is connected to the shield gate 144. The material of the metal conductive layer may be one or a combination of metals including Ti, TiN, TiSi, W, Al, AlSi, AlCu, AlSiCu, Cu, Ni, and the like. Wherein, the metal etching adopts one or more of wet etching and plasma etching to form a substrate electrode 163, a first contact electrode 161, a second contact electrode 162, a first gate electrode 164 and a second gate electrode 165, and voltage or current is applied through the 5 electrodes to realize the performance of the device. The third contact region 153 is connected to the substrate electrode 163 and the conductive via 170, so as to reduce the bulk resistance, enhance the charge collection capability of the semiconductor substrate 101, and improve the parameter performance of the power device.
In the present embodiment, the position of the first gate electrode 164 corresponds to the trench 111b, and the position of the second gate electrode 165 corresponds to the trench 111 c. However, the embodiment of the invention is not limited thereto, and since the plurality of trenches 111a to 111d are connected, so that the control gates 142 in the plurality of trenches 111a to 111d are connected to each other and the shielding gates 144 in the plurality of trenches are connected to each other, the position of the second gate electrode 165 may also correspond to the trench 111a and/or the trench 111 d. The control gate 142 in the first trench region 103 and the control gate 142 in the second trench region 104 are led out through the first gate electrode 164, and the shield gate 144 in the first trench region 103 is led out through the second gate electrode 165.
In some embodiments, the first gate electrode 164 is connected to the second gate electrode 165 to connect the control gate 142 and the shield gate 144, so that the shield gate 144 overlaps the first-type sub-doped region 121 and the second-type sub-doped region 122, and a single poly-like structure is formed. When the voltages of the control gate 142 and the shielding gate 144 rise, the parasitic capacitance is charged, and the bidirectional power device is turned on; when the voltages of the control gate 142 and the shield gate 144 are reduced, the parasitic capacitance discharges and the bi-directional power device turns off. When the bidirectional power device is switched on and off at a high speed, the charging and discharging time of the parasitic capacitor can reduce the switching frequency, and the parasitic capacitor is charged and discharged to generate extra power consumption.
In other embodiments, the first gate electrode 164 can be separated from the second gate electrode 165 to receive different control voltages, i.e., the upper poly is connected separately to control the electric field in the upper half. For example, the second gate electrode 165 is connected to the substrate electrode 163 to connect the shielding gate 144 to the substrate 101, and the voltage of the shielding gate 144 is fixed during the switching process of the device, so that the charging and discharging of parasitic capacitance caused by the voltage variation of the shielding gate 144 can be avoided, the switching frequency of the bidirectional power device can be increased, and the power consumption can be reduced. The bidirectional power device can be used as a high-speed switch in certain application occasions requiring that the bidirectional power device not only has the lowest resistance as possible, but also has small parasitic capacitance.
Further, the embodiment of the utility model discloses two-way power device can also optimize wiring mode and method through increasing the metal level, makes device application in-process resistance fall to minimumly, reduces signal interference in the at utmost.
Further, the embodiment of the utility model provides a two-way power device is disclosed, can combine product in-service use, increase passivation layer, polyimide isotructure to the protection device strengthens the reliability.
Further, the embodiment of the utility model provides a two-way power device can form the required structure of product through back processes such as attenuate, back evaporation, realize the function.
Further, the bidirectional power device with bidirectional conduction function according to the embodiment of the present invention can lead out the first gate electrode 164, the second gate electrode 165, the substrate electrode 163, the first contact electrode 161, and the second contact electrode 162 from the surface of the semiconductor structure, and can meet the packaging requirements of Chip Scale Package (CSP).
Further, the embodiment of the utility model discloses a two-way power device can apply to in products such as power MOSFET, CMOS, BCD, high-power transistor, IGBT and schottky.
According to the utility model provides a two-way power device forms first doped region in the epitaxial layer to make first doped region be separated for first class of alternative sub-doped region and second class sub-doped region by the slot, and form first contact zone and second contact zone in first class of sub-doped region and second class sub-doped region respectively, thereby two doped regions of two-way power device have been constituted, these two doped regions are each other source region and drain region, the area of device has been reduced. Furthermore, the body resistance of the device is reduced through the conductive channel connected with the substrate, and the performance of the bidirectional power device is improved.
More specifically, the first doped region is typically deeper, and higher diffusion temperatures and longer diffusion times are required to achieve deeper junction depths. Therefore, the first doping region is formed in the first step of the manufacturing method according to the requirements of product parameters, and the requirements of product structures and parameters can be realized by selecting proper doping conditions. Under the condition that the junction depth requirement of the first doped region is shallow, the first doped region can be formed without the first step of the manufacturing method, and the first doped region can also be annealed in the annealing process of other doped regions in the subsequent manufacturing method, so that the requirements of the junction depth and parameters required by the device structure are met.
Furthermore, by forming the control gates and the shielding gates in the plurality of grooves, when the bidirectional power device is cut off, the shielding gates deplete charges in the source region and the drain region through the shielding dielectric layer, and the voltage resistance of the device is improved; in the case of conduction of the bidirectional power device, the source region and/or the drain region and the channel region provide a low-impedance conduction path.
Furthermore, the control gate and the shielding gate in the device structure are separated from each other, the control gate in the first groove region and the control gate in the second groove region are connected and are led out through the electrodes, the shielding gate in the first groove region is led out through the electrodes, the connection between the shielding gate and the control gate can be realized through the leading-out electrodes (a structure similar to single polycrystal is formed), the shielding gate and the control gate can be isolated through the leading-out electrodes for separating the shielding gate from the control gate (namely, the upper section of polycrystal is independently connected), the electric field of the upper section is controlled, the independent control of the shielding gate is realized, and the shielding effect can be flexibly adjusted according to needs.
Further, when the bidirectional power device is conducted, the substrate electrode connected with the substrate is in short circuit with one of the first contact electrode and the second contact electrode, and bidirectional selection of the current direction is achieved. Under the condition that the substrate electrode is in short circuit with the first contact electrode, current flows to the first contact electrode from the second contact electrode through the second type sub-doping area, the channel area and the first type sub-doping area in sequence; under the condition that the substrate electrode is in short circuit with the second contact electrode, current flows to the second contact electrode from the first contact electrode through the first type sub-doping area, the channel area and the second type sub-doping area in sequence.
Further, the channel length, and thus the channel resistance, may be reduced by reducing the width of the trench.
Furthermore, the device adopts a longitudinal control grid field structure, makes full use of a charge balance mechanism, and effectively improves the conduction efficiency and reduces the chip size by making the drift region resistance small under the condition of meeting the withstand voltage requirement.
Further, in the case that the control gate and the shield gate are located in the same trench, for example, in the first trench region, since the vertical depth of the entire trench is implemented at one time, the vertical distance from the central line of the control gate extending in the substrate thickness direction to the inner boundaries of the shield dielectric layers located on the two side walls of the trench is the same, and the vertical distance from the central line of the control gate extending in the substrate thickness direction to the outer boundaries of the shield dielectric layers located on the two side walls of the trench is the same, that is, the control gate is located right below the shield gate.
The embodiments of the present invention have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present invention. The scope of the invention is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present invention, and these alternatives and modifications are intended to fall within the scope of the present invention.

Claims (18)

1. A bi-directional power device, comprising:
a substrate;
an epitaxial layer on the substrate;
the first doping area is positioned in the epitaxial layer;
a conductive channel extending from the epitaxial layer surface toward the substrate and in contact with the substrate;
the plurality of grooves of the first groove area are positioned in the first doping area and divide the first doping area into a first sub-doping area and a second sub-doping area which are alternated;
the gate dielectric layer covers the lower side walls of the plurality of grooves of the first groove area;
the control gate is positioned at the lower parts of the plurality of trenches of the first trench region and is in contact with the gate dielectric layer;
the shielding dielectric layer covers the upper side walls of the plurality of trenches in the first trench region and is positioned on the surface of the control gate; and
a shield gate disposed on an upper portion of the plurality of trenches of the first trench region and in contact with the shield dielectric layer,
wherein the shielding dielectric layer separates the control gate from the shielding gate.
2. The bidirectional power device of claim 1, wherein in the case that one of the first type sub-doped region and the second type sub-doped region serves as a source region, the other of the first type sub-doped region and the second type sub-doped region serves as a drain region, and the source region and the drain region are interchangeable.
3. The bi-directional power device of claim 1, wherein the conductive channel comprises a doped region in the epitaxial layer, the doped region having a same doping type as the epitaxial layer.
4. The bi-directional power device of claim 1, wherein the conductive via comprises a polysilicon conductive via.
5. The bi-directional power device of claim 1, further comprising a trench of a second trench region located in the epitaxial layer and separated from the first doped region,
wherein the gate dielectric layer also covers the side wall of the trench of the second trench region,
the control gate is also positioned in the groove of the second groove region, the groove of the first groove region is communicated with the groove of the second groove region, and the control gate positioned in the groove of the first groove region is connected with the control gate positioned in the groove of the second groove region.
6. The bi-directional power device of claim 1, further comprising:
the first contact region is positioned in the first-type sub-doping region;
the second contact region is positioned in the second type sub-doping region; and
a third contact region in the epitaxial layer.
7. The bi-directional power device of any of claims 1-6, further comprising a channel region in the epitaxial layer and adjacent to the control gate.
8. The bi-directional power device of claim 6, further comprising:
the covering dielectric layer is positioned on the surface of the epitaxial layer; and
the substrate electrode penetrates through the covering dielectric layer, the first contact electrode, the second contact electrode, the first gate electrode and the second gate electrode, the substrate electrode is connected with the third contact area, the first contact electrode is connected with the first contact area, the second contact electrode is connected with the second contact area, the first gate electrode is connected with the control grid, and the second gate electrode is connected with the shielding grid.
9. The bi-directional power device of claim 8, wherein the first gate electrode and the second gate electrode are connected to receive a same control voltage.
10. The bi-directional power device of claim 8, wherein the first gate electrode is electrically isolated from the second gate electrode to receive different control voltages.
11. The bi-directional power device of any of claims 1-6, wherein the thickness of the shield dielectric layer is greater than the thickness of the gate dielectric layer.
12. The bi-directional power device of any of claims 1-6, wherein the thickness of said shield dielectric layer at the surface of said control gate is greater than the thickness of said shield dielectric layer covering the upper sidewalls of the plurality of trenches of said first trench region.
13. The bi-directional power device of any of claims 1-6, wherein the gate dielectric layer has a thickness in a range including
Figure FDA0002745151770000021
14. The bi-directional power device of any of claims 1-6, wherein the thickness of the shielding dielectric layer on the control gate surface ranges from:
Figure FDA0002745151770000022
15. the bi-directional power device of any of claims 1-6, wherein the thickness of the shield dielectric layer covering the plurality of trench upper sidewalls of the first trench regionThe range of degrees includes
Figure FDA0002745151770000031
16. The bidirectional power device of claim 5, wherein a depth of the plurality of trenches in the first and second trench regions ranges from 0.1 μm to 50 μm.
17. The bidirectional power device of any of claims 1-6, wherein a distance from a surface of the control gate located in the first trench region to a surface of the epitaxial layer comprises 0.1 μm to 49 μm.
18. The bi-directional power device of any of claims 1-6, wherein the shield gate depletes the charge of the first and second sub-doped regions through the shield dielectric layer when the bi-directional power device is turned off, so as to improve the voltage withstand characteristics of the bi-directional power device.
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