JP2000188398A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device, where overshoot quantity of drain voltage at turn-off is reduced, while suppressing the prolongation of turn-off time. SOLUTION: In a semiconductor device, the resistance of a discharge path at pull out of minority carriers introduced to a drain region 2, excepting a channel region 7, is not changed but the resistance of the discharge path at pull out of the minority carries introduced to the channel region 7 is enlarged. More specifically, fixed potential insulating electrodes 6 sandwiching a source region 3 are formed connected in a gate region 8 or an opposite conductivity- type resistance region of low concentration is installed, so that it is brought into contact with a main surface and the gate region 8 but is not brought into contact with the source region 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bipolar type vertical power device.

[0002]

2. Description of the Related Art Japanese Patent Application Laid-Open No. 6-252408 filed by the present applicant is cited as a background art of the present invention. 7 and 8 are structural views of the semiconductor device cited from the above publication. It should be noted that the numbers and the names of parts in the drawings are appropriately changed and described for explanation. 7 is a perspective view for explaining the basic structure, and FIG. 8 is the same cross-sectional view as the side surface of FIG. 7, showing two units of the basic structure shown in FIG.

In the figures, reference numeral 51 denotes an n + -type substrate region, 52 denotes an n-type drain region, 53 denotes an n + -type source region, 54 denotes a MOS electrode, and 55 denotes an insulating film. MO
The S-type electrode 54 is made of high-concentration p + type polysilicon.
Reference numeral 61 denotes a drain electrode, which is in ohmic contact with the substrate region 51. 63 is a source electrode, and the source region 53
And an ohmic contact with the MOS electrode 54. That is, the MOS type electrode 54 is fixed at the source potential. Therefore, the MOS type electrode 54 and the insulating film 55
Are collectively referred to as “fixed potential insulating electrode” 56. The cross-sectional structure of the fixed potential insulating electrode 56 has a side wall formed in a substantially vertical groove, for example, like a letter “U”. Also,
Drain region 52 sandwiched between fixed potential insulating electrodes 56
Is called a channel region 57.

Further, the source region 5 is in contact with the insulating film 55.
A p-type gate region 58 is present at a position distant from 3. In FIG. 8, reference numeral 68 denotes an electrode in ohmic contact with the gate region 58, which is called a "gate electrode". Note that 60
Is an interlayer insulating film. The “dashed line” in FIG. 8 indicates the presence of the fixed potential insulating electrode 56 in the depth direction of the paper as can be seen from the relationship with FIG.

In this device, for example, the source electrode 63 is grounded (to 0 V), and the drain electrode 61 is used by applying an appropriate positive potential via a load. When the gate electrode 68 is grounded or applied with a negative potential, a depletion layer is formed around the fixed potential insulating electrode 56 due to the built-in potential of the MOS type electrode 54, and the channel region 57 is formed by the depletion region. Since a sufficient potential barrier for conduction electrons is formed, the element is in a cutoff state. When a positive potential is applied to the gate electrode 68, the potential of the p-type gate region 58 rises, holes flow into the interface of the insulating film 55, and an inversion layer is formed. Since the inversion layer shields the line of electric force from the p + type MOS electrode 54 to the channel region 57, the depletion region is reduced or disappears, the channel is opened, and the channel is opened.

Further, when the potential applied to the gate electrode 68 is increased, the pn junction composed of the gate region 58 and the surrounding n-type region is in a forward bias state, and holes are directly injected into the drain region 52 and the channel region 57. You. Since these n-type regions are formed with a low impurity concentration in order to maintain the breakdown voltage or the blocking property of the channel, the conductivity is improved when a large amount of holes are injected, and the electrons emitted from the source region 53 It moves to the substrate region 51 with high conductivity. That is, the n-type region is in a high-level injection state, and the drain current flows with a low resistance.

[0007]

When the element is switched from a conductive state to a cut-off state by applying a ground or a negative potential to the gate electrode 68, an excessive positive potential in the drain region 52 and the channel region 57 is obtained. The holes begin to flow into p-type gate region 58. Eventually, excess holes in the drain region 52 and the channel region 57 disappear, and the potential barrier for electrons is restored in the channel region 57, and the drain current is cut off. At this time,
When holes in the channel region 57 are rapidly extracted and the potential barrier against electrons is suddenly restored, the drain potential of this element rises sharply in order to maintain the drain current that has flowed, and is applied via the load. Is applied to the drain electrode 61. That is, the amount of overshoot of the drain voltage at the time of turn-off increases.

When a turn-off signal is applied to the gate electrode 68 via a resistor in order to reduce the amount of overshoot of the drain voltage at the time of turn-off by an external circuit, the speed at which holes are extracted from the channel region 57 is reduced. This solves the problem, but at the same time, the speed at which holes are extracted from the drain region 52 is also reduced. Therefore, the turn-off time from when the turn-off signal is applied to the gate electrode 68 until the main current is cut off is reduced. Becomes longer. That is, this conventional structure has a limit in reducing the amount of overshoot of the drain voltage at the time of turn-off without extending the turn-off time.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and it is an object of the present invention to provide a semiconductor device in which the amount of overshoot of the drain voltage at the time of turn-off is reduced while suppressing the extension of the turn-off time. It is intended to provide.

[0010]

Means for Solving the Problems In order to achieve the above-mentioned object, the present invention has a structure as described in the claims. That is, according to the first aspect of the present invention, the same conductivity type (here, n type) is in contact with one main surface of one conductivity type (for example, n type) semiconductor substrate which is a drain region.
And a groove arranged in contact with the main surface so as to sandwich the source region. Inside the groove, there is a fixed potential insulating electrode insulated from the drain region by an insulating film and kept at the same potential as the source region, and the fixed potential insulating electrode is adjacent via the insulating film. Conductive material having a work function such as forming a depletion region in the drain region (eg, p-type polysilicon)
Consists of And a channel region that is part of the drain region that is in contact with the source region and that is sandwiched between the fixed potential insulating electrodes. The channel region has a potential barrier formed by the depletion region formed around the fixed potential insulating electrode to prevent the movement of majority carriers. An electric field from the drain region in the cutoff state is generated by the source region. The distance from the bottom of the groove to the source region in the channel region, that is, the channel length is the distance between the side walls of the groove facing the channel region, that is, the channel thickness so as not to affect the vicinity of the region. At least 2 to 3 times or more. Furthermore, minority carriers are introduced at the interface of the insulating film surrounding the fixed potential insulating electrode to form an inversion layer, and an electric field from the fixed potential insulating electrode to the drain region is shielded and formed in the channel region. In order to open a channel by reducing or eliminating a potential barrier, a gate region of an opposite conductivity type (for example, p-type) is provided in contact with the insulating film and the drain region but not with the source region. Furthermore, the structure of increasing the resistance of the discharge path when extracting the minority carriers introduced into the channel region without changing the resistance of the discharge path when extracting the minority carriers introduced into the drain region other than the channel region is not changed. Provided.

Further, in the invention according to claim 2,
2. The semiconductor device according to claim 1, wherein an obstacle to the minority carrier is provided in the gate region, and the minority carrier is detoured in the gate region to increase a path length, thereby being introduced into the channel region. 3. In addition, the resistance of the minority carrier discharge path is increased.

Further, in the invention according to claim 3,
As the obstacle according to claim 2, an obstacle in which the fixed potential insulating electrodes sandwiching the source region are formed in a shape connected to each other in the gate region is used.

Further, in the invention according to claim 4,
As an obstacle according to claim 2, an insulating layer or a groove is provided in the gate region.

Further, in the invention according to claim 5,
2. The semiconductor device according to claim 1, wherein a high resistance region is provided in a discharge path of the minority carrier introduced into the channel region, thereby increasing a resistance of a discharge path of the minority carrier introduced into the channel region. is there.

The invention described in claim 6 is the same as the invention in claim 5
Wherein a low-concentration opposite-conductivity-type resistance region is provided in contact with the main surface and the gate region so as not to contact the source region.

The operation of such a configuration will be described. When a ground potential or a negative potential is applied to apply a positive potential to the gate region and turn a conductive element into a cutoff state, minority carriers (here, holes) accumulated in the drain region are applied. Is the opposite conductivity type (p-type)
Flows into the gate region, and the minority carrier (hole) concentration gradually decreases from near the gate region. Further, in the channel region, the supply of the minority carriers (holes) stops, and when the minority carriers (holes) are discharged and the density of the minority carriers (holes) decreases, the high injection level state is released and the minority carriers (holes) are released. The holes form an inversion layer at the interface of the insulating film, and thereafter the minority carriers (holes) flow through the inversion layer and flow into the gate region of the opposite conductivity type (p-type). Further, when the minority carriers (holes) at the interface of the insulating film are also depleted, the lines of electric force from the fixed potential insulating electrode shielded by the minority carriers (holes) to the channel region are restored, and the majority carriers (holes) are restored. A potential barrier to (here, conduction electrons) is formed again, and the channel is cut off. At this time, if there is a structure that increases the resistance of the minority carrier discharge path, the rapid depletion of the minority carriers (holes) in the channel region is alleviated, and the potential barrier for the majority carriers (electrons) sharply increases. Resurrection is eased. As a result, the amount of overshoot of the drain voltage of this element decreases.

For example, by providing the obstacle for the minority carrier (hole) in the gate region as described in claim 2, the minority carrier (hole) can be circumvented. The length is increased, thereby increasing the resistance of the discharge path of the minority carrier (hole).

The obstacle may have a structure in which the fixed potential insulating electrodes sandwiching the source region in the gate region are connected to each other as described in claim 3, or as described in claim 4. In addition, an insulating layer or a groove may be provided in the gate region.

Further, as set forth in claim 5, a high resistance region may be provided in a discharge path of the minority carriers (holes) introduced into the channel region. Specifically, for example, a low-concentration opposite-conductivity-type (p-type) resistance region is provided in contact with the main surface and the gate region and not in contact with the source region. Provide.

In the above structure, when a ground or a negative potential is applied to the gate electrode at the time of turn-off, the excess minority carriers (holes) in the drain region flow into the gate region, and The (hole) concentration gradually decreases from near the gate region, but this operation is the same as in the conventional device. That is,
Since the resistance of the discharge path when extracting the minority carriers (holes) introduced into the drain region other than the channel region has not changed, the extraction speed of the minority carriers (holes) in the drain region is: It is equivalent to a conventional element. Therefore, the turn-off time from when the turn-off signal is applied to the gate electrode until when the drain current is cut off is not different from the conventional device. Therefore, the amount of overshoot of the drain voltage at the time of turn-off can be reduced while suppressing the extension of the turn-off time.

[0021]

According to the present invention, an excellent effect that the overshoot of the drain voltage at the time of turn-off can be reduced while suppressing the extension of the turn-off time is obtained.

Further, according to the constitutions of claims 2 to 4, the invention of claim 1 can be easily realized. In particular, according to claim 3, it can be easily realized by the conventional manufacturing process. Further, according to the configuration of claim 5, the invention of claim 1 can be realized with a configuration different from that of claim 2. Claim 6
According to this, the invention of claim 5 can be easily realized.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on embodiments. 1 to 4 are views showing a first embodiment of the present invention. 1 is a perspective view illustrating the basic structure of the element, FIG. 2 is a cross-sectional view showing the same portion as the front surface of FIG. 1, FIG. 3 is a surface view showing the same portion as the front surface of FIG. 1, and FIG. It is the same sectional view as. FIG. 2 is a cross-sectional view taken along the line AA in the front view of FIG. 3 and perpendicular to the paper surface, and FIG. 4 is a cross-sectional view taken along the line BB. 3 and 4 both show two units of the basic structure shown in FIG. In FIGS. 1 and 3,
For the purpose of explanation, a state in which a metal film and a surface protective film which are electrodes on the surface are removed is illustrated. Although the semiconductor is described as silicon in this embodiment, the semiconductor is not limited to silicon.

First, the element structure will be described. First, in FIGS. 1 to 4, reference numeral 1 denotes an n + -type substrate region, 2 denotes an n-type drain region, 3 denotes an n + -type source region, 4 denotes a MOS electrode, and 5 denotes an insulating film. The MOS type electrode 4 has a high concentration of p
Made of + type polysilicon. Reference numeral 11 denotes a drain electrode, which is in ohmic contact with the substrate region 1. A source electrode 13 is in ohmic contact with the source region 3 and the MOS type electrode 4. Therefore, the MOS type electrode 4 is fixed at the source potential. Therefore, the MOS type electrode 4 and the insulating film 5 are collectively referred to as a “fixed potential insulating electrode” 6. As shown in FIG. 2, the cross-sectional structure of the fixed potential insulating electrode 6 is such that the side wall is formed in a substantially vertical groove, for example, like a letter "U". In the figure, a source region 3 is an insulating film 5
However, if the source region 3 is arranged so as to be sandwiched between the fixed potential insulating electrodes 6, the source region 3 does not have to be in contact. In FIG. 2, the drain region 2 sandwiched between the fixed potential insulating electrodes 6 is
Call. Further, as shown in FIGS. 1 and 4, a p-type gate region 8 exists in contact with the insulating film 5 and away from the source region 3. In FIG. 4, reference numeral 18 denotes an electrode which makes ohmic contact with the gate region 8 and is called a “gate electrode”. Reference numeral 10 denotes an interlayer insulating film. The configuration up to this point is the same as that of the conventional example shown in FIG.

Further, in the present invention, the fixed potential insulating electrodes 6 arranged so as to sandwich the source region 3 are connected to each other in the gate region 8. In other words, the striped fixed potential insulating electrode 6 sandwiching the source region
And the same fixed potential insulating electrode 6 is formed in the gate region 8 so as to intersect. In the present embodiment, the structure is shown in which the fixed potential insulating electrodes 6 are connected so as to be orthogonal to the ends of the striped fixed potential insulating electrodes 6 sandwiching the source region 3. It does not matter even if they are not perpendicular to each other.

Next, the operation will be described. In this device, for example, the source electrode 13 is grounded (0 V) and the drain electrode 11
Is used by applying an appropriate positive potential via a load. First, when a negative potential is applied to the gate electrode 18, the element is in a cutoff state. Referring to FIG. 2, a depletion layer is formed around the fixed potential insulating electrode 6 due to the built-in potential of the MOS type electrode 4, but between the two fixed potential insulating electrodes 6 opposed in the channel region 7. (Hereinafter, referred to as “channel thickness H”) is sufficiently small, a sufficient potential barrier for conduction electrons is formed in the channel region 7 by the depletion region. For example, if the thickness of the insulating film 5 is set to 100 nm or less, the impurity concentration of the channel region 7 is set to 1 × 10 ¹⁴ cm ⁻³ or less, and the “channel thickness H” is set to 2 μm or less, the conduction electrons in the source region 3 Thus, a sufficient potential barrier can be formed which prevents movement to the drain region 2 side through the gate electrode 7. The distance from the source region 3 to the bottom of the fixed potential insulating electrode 6 (hereinafter referred to as “channel length L”) so that the potential barrier is not reduced by the influence of the electric field from the drain region 2. Is set to be 2 to 3 times or more of the channel thickness H.

Next, in the conductive state, the potential of the gate electrode 18, that is, the potential of the p-type gate region 8 is, for example, +
When a positive potential of 0.5 V is applied, holes become p
From the type gate region 8, it flows into the interface of the insulating film 5 to form an inversion layer, and shields the lines of electric force from the MOS type electrode 4, which forms a potential barrier, to the channel region 7. It lowers the potential barrier for electrons. That is, the drain region 2 and the source region 3 are brought into conduction. Further, when the potential of the gate electrode 18 is increased, the pn junction composed of the p-type gate region 8 and the surrounding n-type region is forward-biased, and holes are directly transferred to the drain region 2.
And into the channel region 7. As a result, the conductivity of these n-type regions, which have been made low in impurity concentration and high in resistance in order to maintain the withstand voltage of the device, is increased, and current flows with low resistance.

Next, when the ground or a negative potential is applied to the gate electrode 18 in order to turn off the device, excess holes in the drain region 2 flow into the p-type gate region 8 and the holes are removed. The concentration gradually decreases from near the gate region 8. This operation is similar to that of the conventional device. That is, since the resistance of the discharge path when extracting the minority carriers introduced into the drain region 2 other than the channel region 7 does not change, the speed of extracting holes in the drain region 2 is equal to that of the conventional device. Therefore, the turn-off time from when the turn-off signal is applied to the gate electrode 18 until the drain current is cut off is not different from the conventional device.

When the supply of holes is stopped in the channel region 7 and the hole density decreases, the high-level injection state is released, and the holes form an inversion layer at the interface with the insulating film 5. Thereafter, it flows through the inversion layer, flows into the p-type gate region 8, and is discharged to the gate electrode 18. At this time, as shown in FIG. 4, the fixed potential insulating electrode 6 orthogonal to the channel region 7 exists in the gate region 8, so that holes discharged from the channel region 7 bypass the fixed potential insulating electrode 6. Therefore, the path in the high-resistance region in the gate region 8 is long. That is, since the resistance of the discharge path is large for holes, rapid depletion of holes in the channel region 7 is reduced.

As a result, in the conventional structure as shown in FIG. 7, the holes forming the inversion layer at the interface of the insulating film 55 of the fixed potential insulating electrode 56 are rapidly depleted and are blocked by the holes. Since the lines of electric force from the fixed potential insulating electrode 56 to the channel region 57 suddenly recover, the drain potential has risen sharply in order to maintain the drain current that had been flowing until then. In the first embodiment, the rise of the drain potential is reduced. That is, the amount of overshoot of the drain potential at the time of turn-off is reduced.

In the structure of the first embodiment, since the fixed potential insulating electrodes 6 arranged so as to sandwich the source region 3 are connected to each other by the fixed potential insulating electrodes 6, the conventional manufacturing method is employed. It can be easily realized in the process. Also,
The structure is not limited to the above structure, and an obstacle having an effect of increasing resistance of a discharge path for holes discharged from the channel region 7 at the time of turn-off may be formed.
For example, an insulating layer such as an oxide film or a simple groove may be formed in the gate region 8. Further, the fixed potential insulating electrodes 6 need not be connected to each other.

Next, FIGS. 5 and 6 show a second embodiment of the present invention. FIG. 5 is a perspective view for explaining the basic structure of the element, and FIG. 6 is a sectional view of the same side as FIG.
FIG. 6 shows two units of the basic structure shown in FIG. FIG. 5 illustrates a state in which the metal film and the surface protective film, which are electrodes on the surface, are removed for explanation. Although the semiconductor is described as silicon in this embodiment, the semiconductor is not limited to silicon.

In the structure of FIG. 5 and FIG.
4 to FIG. 4 will be described. In the structure of the second embodiment, a p-type high resistance region 9 is present at a position in contact with the gate region 8 and sandwiched between the fixed potential insulating electrodes 6. In the second embodiment, the high resistance region 9 has a shape formed by ion implantation into the surface and diffusion by heat. However, it may be formed as a buried region.

Next, the operation will be described. Since the basic operation is the same as that of the first embodiment, only the operation at the time of turn-off will be described.

When ground or a negative potential is applied to the gate electrode 18 to turn off the device, excess holes in the drain region 2 flow into the p-type gate region 8 and the hole concentration becomes It gradually decreases from around 8. This operation is similar to that of the conventional device. That is, since the resistance of the discharge path when extracting holes introduced into the drain region 2 other than the channel region 7 does not change, the speed of extracting holes in the drain region 2 is equal to that of the conventional device. The turn-off time from when the turn-off signal is applied to the gate electrode 18 until the drain current is cut off is not different from the conventional device. When the supply of holes stops in the channel region 7 and the hole density decreases, the high-level injection state is released, and the holes form an inversion layer at the interface of the insulating film 5. It flows through the layer, flows into the p-type gate region 8, and is discharged to the gate electrode 18. At this time, holes extracted from the channel region 7 are discharged through the high resistance region 9 as shown in FIG. That is,
Since the resistance of the discharge path is large for the holes extracted from the channel region 7, the rapid depletion of the holes in the channel region 7 is reduced. Therefore, the first
The same effect as described in the embodiment can be obtained.

[Brief description of the drawings]

FIG. 1 is a perspective view of a first embodiment of the present invention.

FIG. 2 is a sectional view of the first embodiment of the present invention.

FIG. 3 is a sectional view showing a surface structure according to the first embodiment of the present invention.

FIG. 4 is a sectional view of the first embodiment of the present invention viewed from another angle.

FIG. 5 is a perspective view of a second embodiment of the present invention.

FIG. 6 is a sectional view of a second embodiment of the present invention.

FIG. 7 is a perspective view of a conventional example.

FIG. 8 is a sectional view of a conventional example.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Substrate region 2 ... Drain region 3 ... Source region 4 ... MOS type electrode 5 ... Insulating film 6 ... Fixed potential insulating electrode 7 ... Channel region 8 ... Gate region 9 ... High resistance region 10 ... Interlayer insulating film 11 ... Drain electrode 13 ... Source electrode 18 ... Gate electrode 51 ... Substrate region 52 ... Drain region 53 ... Source region 54 ... MOS
Type electrode 55 ... Insulating film 56 ... Fixed potential insulating electrode 57 ... Channel region 58 ... Gate region 60 ... Interlayer insulating film 61 ... Drain electrode 63 ... Source electrode 68 ... Gate electrode H ... Channel thickness L ... Channel length

Claims (6)

[Claims] A trench having a source region of the same conductivity type in contact with one main surface of a semiconductor substrate of one conductivity type, which is a drain region; and a groove arranged in contact with the main surface and sandwiching the source region. A fixed potential insulating electrode that is insulated from the drain region by an insulating film inside the trench, and that is kept at the same potential as the source region. A conductive material having a work function such that a depletion region is formed in the drain region adjacent to the source region, a part of the drain region in contact with the source region, and a channel region sandwiched by the fixed potential insulating electrode A potential barrier for preventing movement of majority carriers is formed in the channel region by the depletion region formed around the fixed potential insulating electrode; In the channel region, the distance from the bottom of the groove to the source region, that is, the channel length is in the channel region so that the electric field from the drain region side does not affect the vicinity of the source region. The distance between the side walls of the groove facing each other, that is, at least two to three times the channel thickness, and the inversion layer is formed by introducing minority carriers into the interface of the insulating film surrounding the fixed potential insulating electrode. Contacting the insulating film and the drain region to shield an electric field from the fixed potential insulating electrode to the drain region to reduce or eliminate a potential barrier formed in the channel region to open a channel; In a semiconductor device having a gate region of the opposite conductivity type which is not in contact with a region, A structure is provided in which the resistance of the discharge path when extracting the minority carriers introduced into the channel region is increased without changing the resistance of the discharge path when extracting the minority carriers introduced into the drain region. Semiconductor device. 2. An obstacle to the minority carrier is provided in the gate region and the minority carrier is bypassed in the gate region, thereby increasing a resistance of a discharge path of the minority carrier introduced into the channel region. The semiconductor device according to claim 1, wherein: 3. The semiconductor according to claim 2, wherein the obstacle is formed such that the fixed potential insulating electrodes sandwiching the source region are connected to each other in the gate region. apparatus. 4. The semiconductor device according to claim 2, wherein the obstacle is an insulating layer or a groove provided in the gate region. 5. The resistance of the discharge path of the minority carrier introduced into the channel region is increased by providing a high resistance region in the discharge path of the minority carrier introduced into the channel region. 2. The semiconductor device according to 1. 6. In contact with said main surface and said gate region,
6. The semiconductor device according to claim 5, wherein a low-concentration opposite-conductivity-type resistance region is provided so as not to contact the source region.