JP3533925B2 - Semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bipolar normally-off vertical power device.

[0002]

2. Description of the Related Art As the prior art which is the background of the present invention, Japanese Patent Application Laid-Open No. 6-252408 filed by the applicant of the present application is cited. 8 to 11 are structural views of the semiconductor device cited from the above publication. It should be noted that the numbers and names of parts in the drawings are appropriately changed for description. 8 is a perspective view showing the basic structure, FIG. 9 is a sectional view showing the same part as the front surface of FIG. 8, FIG. 10 is a surface view showing the same part as the upper surface of FIG. 8, and FIG. 11 is the same cross section as the side surface of FIG. It is a figure. Further, a cross-sectional view taken along line AA in the surface view of FIG. 10 perpendicular to the paper surface corresponds to FIG. 9, and a cross-sectional view taken along line BB similarly corresponds to FIG. 11. To do. 10 and 11 both show four units of the basic structure shown in FIG.

In the above figures, reference numeral 51 is an n + type substrate region, 52 is an n type drain region, 53 is an n + type source region, 54 is a MOS type electrode, and 55 is an insulating film. MO
The S-type electrode 54 is made of high-concentration p + -type polysilicon.
A drain electrode 61 is in ohmic contact with the substrate region 51. Reference numeral 63 shown in FIGS. 9 and 11 denotes a source electrode which makes ohmic contact with the source region 53 and the MOS type electrode 54. That is, the MOS electrode 54 is fixed at the source potential. Therefore, this M
The OS type electrode 54 and the insulating film 55 are collectively referred to as “fixed potential insulating electrode” 56. As shown in FIG. 9, the sectional structure of this fixed potential insulated electrode is formed in a groove whose side wall is substantially vertical like a letter "U".

Further, in FIG. 9, a portion sandwiched between the fixed potential insulating electrodes 56 in the drain region 52 is called a channel region 57. Further, the distance between two fixed potential insulated electrodes facing each other in the channel region is called “channel thickness H”, and the distance from the source region 3 to the bottom of the fixed potential insulated electrode 6 is called “channel length L”. To do. The channel length L is set to be 2 to 3 times or more the channel thickness H. Under this condition, the cutoff state of the channel region 7 is maintained until the avalanche breakdown condition.

Further, as shown in FIGS. 8 and 11, there is a p-type gate region 58 in contact with the insulating film 55 and away from the source region 53. 6 in FIG.
Reference numeral 8 denotes an electrode which makes ohmic contact with the gate region 58 and is called a "gate electrode". Reference numeral 60 is an interlayer insulating film. Also, as can be seen from the relationship with FIG. 8, the “dashed line” in FIG. 11 indicates the fixed potential insulated electrode 5 in the depth direction of the paper surface.
6 shows the existence of 6. Reference numeral 59 in FIG. 10 denotes a gate contact hole where the gate electrode 68 makes ohmic contact with the gate region 58.

The above semiconductor device is a current control type semiconductor device in which the drain current is controlled by the gate current value, and is a so-called normally-off type element which is in a cutoff state when the gate electrode is grounded. .

[0007]

One of the indexes showing the characteristics of the current control type semiconductor device is a ratio of "drain current value / gate current value", that is, a so-called "current amplification factor". From the viewpoint of easiness of control, it is desirable that the current amplification factor is large, that is, the gate current value required to flow the same drain current value is small. The component of the gate current is
(1) A hole current injected from the p-type gate region 58 into the n-type region, and (2) an electron current jumping from the n + -type source region 53 to the p-type gate region 58. Furthermore, the former (1) can be classified into (1a) a component that disappears in the high-level-implanted drain region 52, and (1b) a component that disappears by jumping into the n + -type source region 53.
In order to improve the current amplification factor, it is necessary to suppress these three types of components.

Considering this semiconductor device as a switching device, the component (1a) is not dominant in the high current mode in which the drain current density is several tens A / cm ² or more. To suppress the component (1b), the size of the n + type source region 53 may be reduced. This can be achieved relatively easily, and FIG. 11 and the like also show a diagram in which the source region 53 is formed small.

In order to suppress the above component (2), p
It is sufficient to reduce the size of the gate region 58 of the mold, but this has a limit. That is, in the conventional example shown in FIGS. 8 to 11, the gap between the fixed potential insulating electrodes 56 corresponding to the “channel thickness H” in order to realize the above-mentioned cutoff state is improved by the photo device in order to improve the element characteristics. It will be formed with the smallest feasible pattern size. Therefore, the gate contact hole 59 that connects the gate region 58 and the gate electrode 68 cannot be formed in the gap between the fixed potential insulating electrodes 56 having the same potential as the source electrode 63. Therefore, as shown in FIG. 10 and the like, the fixed potential insulating electrode 56 must be interrupted only in the region where the gate contact hole 59 is formed, and the fixed potential insulating electrode 56 has an end portion. This gate contact hole 59
In the same manner as described above, even if the size is set to the minimum size, the distance between the contact hole 59 and the fixed potential insulated electrode 56 must be set to the above minimum unit. Therefore, the end portions of the fixed potential insulated electrode 56 facing each other are relatively separated from each other, as shown in the central portion of FIG. Therefore, with such a structure, there is a problem that the drain electric field in the cutoff state is concentrated on the end portion of the fixed potential insulating electrode 56, and the breakdown voltage of the element deteriorates.

In order to prevent this, even if the drain voltage rises and a strong electric field is generated in the drain region 52 in the cut-off state of the element, the gate is deep and dark enough that the electric field is not applied to the end of the fixed potential insulating electrode 56. It was necessary to form the region 58 so as to cover the end of the fixed potential insulating electrode 56. However, in doing so, the gate region 58
Also spreads laterally, and the gate region 58 becomes large. Therefore, there is a problem in that there is a limit to reducing the size of the gate region 58 and suppressing the component (2) of the gate current, that is, the electron current jumping into the gate region 58 in the conductive state.

It is an object of the present invention to provide a semiconductor device having a high current amplification factor while keeping the breakdown voltage of the element in view of the above problems.

[0012]

In order to achieve the above object, the present invention has a structure as set forth in the claims. That is, according to the first aspect of the invention, the semiconductor substrate of one conductivity type (for example, n type) that is the drain region is in contact with one main surface of the same conductivity type (here, n type).
A source region of the mold), having several double the first grooves which are arranged so as to sandwich the source region in contact with the main surface. Two grooves are generally required to sandwich the source region, but one source having a U-shape may be used. Further, inside the first groove, a first insulating electrode insulated from the drain region by a first insulating film and kept at the same potential as the source region (for example, fixed potential insulation shown in FIG. 1 described later). Corresponding to the electrode 56), and the first insulating electrode has a work function conductive material (for example, p-type polysilicon) that forms a depletion region in the drain region adjacent to the first insulating film. ) Consists of. A part of the drain region in contact with the source region has a channel region sandwiched by the first insulating electrode, and the channel region is formed around the first insulating electrode. The depletion region forms a potential barrier that blocks the movement of majority carriers (conduction electrons here). Further, in order to prevent the electric field from the drain region side in the cutoff state from affecting the vicinity of the source region, the distance from the bottom of the first groove to the source region in the channel region, that is, the channel length, At least 2 of the distance between the side walls of the first groove facing each other in the channel region, that is, the channel thickness.
To 3 times or more.

Further, it has a first groove and a second groove which is not in contact with the source region and faces the main surface. Inside the second groove, the drain is formed by a second insulating film. A second insulated electrode insulated from the area (see, for example, FIG.
Corresponding to the variable potential insulating electrode 16). Further, in the cutoff state, the second groove is arranged in the vicinity of the end of the first groove in order to reduce the concentration of the electric field from the drain region at the end of the first groove. ing.

Further, minority carriers (here, holes) are introduced into the interface of the first insulating film surrounding the first insulating electrode to face the main surface to form an inversion layer. In order to shield the electric field from the insulating electrode to the drain region and reduce or eliminate the potential barrier formed in the channel region to open the channel, the source region is in contact with the second insulating film. It has a gate region of the opposite conductivity type (for example, p-type) which is not in contact with the gate region and is connected to the second insulating electrode. The above configuration corresponds to, for example, the embodiment shown in FIGS.

The operation of this structure will be described. A state in which the gate region is kept at the same potential as the source region, that is, when the element is in a blocking state, because the second groove is formed near the end of the first groove,
Even if the drain potential rises, the electric field is not concentrated on the end portion of the first groove and the avalanche breakdown condition is not reached. Further, when the element is in a conductive state, minority carriers (here, holes) are supplied from the gate region of opposite conductivity type (here, p type) to the drain region of the same conductivity type (here, n type). It is injected into a high-level injection state, and majority carriers (here, conduction electrons) also exist in many places. Some of the majority carriers (here, conduction electrons) jump into the gate region of the opposite conductivity type (here, p type) to form a part of the gate current, but the gate region is shallow and spreads in the lateral direction. If it is formed to be small, the proportion of majority carriers (conduction electrons here) that jump into the gate region and disappear is relatively small, and the gate current value required to flow a constant main current can be kept low.

Further, in the invention described in claim 2,
The first insulating electrode and the second insulating electrode are not aligned in a straight line in the length direction but are arranged at positions displaced from each other. Note that this configuration corresponds to, for example, the embodiment of FIG. 5 described later.

Further, in the invention described in claim 3,
The plurality of first insulated electrodes arranged in parallel and the plurality of second insulated electrodes arranged in parallel are arranged such that their end portions are displaced from each other.
Note that this configuration corresponds to, for example, the embodiment of FIG. 6 described later. In this case, as shown in FIG. 6, the end portion of the second insulated electrode may enter between the first insulated electrodes.

Further, in the invention described in claim 4,
In which the gate region is not in contact with the first insulating film of said first insulated electrode. Note that this configuration corresponds to, for example, the embodiment of FIG. 7 described later.

[0019]

According to the present invention, since the size of the gate region can be reduced, the current amplification factor is improved. Further, since the cell size is reduced, the current amplification factor is further improved and the turn-off time is shortened. Further, in the inventions according to claims 2 to 4, in addition to the above effects, the degree of freedom in design is improved and the cell size can be further reduced. Therefore, the cell density is improved, the current amplification factor is improved, and the turn-off time is further shortened.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described in detail below with reference to embodiments. (First Embodiment) FIGS. 1 to 4 are views showing a first embodiment of the present invention. This corresponds to claim 1. 1 is a perspective view showing the basic structure of the device, FIG. 2 is a sectional view showing the same part as the front surface of FIG. 1, FIG. 3 is a surface view showing the same part as the upper surface of FIG. 1, and FIG. 4 is a side view of FIG. It is the same sectional view. 2 is a sectional view taken along line AA in the front view of FIG. 3 and perpendicular to the paper surface, and FIG. 4 is a sectional view taken along line B-B. 3 and 4 both show four units of the basic structure shown in FIG. Also,
In FIG. 1 and FIG. 3 described above, a state in which the metal film which is the electrode on the surface and the surface protective film are removed is illustrated for the sake of explanation. In this embodiment, the semiconductor will be described as silicon.

First, the device structure will be described. First, in FIGS. 1 to 4, reference numeral 1 is an n + type substrate region, 2 is an n type drain region, 3 is an n + type source region, and 4 is a first M region.
The OS type electrode 5 is a first insulating film. The first MOS type electrode 4 is made of high concentration p + type polysilicon. A drain electrode 11 is in ohmic contact with the substrate region 1. A source electrode 13 is in ohmic contact with the source region 3 and further with the first MOS type electrode 4.
That is, the first MOS type electrode 4 is fixed to the source potential. Therefore, the first MOS type electrode 4 and the first insulating film 5 are collectively referred to as "fixed potential insulating electrode" 6 (corresponding to the first insulating electrode in the claims). As shown in FIG. 2, the cross-sectional structure of the fixed potential insulated electrode 6 is formed in a groove whose side wall is substantially vertical like a letter "U". Further, in the figure, the source region 3 is drawn so as to be in contact with the first insulating film 5, but if the source region 3 is arranged so as to be sandwiched between the fixed potential insulating electrodes 6, it does not have to be in contact. . Further, in FIG. 2, the drain region 2 sandwiched between the fixed potential insulating electrodes 6 is replaced by the channel region 7
Call. Up to this point, the configuration is similar to that of the conventional example.

Further, in this embodiment, as shown in FIGS. 1 and 4, the source region 3 is in contact with the first insulating film 5.
There is a shallowly formed p-type gate region 8 at a position away from. In FIG. 4, reference numeral 18 denotes an electrode which makes ohmic contact with the gate region 8 and is called a “gate electrode”.

Then, as shown in FIG. 1 and FIG.
The variable potential insulating electrode 16 formed by the second MOS electrode 14 so as to contact the gate region 8 and not to contact the source region 3 and the second insulating film 15 for insulating the second MOS electrode 14 from the drain region 2 ( (Corresponding to the second insulated electrode in the claims). Like the fixed potential insulating electrode 6, the variable potential insulating electrode 16 has a sectional structure in which a side wall is formed in a groove having a substantially vertical shape like a letter "U". Second MOS
As shown in FIG. 3, the mold electrode 14 is formed on the gate electrode 18 through the gate contact hole 9 common to the gate region 8.
Ohmic contact with. In addition, the second MOS
The type electrode 14 is the same conductive material as the first MOS type electrode 4,
That is, for example, high-concentration p + type polysilicon may be used.
The second insulating film may be the same as the first insulating film.

Reference numeral 10 is an interlayer insulating film. Also, as can be seen from the relationship with FIG. 1, the “broken line” in FIG. 4 indicates the existence of the fixed potential insulating electrode 6 and the variable potential insulating electrode 16 in the depth direction of the paper surface. 1 and 4, the fixed-potential insulated electrode 6 and the variable-potential insulated electrode 16 are drawn so that the ends thereof are at a right angle, but the ends may be polygonal or curved.

Next, the operation will be described. In this element, for example, the source electrode 13 is grounded (0 V) and the drain electrode 11 is
Is used by applying an appropriate positive potential via a load. (Blocking State) First, when the gate electrode 18 is grounded, the element is in a blocking state. Referring to FIG. 2,
A depletion layer due to the built-in potential of the first MOS electrode 4 is formed around the fixed potential insulating electrode 6, but the distance between two fixed potential insulating electrodes 6 facing each other in the channel region 7 (hereinafter, If this is called "channel thickness H"), the depletion region forms a sufficient potential barrier for conduction electrons in the channel region 7. For example, if the thickness of the insulating film 5 is 100 nm or less, the impurity concentration of the channel region 7 is 1 × 10 ¹⁴ cm ³ or less, and the “channel thickness H” is 2 μm or less, conduction electrons in the source region 3 are generated. It is possible to form a sufficient potential barrier that prevents movement toward the drain region 2 side through 7.

Further, the potential barrier is not lowered by the influence of the electric field from the drain region 2,
Distance from the source region 3 to the bottom of the fixed potential insulating electrode 6 (hereinafter, referred to as "channel length L")
Is set to 2-3 times or more the channel thickness H.

When this embodiment is embodied in a vertical transistor chip, a breakdown voltage structure such as a guard ring is arranged on the outer periphery of the chip to reduce electric field concentration.
The drain voltage at which avalanche breakdown occurs in the breakdown voltage structure becomes the device breakdown voltage. Under the above conditions, the cutoff state of the channel region 7 can be designed to be maintained up to this element breakdown voltage.

Further, for example, in FIG. 4, the end portion of the fixed potential insulating electrode 6 is exposed to the electric field from the drain region 2 in the cutoff state, but in this embodiment, the end portion of the fixed potential insulating electrode 6 is exposed. In order to alleviate the electric field concentration, a variable potential insulating electrode 16 is arranged in the immediate vicinity so that avalanche breakdown does not occur at the end of the fixed potential insulating electrode 6. For example, if the fixed potential insulating electrode 6 and the variable potential insulating electrode 16 are arranged such that the distance between the end portions of the adjacent fixed potential insulating electrode 6 and the variable potential insulating electrode 16 is equal to or less than the channel thickness H, the ends of the fixed potential insulating electrode 6 and the variable potential insulating electrode 16 are arranged. It has been clarified by experiments that the part does not reach the avalanche breakdown condition up to the device breakdown voltage.

(Conductive state) Next, in the conductive state, when +0.5 V, for example, is applied as the potential of the gate electrode 18, that is, the potential of the p-type gate region 8, holes are opposite to the above, and the p-type gate region is reversed. 8 flows into the interface of the first insulating film 5 in contact therewith to form an inversion layer, and shields the lines of electric force from the first MOS type electrode 4 forming the potential barrier to the channel region 7. , Lowers the potential barrier for conduction electrons in the channel region 7. That is, this brings the drain region 2 and the source region 3 into conduction. Further, as the potential of the gate electrode 18 is increased, a pn formed of the p-type gate region 8 and the peripheral n-type region is formed.
The junction is forward biased and holes are directly injected into the drain region 2 as well as the channel region 7. Then, the conductivity is increased in these n-type regions, which have been made to have a high impurity resistance and a low impurity concentration in order to maintain the breakdown voltage of the device, and the current flows with a low resistance.

As described above, the semiconductor device of this embodiment is a current control type semiconductor device in which the drain current value is controlled by the gate current value. There is a so-called “current amplification factor” as one index showing the characteristics of the current control type semiconductor device, and here, it is represented by the ratio of “drain current value / gate current value”. It is desirable that the current amplification factor is large in view of the ease of control. That is, it is desirable that the gate current value required to pass the same drain current value is small. The components of the gate current are (1) a hole current injected from the p-type gate region 8 to the n-type region, and (2) an electron current jumping from the n + -type source region 3 to the p-type gate region 8. Consists of. Further, the above (1) includes (1a) a component that causes pair annihilation in the drain region 2 in the high level implantation state, and (1b) n.
It can be classified as a component that jumps into the + type source region 3 and disappears. In order to improve the current amplification factor, it is necessary to suppress these three types of components.

Considering this semiconductor device as a switching device, the component (1a) is not dominant in a high current mode in which the drain current density is several tens A / cm ² or more. Further, in order to suppress the component (1b), the size of the n + type source region 3 may be reduced. This can be realized relatively easily even in the conventional technique, and FIG. 4 and the like show the figure in which the source region 3 is formed small.

In order to suppress the above component (2), p
The size of the mold gate region 8 may be reduced. Although the gate region 8 cannot be made small in the above-mentioned conventional example, in the present embodiment, the presence of the variable potential insulating electrode 16 eliminates the need for the gate region 8 to be deep and large, and can be made as shallow and small as possible. From this, the component (2) is reduced and the current amplification factor is improved. Further, by forming the gate region 8 shallowly, the lateral expansion is suppressed, so that the gate region 8 can be formed smaller, and thus the cell size can be reduced. That is, FIGS.
In a transistor chip having the above structure, when a constant current is applied to a constant area, the density of the current flowing through the source region 3 per unit cell is reduced, and as a result, the current amplification factor is improved.

(Turn Off) Next, turn off will be described. In order to turn off the element in the conductive state, the potential of the gate electrode 18 is set to 0 in FIG. 1 of this embodiment mode.
Or it turns to a negative potential. Then, excess holes in the drain region 2 and the channel region 7 begin to flow into the p-type gate region 8, and eventually, all the excess holes in the channel region 7 are eliminated, and the potential barrier for electrons is restored. At this time, in the present embodiment, since the lateral expansion is suppressed by forming the gate region 8 shallowly, the cell size can be reduced and the source region 3 can be reduced.
Since the distance from the gate region 8 to the gate region 8 is shortened, it is possible to shorten the time until all excess holes accumulated in the device are discharged to the outside of the device, that is, the turn-off time.

(Second Embodiment) FIG. 5 is a diagram showing a second embodiment. This is a surface view of the element corresponding to FIG. 3 described above, and the same reference numerals in the figure indicate the same elements.
As shown in FIG. 5, the fixed potential insulating electrodes 6 and the variable potential insulating electrodes 16 are not aligned in a straight line in the length direction but are arranged at positions displaced from each other. With such a configuration, the same effect as that of the first embodiment can be obtained. In the structure shown in FIG. 3, a region wider than the channel thickness H is produced in the area where the fixed potential insulating electrode 6 and the variable potential insulating electrode 16 face each other, but in the arrangement shown in FIG. Since it can be made small, the effect of alleviating the electric field at the ends of the fixed potential insulating electrode 6 and the variable potential insulating electrode 16 is high.

(Third Embodiment) FIG. 6 is a diagram showing a third embodiment. This is also a surface view of the element corresponding to FIG. 3 described above, and the same reference numerals in the figure indicate the same elements. As shown in FIG. 6, the variable potential insulated electrodes 16 arranged in parallel with each other and the fixed potential insulated electrodes 6 arranged in parallel with each other have their end portions displaced from each other (alternatively every other position). The positions of the ends are displaced). Even in such a case, the same effect as that of the first embodiment can be obtained. In this case, as shown in FIG. 6, the end of the variable potential insulating electrode 16 may enter between the fixed potential insulating electrodes 6.

(Fourth Embodiment) FIG. 7 is a diagram showing a fourth embodiment. This is also a surface view of the element corresponding to FIG. 3 described above, and the same reference numerals in the figure indicate the same elements. The fourth embodiment has a structure in which the gate region 8 is not in contact with the fixed potential insulating electrode 6 as compared with the first embodiment. Even with such a structure, the movement path of holes in the blocking state is not blocked, and holes can be exchanged between the gate region 8 and the fixed potential insulating electrode 6. This is a fixed potential insulated electrode 6
Since the distance between the variable potential insulating electrode 16 and the variable potential insulating electrode 16 is as short as about the channel thickness H or less, if holes increase at some interfaces of the insulating film and the interface potential decreases, the holes accumulated there are easily opposed to each other. This is because it can move to the interface. That is, although there is a difference in resistance related to the movement of holes between the gate region 8 and the source region 3, the gate region 8 may or may not be in contact with the interface of the first insulating film 5 and does not affect the basic operation. . However, with such an arrangement, the cell size can be reduced more than that of the first embodiment. From this, the cell density is improved, so that the current density flowing in the source region 3 of the unit cell can be reduced, and the current amplification factor is further improved. In addition, the turn-off time is further shortened by reducing the cell size.

[Brief description of drawings]

FIG. 1 is a perspective view of a first embodiment of the present invention.

FIG. 2 is a sectional view of the first embodiment of the present invention.

FIG. 3 is a sectional view showing a surface structure in the first embodiment of the present invention.

FIG. 4 is a sectional view of the first embodiment of the present invention viewed from another angle.

FIG. 5 is a front view of a second embodiment of the present invention.

FIG. 6 is a front view of a third embodiment of the present invention.

FIG. 7 is a front view of a fourth embodiment of the present invention.

FIG. 8 is a perspective view of a conventional example.

FIG. 9 is a sectional view of a conventional example.

FIG. 10 is a sectional view showing a surface structure in a conventional example.

FIG. 11 is a sectional view of the conventional example seen from another angle.

[Explanation of symbols]

1 ... Substrate region 2 ... Drain region 3 ... Source region 4 ... First MOS
Mold electrode 5 ... First insulating film 6 ... Fixed potential insulating electrode 7 ... Channel region 8 ... Gate region 9 ... Gate contact hole 10 ... Interlayer insulating film 11 ... Drain electrode 13 ... Source electrode 14 ... Second MOS type electrode 15 Second insulating film 16 Variable potential insulating electrode 18 Gate electrode 51 Substrate region 52 Drain region 53 Source region 54 MOS electrode 55 Insulating film 56 Fixed potential insulating electrode 57 Channel region 58 Gate Region 59 ... Gate contact hole 60 ... Interlayer insulating film 61 ... Drain electrode 63 ... Source electrode 68 ... Gate electrode H ... Channel thickness L ... Channel length

Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 29/78 654

Claims (4)

(57) [Claims] 1. A first region having a source region of the same conductivity type in contact with one main surface of a semiconductor substrate of one conductivity type, which is a drain region, and arranged so as to sandwich the source region in contact with the main surface. groove having several double of the inside of the first groove is insulated from the drain region by a first insulating film, and have a first insulating electrode which is kept at the same potential as the source region The first insulating electrode is made of a conductive material having a work function so as to form a depletion region in the drain region adjacent to the first insulating film, and the drain region in contact with the source region is formed. A part thereof has a channel region sandwiched by the first insulating electrode, and the depletion region formed around the first insulating electrode blocks movement of majority carriers in the channel region. Potential barrier The distance from the bottom of the first groove to the source region in the channel region, that is, the channel, so that the electric field from the drain region side in the cutoff state does not affect the vicinity of the source region. The length is at least 2 to 3 times or more the distance between the side walls of the first groove facing each other in the channel region, that is, the channel thickness. Further, the length of the first groove faces the main surface. And a second groove that is not in contact with the source region, and a second insulating electrode that is insulated from the drain region by a second insulating film inside the second groove, In order to reduce the concentration of the electric field from the drain region at the end of the first groove, the second groove is near the end of the first groove, and the main surface is Facing the The minority carriers are introduced into the interface of the first insulating film surrounding the first insulating electrode to form an inversion layer, and the electric field from the first insulating electrode to the drain region is shielded to the channel region. A gate region of opposite conductivity type, which is in contact with the second insulating film and is not in contact with the source region, so as to open or open a channel by reducing or eliminating the formed potential barrier; Is connected to the second insulating electrode. 2. The first insulated electrode and the second insulated electrode are not aligned in a straight line in the lengthwise direction but are arranged at positions displaced from each other. Item 1
The semiconductor device according to. 3. A plurality of first insulated electrodes arranged in parallel and a plurality of second insulated electrodes arranged in parallel are arranged such that their end portions are displaced from each other. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device. Wherein said gate region, the first is not in contact with the first insulating film of insulated electrodes, the semiconductor device according to claim 1, characterized in that.