JP3279092B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device comprising a bipolar type normally-off type vertical power element.

[0002]

2. Description of the Related Art As a prior art related to the present invention, first, a trench j-MOS transistor ("Charactee") published in a magazine IEEE Electron Device Letters, Inc.
risticsof Trench j-MOS Power Transistors ”BERNARD
A.MacIVER.STEPHEN J.VALERI, KAILASH C.JAIN, JAMES C.
ERSKINE, REBECCA ROSSEN, IEEE ELECTRON DEVICE LETTER
S, VOL.10, NO.8, p.380-382, AUGUST 1989)

FIGS. 16 to 18 are views showing an element structure described in the above-mentioned document. FIG. 16 is a surface structure diagram of the element, and FIGS. 17 and 18 are line segments A in FIG.
It is sectional drawing cut out by -A 'or line segment BB', and seen in the direction of each arrow.

First, the structure will be described. The semiconductor is silicon. In the figure, reference numeral 81 denotes an n ⁺ -type drain region serving as a substrate, 82 denotes an n-type channel region, and 83 denotes an n ⁺ -type source region. 84 is an insulating film, 85 is a gate electrode made of conductive polycrystalline silicon, and 86 is an interlayer insulating film. Hereinafter, 84, 85, and 86 are collectively referred to as “insulated gate” 87. The insulated gate 87 is formed inside a groove which is vertically dug in the side wall from the surface of the substrate, and the bottom reaches the drain region 81. Reference numeral 88 denotes a p-type region, which is formed in the channel region and provided near the insulated gate 87. Reference numeral 93 denotes a metal serving as a source electrode, which is in ohmic contact with the source region 83. An electrode metal 95 is in ohmic contact with the gate electrode 85, and is hereinafter referred to as a "MOS gate". Reference numeral 98 denotes an electrode metal that makes ohmic contact with the p-type region 88, and is hereinafter referred to as a “junction gate”. Reference numeral 91 denotes a drain electrode, which is a metal that makes ohmic contact with the drain region 81. Although the drain electrode 91 was not specified in the above-mentioned document, it was added for easy understanding. In the device described in the above document, the specific resistance of the channel region 82 is 0.98
Ω-cm, which corresponds to an impurity concentration of about 5 × 10 ¹⁵ cm ³ . The channel length L shown in FIG. 18 is 6 μm, the channel thickness a is 3 μm, and the thickness b of the insulated gate itself is 2 μm
It is.

Next, the operation of this device will be described. A positive potential is applied to the drain electrode 91, and the source electrode 93 is grounded (0 V). This device is a four-terminal device having two control electrodes, a MOS gate 95 and a junction gate 98. Also, both can be connected and used as a three-terminal element. Current when driven as a three-terminal element
Voltage characteristics are shown in FIG. 19, cited from the above document. FIG.
FIG. 9 shows a characteristic curve when both gate potentials are applied from −16 to 0 V in increments of 2 V. The element is a normally-on type, and the higher the negative potential of the gate, the more the main current is suppressed.

FIG. 20 shows the current / voltage characteristics of a four-terminal element, similarly cited from the above-mentioned document. This is a diagram when the potential of the MOS gate is fixed and the potential of the junction gate is changed. In the figure, +16 is added to the MOS gate.
The case where V is applied and the case where -16 V is applied are shown at the same time.

When a positive potential is applied to the MOS gate 95, it exhibits a very low on-resistance. This is because the accumulation layer induced at the insulated gate film interface in FIG. 18 becomes a conductive path connecting the n ⁺ -type drain region 81 and the n ⁺ -type source region 83. At this time, the potential of the junction gate 98 does not significantly affect the current-voltage characteristics.

When a negative potential is applied to the MOS gate 95, the current / voltage characteristics change depending on the potential applied to the junction gate 98. In FIG. 20, -3.5 to-
It shows a characteristic curve when voltage is applied to 0 V in 0.5 V steps. The operation mechanism in this state will be briefly described.
First, when the junction gate 98 is at 0V, in a linear region of the characteristic curve, that is, in a region where the drain potential is low, M
When a negative potential is applied to the OS gate 95, the insulating gate 8
A depletion layer is formed in the channel region 82 near 7, and an inversion layer is formed at the gate insulating film interface by holes generated there. The presence of the inversion layer shields the electric field from the gate electrode 85. Therefore, the extent of the depletion layer is JFET
Unlike the case, it stays in a certain range. When converted from the data in the above-mentioned literature, the value is about 0.4μ on one side.
m, a neutral region of about 2 μm remains in the channel region. The main current flows through the neutral region remaining in the channel. When the drain potential increases, the channel region becomes in a pinch-off state as in the case of a normal long channel JFET.
The current value saturates.

Next, when a negative potential, that is, a reverse bias is applied to the junction gate 98, the depletion layer from the p-type region 88 reaches the insulating gate 87 close to the p-type region 88. Then, a part of the holes in the inversion layer at the interface of the insulating film flows to the p-type region 88, and the potential at the interface of the insulating film is affected by the potential of the junction gate 98. As a result, the depletion region of the channel region expands, the conductive path in the channel region narrows, and the main current decreases.

According to the above documents, the main advantages of this device structure are that, when used as a four-terminal device, (1) low on-resistance, (2) high transconductance due to a junction gate, and (3) blocking. High gain, (4) fast switching speed, (5) operation as a three-terminal element, and the like.

However, this device has the following limitations.

First, this element structure is not suitable for increasing the breakdown voltage. As mentioned earlier, the reason the on-resistance of the device structure low, the insulated gate is in contact with both of the substrate in the source region and the n ⁺ -type n ⁺ -type, along both the gate insulating film formation The purpose is to communicate with the accumulation layer. The design withstand voltage of the device in the literature was 60 V. However, if this structure is to be extended to a device with a higher withstand voltage, the insulating gate becomes n.
⁺ This structure in contact with the drain region becomes impossible.

Next, this element is essentially a four-terminal element, and the driving method is inevitably complicated. Of course, as described above, the junction gate and the MOS gate can be connected and used as a three-terminal element. However, as can be seen by comparing FIGS. 19 and 20, in the three-terminal mode, the low on-resistance, which is an advantage, is reduced. I can't get it.

Further, this element has a normally-on characteristic, and a main current flows when no control signal is given. Therefore, in a device using this element, care must be taken to ensure safety, such as by providing a separate current interrupt device.

Next, as a second conventional example, the one disclosed in a patent publication (Japanese Patent Laid-Open No. 57-172765, "Electrostatic induction thyristor") will be introduced.

FIG. 21 is a cross-sectional view of the device with reference to the above publication. FIG. 21 illustrates three units of the structure described in the above-mentioned publication to facilitate understanding that this structure is a device to which a U-shaped insulated gate is applied.

First, the structure will be described. In the figure, reference numeral 61 indicates p
⁺ Type anode region, 62 is n ⁻ type base region, 63 is n
^{A +} cathode region 68 is ap ⁺ gate region.
Reference numeral 64 denotes an insulating film, and the n ⁻ -type base region 62, n ⁺
The cathode region 63 is in contact with the p ⁺ gate region 68. Reference numeral 71 denotes an anode electrode, and 73 denotes a cathode electrode. The p ⁺ -type anode region 61 and the n ⁺ -type cathode region 63 respectively.
Ohmic contact with A gate electrode 65 is in ohmic contact with the p ⁺ -type gate region 68 and also in contact with the insulating film 64. That is, this element structure is such that "an insulating gate is formed in a trench dug from the surface, and a gate electrode 6 is formed at the bottom of the trench.
5 is connected to the p ⁺ -type gate region 68 ”. Further, in the n ⁻ -type base region 62,
A region sandwiched between adjacent insulating gates is referred to as a “channel region”.

Next, the operation will be described. The cathode electrode 73 is grounded (to 0 V), and a positive potential is applied to the anode electrode 71. The off state of the element is maintained by applying a negative potential to the gate electrode 65 and forming a depletion layer in the channel region in front of the cathode region 63. That is, similarly to the first conventional example, this element is a normally-on element.

To turn the element on, a positive potential is applied to the gate electrode 65. Then, the depletion layer in the base region disappears and the current path opens, and an accumulation layer of electrons is instantaneously formed at the interface of the insulated gate, lowering the potential in front of the cathode region and promoting the turn-on of the device. . To obtain this effect, it is desirable that the distance between the insulated gate and the main current path be within the diffusion length of the carriers. In addition, since the storage layer has a high conductivity, there is an advantage that a gate current flows quickly, and the turn-on time is shorter than that of an electrostatic induction thyristor without this mechanism.

Once turned on, the on state is maintained even if the gate potential is released. The turn-off is achieved by applying a negative potential to the gate electrode, extracting minority carriers in the base region 62, and forming a depletion layer in the base region again.

The advantages of this device are that an ordinary static induction thyristor is provided with an insulating gate in conjunction with a junction gate. On time is shortened,
(2) At the time of turn-off, a depletion layer near the insulating film is formed to easily pinch off the current, so that the turn-off time is shortened.

However, the above element structure has the following difficult points. First, a normally-on type device. Secondly, since it is basically a thyristor, the element cannot be turned off unless a shut-off signal is actively given to the control electrode. Third, in the structure of FIG. 21, a gate insulating film must be formed in the trench, and a contact hole with the p ⁺ -type gate region must be formed at the bottom. In order to allow the device to have a sufficient blocking gain, the depth of the groove forming the insulated gate is required to be several μm. However, even if the width of the groove is much larger than that shown in FIG. It is difficult to form a contact hole at the bottom of such irregularities.
In particular, when trying to reduce the size of a pattern in order to increase the current capacity, it becomes difficult with a trivial photo-etching technique.

[0023]

As described above, in the first conventional example, an extremely low on-resistance can be obtained, but there is a problem that the capacity and the breakdown voltage of the chip cannot be increased. In the second conventional example, there is no problem in increasing the withstand voltage, but the structure is not suitable for miniaturization for increasing the capacity, and there is a limit in reducing the on-resistance due to the structure of the element. There is.

The present invention has been made in view of such conventional problems, and is of a normally-off type, has excellent controllability, has low on-resistance, can improve switching speed, and has high reliability in operation. It is an object of the present invention to provide a semiconductor device having improved structure and having a structure suitable for miniaturization and high breakdown voltage.

[0025]

In order to solve the above-mentioned problems, the invention according to claim 1 is directed to a plurality of one-type semiconductor substrates which are drain regions and are arranged in parallel with each other facing one main surface of the semiconductor substrate. A first groove, and a substantially longitudinal direction of the plurality of first grooves ;
In a central portion, a second groove arranged orthogonal to each of the first grooves
And a source region of one conductivity type in a region facing the main surface and surrounded by the first groove and the second groove on three sides. Has a fixed potential insulating region that is insulated from the drain region by an insulating film and is kept at the same potential as the source region inside the trench, and the fixed potential insulating electrode is adjacent via the insulating film. The first groove is made of a conductive material having a property of forming a depletion region in the drain region.
Arranged, not having contact with the source region, having an opposite conductivity type injector region in contact with the drain region and each of the insulating films, a part of the drain region adjacent to the source region, In a state where the potential of the injector region is kept at the same potential as the potential of the source region between the fixed potential insulating electrodes, the potential barrier formed by the depletion region electrically connects the source region and the drain region. It is a gist of the present invention to have a channel region which is in a state of being cut off.

According to a second aspect of the present invention, in the semiconductor device of the first aspect, the channel length, that is, the distance from the interface between the channel region and the source region to the bottom of the groove along the side wall of the groove. , The thickness of the channel, that is, the distance between the side walls of the first groove facing each other in the channel region is twice or more.

According to a third aspect of the present invention, in the semiconductor device according to the first or second aspect, the source region has a thickness from the side surface of the second groove along the first groove or the channel thickness. The point is that it exists up to the following positions.

The invention according to claim 4 is the invention according to claims 1 and 2.
In the semiconductor device according to the third aspect, the semiconductor substrate may include an anode region of an opposite conductivity type on another main surface of the semiconductor substrate opposite to the one main surface where the source region exists.

[0029]

According to the first aspect of the present invention, a depletion layer is formed in the channel region around the fixed potential insulating electrode fixed at the source potential due to a work function difference from the material of the fixed potential insulating electrode. The channel region is depleted, and the source region and the drain region are electrically disconnected. Further, the fixed potential insulating electrode has a structure in which the channel is not opened by the drain electric field even when the drain potential increases. That is, the element structure is in the cutoff state from the beginning. However, minority carriers excited from the depletion layer in the drain region accumulate at the interface of the insulating film, and if left alone, the depletion layer in the channel region recedes and the main current leaks. Is in ohmic contact with the external electrode (hereinafter referred to as “injection electrode”) for applying an arbitrary potential to the injector region, so that when the injection electrode is grounded, the As the minority carriers at the interface flow out to the injection electrode, the potential at the insulating film interface does not rise,
The element keeps the cutoff state. On the other hand, when a positive potential is applied to the injection electrode, conversely, minority carriers flow into the interface of the insulating film to increase the potential at the interface, the depletion layer recedes, a neutral region appears at the center of the channel, and current flows. Further, when the injection potential becomes equal to or higher than a predetermined value, the pn junction formed by the injector region and the channel region is forward-biased, and minority carriers are injected into the channel region and the drain region to conduct conductivity modulation. Will flow. At this time, the interface of the insulating film functions as a conductive path to select a minority carrier current in the entire channel region. Furthermore, the first
Since the distance between the injector region and the source region is widened by setting the source region small in a region surrounded by the three grooves of the second groove and the second groove, holes injected from the injector region into the source region are reduced. , _HFE is improved. Then, in order to turn off, the potential of the injection electrode is set to the ground or the opposite potential. At this time, a depletion layer is formed in the channel region, that is, in the drain region near the source region due to a work function difference from the material of the fixed insulating region, whereby the channel region is depleted and the source region and the drain region are electrically connected. Is shut off. At this time, the depletion of the channel region is performed quickly by surrounding the three sides on the front surface of the source region with the fixed insulating region. In the present invention, the element structure is fine, and the potential of the channel region is directly linked to the potential of the injection electrode. Further, since the source region is small, holes are injected from the injector region to the source region. since the rate is reduced that, it is possible than single bipolar transistor obtaining large h _FE. Further, the on-resistance is low, and a large amount of main current can be controlled with a small control current. Furthermore, since the source region, that is, the channel region is surrounded from three sides by the fixed potential insulating electrode, the channel is depleted at the time of turn-off, and the main current is cut off quickly. In addition, since the fixed potential insulating electrodes are connected to one, the reliability of operation can be increased.

According to the second aspect of the present invention, the effect of the potential drop at the source end of the channel region is limited to about 1 to 1.5 times the channel thickness in the channel length direction. On the other hand, in the portion of the channel region facing the drain region, the effect that the potential of the channel region is reduced by the drain electric field is substantially the same as described above, and stops at 1 to 1.5 times the channel thickness in the channel direction. Therefore, by setting the channel length to be at least twice the channel thickness or more, normally
An off structure is realized.

According to the third aspect of the present invention, when the semiconductor device is turned off, the potential of the injection electrode is set to the ground or the opposite potential. At this time, before the depletion layers extending from the fixed potential insulating electrodes facing each other in parallel overlap each other, depletion is quickly realized in the portion of the channel region surrounded by the fixed potential insulating electrodes from three sides. Therefore, the source region is formed in a region surrounded by these three sides, and its size is determined by the channel thickness,
Or, by forming it less than that, quick turn-off is realized.

According to the fourth aspect of the present invention, by forming an anode region of the opposite conductivity type on the other main surface of the semiconductor substrate, an opposite conductivity type region having the same conductivity type as the anode region is formed in the region where the main current flows. With one less structure, it is possible to realize a semiconductor device that operates in the same manner as a normal electrostatic induction thyristor.

[0033]

The present invention will be described below in detail with reference to examples.

FIGS. 1 to 4 show a first embodiment of the present invention. 1 is a perspective view for explaining the basic structure of the device, FIG. 2 is a cross-sectional view showing the same part as the front surface of FIG. 1, and FIG. 3 is a surface view of the device. 2 except for the electrode (metal film). That is, FIG.
Indicates a section cut along a line AA ′ in FIG. 2 and perpendicular to the paper surface. Conversely, FIG. 2 is a cross-sectional view taken along a plane perpendicular to the plane of FIG. 3 through line AA ′. FIG. 4 is a cross-sectional view taken along a plane perpendicular to the plane of FIG. 3 through a line BB ′ in FIG. 3, and is cut along a line BB ′ in FIG. FIG. In this embodiment, the semiconductor will be described as silicon.

Next, the structure of the element will be described. First, Figure 1
In FIG. 4, reference numeral 1 denotes an n ⁺ -type substrate region as a substrate, 2 denotes an n-type drain region, and 3 denotes an n ⁺ -type source region. Reference numeral 4 denotes a MOS-type electrode, which is made of a high-concentration p-type polycrystalline semiconductor, has an ohmic contact with a source electrode described later, and has a fixed potential. Also, 5 is M
This is an insulating film that insulates the OS type electrode 4 from the drain region 2. These 4 and 5 are collectively referred to as “fixed insulated electrodes” 6. The fixed insulating electrode 6 is formed in a groove whose side wall is dug vertically from the element surface. A region of the n-type drain region 2 sandwiched between the fixed insulating electrodes 6 is referred to as a “channel region” 7. This channel region 7
Since the MOS type electrode 4 adjacent via the insulating film 5 is a high concentration p-type semiconductor, a potential barrier for conduction electrons is formed in the channel region by the depletion layer formed by the work function difference. The source region 3 and the drain region 2 are electrically disconnected from the beginning. Reference numeral 11 denotes a drain electrode, which is in ohmic contact with the n ⁺ type substrate region 1. Reference numeral 13 denotes a source electrode, which is in ohmic contact with the source region 3 and the MOS electrode 4. That is, the potential of the MOS electrode 4 is fixed to the potential of the source electrode 13. In the figure, H is called a channel thickness and L is called a channel length.

Next, in FIG. 3, in this embodiment, the fixed insulating electrodes 6 are connected and integrated by grooves (second grooves) of the same shape crossing the plurality of stripe-shaped grooves. . The n ⁺ -type source region 3 is formed in a concave portion that is in contact with the connected source electrode 13 on the semiconductor surface and is surrounded by the fixed insulating electrode from three sides.
The convex portion of the fixed insulating electrode 6 is in contact with the p ⁺ type region (injector region) 8. Thus, the channel region 7 surrounded by the fixed insulating electrode 6 and the p ⁺ type region 8 forms one unit cell, and FIG. 3 shows eight units of the cell. In FIG. 4, reference numeral 18 denotes an electrode in ohmic contact with the p ⁺ -type region 8 and supplies minority carriers to the drain region 2. This is called an "injection electrode". The broken line in the figure indicates the presence of the fixed insulating electrode 6.
Reference numeral 15 denotes an interlayer insulating film.

In the drawings of the present application, the corners of the insulating film of the fixed insulating electrode in the cross-sectional view and the corners of the insulating film in the surface view are depicted as being angular, but these are schematic diagrams and actually It may be rounded. That is,
Making these corners round in order to suppress the electric field concentration is widely adopted.

Next, the operation will be described.

In this device, the source electrode 13 is grounded (0
V), a positive potential is applied to the drain electrode 11.

First, the cutoff state will be described.

When the injection electrode 18 is in the ground state, the device is in the cutoff state. As described above, since the MOS-type electrode 4 is made of a high-concentration p-type semiconductor and is fixed at the source electrode potential, a depletion layer is formed around the fixed insulating electrode 6, The channel region 7 is depleted so that the source region 3 and the drain region 2 are electrically isolated.

Normally, in such a structure like a MOS diode, even if a voltage is applied to expand the depletion layer, carriers generated in the depletion layer in the drain region accumulate at the interface of the insulating film to form an inversion layer, and depletion occurs. The potential at the interface of the insulating film rises without the layer spreading. However, in this structure, the insulating film 5
Since it is in contact with the grounded p ⁺ type region 8, carriers generated in the depletion layer reach the interface of the insulating film 5, but are immediately removed from the element through the p ⁺ type region 8. That is, the potential at the interface of the insulating film is fixed without increasing, and the depletion layer spreads according to the drain potential.

There are two conditions that the structure of the channel must satisfy in order for this device to have a normally-off structure. First, there is a relationship between the channel thickness and the impurity concentration. FIG. 5 is a diagram showing a calculated potential distribution of the channel region 7 along a line CC ′ near the center of the channel region 7 in FIG. The vertical axis in FIG. 5 is the potential at the center of the energy band based on the Fermi level. Hereinafter, the “potential at the center of the energy band based on the Fermi level” is simply referred to as “potential”. Here, the calculation was performed on the assumption that the build-in potential of the MOS electrode 4 was 0.6 eV, the insulating film was silicon dioxide, and the thickness was 100 nm. The broken lines at both ends are auxiliary lines indicating the potential distribution in the insulating film.
The dashed line at the center indicates the potential position of the semiconductor in the channel region 7 in the neutral state.

In FIG. 5, when the injection electrode potential V _j is 0 V, the potential of the entire channel is positive.
No conduction electrons exist in the channel region 7. To satisfy this condition, the impurity concentration N _D , the channel thickness H, and the insulating film thickness t _ox of the channel region 7 must satisfy the following expressions.

First, assuming that the build-in potential of the MOS type electrode 4 is P and the potential of the interface between the channel region 7 and the semiconductor insulating film is Q, the electric field strength E _ox in the insulating film is constant. It is shown by the expression 1).

[0046]

(Equation 1) On the other hand, since the entire region of the channel region 7 is depleted in the cutoff state, the potential distribution V _ch can be approximately approximated by a quadratic curve as shown in the following equation (2).

[0047]

(Equation 2) Here, in the above equation (2), q is a unit charge, ε _si
Is the dielectric constant of the semiconductor in the channel region, and x is the C-
The distance R measured in the direction of the insulating film from the center of the C ′ section, that is, the center of the horizontal axis in FIG. 5, is the lowest point of the potential.

The potential Q at the interface between the channel region 7 and the insulating film is expressed by the following equation (3).

[0049]

(Equation 3) The electric field E _{si at} this point is expressed by the following (Equation 4).

[0050]

(Equation 4) Furthermore, since the electric flux must be the same at the interface, the following equation (5) must be satisfied.

Ε _ox E _ox = ε _si E _si (Equation 5) The build-in potential of the MOS electrode 4 is 0.6 e
V, the minimum value R of the potential of the channel region 7 is set to 0.3 eV so that the channel is not easily opened due to noise of the control signal or the like, and satisfying the above-mentioned equations (1) to (5). FIG. 6 shows a relationship between the impurity concentration N _D of the channel region 7, the insulating film thickness t _ox , and the channel thickness H. FIG. 6 shows curves when the insulating film thickness t _ox is 50 nm and when the insulating film thickness is 100 nm. The lower left region of each line is a condition to be satisfied by this device. For example,
In either case of the above two insulating film thicknesses, the impurity concentration N _D
= 1 × 10 ¹⁴ / cm ³ and channel thickness H = 2 μm are suitable conditions.

Next, as a second condition for the device to have normally-off characteristics, there is a condition that the channel thickness H and the channel length L must be satisfied. FIG.
It is the result of numerical calculation of the potential distribution in the channel region. The base plane is a view of the central part of the channel from the source interface side of the channel region 7 in FIG. 2, and the vertical axis indicates the potential. Although FIG. 7 shows equipotential lines, it can be seen that the potential of the channel region is reduced due to the influence of the source region (not shown) in the foreground. The side surface is the interface with the insulating film, and the back surface in the figure is the line CC ′ in FIG.
And the potential distribution there is not affected by the source region, and is equivalent to the curve of V _j = 0 in FIG. As a result of performing similar numerical calculations with several settings satisfying the conditions of FIG.
It has been found that the effect of the potential drop at the source end portion of FIG. 4A is limited to about 1 to 1.5 times the channel thickness in the channel length direction. On the other hand, in the portion of the channel region 7 facing the drain region, the effect that the channel potential is lowered by the drain electric field is almost the same. The condition that the channel does not open due to the effect is (channel length L) /
The ratio of (channel thickness H) is 2 to 3 or more.

For example, if the impurity concentration of the channel is 1 × 10
¹⁴ / cm ³ , that is, when the specific resistance is about 40 Ω-cm and the insulating film thickness is 100 nm or less, the channel thickness H is 2
In the case of μm, a channel length of 6 μm is sufficient.

Next, a mechanism for switching from the cutoff state to the conduction state will be described.

In FIG. 5, the injection electrode potential V _j =
When the voltage is 0 V, the potential of the entire region of the CC ′ section of the channel region 7 is positive, and the channel region 7 is in a cutoff state. The injection electrode potential V _j becomes to 0.3V rises, the central portion of the channel region 7 can negative region of potential, a state where the conduction electrons can flow. The reason why the potential of the channel region 7 Increasing the potential of the injector electrode 18 is reduced so that, by the potential of the injector electrode 18 and ohmic contact p ⁺ -type region 8 is increased, p ⁺
Minority carriers are supplied to the interface of the insulating film 5 where the mold region 8 is in contact, and this shields the electric field from the MOS type electrode 4 of the fixed insulating electrode 6 to the channel region 7, so that the depletion layer of the channel region 7 recedes. To do that.

Further, when the injection potential becomes 0.5 eV or more, the potential becomes lower than the one-dot chain line, and the band shape in the channel region 7 becomes flat. This is because the junction between the n-type drain region 2 and the p ⁺ -type region 8 is in a forward bias state, and the entire drain region is in a high level implantation state. At this time, holes are directly injected from the p ⁺ -type region 8 and also supplied to the drain region 2 from the interface of the insulating film 5. That is, under this condition, the interface of the insulating film functions as a conductive path having high conductivity to carry hole current. At this stage, it is easier to understand the control of the drain current by focusing on the injection current than on the injection electrode potential. That is, the conductivity of the drain region 2 is controlled by the amount of hole current injected into the drain region 2, and the amount of drain current is controlled.

Next, a mechanism for changing from the conduction state to the interruption state will be described.

In order to turn off, the injection electrode 18
Is grounded (to 0 V) or negative potential. Then, a large amount of holes existing in the drain region 2 and the channel region 7 disappear or are eliminated outside the device through the p ⁺ -type region 8, and the channel region is filled with the depletion layer again. This mechanism is similar to, for example, the turn-off mechanism of an electrostatic induction thyristor. At this time, since the channel region 7 has a structure surrounded by the fixed insulating region from three sides, the depletion layer extends from the three sides to cut off the channel. In addition, a channel region 7 effective for the device
Is surrounded by the fixed insulating electrodes from three sides, so that the interruption of the current is promoted. FIG. 8 is a cross-sectional view taken along a plane including a line CC ′ in FIG. 2, showing a state in which the end of the depletion layer moves as the injector potential approaches 0 V from the positive potential, and the channel closes. ing. The curve in the figure shows the edge of the depletion layer obtained by the numerical calculation, and the conditions of the numerical calculation were the same as those in FIG. 5 and FIG. However, in this figure, the end of the depletion layer is a line that is half the density of majority carriers in the neutral state of the channel region 7. Referring to this figure, before the depletion layers extending from the opposed fixed insulating electrodes overlap each other, 3
It can be seen that depletion is realized in the channel region 7 surrounded by the other. Therefore, by forming the source region 3 in this region and forming the size thereof to be equal to or less than the channel thickness H, it is expected that rapid current interruption can be realized.

The current-voltage characteristic of this device has a pentode characteristic almost similar to that of a single bipolar transistor. As for the drain current, if there is a current from the injection electrode, a sufficient current flows even at a low drain potential. When the drain potential increases, the current is pinched off by the depletion layer extending from the fixed insulating electrode to the drain region, and the current value is saturated.

Since the drain current is determined by the injected hole current, h _FE (direct current gain) similar to that of the bipolar transistor can be defined. In this element, the element structure is fine, since the potential of the channel region is a mechanism that works with direct injection electrode potential can than single bipolar transistor expect large h _FE. Further, as described above, by setting small, the proportion of the holes injected from the injector region reaches the source region is reduced, further it can be expected that the h _FE is improved.

Next, FIGS. 9 to 14 are perspective views showing an example of the manufacturing method of the first embodiment shown in FIGS.

First, as shown in FIG.
^An n-type drain region 2 is formed on the surface of a ⁺ -type substrate by epitaxial growth. Further formed with n ⁺ -type region serving as a source region 3 on the surface thereof, a p ⁺ -type region serving as injection region 8.

Next, as shown in FIG.
Then, a pattern for forming a groove for the fixed insulating electrode is formed. This is etched by anisotropic dry etching to dig a groove whose side wall is almost vertical as shown in FIG. The depth of the groove is two to three times or more than the interval between the grooves.

The cross-sectional shape of the groove, that is, the shape of the fixed insulating electrode is shown in FIG. 2 or FIG. 11 as an example of a U-shape in which the side wall is substantially vertical.
As long as the condition of the channel for turning off is satisfied, the sectional shape may be a barrel shape, a wedge shape, a diamond shape, or the like. Also, the groove may be dug obliquely, not vertically, and if possible, the fixed insulating electrode may be completely buried in the substrate.

Further, as long as the surface pattern also satisfies the channel cutoff condition, the thickness of the channel does not necessarily have to be uniform everywhere, and the width of the groove does not need to be uniform.

Next, as shown in FIG. 12, the insulating film 5 is formed by oxidizing the inner wall of the groove, and the high-concentration p
Deposit polysilicon.

Next, as shown in FIG. 13, etching is performed so that p-type polysilicon remains only in the trench.

Next, as shown in FIG. 14, the mask material 100 is removed, and an interlayer insulating film and an electrode are formed to obtain the structure shown in FIGS.

The fixed insulating electrode 6 may be formed of the same metal as the source electrode 13 if the condition that the channel is not opened by the drain electric field when the injection electrode potential is in the cutoff state is satisfied.

FIG. 15 is a sectional view showing a second embodiment of the present invention.

In this embodiment, a p ⁺ type region 9 is used as a substrate instead of an n ⁺ type in a perspective view corresponding to FIG.
This is an electrostatic induction thyristor type device. The operation is similar to that of a normal electrostatic induction thyristor. The source electrode is grounded, and a positive potential is applied to the drain electrode 11. The cutoff state is maintained by grounding the MOS electrode 4. Turn-on can be achieved by applying a positive potential to the injection electrode. Once turned on, the on-state is maintained even when the injector signal is released. The turn-off may be performed by applying a negative potential to the MOS-type electrode 4 to eliminate excess minority carriers in the channel region. By using this structure, a similar operation can be obtained with a structure in which there is one less p region in the region where the main current flows as compared with a normal thyristor.

Next, differences between the above embodiments and the conventional example will be described together.

First, each embodiment and the first conventional example (FIGS.
19), in the first conventional example, the potential of the insulating electrode (MOS gate 95) is variable. By making the potential of the insulating electrode positive, an electron accumulation layer is formed at the interface of the insulating film. Insulating electrodes are used as control electrodes to achieve low channel resistance. On the other hand, in each embodiment, the insulating electrode (fixed insulating electrode 6) is fixed at the source potential, and is not basically a control electrode. This is crucially different.

In the first conventional example, the device is a normally-on type device. In order to cut off the main current, a negative potential must be positively applied to the junction gate 98 and the MOS gate 95. . However, the apparatus of each embodiment is a normally-off type device, and cannot be otherwise. Therefore, in order to maintain the off state, the injection control electrode 18 may have the same potential as the source region 3, that is, the ground potential.

In each embodiment, it is essential that the injector region 8 is in contact with the interface of the insulating film 5, whereby the potential of the interface of the insulating film 5 is positively controlled by the potential of the injection control electrode 18. To control. On the other hand, the junction gate 98 in the first conventional example does not contribute to the ON state of the device at all. As far as described in the document of the first conventional example, the p-type region 88 is separated from the insulating film 84, so that even if the potential of the junction gate 98 is made positive, the state of the interface of the insulating film is thereby controlled. It is not possible.

The ON state of the device of each embodiment is as follows.
The channel is opened by supplying minority carriers from the injector region and modulates the conductivity of the drain region as well as the channel region. On the other hand, in the first conventional example, even if a positive potential is applied to the junction gate 98,
Even if minority carriers are injected, the conductivity of the channel region 82 containing impurities is hardly affected because the main current of the monopolar flows at a low on-resistance. Thus, while the first conventional example is a monopolar device, each embodiment is clearly different in that it is a bipolar device.

Next, differences from the second conventional example (FIG. 21) will be described.

In the second conventional example, the p-type region (p ⁺ gate region 68) serving as a control electrode is an insulating electrode (gate electrode 6).
It is located at the bottom of the groove where 5) is located, and at the bottom, is in ohmic contact with the insulating electrode. The second conventional example is essentially different from the first embodiment in that the potential of the insulating electrode is variable, as in the first conventional example. Further, the position of the p-type region is different, and this is also different in that it is linked to the potential of the insulating electrode. Of course, in addition to surface structure, in the second conventional example from the p ⁺ -type anode region 61 n ^- high resistance by minority carriers are injected into the mold base region 62 n ^-
While the conductivity of the mold base region 62 is modulated to realize a low on-resistance, in each embodiment, a small number of p-type regions 8 different from the main current path on the surface on the cathode side (source side) are provided. The point that the carrier is injected to modulate the conductivity of the high-resistance drain region 1 is also clearly different.

As described above, in the second conventional example,
Since the main current path has a pn junction, there is a characteristic that a satisfactory current does not flow unless the voltage of relaxation of the main current end becomes approximately 0.7 V or more. However, since the device shown in the first embodiment does not have such a pn junction, a sufficient current can flow even at a lower voltage.

[0080]

As described above, according to the first aspect of the present invention, the plurality of first trenches arranged in parallel with each other facing one main surface of the one conductivity type semiconductor substrate which is the drain region. And a second groove that intersects the plurality of first grooves. One conductivity type is provided in a region facing the main surface and surrounded by the first groove and the second groove on three sides. Having a source region of
A fixed potential insulating electrode insulated from the drain region by an insulating film and kept at the same potential as the source region inside the groove and the second groove, wherein the fixed potential insulating electrode is Made of a conductive material having a property of forming a depletion region in the drain region adjacent through the
The fixed potential insulating electrode is a part of the drain region adjacent to the source region, the injector region having an opposite conductivity type injector region not in contact with the source region and in contact with the drain region and each of the insulating films. Between the source region and the drain region by a potential barrier formed by the depletion region when the potential of the injector region is maintained at the same potential as the potential of the source region. Because it has a configuration with a channel region, it has no parasitic elements and is a current control type three-terminal device that can control a large amount of main current with a small control current injected from the injector region, and has excellent controllability. Since the conductivity of the drain region is modulated by the injected minority carriers, the on-resistance can be reduced, and the fixed voltage can be reduced. Since the source region, i.e., the channel region, is surrounded from three sides by the insulating electrode, the depletion of the channel at the time of turn-off can be accelerated to improve the switching speed, and the fixed potential insulating electrode is connected to one. Therefore, the reliability of operation can be improved, and further miniaturization and high breakdown voltage can be realized.

According to the second aspect of the present invention, the channel length, that is, the distance from the interface between the channel region and the source region to the bottom of the groove along the side wall of the groove is determined by:
Since the thickness of the channel, that is, the distance between the side walls of the first groove facing each other in the channel region, is twice or more, in addition to the effect of the invention described in claim 1, a normally-off structure is more reliably realized. can do.

According to the third aspect of the present invention, the source region exists from the side surface of the second groove to the position at or below the channel thickness along the first groove. In addition to the effect of the first aspect of the present invention, the source region is formed small in a region surrounded from three sides by the fixed potential insulating electrode, so that more rapid turn-off can be realized. Furthermore, by the source region is reduced, since the rate at which holes are injected from the injector region to the source region is reduced, h _FE
Is improved.

According to the fourth aspect of the present invention, since the semiconductor substrate has an anode region of the opposite conductivity type on the other main surface opposite to the one main surface where the source region exists, the region where the main current flows is provided. In this case, a semiconductor device that operates in the same manner as a normal static induction thyristor can be realized with a structure in which there is one less conductive region of the same conductivity type as the anode region.

[Brief description of the drawings]

FIG. 1 is a perspective view of a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of the first embodiment of the present invention.

FIG. 3 is a sectional view showing a surface structure according to the first embodiment of the present invention.

FIG. 4 is a sectional view seen from another angle of the first embodiment of the present invention.

FIG. 5 is a potential distribution diagram of a channel region in the first embodiment.

FIG. 6 is a diagram showing a relationship among an impurity concentration of a channel region, an insulating film thickness, and a channel thickness in the first embodiment.

FIG. 7 is a diagram three-dimensionally showing a potential distribution of a channel region in the first embodiment.

FIG. 8 is a cross-sectional view showing an injector potential and a position of a depletion layer end in a channel region in the first embodiment.

FIG. 9 is a cross-sectional view showing a part of the manufacturing process according to the first embodiment of the present invention.

FIG. 10 is a sectional view showing another part of the manufacturing process according to the first embodiment of the present invention.

FIG. 11 is a sectional view showing another part of the manufacturing process according to the first embodiment of the present invention.

FIG. 12 is a cross-sectional view showing another part of the manufacturing process according to the first embodiment of the present invention.

FIG. 13 is a cross-sectional view showing another part of the manufacturing process according to the first embodiment of the present invention.

FIG. 14 is a sectional view showing another part of the manufacturing process of the first embodiment of the present invention.

FIG. 15 is a sectional view of a second embodiment of the present invention.

FIG. 16 is a plan view of a first conventional example.

FIG. 17 is a sectional view of a first conventional example.

FIG. 18 is another sectional view of the first conventional example.

FIG. 19 is a current-voltage characteristic diagram when the first conventional example is operated as a three-terminal element.

FIG. 20 is a current-voltage characteristic diagram when the first conventional example is operated as a four-terminal element.

FIG. 21 is a sectional view of a second conventional example.

[Explanation of symbols]

Reference Signs List 1 substrate region 2 drain region 3 source region 4 MOS type electrode 5 insulating film 6 fixed insulating electrode 7 channel region 8 p ⁺ type region (injector region) 11 drain electrode 13 source electrode 18 injection electrode

────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-6-252408 (JP, A) JP-A-7-335868 (JP, A) JP-A-7-202182 (JP, A) JP-A-8-208 46192 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 29/78 H01L 29/80

Claims (4)

(57) [Claims] 2. A semiconductor device comprising: a plurality of first conductive members arranged in parallel with each other and facing one main surface of a semiconductor substrate of one conductivity type serving as a drain region;
And grooves at substantially longitudinal central portion of the plurality of first grooves, each of said first
And a second groove disposed orthogonal to the groove of the first conductivity type. A source region of one conductivity type is formed in a region facing the main surface and surrounded by the first groove and the second groove on three sides. A fixed potential insulating region insulated from the drain region by an insulating film and kept at the same potential as the source region inside the first groove and the second groove; The potential insulating electrode is made of a conductive material having a property of forming a depletion region in the drain region adjacent via the insulating film, and is disposed at both ends in the longitudinal direction of the first groove, respectively.
A part of the drain region adjacent to the source region, the injector region having an opposite conductivity type injector region not in contact with the source region and in contact with the drain region and each of the insulating films; In a state where the potential of the injector region is kept at the same potential as the potential of the source region between the electrodes, the potential barrier formed by the depletion region electrically disconnects the source region and the drain region. A semiconductor device having a channel region described as follows. 2. The channel length, ie, the distance from the interface between the channel region and the source region to the bottom of the groove along the side wall of the groove, is the channel thickness, ie, the first groove facing the channel region. 2. The semiconductor device according to claim 1, wherein the distance between the side walls is twice or more. 3. The semiconductor device according to claim 1, wherein the source region extends from a side surface of the second groove to a position at or below the channel thickness along the first groove. Semiconductor device. 4. The semiconductor device according to claim 1, wherein the semiconductor substrate has an anode region of an opposite conductivity type on another main surface opposite to the one main surface where the source region exists.