CN114582863A - Trench gate power device - Google Patents

Trench gate power device Download PDF

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CN114582863A
CN114582863A CN202011379469.2A CN202011379469A CN114582863A CN 114582863 A CN114582863 A CN 114582863A CN 202011379469 A CN202011379469 A CN 202011379469A CN 114582863 A CN114582863 A CN 114582863A
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conductive material
gate
hole
region
trench
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曾大杰
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Nantong Shangyangtong Integrated Circuit Co ltd
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Nantong Shangyangtong Integrated Circuit Co ltd
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Abstract

The invention discloses a trench gate power device.A plurality of gate trenches are formed on a semiconductor substrate, and the gate trenches and mesa regions are alternately arranged; a first conductive material layer is formed in the grid groove, a first through hole which is in contact with the source region is arranged at the top of the mesa region, the first conductive material layer on the first side of the first through hole is connected to the grid, and the top of the first conductive material layer on the second side of the first through hole is connected to the source electrode; the first through hole and the grid groove on the first side have a first distance and the grid groove on the second side have a second distance, and the second distance is smaller than the first distance. The invention combines the electrode connection arrangement of the first conductive material layer of the trench gate and the arrangement of the through hole at the top of the source region of the mesa region, so that the minimum value which can be reached by the width of the mesa region can be reduced, the step formed by the gate trench and the mesa region can be reduced, and the performance of the device can be improved.

Description

Trench gate power device
Technical Field
The present invention relates to semiconductor integrated circuits, and more particularly, to a trench gate power device.
Background
Power devices are mainly classified into two categories, one is a unipolar device represented by a MOSFET, and the unipolar device is characterized by high switching speed. Another type is a bipolar device represented by an IGBT, which is characterized in that when the device is turned on, the electron and hole concentrations in the drift region are greatly increased due to the conductance modulation effect. When the device is turned off, the excess carriers need to be pumped away, so the switching speed is slow.
The current density of power devices is continuously mentioned in the development trend of the power devices, so that the area of the power devices is smaller, the corresponding capacitance is lower and the switching speed is higher under the condition of the same current capacity.
The power device is generally formed by connecting a plurality of device unit structures in parallel, and the most important means for improving the power density is to reduce the step (Pitch) of the device, wherein the step of the device is the width of the device unit structure. For a power device with a trench gate structure, the step of the device is the sum of the width and the interval of the gate trenches.
The shielding grid groove MOSFET is a groove grid MOSFET with active polysilicon formed in the grid groove, and the active polysilicon is used as a source electrode field plate to shield the polysilicon grid. As shown in fig. 1, the structure of a conventional SGT MOSFET is schematically illustrated, in which a plurality of gate trenches are formed on a semiconductor substrate 1, the semiconductor substrate 1 between the gate trenches forms mesa regions, and the gate trenches and the mesa regions are alternately arranged, and one gate trench and an adjacent mesa region form a unit structure. In fig. 1, the formation region of the gate Trench is shown as a double-arrow line corresponding to a mark 101, and the gate Trench is also denoted by Trench; the Mesa region is formed as indicated by the double arrow line corresponding to the mark 102, and the Mesa region is also indicated by Mesa.
A gate conductive material layer, such as a polysilicon gate 6, is formed in the gate trench, with a gate dielectric layer 5 interposed between the gate conductive material layer 6 and the sides of the gate trench.
A channel region 7 is formed on the surface of the semiconductor substrate 1 of each mesa region, and each gate trench passes through the channel region 7;
a source region 8 is formed at the surface of the channel region 7.
An interlayer film 11 covers the mesa region where the active region 8 is formed and the surface of the gate trench region where the gate conductive material layer 6 is formed.
A through hole (CT) is formed in the interlayer film 11 to pass through the interlayer film 11.
A gate electrode and a source electrode patterned by the front metal layer 10 are formed on the surface of the interlayer film 11.
The through hole comprises a first through hole 9 arranged at the top of the mesa region, the bottom of the first through hole 9 is contacted with the source region 8, the bottom of the first through hole 9 penetrates through the source region 8 to be contacted with the channel region 7, and the top of the first through hole 9 is connected with the source electrode. As shown in fig. 1, the first through hole 9 is disposed in the center of the mesa region, that is, when layout design is performed, the middle position of the first through hole 9 is aligned with the middle position of the mesa region, distances d102 and d103 between two sides of the first through hole 9 and corresponding gate trenches are equal, and a width of the first through hole 9 is d101, so that the step of the structure shown in fig. 1 can be minimized by the symmetrically disposed structure, that is, both d102 and d103 can be minimum values meeting requirements.
The distances d102 and d103 are limited by the alignment process deviation of the first via 9 and the corresponding gate trench and the distances d102 and d103 are limited by the minimum distance value of the first via 9 and the corresponding gate trench. Typically, a heavily doped contact region of opposite doping type to the channel region 7 is implanted at the bottom of the first via 9, and if the spacing between the first via 9 and the gate trench is too small, the doping of the contact region affects the doping of the channel region 7 and thus the threshold voltage of the device. When the distances d102 and d103 are larger than the minimum distance value, the threshold voltage of the channel region 7 on the side surface of the gate groove on the corresponding side of the first through hole 9 is not influenced; the layout design values of the distances d102 and d103 are greater than or equal to the sum of the minimum distance value and the alignment process deviation of the first through hole 9 and the gate trench on the first side.
The width of the mesa region is the sum of the distances d102 and d103 and the width d101 of the first through hole 9.
A first epitaxial layer 2 is further formed on the semiconductor substrate 1, and the gate trench is formed in the first epitaxial layer 2. The gate dielectric layer 5 comprises an oxide layer.
The drain region is formed on the back surface of the semiconductor substrate 1. Generally, the semiconductor substrate 1 is generally a silicon substrate and is heavily doped, and the drain region is directly composed of the thinned semiconductor substrate 1; or, the drain region is formed by performing back heavy doping and drain injection on the thinned semiconductor substrate 1.
A drift region is formed by the first epitaxial layer 2 on the surface of the semiconductor substrate 1 between the drain region and the channel region 7.
Active conductive material layers such as source polysilicon 4 and shielding dielectric layers 3 are also formed in the gate trenches, and the shielding dielectric layers 3 are isolated between the active conductive material layers 4 and the corresponding inner side surfaces of the gate trenches.
The gate conductive material layer 6 and the source conductive material layer 4 form an upper and lower structure, the gate conductive material layer 6 is positioned on the top of the source conductive material layer 4, and a conductive material interlayer dielectric layer is isolated between the gate conductive material layer 6 and the source conductive material layer 4.
Taking an N-type device as an example, the semiconductor substrate 1 is provided with N-type heavy doping; the first epitaxial layer 2 is doped lightly in an N-type manner, the channel region 7 is doped lightly in a P-type manner, the source region 8 is doped heavily in an N-type manner, and the heavily doped heavily in a P-type manner is formed at the bottom of the first contact hole 9 a.
In fig. 1, the sum of the widths of the gate trench corresponding to the mark 101 and the mesa region corresponding to the mark 102.
In order to reduce the back-diffusion of the semiconductor substrate 1, a substrate of Arsenic (Arsenic) is usually chosen. But the lowest resistivity that can be achieved in the current process is lower than that of the substrate of the inductive, because of the phosphor (phosphor) substrate. Therefore, phosphor substrates are also frequently used in applications where the substrate resistance ratio is relatively high, such as low voltage devices below 40V. The thinner the substrate is, the better the heat dissipation of the device is, and the substrate resistance can be reduced more remarkably.
The biggest difference between the SGT MOSFET and the conventional Trench MOSFET is that a longitudinal source field plate, i.e. source polysilicon 4, is inserted in the lateral direction of the drift region 2.
The shielding dielectric layer 3 realizes the isolation between the source polysilicon 4 and the drift region 2. The shielding dielectric layer 3 needs to withstand the breakdown voltage of the device, which can be approximately
Figure BDA0002808994020000031
An estimation is performed.
Here EcritIs the critical electric field strength of the silicon material, which is related to the width of Mesa. The wider the Mesa, the lower its corresponding critical electric field strength, and the narrower the Mesa. EpsilonsiIs the dielectric constant, ε, of a silicon materialdielectricIs the dielectric constant of the insulating layer. t is toxIs the thickness of the shielding dielectric layer 3. The thickness of the shielding dielectric layer 3 can be reduced by selecting the shielding dielectric layer 3 with lower dielectric constant, thereby reducing the Pitch of the device. The shielding dielectric layer 3 is most commonly made of silicon dioxide at present, and can also be a sandwich structure of silicon dioxide, silicon nitride and silicon dioxide.
The source polysilicon 4 and the drift region 2 are laterally depleted, so that the doping concentration of the drift region can be greatly improved under the condition of not reducing the breakdown voltage of the device. However, if the doping concentration of the drift region is too high, the lateral electric field cannot completely deplete the drift region, which may result in a reduction in breakdown voltage. The doping concentration is inversely proportional to the width of Mesa. Therefore, in order to improve the performance of the power device, the width of Mesa needs to be continuously reduced.
The specific on-resistance of the device mainly comprises the following four parts:
the channel resistance.
The diffusion resistance, which is primarily referred to as the MOSFET current, diffuses from along the channel surface to the entire drift region.
Both a and B can be reduced by reducing the thickness of the gate dielectric layer 5 and increasing the channel density. Reducing the width of Mesa can reduce Pitch well, thereby increasing channel density.
The resistance of the drift region depends mainly on the doping concentration of the drift region and the thickness of the drift region. The thickness of the drift region is proportional to the breakdown voltage and the doping concentration of the drift region is inversely proportional to the width of Mesa.
A substrate resistance.
It can be seen that the resistance of the MOSFET is reduced, one of the most critical factors being the reduction of the Mesa width.
But in practice the width of Mesa is limited to several aspects:
A. the width d101 of the first via 9 depends on the accuracy of the lithography and the corresponding etching capability. Since the first via hole 9 needs to be etched through the interlayer film 11, the interlayer film 11 is generally thick
Figure BDA0002808994020000042
The above; at the same time, for better protection against parasitic transistor conduction, it is necessary to continue etching silicon down, i.e. through the source region 8, usually to a depth that is sufficient to prevent parasitic transistor conduction
Figure BDA0002808994020000041
Nearby. The width d101 of the smallest of the first through holes 9 that can be realized in the current technology is typically around 0.15 μm.
B. The minimum distance of the first via 9 to the gate trench. This is because a better ohmic contact between the first via 9 and the channel region 7 is achieved. After the first via 9 is formed, a high concentration via implant is typically required. The dosage of the through hole injection is very high at 1e15/cm3Nearby, the implantation dosage is far greater than that of the current channel region, and the implantation dosage of the channel region 7 is 1e 12-1 e13/cm3In the meantime. To prevent the via implant from affecting the threshold voltage, a minimum distance between the two is required. Typically around 0.1 μm.
C. The alignment accuracy of the first through-hole 9. This is more pronounced for SGT MOSFETs. This is because the SGT MOSFET has a relatively deep gate trench and a relatively thick shield dielectric layer 3. This results in a relatively large stress in the wafer surface and a relatively severe warpage of the wafer surface. This presents great difficulties in alignment. The current alignment accuracy process of CT is typically controlled around 0.1 μm.
Therefore, the width of Mesa is usually designed to be larger than 0.55 μm, i.e., (a +2B +2C), which causes great difficulty in further reducing the Pitch of MOSFET.
The existing self-aligning through hole technology can well avoid the deviation of CT alignment precision. But it adds complexity to the process.
As shown in fig. 2, it is a schematic structural diagram of a conventional trench gate IGBT; a plurality of grid grooves are formed on a semiconductor substrate, mesa areas are formed on the semiconductor substrate between every two grid grooves, every grid groove and every mesa area are arranged alternately, and a unit structure is formed by one grid groove and an adjacent mesa area. In fig. 2, the formation region of the gate Trench is shown as a double-arrow line corresponding to a reference 301, and the gate Trench is also denoted by Trench; the Mesa region is formed as indicated by the double arrow line corresponding to the mark 302, and the Mesa region is also indicated by Mesa.
A first layer of conductive material is formed in the gate trench as shown at 206a and 206b in figure 2, with a gate dielectric layer 205 between the first layer of conductive material and the sides of the gate trench.
A channel region 207 is formed on the surface of the semiconductor substrate of each mesa region, and each gate trench passes through the channel region 207;
a source region 208 is formed at the surface of the channel region 207. The source region 208 is also commonly referred to as an emitter region in an IGBT.
An interlayer film 211 covers the mesa region where the source region 208 is formed and the surface of the gate trench region where the first conductive material layer is formed.
A through hole is formed in the interlayer film 211 to pass through the interlayer film 211.
A gate electrode and a source electrode patterned by the front metal layer 210 are formed on the surface of the interlayer film 211.
The through hole comprises a first through hole 209 arranged at the top of the mesa region, the bottom of the first through hole 209 is contacted with the source region 208, the bottom of the first through hole 209 is contacted with the channel region 207 through the source region 208, and the top of the first through hole 209 is connected with the source electrode.
Each of the first through holes 209 has one first conductive material layer on each of two sides thereof, the top of the first conductive material layer 206a on the first side of the first through hole 209 is connected to the gate through the corresponding through hole (not shown), and the top of the first conductive material layer 206b on the second side of the first through hole 209 is connected to the source through the corresponding through hole (not shown).
In the existing trench gate IGBT, the first through hole 209 is disposed in the middle of the mesa region, and both sides of the first through hole 209 are symmetrical, that is, the distance between both sides of the first through hole 209 and the corresponding gate trench is equal. As with the conventional SGT MOSFET shown in fig. 1, the size limitation of the spacing on both sides of the first via 209 in fig. 2 may make the mesa region unable to be further reduced.
The semiconductor substrate includes a silicon substrate.
A first epitaxial layer 202 is further formed on the semiconductor substrate, and the gate trench is formed in the first epitaxial layer 202. The material of the first conductive material layer comprises polysilicon. The gate dielectric layer 205 includes an oxide layer.
The collector region 201 is formed on the back surface of the semiconductor substrate; generally, the collector region 201 is formed by back heavily doped ion implantation of the thinned semiconductor substrate.
A drift region is formed by the semiconductor substrate between the collector region 201 to the channel region 207. Typically, a buffer layer 203 is also formed between the collector region 201 and the drift region.
A Carrier Stored (CS) layer 204 is also formed at the bottom of the channel region 207.
Taking an N-type device as an example, the collector region 201 has P-type heavy doping; the first epitaxial layer 202 has N-type lightly doped regions, the channel region 207 is P-type doped regions, the source region 208 is N-type heavily doped regions, and P-type heavily doped regions are formed at the bottoms of the first contact holes 209 a.
As shown in fig. 2, it is a schematic structural diagram of a conventional trench gate IGBT; a plurality of grid grooves are formed on a semiconductor substrate, mesa areas are formed on the semiconductor substrate between every two grid grooves, every grid groove and every mesa area are arranged alternately, and a unit structure is formed by one grid groove and an adjacent mesa area. In fig. 2, the formation region of the gate Trench is shown by a double-arrow line corresponding to a mark 301, and the gate Trench is also denoted by Trench; the Mesa region is formed as indicated by the double arrow line corresponding to the mark 302, and the Mesa region is also indicated by Mesa.
A layer of gate conductive material is formed in the gate trench, as indicated by reference numerals 206a and 206b in figure 2, with a gate dielectric layer 205 being interposed between the layer of gate conductive material and the sides of the gate trench.
A channel region 207 is formed on the surface of the semiconductor substrate of each mesa region, and each gate trench passes through the channel region 207;
a source region 208 is formed at the surface of the channel region 207. The source region 208 is also commonly referred to as an emitter region in an IGBT.
An interlayer film 211 covers the mesa region where the source region 208 is formed and the surface of the gate trench region where the gate conductive material layer is formed.
A through hole is formed in the interlayer film 211 so as to penetrate through the interlayer film 211.
A gate electrode and a source electrode patterned by the front metal layer 210 are formed on the surface of the interlayer film 211.
The through hole comprises a first through hole 209 arranged at the top of the mesa region, the bottom of the first through hole 209 is contacted with the source region 208, the bottom of the first through hole 209 is contacted with the channel region 207 through the source region 208, and the top of the first through hole 209 is connected with the source electrode.
Each of the first through holes 209 has one gate conductive material layer on both sides thereof, the top of the gate conductive material layer 206a on the first side of the first through hole 209 is connected to the gate through the corresponding through hole (not shown), and the top of the gate conductive material layer 206b on the second side of the first through hole 209 is connected to the source through the corresponding through hole (not shown).
In the existing trench gate IGBT, the first through hole 209 is disposed in the middle of the mesa region, and two sides of the first through hole 209 are symmetrical, that is, the distances between two sides of the first through hole 209 and the corresponding gate trenches are equal. As with the conventional SGT MOSFET shown in fig. 1, the size limitation of the spacing on both sides of the first via 209 in fig. 2 may make the mesa region unable to be further reduced.
The semiconductor substrate includes a silicon substrate.
A first epitaxial layer 202 is further formed on the semiconductor substrate, and the gate trench is formed in the first epitaxial layer 202. The material of the gate conductive material layer comprises polysilicon. The gate dielectric layer 205 includes an oxide layer.
The collector region 201 is formed on the back surface of the semiconductor substrate; generally, the collector region 201 is formed by back heavily doped ion implantation of the thinned semiconductor substrate.
A drift region is formed by the semiconductor substrate between the collector region 201 to the channel region 207. Typically, a buffer layer 203 is also formed between the collector region 201 and the drift region.
A Carrier Stored (CS) layer 204 is also formed at the bottom of the channel region 207.
Taking an N-type device as an example, the collector region 201 has P-type heavy doping; the first epitaxial layer 202 has N-type lightly doped regions, the channel region 207 is P-type doped regions, the source region 208 is N-type heavily doped regions, P-type heavily doped regions are formed at the bottoms of the first contact holes 209a, and the carrier storage layer 204 is N-type heavily doped regions.
The carrier storage layer 204 functions as a blocking layer for hole diffusion when the IGBT is turned on, and the doping concentration of holes is steep in the CS layer 204 due to the impedance of the built-in electric field, so that the concentration of holes is increased, and the voltage drop when the IGBT is turned on is reduced. The higher the doping concentration of the CS layer 204, the more significant the carrier storage effect. But the CS layer 204 is doped too heavily to be fully depleted, resulting in a reduced breakdown voltage. The highest doping concentration that can be achieved by the CS layer 204 is inversely proportional to the width of Mesa. Therefore, reducing the width of Mesa, i.e., reducing Pitch, has been the direction of increasing effort in IGBTs.
The IGBT has a conductance modulation effect when turned on, and therefore, when the drain load is short-circuited, the current is large. It is currently generally required that IGBTs be capable of 10 mus short circuit capability. This requires that the IGBT current be reduced during short-circuiting, and a common method is to use a Dummy Gate (Dummy Gate). The Dummy Gate is formed by connecting a portion of the Gate conductive material layer to the source electrode, i.e., the Gate conductive material layer 206a in fig. 2, and connecting a portion of the Gate conductive material layer to the Gate electrode, i.e., the Gate conductive material layer 206b in fig. 2. The connection with the source electrode ensures that the channel cannot be opened, so that the current of the IGBT can be remarkably reduced when the load is short-circuited.
In fig. 2, the Gate conductive material layer 206b is an Active Gate, the Gate conductive material layer 206a is a Non-Active Gate, and the ratio of the Active Gate to the Non-Active Gate is 1: 1. In order to further reduce the saturation current of the load short circuit, the ratio of Active Gate to Non-Active Gate may be 1:2, even 1:3, and so on.
Because the width of Mesa is reduced, the performance of the IGBT can be improved.
But like the previously described MOSFETs, the Mesa width is also affected by the width of the first via 209, the distance between the first via 209 and the gate trench, and the alignment accuracy.
With alignment accuracy, IGBTs are more difficult to control than MOSFETs. This is because IGBTs typically employ a float-zone (FZ) single crystal silicon substrate wafer (wafer), i.e., an FZ wafer, which is more prone to warping. The alignment accuracy is usually controlled to 0.2 μm. This IGBT presents great difficulties in reducing Mesa.
Disclosure of Invention
The invention provides a trench gate power device, which combines the electrode connection arrangement of a first conductive material layer of a trench gate and the arrangement of a through hole at the top of a source region of a mesa region, so that the minimum value which can be reached by the width of the mesa region can be reduced, the step formed by a gate trench and the mesa region can be reduced, and the performance of the device can be improved.
In order to solve the above technical problem, in the trench gate power device provided by the present invention, a plurality of gate trenches are formed on a semiconductor substrate, the semiconductor substrate between each gate trench forms mesa regions, and each gate trench and each mesa region are alternately arranged, because one gate trench and an adjacent mesa region form a unit structure.
A first conductive material layer is formed in the grid groove, and a grid dielectric layer is arranged between the first conductive material layer and the side face of the grid groove in an interval mode.
A channel region is formed on the surface of the semiconductor substrate of each mesa region, and each gate trench penetrates through the channel region;
the source region is formed on the surface of the channel region.
An interlayer film covers surfaces of the mesa region where the source region is formed and the gate trench region where the first conductive material layer is formed.
A through-hole is formed in the interlayer film to pass through the interlayer film.
And a grid electrode and a source electrode which are formed by patterning the front metal layer are formed on the surface of the interlayer film.
The through hole comprises a first through hole arranged at the top of the mesa region, the bottom of the first through hole is in contact with the source region, the bottom of the first through hole penetrates through the source region and is in contact with the channel region, and the top of the first through hole is connected with the source electrode.
The two sides of each first through hole are respectively provided with one first conductive material layer, the top of the first conductive material layer on the first side of each first through hole is connected to the grid electrode through the corresponding through hole, and the top of the first conductive material layer on the second side of each first through hole is connected to the source electrode through the corresponding through hole.
The first through hole and the gate groove on the first side have a first pitch, the first through hole and the gate groove on the second side have a second pitch, and the second pitch is smaller than that of the first pitch.
The first pitch is limited by alignment process deviation of the first through hole and the gate trench on the first side and is limited by a minimum pitch value of the first through hole and the gate trench on the first side, and when the first pitch is larger than the minimum pitch value, a threshold voltage of the channel region on the side face of the gate trench on the first side of the first through hole is not influenced; and the layout design value of the first interval is greater than or equal to the sum of the alignment process deviation of the first through hole and the grid groove on the first side and the minimum interval value.
The second distance is not limited by the minimum distance value of the gate trenches on the first through hole and the second side, and the second distance ensures that after alignment deviation of the gate trenches on the first through hole and the second side occurs, the first side of the first through hole is located in the mesa region and the second side of the first through hole is located in the formation region of the gate trench on the mesa region or the second side of the first through hole.
The width of the mesa region is the sum of the first distance, the width of the first through hole and the second distance, and the width of the mesa region is reduced by reducing the second distance, so that the step of the unit structure is reduced.
In a further refinement, the semiconductor substrate comprises a silicon substrate or a silicon carbide substrate.
In a further improvement, a first epitaxial layer is further formed on the semiconductor substrate, and the gate trench is formed in the first epitaxial layer.
In a further refinement, the material of the first layer of conductive material comprises polysilicon.
In a further improvement, the gate dielectric layer comprises an oxide layer.
The further improvement is that the trench gate power device is a trench gate MOSFET;
the drain region is formed on the back surface of the semiconductor substrate.
And a drift region is formed by the semiconductor substrate between the drain region and the channel region.
In a further improvement, the trench-gate MOSFET is an SGT MOSFET.
And an active conductive material layer and a shielding dielectric layer are also formed in the grid groove, and the shielding dielectric layer is isolated between the active conductive material layer and the corresponding inner side surface of the grid groove.
The further improvement is that the first conductive material layer and the source conductive material layer form an upper and lower structure, the first conductive material layer is positioned on the top of the source conductive material layer, and a dielectric layer between conductive materials is isolated between the first conductive material layer and the source conductive material layer.
In a further improvement, the first through holes on both sides of the first conductive material layer connected to the source electrode are connected to form an integral structure.
In a further improvement, the first conductive material layer and the source conductive material layer form a left-right structure;
the top surface of the source conductive material layer is exposed out of the top surface of the grid groove, the first conductive material layers are located on the left side and the right side of the source conductive material layer, and a dielectric layer between the conductive materials is arranged between the source conductive material layers and the first conductive material layers in an interval mode.
In a further improvement, the first conductive material layers on the left and right sides of the source conductive material layer in the same gate trench are connected to the source or to the gate or to the source and the gate.
In a further improvement, when the first conductive material layers on the left and right sides of the source conductive material layer in the corresponding gate trench are connected to the source electrode, the first through holes on both sides of the gate trench are connected to form an integral structure.
The further improvement is that the trench gate power device is a trench gate IGBT;
the collector region is formed on the back surface of the semiconductor substrate;
a drift region is formed from the semiconductor substrate between the collector region and the channel region.
In a further improvement, the first through holes on both sides of the first conductive material layer connected to the source electrode are connected to form an integral structure.
In a further improvement, a carrier storage layer is also formed at the bottom of the channel region.
In a further improvement, the material of the source conductive material layer comprises polysilicon; the material of the shielding dielectric layer comprises silicon dioxide or silicon nitride.
In the alternating arrangement structure formed by the gate trenches and the mesa regions, the electrode connections of the first conductive material layers in the gate trenches on the two sides of the first contact hole corresponding to the source region are specially arranged, and the distances between the first contact hole and the corresponding gate trench, namely the first distance and the second distance, are arranged according to the electrode connections of the first conductive material layers on the two sides, the second distance is not limited by the minimum distance value of the gate trenches on the first through hole and the second side, and the second side of the first through hole can be shifted into the region of the gate trench, so that the second distance only needs to ensure that the first side of the first through hole is positioned in the mesa region after the alignment deviation of the gate trenches on the first through hole and the second side, and the second side of the first through hole can be positioned in the mesa region and the region where the gate trench on the second side of the first through hole is formed, therefore, the second distance of the alternating arrangement structure can be greatly reduced or even negative, the negative value of the second interval indicates that the second side of the first through hole is positioned on the forming area of the grid groove, so that the width of the mesa area is only limited by the width of the first through hole and the first interval and is not limited by the second interval basically.
The invention can be well applied to the SGT MOSFET, and the specific on-resistance of the device can be well reduced due to the reduction of the stepping of the grid groove and the mesa area, mainly the resistance of a drift area can be reduced; although the channel density is reduced and the channel resistance and the diffusion resistance of the device are increased due to the first conductive material layer of the second side of the first via hole being connected to the source, the increase of the channel resistance and the diffusion resistance can be compensated for by the reduction of the resistance of the drift region. The first conductive material layer connected with the source electrode can greatly reduce the grid capacitance of the device, which can be the reduction of the quality Factor (FOM) value of the MOSFET, namely Rsp Qg, wherein Rsp represents the specific on-resistance of the device, Qg represents the grid charge, and Qg can be reduced because the grid capacitance of the device is reduced, so that the FOM value is reduced, the improvement of the switching speed of the MOSFET is facilitated, and the loss of the MOSFET in the switching process is reduced.
The invention can be well applied to a trench gate IGBT, and compared with an MOSFET (metal oxide semiconductor field effect transistor), the alignment precision between a through hole and a gate trench of the IGBT is more difficult to control, at the moment, because a semiconductor substrate adopted by the IGBT is an FZ wafer, the wafer is easier to warp, so that the alignment precision range, namely the alignment process deviation, is larger, and great difficulty is brought to the reduction of the width of a mesa area of the IGBT.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
FIG. 1 is a schematic diagram of a prior art SGT MOSFET structure;
FIG. 2 is a schematic structural diagram of a conventional trench gate IGBT;
FIG. 3 is a schematic diagram of a SGT MOSFET according to a first embodiment of the present invention;
FIG. 4 is a schematic diagram of a SGT MOSFET according to a second embodiment of the present invention;
fig. 5 is a schematic structural diagram of a trench gate IGBT according to a fifth embodiment of the present invention.
Detailed Description
First embodiment of the invention SGT MOSFET:
fig. 3 is a schematic structural diagram of an SGT MOSFET according to a first embodiment of the present invention; the trench gate power device according to the first embodiment of the present invention is an SGT MOSFET, and therefore is also referred to as an SGT MOSFET according to the first embodiment of the present invention, a plurality of gate trenches are formed on a semiconductor substrate 1, mesa regions are formed in the semiconductor substrate 1 between the gate trenches, the gate trenches and the mesa regions are alternately arranged, and one gate trench and an adjacent mesa region form a cell structure. In fig. 3, the formation region of the gate Trench is shown as a double-arrow line corresponding to the mark 101, and the gate Trench is also denoted by Trench; the Mesa region is formed as indicated by the double arrow line corresponding to the mark 102, and the Mesa region is also indicated by Mesa.
A first conductive material layer is formed in the gate trench, as shown by reference numerals 6a and 6b of fig. 3, with a gate dielectric layer 5 interposed between the first conductive material layer and the side surface of the gate trench.
A channel region 7 is formed on the surface of the semiconductor substrate 1 of each mesa region, and each gate trench passes through the channel region 7;
a source region 8 is formed at the surface of the channel region 7.
An interlayer film 11 covers the mesa region where the active region 8 is formed and the surface of the gate trench region where the first conductive material layer is formed.
A through hole is formed in the interlayer film 11 so as to penetrate the interlayer film 11.
A gate electrode and a source electrode patterned by the front metal layer 10 are formed on the surface of the interlayer film 11.
The through holes comprise a first through hole 9a arranged at the top of the mesa region, the bottom of the first through hole 9a is contacted with the source region 8, the bottom of the first through hole 9a is contacted with the channel region 7 through the source region 8, and the top of the first through hole 9a is connected with the source electrode.
Two sides of each of the first through holes 9a are respectively provided with one first conductive material layer, the top of the first conductive material layer 6a on the first side of the first through hole 9a is connected to the gate through the corresponding through hole (not shown), and the top of the first conductive material layer 6b on the second side of the first through hole 9a is connected to the source through the corresponding through hole (not shown).
The first via 9a and the gate trench on the first side have a first pitch d2, the first via 9a and the gate trench on the second side have a second pitch d3, and the second pitch d3 is smaller than the first pitch d 2. The first through hole 9a has a width d 1.
The first pitch d2 is limited by alignment process variations of the first via 9a and the gate trench of the first side and the first pitch d2 is limited by a minimum pitch value of the first via 9a and the gate trench of the first side, a threshold voltage of the channel region 7 at the side of the gate trench of the first side of the first via 9a is not affected when the first pitch d2 is greater than the minimum pitch value; the layout design value of the first pitch d2 is greater than or equal to the sum of the minimum pitch value and the alignment process deviation of the first via 9a and the gate trench on the first side.
The second distance d3 is not limited by the minimum distance value of the gate trenches on the first via 9a and the second side, and the second distance d3 ensures that the first side of the first via 9a is located in the mesa region and the second side of the first via 9a is located in the formation region of the gate trench on the mesa region or the second side of the first via 9a after the alignment deviation of the gate trenches on the first via 9a and the second side. That is, in the first embodiment of the present invention, the first via 9a can move laterally in the direction of the gate trench on the second side thereof, and the second side of the first via 9a can also move onto the formation region of the gate trench, only by ensuring that the first side of the first via 9a can still be located in the mesa region and contact the source region 8 after the first via 9a is aligned and shifted to the second side thereof.
The width of the mesa region is the sum of the first spacing d2, the width d1 of the first via 9a and the second spacing d3, and the step of the cell structure is reduced by reducing the second spacing d3 to reduce the width of the mesa region. The second spacing d3 can also be negative, i.e. the spacing between the second side of the first via 9a and the corresponding side of the gate trench when the second side of the first via 9a is moved over the area of the gate trench.
In the first embodiment of the present invention, the semiconductor substrate 1 includes a silicon substrate or a silicon carbide substrate.
A first epitaxial layer 2 is further formed on the semiconductor substrate 1, and the gate trench is formed in the first epitaxial layer 2. The material of the first conductive material layer comprises polysilicon. The gate dielectric layer 5 comprises an oxide layer.
The drain region is formed on the back surface of the semiconductor substrate 1. In the first embodiment of the present invention, the semiconductor substrate 1 is heavily doped, and the drain region is directly composed of the thinned semiconductor substrate 1; or, the drain region is formed by performing back heavy doping and drain injection on the thinned semiconductor substrate 1.
A drift region is formed by the semiconductor substrate 1 between the drain region and the channel region 7.
An active conductive material layer 4 and a shielding dielectric layer 3 are further formed in the gate trench, and the shielding dielectric layer 3 is isolated between the active conductive material layer 4 and the inner side surface of the corresponding gate trench. The material of the source conductive material layer 4 comprises polysilicon; the material of the shielding dielectric layer 3 comprises silicon dioxide or silicon nitride.
The first conductive material layer and the source conductive material layer 4 form an upper and lower structure, the first conductive material layer is positioned on the top of the source conductive material layer 4, and a conductive material medium layer is isolated between the first conductive material layer and the source conductive material layer.
Taking an N-type device as an example, the semiconductor substrate 1 is provided with N-type heavy doping; the first epitaxial layer 2 is doped lightly in an N-type manner, the channel region 7 is doped lightly in a P-type manner, the source region 8 is doped heavily in an N-type manner, and a heavily doped P-type region is formed at the bottom of the first contact hole 9 a. And (4) switching the N type and the P type of each doping type to obtain the P type device.
In the first embodiment of the present invention, in the alternating arrangement structure formed by the gate trenches and the mesa regions, the electrode connections of the first conductive material layers in the gate trenches at both sides of the first contact hole corresponding to the source region 8 are specially arranged, and the first spacing d2 and the second spacing d3, which are the spacings between the first contact hole and the corresponding gate trench, are arranged according to the electrode connections of the first conductive material layers at both sides, the second spacing d3 is not limited by the minimum spacing values of the gate trenches at the first side and the second side of the first through hole 9a, and the second side of the first through hole 9a can be shifted into the region of the gate trench, so the second spacing d3 only needs to ensure that the first side of the first through hole 9a is located in the mesa region after the alignment deviation occurs between the gate trenches at the first side and the second side of the first through hole 9a, and the second side of the first through hole 9a can be located in the region where the gate trench is formed in both the mesa region and the second side of the first through hole 9a, therefore, the second distance d3 of the present invention can be greatly reduced or even negative, and the negative value of the second distance d3 indicates that the second side of the first via 9a is located on the formation region of the gate trench, so that the width of the mesa region is limited only by the width of the first via 9a itself and the first distance d2, and is not limited by the second distance d3, therefore, the present invention can reduce the minimum value that the width of the mesa region can reach, thereby reducing the width of the mesa region and thus reducing the step formed by the gate trench and the mesa region, and thus improving the performance of the device.
In the SGT MOSFET of the first embodiment of the present invention, the step size of the gate trench and the mesa region is reduced, so that the specific on-resistance of the device can be well reduced, and mainly the resistance of the drift region can be reduced; although the channel density is reduced and the channel resistance and the diffusion resistance of the device are increased because the first conductive material layer of the second side of the first via hole 9a is connected to the source, the increase of the channel resistance and the diffusion resistance can be compensated for by the reduction of the resistance of the drift region. The first conductive material layer connected with the source electrode can greatly reduce the grid capacitance of the device, which can be the reduction of the quality Factor (FOM) value of the MOSFET, namely Rsp Qg, wherein Rsp represents the specific on-resistance of the device, Qg represents the grid charge, and Qg can be reduced because the grid capacitance of the device is reduced, so that the FOM value is reduced, the improvement of the switching speed of the MOSFET is facilitated, and the loss of the MOSFET in the switching process is reduced.
In contrast to the prior art structure shown in fig. 1, in the first embodiment of the present invention, the first conductive material layer is no longer connected to the gate electrode but acts as a gate conductive material layer such as a polysilicon gate, but the first conductive material layer 6a is connected to the gate electrode and the first conductive material layer 6b is connected to the source electrode.
Meanwhile, the first via hole 9a is not in the middle of Mesa, but is close to the first conductive material layer 6b and far from the first conductive material layer 6 a.
The benefits of this are:
1. the minimum distance from the first via 9a to the gate trench, i.e. the minimum pitch value, as before 0.1 μm, only needs to consider a single side. I.e. the distance of said first via 9a from the first layer 6a of conductive material. The first via 9a can be located very close to the first conductive material layer 6b because there is no channel and there is no need to worry about the effect of the via implant of the first via 9a on the threshold voltage.
2. The deviation of the alignment accuracy of the first through hole 9a causes the actual position of the first through hole 9a to deviate from the original design value. However, in the structure of fig. 3, only the process deviation of the first via hole 9a from the first conductive material layer 6a needs to be considered, and the process deviation of the first via hole 9a from the first conductive material layer 6b does not need to be considered. Even in the worst case, it does not matter that the first via 9a is in contact with the first layer of conductive material 6b, since the first layer of conductive material 6b would have to be connected to the source, which would have been equipotential.
Thus, in contrast to the prior art structure corresponding to fig. 1, the minimum width of Mesa is 0.55 μm under the process conditions of the first embodiment of the present invention. With this structure, the minimum width of Mesa can be greatly reduced.
One possible way is that the width of Mesa becomes 0.4 μm, the distance of the first via 9a from the first conductive material layer 6a is 0.2 μm, where it is considered that the alignment accuracy of the first via 9a is 0.1 μm and the via implantation of the first via 9a needs 0.1 μm as little as possible for the threshold impact, the width of the first via 9a itself is 0.15 μm, and the distance of the first via 9a from the first conductive material layer 6b is 0.05 μm. The first via 9a is only 0.05 μm away from the first conductive material layer 6b, so that with the worst alignment accuracy of the first via 9a, 0.1 μm of the first via 9a will fall on Mesa and another 0.05 μm on the gate dielectric layer 5 of the gate trench. In case the gate dielectric layer 5 is relatively thin, even above the first conductive material layer 6 b. But this has no effect on the device.
In doing so, there is also an advantage:
a portion of the first conductive material layer 6b is connected to the source electrode. Thus, channel resistance and diffusion resistance increase due to the decrease in channel density. However, the decrease in Mesa width causes a decrease in Pitch, and the deterioration in specific on-resistance caused by the increase in channel resistance can be compensated for. More importantly, the first conductive material layer 6b is connected with the source electrode, so that the gate capacitance of the MOSFET can be greatly reduced, which can bring the MOSFET FOM value Rsp*QgThis helps to increase the switching speed of the MOSFET and reduces the losses of the MOSFET during switching.
SGTMOSFET of the second embodiment of the present invention:
the difference between the SGTMOSFET device of the second embodiment of the present invention and the SGTMOSFET of the first embodiment of the present invention is that the SGTMOSFET device of the second embodiment of the present invention has the following characteristics:
fig. 4 is a schematic structural view of an SGTMOSFET according to a second embodiment of the present invention, wherein the first through holes 9b on both sides of the first conductive material layer 6b connected to the source are connected to form an integral structure.
That is, the second sides of the first via holes 9a of two adjacent mesa regions in fig. 3 extend to the formation region of the adjacent first conductive material layer 6b and are fused together to form the first via hole 9b of fig. 4. The second distance d3 in fig. 3 is not required to be set for the first through holes 9b, so that the width of the Mesa region, i.e., Mesa region, can be further reduced. Also, the width d4 of the first via hole 9b in fig. 4 is greater than the width d1 of the first via hole 9b in fig. 3, which can reduce the complexity of the process of forming the first via hole 9b, thereby reducing the cost.
Third embodiment of the invention SGT MOSFET:
the third SGT MOSFET device according to the present invention is different from the first SGT MOSFET according to the present invention in that the third SGT MOSFET device according to the present invention has the following features:
the first conductive material layer and the source conductive material layer 4 form a left-right structure;
the top surface of the source conductive material layer 4 is exposed from the top surface of the gate trench, the first conductive material layers are located on the left side and the right side of the source conductive material layer 4, and a dielectric layer between conductive materials is arranged between the source conductive material layer 4 and the first conductive material layers.
The first layers of conductive material on the left and right sides of the source layer of conductive material 4 in the same gate trench are either both connected to the source or both connected to the gate or one connected to the source and the other connected to the gate.
Fourth embodiment of the invention SGT MOSFET:
the fourth embodiment SGT MOSFET device of the present invention is different from the third embodiment SGT MOSFET device of the present invention in that the fourth embodiment SGT MOSFET device of the present invention has the following features:
on the basis of the third embodiment of the present invention, the first conductive material layers on the left and right sides of the source conductive material layer 4 in the corresponding gate trench are connected to the source electrode, and the first through holes on the two sides of the gate trench are connected into an integral structure. The first through-hole in the fourth embodiment of the present invention is also the same as the first through-hole 9b in the second embodiment of the present invention. The structure of the fourth embodiment of the present invention can be obtained by changing the top-bottom structure composed of the first conductive material layer and the source conductive material layer 4 in fig. 4 into a left-right structure.
Fifth embodiment of the invention IGBT:
fig. 5 is a schematic structural diagram of a trench gate IGBT according to a fifth embodiment of the present invention; the trench gate power device according to the fifth embodiment of the present invention is an IGBT, and therefore is also referred to as an IGBT according to the fifth embodiment of the present invention, a plurality of gate trenches are formed on a semiconductor substrate, mesa regions are formed in the semiconductor substrate between the gate trenches, and the gate trenches and the mesa regions are alternately arranged, and one gate trench and an adjacent one of the mesa regions form a cell structure. In fig. 5, the formation region of the gate Trench is shown as a double-arrow line corresponding to a reference 301, and the gate Trench is also denoted by Trench; the Mesa region is formed as indicated by the double arrow line corresponding to the mark 302, and the Mesa region is also indicated by Mesa.
A first layer of conductive material is formed in the gate trench as shown at 206a and 206b in figure 5, with a gate dielectric layer 205 between the first layer of conductive material and the sides of the gate trench.
A channel region 207 is formed on the surface of the semiconductor substrate of each mesa region, and each gate trench passes through the channel region 207;
a source region 208 is formed at the surface of the channel region 207. The source region 208 is also commonly referred to as an emitter region in an IGBT.
An interlayer film 211 covers the mesa region where the source region 208 is formed and the surface of the gate trench region where the first conductive material layer is formed.
A through hole is formed in the interlayer film 211 to pass through the interlayer film 211.
A gate electrode and a source electrode patterned by the front metal layer 210 are formed on the surface of the interlayer film 211.
The through hole comprises a first through hole 209a arranged at the top of the mesa region, the bottom of the first through hole 209a is contacted with the source region 208, the bottom of the first through hole 209a is contacted with the channel region 207 through the source region 208, and the top of the first through hole 209a is connected with the source electrode.
Two sides of each of the first through holes 209a are respectively provided with one first conductive material layer, the top of the first conductive material layer 206a on the first side of the first through hole 209a is connected to the gate through the corresponding through hole (not shown), and the top of the first conductive material layer 206b on the second side of the first through hole 209a is connected to the source through the corresponding through hole (not shown).
The first via 209a and the gate trench on the first side have a first pitch, and the first via 209a and the gate trench on the second side have a second pitch, which is smaller than the first pitch.
The first pitch is limited by the alignment process deviation of the first via 209a and the gate trench on the first side and the minimum pitch value of the first via 209a and the gate trench on the first side, and the threshold voltage of the channel region 207 on the side of the gate trench on the first side of the first via 209a is not affected when the first pitch is greater than the minimum pitch value; the layout design value of the first pitch is greater than or equal to the sum of the minimum pitch value and the alignment process deviation of the first through hole 209a and the gate trench on the first side.
The second pitch is not limited by the minimum pitch value of the gate trenches on the first via 209a and the second side, and the second pitch ensures that the first side of the first via 209a is located in the mesa region and the second side of the first via 209a is located in the formation region of the gate trench on the mesa region or the second side of the first via 209a after the alignment deviation of the gate trenches on the first via 209a and the second side occurs. That is, in the fifth embodiment of the present invention, the first via 209a can move laterally in the direction of the gate trench on the second side thereof, and the second side of the first via 209a can also move onto the formation region of the gate trench, only by ensuring that the first side of the first via 209a can still be located in the mesa region and contact the source region 208 after the first via 209a is aligned and shifted to the second side thereof.
The width of the mesa region is the sum of the first pitch, the width of the first via 209a, and the second pitch, and the step size of the cell structure is reduced by reducing the width of the mesa region by reducing the second pitch. The second pitch can also be negative, i.e., the pitch of the second side of the first via 209a and the corresponding side of the gate trench when the second side of the first via 209a is moved over the region of the gate trench.
In a fifth embodiment of the present invention, the semiconductor substrate includes a silicon substrate or a silicon carbide substrate.
A first epitaxial layer 202 is further formed on the semiconductor substrate, and the gate trench is formed in the first epitaxial layer 202. The material of the first conductive material layer comprises polysilicon. The gate dielectric layer 205 includes an oxide layer.
The collector region 201 is formed on the back surface of the semiconductor substrate; in the fifth embodiment of the present invention, the collector region 201 is formed by performing back heavy doping ion implantation on the thinned semiconductor substrate.
A drift region is formed by the semiconductor substrate between the collector region 201 to the channel region 207. Typically, a buffer layer 203 is also formed between the collector region 201 and the drift region.
A carrier storage layer 204 is also formed at the bottom of the channel region 207.
Taking an N-type device as an example, the collector region 201 has P-type heavy doping; the first epitaxial layer 202 has N-type lightly doped regions, the channel region 207 is P-type doped regions, the source region 208 is N-type heavily doped regions, the carrier storage layer 204 is N-type heavily doped regions, and P-type heavily doped regions are further formed at the bottoms of the first contact holes 209 a. And (4) switching the N type and the P type of each doping type to obtain the P type device.
Compared with an MOSFET, the alignment accuracy between the through hole 209a and the gate trench of the IGBT according to the fifth embodiment of the present invention is more difficult to control, and at this time, because the semiconductor substrate generally used in the IGBT is an FZ wafer, such a wafer is easier to warp, so that the alignment accuracy range, i.e., the alignment process deviation, is larger, which brings great difficulty in reducing the width of the mesa region of the IGBT.
IGBT according to a sixth embodiment of the present invention:
the difference between the IGBT according to the sixth embodiment of the present invention and the IGBT according to the fifth embodiment of the present invention is that the IGBT according to the sixth embodiment of the present invention has the following features:
the first via holes 209a at both sides of the first conductive material layer 206b connected to the source electrode are connected to an integrated structure.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.

Claims (16)

1. A trench-gate power device, comprising:
forming a plurality of gate trenches on a semiconductor substrate, wherein mesa regions are formed on the semiconductor substrate between the gate trenches, and the gate trenches and the mesa regions are alternately arranged, and a unit structure is formed by one gate trench and an adjacent mesa region;
a first conductive material layer is formed in the grid groove, and a grid dielectric layer is arranged between the first conductive material layer and the side face of the grid groove in an interval mode;
a channel region is formed on the surface of the semiconductor substrate of each mesa region, and each gate trench penetrates through the channel region;
the source region is formed on the surface of the channel region;
an interlayer film covers the mesa region where the active region is formed and the surface of the gate trench region where the first conductive material layer is formed;
forming a through hole in the interlayer film to pass through the interlayer film;
forming a grid electrode and a source electrode which are formed by patterning a front metal layer on the surface of the interlayer film;
the through hole comprises a first through hole arranged at the top of the mesa region, the bottom of the first through hole is contacted with the source region, the bottom of the first through hole penetrates through the source region and is contacted with the channel region, and the top of the first through hole is connected with the source electrode;
the two sides of each first through hole are respectively provided with one first conductive material layer, the top of the first conductive material layer on the first side of each first through hole is connected to the grid electrode through the corresponding through hole, and the top of the first conductive material layer on the second side of each first through hole is connected to the source electrode through the corresponding through hole;
the first through hole and the grid groove on the first side have a first spacing, the first through hole and the grid groove on the second side have a second spacing, and the second spacing is smaller than the first spacing;
the first distance is limited by alignment process deviation of the first through hole and the grid groove on the first side, and the first distance is limited by a minimum distance value of the first through hole and the grid groove on the first side, and when the first distance is larger than the minimum distance value, the threshold voltage of the channel region on the side face of the grid groove on the first side of the first through hole is not influenced; the layout design value of the first distance is more than or equal to the sum of the alignment process deviation of the first through hole and the grid groove on the first side and the minimum distance value;
the second distance is not limited by the minimum distance value of the gate trenches on the first through hole and the second side, and the second distance ensures that after alignment deviation of the gate trenches on the first through hole and the second side, the first side of the first through hole is positioned in the mesa area and the second side of the first through hole is positioned in the formation area of the gate trench on the mesa area or the second side of the first through hole;
the width of the mesa region is the sum of the first distance, the width of the first through hole and the second distance, and the width of the mesa region is reduced by reducing the second distance, so that the step of the unit structure is reduced.
2. The trench-gate power device of claim 1 wherein: the semiconductor substrate includes a silicon substrate or a silicon carbide substrate.
3. The trench-gate power device of claim 2 wherein: a first epitaxial layer is further formed on the semiconductor substrate, and the gate trench is formed in the first epitaxial layer.
4. The trench-gate power device of claim 2 wherein: the material of the first conductive material layer comprises polysilicon.
5. The trench-gate power device of claim 2 wherein: the gate dielectric layer comprises an oxide layer.
6. The trench-gate power device of claim 1, 2 or 3 wherein: the trench gate power device is a trench gate MOSFET;
the drain region is formed on the back surface of the semiconductor substrate;
and a drift region is formed by the semiconductor substrate between the drain region and the channel region.
7. The trench-gate power device of claim 6 wherein: the trench gate MOSFET is an SGT MOSFET;
and an active conductive material layer and a shielding dielectric layer are also formed in the grid groove, and the shielding dielectric layer is isolated between the active conductive material layer and the corresponding inner side surface of the grid groove.
8. The trench-gate power device of claim 7 wherein: the first conductive material layer and the source conductive material layer form an upper structure and a lower structure, the first conductive material layer is positioned on the top of the source conductive material layer, and a dielectric layer between conductive materials is isolated between the first conductive material layer and the source conductive material layer.
9. The trench-gate power device of claim 8 wherein: the first through holes on two sides of the first conductive material layer connected with the source electrode are connected into an integral structure.
10. The trench-gate power device of claim 7 wherein: the first conductive material layer and the source conductive material layer form a left-right structure;
the top surface of the source conductive material layer is exposed out of the top surface of the grid groove, the first conductive material layers are located on the left side and the right side of the source conductive material layer, and a dielectric layer between the conductive materials is arranged between the source conductive material layers and the first conductive material layers in an interval mode.
11. The trench-gate power device of claim 10 wherein: the first conductive material layers on the left and right sides of the source conductive material layer in the same gate trench are connected to either the source or the gate or one to the source and the other to the gate.
12. The trench-gate power device of claim 11 wherein: when the first conductive material layers on the left and right sides of the source conductive material layer in the corresponding gate trench are connected to the source electrode, the first through holes on the two sides of the gate trench are connected into an integral structure.
13. The trench-gate power device of claim 1, 2 or 3 wherein: the trench gate power device is a trench gate IGBT;
the collector region is formed on the back surface of the semiconductor substrate;
a drift region is formed from the semiconductor substrate between the collector region and the channel region.
14. The trench-gate power device of claim 13 wherein: the first through holes on two sides of the first conductive material layer connected with the source electrode are connected into an integral structure.
15. The trench-gate power device of claim 13 wherein: a carrier storage layer is also formed at the bottom of the channel region.
16. The trench-gate power device of claim 7 wherein: the material of the source conductive material layer comprises polycrystalline silicon; the material of the shielding dielectric layer comprises silicon dioxide or silicon nitride.
CN202011379469.2A 2020-12-01 2020-12-01 Trench gate power device Pending CN114582863A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114880880A (en) * 2022-07-04 2022-08-09 成都复锦功率半导体技术发展有限公司 SGT MOSFET device optimization design method
CN116364755A (en) * 2023-03-14 2023-06-30 瑶芯微电子科技(上海)有限公司 Shielded gate trench type MOSFET device and manufacturing method thereof
CN117747672A (en) * 2024-02-20 2024-03-22 深圳市威兆半导体股份有限公司 SGT device and method of making same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114880880A (en) * 2022-07-04 2022-08-09 成都复锦功率半导体技术发展有限公司 SGT MOSFET device optimization design method
CN114880880B (en) * 2022-07-04 2022-10-11 成都复锦功率半导体技术发展有限公司 SGT MOSFET device optimization design method
CN116364755A (en) * 2023-03-14 2023-06-30 瑶芯微电子科技(上海)有限公司 Shielded gate trench type MOSFET device and manufacturing method thereof
CN117747672A (en) * 2024-02-20 2024-03-22 深圳市威兆半导体股份有限公司 SGT device and method of making same

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