CN114880880B - SGT MOSFET device optimization design method - Google Patents

SGT MOSFET device optimization design method Download PDF

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Publication number
CN114880880B
CN114880880B CN202210777865.3A CN202210777865A CN114880880B CN 114880880 B CN114880880 B CN 114880880B CN 202210777865 A CN202210777865 A CN 202210777865A CN 114880880 B CN114880880 B CN 114880880B
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resistance
specific
mosfet device
drift region
sgt mosfet
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CN114880880A (en
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王新
代同振
周仲建
张乃介
张帅
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Chengdu Fujin Power Semiconductor Technology Development Co ltd
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Chengdu Fujin Power Semiconductor Technology Development Co ltd
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Abstract

The invention relates to the technical field of semiconductor devices, and discloses an optimized design method of an SGT MOSFET device. The method can accurately analyze the trend of the on-resistance of the device changing along with the structural parameters, and has a certain reference value for guiding the development of the device.

Description

SGT MOSFET device optimization design method
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to an optimized design method of an SGT MOSFET device.
Background
With the rise of mobile phone fast charging, electric vehicles, brushless motors and lithium batteries, the demand of medium-voltage MOSFETs is more and more vigorous. The SGT MOSFET, which is a representative of the medium-voltage MOSFET, is widely used as a switching device in a motor drive system, an inverter system, and a power management system, and is a core power control unit.
The SGT MOSFET utilizes the charge coupling effect to change the electric field of the device from triangular distribution to approximately rectangular distribution, and under the condition of adopting the specification of epitaxial materials with the same doping concentration, the device can obtain higher breakdown voltage and lower on-resistance. The introduction of the shielding grid structure can reduce the Miller capacitance of the MOSFET by more than 10 times, and the lower value is achieved, so that the SGT MOSFET is beneficial to reducing the loss of the device in application.
Because of the unique structure of the SGT MOSFET, the on-resistance is mainly determined by the device structure, the cell density, the chip area, and other factors, and how to reduce the on-resistance becomes the key point of the power device design. In the actual design process, a large amount of simulation verification is usually carried out by taking the specific on-resistance as a target, when the requirement of breakdown voltage is met, the smaller the specific on-resistance of the device is expected to be, the better the specific on-resistance of the device is, but how to select the parameters of the device in the initial stage of re-simulation can only be tried by continuously adjusting the structure parameters, and finally, a relatively optimized device structure is obtained.
Disclosure of Invention
In order to solve the problems and the defects in the prior art, the invention provides an optimized design method of an SGT MOSFET device, which is based on the physical structure of the SGT MOSFET, establishes a specific on-resistance model of the device, calculates related parameters, draws a curve chart of the specific on-resistance of the SGT MOSFET device along with the change of the platform area width and the groove width, and finally obtains the platform area width and the groove width of the SGT MOSFET device when the specific on-resistance is optimal from the curve chart.
In order to achieve the above object, the technical solution of the present invention is as follows:
an SGT MOSFET device optimization design method comprises the following steps:
acquiring the on-resistance of the SGT MOSFET device, and establishing a specific on-resistance model of the SGT MOSFET device according to the acquired on-resistance;
verifying a specific on-resistance model of the SGT MOSFET device by adopting simulation software;
and drawing a curve chart of the specific on-resistance of the SGT MOSFET device along with the change of the platform area width and the groove width, and selecting the platform area width and the groove width when the device has the optimal specific on-resistance as the structural design parameters of the SGT MOSFET device according to the curve chart.
Further, the obtaining the on-resistance of the SGT MOSFET device and establishing a specific on-resistance model of the SGT MOSFET device according to the obtained on-resistance includes:
the on-resistance of an SGT MOSFET device is composed of a source contact resistance, a source region bulk resistance, a channel resistance, a drift region resistance, a substrate resistance, and a drain contact resistance, including
Figure 993084DEST_PATH_IMAGE001
；
Wherein, the first and the second end of the pipe are connected with each other,
Figure 706962DEST_PATH_IMAGE002
is the on-resistance of the SGT MOSFET device,
Figure 34169DEST_PATH_IMAGE003
is a resistance of the source contact, and,
Figure 226116DEST_PATH_IMAGE004
is the source region body contact resistance,
Figure 86494DEST_PATH_IMAGE005
in order to be the channel resistance,
Figure 705694DEST_PATH_IMAGE006
in order to be the resistance of the drift region,
Figure 35044DEST_PATH_IMAGE007
is a resistance of the substrate and is,
Figure 515835DEST_PATH_IMAGE008
is a drain contact resistance;
defining the on-resistance in unit area as the specific on-resistance of SGT MOSFET device, and the number of cells in unit area
Figure 981452DEST_PATH_IMAGE009
Since the cells are connected in parallel, the specific on-resistance of the SGT MOSFET device is
Figure 771553DEST_PATH_IMAGE010
；
Wherein, the first and the second end of the pipe are connected with each other,
Figure 574817DEST_PATH_IMAGE011
is the cell area;
then, the calculation expression of the specific on-resistance model of the SGT MOSFET device is as follows
Figure 108567DEST_PATH_IMAGE012
；
Wherein, the first and the second end of the pipe are connected with each other,
Figure 179422DEST_PATH_IMAGE013
is the specific on-resistance of the SGT MOSFET device;
Figure 406004DEST_PATH_IMAGE014
the source contact specific on-resistance;
Figure 709947DEST_PATH_IMAGE015
is the source region bulk specific on-resistance;
Figure 765496DEST_PATH_IMAGE016
is the channel specific on-resistance;
Figure 205705DEST_PATH_IMAGE017
is the drift region specific on-resistance;
Figure 337609DEST_PATH_IMAGE018
substrate specific on-resistance;
Figure 614001DEST_PATH_IMAGE019
drain contact specific on-resistance.
Further, the calculation process of the source contact specific on-resistance is specifically as follows:
the contact resistance to the N + source region in the cell structure of the SGT MOSFET device is determined by the contact resistivity and the junction depth of the N + source region, and the calculation expression is as follows
Figure 489553DEST_PATH_IMAGE020
；
Wherein the content of the first and second substances,
Figure 36465DEST_PATH_IMAGE021
in order to achieve a contact resistance ratio,
Figure 870429DEST_PATH_IMAGE022
is the junction depth of the N + source region,
Figure 617805DEST_PATH_IMAGE023
is the effective width of the channel;
the specific on-resistance is defined as the source contact specific on-resistance obtained by multiplying the source contact resistance by the cell area
Figure 47781DEST_PATH_IMAGE024
；
For the stripe-shaped cells, the cell area is as follows
Figure 197002DEST_PATH_IMAGE025
；
Wherein the content of the first and second substances,
Figure 185556DEST_PATH_IMAGE026
is the mesa region width of the SGT MOSFET device;
Figure 685807DEST_PATH_IMAGE027
is the trench width of the SGT MOSFET device;
in an SGT MOSFET device, the source is formed by two N + source regions connected in parallel, so the source contact specific on-resistance is
Figure 903162DEST_PATH_IMAGE028
。
Further, the calculation process of the source region specific on-resistance is specifically as follows:
the current enters the source region from the contact hole and flows through the source region before reaching the channel, and the square resistor of the source region body resistor is diffused by the N + source region
Figure 188781DEST_PATH_IMAGE029
And N + source region lateral length
Figure 364547DEST_PATH_IMAGE030
The decision, calculation expression is as follows
Figure 350432DEST_PATH_IMAGE031
；
Wherein, the first and the second end of the pipe are connected with each other,
Figure 371477DEST_PATH_IMAGE023
is the effective width of the channel;
the length of the N + source region is determined by the following calculation expression
Figure 980444DEST_PATH_IMAGE032
；
Wherein, the first and the second end of the pipe are connected with each other,
Figure 61533DEST_PATH_IMAGE033
for the mesa width of an SGT MOSFET device,
Figure 270797DEST_PATH_IMAGE034
is the contact hole width;
the specific on-resistance is defined as the product of the contact resistance of the source region and the cell area
Figure 344801DEST_PATH_IMAGE035
；
For the stripe-shaped cells, the cell area is as follows
Figure 323121DEST_PATH_IMAGE036
；
Wherein the content of the first and second substances,
Figure 325844DEST_PATH_IMAGE027
is the trench width of the SGT MOSFET device;
in an SGT MOSFET device, two source regions are contained in each cell, so that the source region has a body specific on-resistance of
Figure 22404DEST_PATH_IMAGE037
。
Further, the calculation process of the channel specific on-resistance is specifically as follows:
the channels in the SGT MOSFET device structure are formed on two longitudinal side walls of the gate2 structure, and each channel contributes to resistance
Figure 385252DEST_PATH_IMAGE038
；
Wherein the content of the first and second substances,
Figure 1435DEST_PATH_IMAGE039
is the channel length;
Figure 893168DEST_PATH_IMAGE040
electron mobility of the channel region;
Figure 77024DEST_PATH_IMAGE041
is unit area gate oxide capacitance;
Figure 259875DEST_PATH_IMAGE042
is the gate-source voltage;
Figure 993214DEST_PATH_IMAGE043
is the device threshold voltage;
Figure 383744DEST_PATH_IMAGE044
is the effective width of the channel;
the gate oxide capacitance per unit area and the channel length were calculated by the following calculation expressions
Figure 867946DEST_PATH_IMAGE045
；
Figure 355952DEST_PATH_IMAGE046
；
Wherein the content of the first and second substances,
Figure 428950DEST_PATH_IMAGE047
is a vacuum dielectric constant;
Figure 475535DEST_PATH_IMAGE048
is the relative dielectric constant of silicon dioxide;
Figure 148831DEST_PATH_IMAGE049
is the thickness of the gate oxide layer;
Figure 188331DEST_PATH_IMAGE050
junction depth of the Pbody area;
Figure 397726DEST_PATH_IMAGE051
is N + source junction depth;
the specific on-resistance is defined and obtained by multiplying the channel resistance by the cell area
Figure 851098DEST_PATH_IMAGE052
；
For the stripe-shaped cells, the cell area is as follows
Figure 762422DEST_PATH_IMAGE053
；
Wherein, the first and the second end of the pipe are connected with each other,
Figure 621925DEST_PATH_IMAGE033
for the mesa width of an SGT MOSFET device,
Figure 449941DEST_PATH_IMAGE027
is the trench width of the SGT MOSFET device;
in an SGT MOSFET device, there are two channels in each structure's cross-section with current flowing from the source to the drift region, so the channel specific on-resistance is
Figure 822017DEST_PATH_IMAGE054
。
Further, the calculation process of the specific on-resistance of the drift region is specifically as follows:
assuming that the current flowing out of the channel region enters the drift region at a certain divergence angle
Figure 705790DEST_PATH_IMAGE055
Extending toward the drain region, passing through the rectangular drift region and then at the bottom of the trench
Figure 821514DEST_PATH_IMAGE056
The angle is expanded towards the substrate and finally the current directly flows towards the substrate, so that when the current flows in the whole drift region, the drift region is divided into the following four parts
(a) The first part
Assuming a channel thickness of
Figure 698510DEST_PATH_IMAGE057
Then there is
Figure 241487DEST_PATH_IMAGE058
；
Wherein, the first and the second end of the pipe are connected with each other,
Figure 346977DEST_PATH_IMAGE059
is unit area gate oxide capacitance;
Figure 266392DEST_PATH_IMAGE042
is the gate-source voltage;
Figure 6684DEST_PATH_IMAGE060
is the device threshold voltage;
Figure 720562DEST_PATH_IMAGE061
is the electron charge amount;
Figure 844507DEST_PATH_IMAGE062
doping concentration of the Pbody area;
current flows from the channel region
Figure 36453DEST_PATH_IMAGE063
The angle is expanded towards the drift region until the current is filled in the drift region, and the resistance of the part after flowing out of the channel is as follows:
Figure 899761DEST_PATH_IMAGE064
；
wherein the content of the first and second substances,
Figure 784540DEST_PATH_IMAGE065
in order to be the resistivity of the drift region,
Figure 848311DEST_PATH_IMAGE066
for the length of the first part of the drift region over which current flows,
Figure 594681DEST_PATH_IMAGE067
is the cross-sectional area of current flow through the first portion of the drift region;
when current flows through the first part of the drift region, its resistance changes with increasing distance of current flowing downwards, and its depth is
Figure 794718DEST_PATH_IMAGE068
At a position with a current flow cross-sectional width of
Figure 850399DEST_PATH_IMAGE069
；
In a first part of the drift region through which current flows, a depth differential unit
Figure 650734DEST_PATH_IMAGE070
The resistance of the thickness is as follows
Figure 184483DEST_PATH_IMAGE071
；
Wherein, the first and the second end of the pipe are connected with each other,
Figure 255339DEST_PATH_IMAGE023
is the effective width of the channel;
a first part of drift region for current flowing, the specific on-resistance of which passes through the pair
Figure 481921DEST_PATH_IMAGE072
And
Figure 254705DEST_PATH_IMAGE073
the product of the resistances is multiplied by the cell area, and the resistances are composed of left and right symmetrical parallel connection, for the strip-shaped cells, the cell area is
Figure 844342DEST_PATH_IMAGE074
Then the specific on-resistance of the first part of the drift region is
Figure 284551DEST_PATH_IMAGE075
；
Wherein, the first and the second end of the pipe are connected with each other,
Figure 416455DEST_PATH_IMAGE026
is the mesa region width of the SGT MOSFET device;
Figure 692847DEST_PATH_IMAGE027
is the trench width of the SGT MOSFET device;
(b) The second part
The current flows in the whole drift region and spreads toward the substrate
Figure 568399DEST_PATH_IMAGE076
；
Wherein, the first and the second end of the pipe are connected with each other,
Figure 112381DEST_PATH_IMAGE077
is the resistivity of the drift region and,
Figure 415187DEST_PATH_IMAGE078
the length of the drift region over which current flows into the source field plate region after flowing through the first portion of the drift region,
Figure 428142DEST_PATH_IMAGE079
is the cross-sectional area of current flow through the second portion of the drift region;
the length of the current flowing through the source field plate region after the current flows through the first part of the drift region and the cross-sectional area of the current flowing through the second part of the drift region are obtained by the following calculation expressions
Figure 858118DEST_PATH_IMAGE080
；
Figure 7339DEST_PATH_IMAGE081
；
Wherein the content of the first and second substances,
Figure 481046DEST_PATH_IMAGE026
is the mesa region width of the SGT MOSFET device;
Figure 967915DEST_PATH_IMAGE082
junction depth of the Pbody area;
Figure 185270DEST_PATH_IMAGE083
is the depth of the groove;
a second part of drift region through which current flows, the specific on-resistance of which is the cell resistance of the part
Figure 188998DEST_PATH_IMAGE084
Multiplied by the cell area, for a stripe cell, the cell area
Figure 584339DEST_PATH_IMAGE085
Then driftThe specific on-resistance of the second part of the shift region is
Figure 306307DEST_PATH_IMAGE086
；
Wherein the content of the first and second substances,
Figure 327353DEST_PATH_IMAGE027
is the trench width of the SGT MOSFET device;
(c) The third part
When current flows through the third portion of the drift region, its resistance changes with increasing distance that the current flows downward, at a depth of
Figure 700434DEST_PATH_IMAGE068
At a position with a current flow cross-sectional width of
Figure 781522DEST_PATH_IMAGE087
；
Wherein, the first and the second end of the pipe are connected with each other,
Figure 741519DEST_PATH_IMAGE026
is the mesa region width of the SGT MOSFET device;
in the third part of drift region where current flows, a depth differential unit
Figure 300677DEST_PATH_IMAGE070
The resistance of the thickness is as follows
Figure 278997DEST_PATH_IMAGE088
；
A third part of drift region for passing current, the specific on-resistance of which is passed through
Figure 607403DEST_PATH_IMAGE072
And
Figure 303963DEST_PATH_IMAGE089
resistance integral between and the cellArea multiplication, for a stripe cell, its cell area
Figure 666811DEST_PATH_IMAGE090
Then the specific on-resistance of the third part of the drift region is
Figure 250371DEST_PATH_IMAGE091
；
Wherein the content of the first and second substances,
Figure 673262DEST_PATH_IMAGE026
for the mesa width of an SGT MOSFET device,
Figure 106386DEST_PATH_IMAGE027
for the trench width of an SGT MOSFET device,
Figure 7346DEST_PATH_IMAGE092
is the drift region resistivity;
(d) Fourth section
Current flowing through
Figure 960258DEST_PATH_IMAGE056
Flowing towards the substrate after an angular expansion, the partial resistance being
Figure 304783DEST_PATH_IMAGE093
；
Wherein, the first and the second end of the pipe are connected with each other,
Figure 710357DEST_PATH_IMAGE094
is the resistivity of the drift region and,
Figure 680587DEST_PATH_IMAGE095
for the length of the rectangular area through which current flows before entering the substrate after flowing through the third portion,
Figure 740203DEST_PATH_IMAGE096
the cross-sectional area of the drift region of the fourth part through which current flows;
the length of the current flowing through the rectangular region after the current flows through the third part and before the current enters the substrate and the cross-sectional area of the drift region of the fourth part through which the current flows are obtained through the following calculation expressions
Figure 504897DEST_PATH_IMAGE097
；
Figure 148499DEST_PATH_IMAGE098
；
Wherein the content of the first and second substances,
Figure 391261DEST_PATH_IMAGE099
is the epitaxial layer thickness of the device;
a fourth part drift region through which current flows, the specific on-resistance of which is the cell resistance of the part
Figure 318766DEST_PATH_IMAGE100
Multiplied by the cell area, for a stripe cell, the cell area
Figure 769208DEST_PATH_IMAGE101
Then the specific on-resistance of the fourth part of the drift region is
Figure 149374DEST_PATH_IMAGE102
；
Finally, the total on-resistance of the drift region is the sum of the four partial on-resistances, i.e.
Figure 212139DEST_PATH_IMAGE103
。
Further, the calculation process of the substrate specific on-resistance is specifically as follows:
when the current passes through the bottom of the drift region and then rapidly diffuses to the whole heavily doped substrate, the current passing through the substrate can be assumed to enter a uniform cross-section area, and the cell resistance of the substrate
Figure 994150DEST_PATH_IMAGE104
Is composed of
Figure 100646DEST_PATH_IMAGE105
；
Figure 220305DEST_PATH_IMAGE106
；
Figure 70450DEST_PATH_IMAGE107
；
Wherein, the first and the second end of the pipe are connected with each other,
Figure 723279DEST_PATH_IMAGE108
is the resistivity of the substrate and is,
Figure 677DEST_PATH_IMAGE109
the cell current flows through the thickness of the substrate,
Figure 604702DEST_PATH_IMAGE110
is the cross-sectional area of the cell current flowing through the substrate;
Figure 258537DEST_PATH_IMAGE111
is the substrate thickness;
the specific on-resistance is obtained by multiplying the substrate cell resistance by the cell area, and for the strip-shaped cell, the cell area
Figure 749561DEST_PATH_IMAGE112
Then there is a substrate specific on-resistance of
Figure 948593DEST_PATH_IMAGE113
。
Further, the drain contact resistance is obtained by the following calculation expression
Figure 790647DEST_PATH_IMAGE114
；
Wherein the content of the first and second substances,
Figure 982594DEST_PATH_IMAGE021
in order to achieve a contact resistance ratio,
Figure 845901DEST_PATH_IMAGE026
for the mesa width of an SGT MOSFET device,
Figure 996260DEST_PATH_IMAGE027
is the trench width of the SGT MOSFET device;
defined by the specific on-resistance, the drain contact specific on-resistance is the product of the drain contact resistance times the cell area, for a stripe cell, the cell area
Figure 810763DEST_PATH_IMAGE112
Then the drain contact specific on-resistance ends up being
Figure 806401DEST_PATH_IMAGE115
。
Further, the verification of the specific on-resistance model of the SGT MOSFET device by using the simulation software means that the specific on-resistance model of the SGT MOSFET device is verified by using the Silvaco software, and the divergence angle is finally determined
Figure 521285DEST_PATH_IMAGE055
And
Figure 576965DEST_PATH_IMAGE056
the value of the angle.
The invention has the beneficial effects that:
the physical model of the specific on-resistance of the SGT MOSFET device can accurately analyze the trend of the on-resistance changing along with structural parameters, particularly the optimization design relation of the platform width and the groove width specific on-resistance, and has certain reference value for guiding the development of the device.
Drawings
The foregoing and following detailed description of the invention will be apparent when read in conjunction with the following drawings, in which:
FIG. 1 is a flow chart of the method of the present invention;
FIG. 2 is a graph of resistance distribution for an SGT MOSFET device;
FIG. 3 is a current profile of an SGT MOSFET device;
FIG. 4 is a SGT MOSFET emulation device structure;
fig. 5 is a 60V SGTMOSFET specific on-resistance curve with mesa width and trench width.
Detailed Description
In order to make those skilled in the art better understand the technical solution of the present invention, the technical solution for achieving the object of the present invention will be further described by several specific examples, and it should be noted that the technical solution claimed in the present invention includes, but is not limited to, the following examples. All other embodiments, which can be obtained by a person skilled in the art without making creative efforts based on the embodiments of the present invention, shall fall within the protection scope of the present invention.
With the rapid charging of mobile phones, the rising of electric vehicles, brushless motors and lithium batteries, the demand of medium voltage MOSFETs is also more and more vigorous. The SGT MOSFET is a representative medium-voltage MOSFET, widely used as a switching device in a motor drive system, an inverter system, and a power management system, and is a core power control unit.
Because of the unique structure of the SGT MOSFET, the on-resistance is mainly determined by the device structure, the cell density, the chip area, and other factors, and how to reduce the on-resistance becomes the key point of the power device design. In the actual design process, a large number of simulation verifications are usually carried out with the specific on-resistance as a target, when the requirement of breakdown voltage is met, the smaller the specific on-resistance of the device is better, but how to select the device parameters in the initial stage of re-simulation can only be tried by continuously adjusting the structure parameters, and finally, a relatively optimized device structure is obtained.
Based on the above, the embodiment of the invention provides an optimized design method of an SGT MOSFET device, which includes establishing a physical model of the specific on-resistance of the SGT MOSFET device, performing simulation verification on the model by using simulation software, drawing a curve chart of the specific on-resistance of the SGT MOSFET device along with the change of the platform area width and the trench width according to a simulation result, and obtaining the platform area width and the trench width of the SGT MOSFET device at the time of the optimal specific on-resistance according to the chart. The optimization design method provided by the invention can accurately analyze the trend of the on-resistance changing along with the structural parameters, particularly the optimization design relation of the platform width and the groove width to the on-resistance, and has certain reference value for guiding the development of the devices.
The embodiment provides an optimized design method of an SGT MOSFET device, which is shown in fig. 1 with reference to the description, and mainly includes the following steps:
s101, firstly, obtaining the on-resistance of the SGT MOSFET device, and establishing a specific on-resistance model of the SGT MOSFET device according to the obtained on-resistance.
In this embodiment, it should be noted that, referring to the description of fig. 2 and 3, the on-resistance of the SGT MOSFET device is shown
Figure 878765DEST_PATH_IMAGE002
Contact resistance by source
Figure 678094DEST_PATH_IMAGE003
Source region bulk resistance
Figure 998217DEST_PATH_IMAGE004
Channel resistance
Figure 465277DEST_PATH_IMAGE005
Drift region resistance
Figure 503640DEST_PATH_IMAGE006
Substrate resistor
Figure 591813DEST_PATH_IMAGE116
And a drain electrodeContact resistance
Figure 32022DEST_PATH_IMAGE008
Then, the calculation expression of the on-resistance of the SGT MOSFET device is as follows
Figure 163926DEST_PATH_IMAGE117
；
The on resistance in a unit area is defined as the specific on resistance of an SGT MOSFET device, and the number of the cells which can be accommodated in the unit area is
Figure 470011DEST_PATH_IMAGE118
And each unit cell is in parallel connection, the specific on-resistance of the SGT MOSFET device is
Figure 158612DEST_PATH_IMAGE119
；
Wherein the content of the first and second substances,
Figure 984486DEST_PATH_IMAGE120
is the cell area;
according to the two calculation expressions, the on-resistance of the SGT MOSFET device can be finally obtained as follows
Figure 336226DEST_PATH_IMAGE121
；
Further, by simplifying the above calculation expression, the calculation expression of the specific on-resistance model of the SGT MOSFET device is as follows
Figure 631073DEST_PATH_IMAGE122
；
Wherein the content of the first and second substances,
Figure 575895DEST_PATH_IMAGE123
is the specific on-resistance of the SGT MOSFET device;
Figure 771122DEST_PATH_IMAGE124
the source contact specific on-resistance;
Figure 526719DEST_PATH_IMAGE125
the source region specific on-resistance;
Figure 26971DEST_PATH_IMAGE016
is the channel specific on-resistance;
Figure 293260DEST_PATH_IMAGE126
is the drift region specific on-resistance;
Figure 828147DEST_PATH_IMAGE127
substrate specific on-resistance;
Figure 285804DEST_PATH_IMAGE128
drain contact specific on-resistance.
Further, in this embodiment, the calculation process of the source contact specific on-resistance is specifically as follows:
the contact resistance to the N + source region in the cell structure of an SGT MOSFET device is determined primarily by the contact resistivity and the junction depth of the N + source region, considering the contact area, there is
Figure 53778DEST_PATH_IMAGE129
；
Wherein the content of the first and second substances,
Figure 340403DEST_PATH_IMAGE130
in order to achieve a contact resistance ratio,
Figure 214949DEST_PATH_IMAGE131
is the junction depth of the N + source region,
Figure 561617DEST_PATH_IMAGE023
is the effective width of the channel;
further, in SGT MOSFET devices, the source contact specific on-resistance
Figure 23078DEST_PATH_IMAGE124
Can pass through source contact resistance
Figure 113394DEST_PATH_IMAGE003
And area of cell
Figure 108026DEST_PATH_IMAGE120
Obtained by multiplication, i.e.
Figure 625595DEST_PATH_IMAGE132
；
For a stripe-shaped cell, the cell area is
Figure 571423DEST_PATH_IMAGE133
；
Wherein the content of the first and second substances,
Figure 934271DEST_PATH_IMAGE026
is the mesa region width of the SGT MOSFET device;
Figure 767098DEST_PATH_IMAGE027
is the trench width of the SGT MOSFET device;
considering two N + source regions in parallel, the source-to-contact specific on-resistance ends up being
Figure 940722DEST_PATH_IMAGE134
。
In this embodiment, it should be noted that the contact resistivity is determined by the work function of the contact metal and the surface doping concentration of the N + source region. In the power device structure, the common method is to use a low barrier height contact metal to increase the doping concentration of the N + source region to be higher than 5 x 10 19 cm 3 Ensure contact resistivity less than 1 x 10 -5 Ω·cm 2 The metal semiconductor becomes an ohmic contact, thereby avoiding a severe impact on the overall on-resistance of the SGT MOSFET.
Further, in this embodiment, the calculation process of the source area specific on-resistance is specifically as follows:
the current enters the source region from the contact hole and flows through the source region before reaching the channel, and the square resistor of the source region body resistor is diffused by the N + source region
Figure 858999DEST_PATH_IMAGE135
And N + source region lateral length
Figure 289454DEST_PATH_IMAGE030
It was decided that the specific calculation expression is as follows
Figure 242367DEST_PATH_IMAGE136
；
Wherein the content of the first and second substances,
Figure 836159DEST_PATH_IMAGE023
is the effective width of the channel;
the length of the N + source region is related to the cell manufacturing process window, and the length is determined by the following calculation expression
Figure 992465DEST_PATH_IMAGE137
；
Wherein the content of the first and second substances,
Figure 697116DEST_PATH_IMAGE033
for the mesa width of an SGT MOSFET device,
Figure 504535DEST_PATH_IMAGE034
is the contact hole width;
the source region specific on-resistance is defined by the specific on-resistance
Figure 518496DEST_PATH_IMAGE125
Is a bulk resistor of a source region
Figure 411366DEST_PATH_IMAGE004
And area of cell
Figure 936019DEST_PATH_IMAGE138
Obtained by multiplication, i.e.
Figure 863524DEST_PATH_IMAGE139
；
For the stripe-shaped cells, the cell area is as follows
Figure 799119DEST_PATH_IMAGE140
；
In the SGT MOSFET device, each unit cell comprises two source regions, so that the specific on-resistance of the source region is finally obtained by combining the formula
Figure 165903DEST_PATH_IMAGE141
。
Further, in this embodiment, the channel specific on-resistance calculation process specifically includes the following steps:
referring to fig. 2 of the specification, channels in the sgt MOSFET device structure are formed on two longitudinal sidewalls of the gate2 structure, and each channel contributes to a resistance of
Figure 477935DEST_PATH_IMAGE142
；
Wherein, the first and the second end of the pipe are connected with each other,
Figure 10679DEST_PATH_IMAGE143
is the channel length;
Figure 851596DEST_PATH_IMAGE040
electron mobility of the channel region;
Figure 453479DEST_PATH_IMAGE041
is unit area gate oxide capacitance;
Figure 552891DEST_PATH_IMAGE042
is the gate-source voltage;
Figure 189408DEST_PATH_IMAGE043
is the device threshold voltage;
Figure 466806DEST_PATH_IMAGE023
is the effective width of the channel;
the unit area gate oxide layer capacitance and the channel length are obtained by the following two calculation expressions
Figure 572296DEST_PATH_IMAGE045
；
Figure 960552DEST_PATH_IMAGE046
Wherein the content of the first and second substances,
Figure 717156DEST_PATH_IMAGE047
is a vacuum dielectric constant;
Figure 417652DEST_PATH_IMAGE048
is the relative dielectric constant of silicon dioxide;
Figure 994127DEST_PATH_IMAGE049
is the thickness of the gate oxide layer;
Figure 936806DEST_PATH_IMAGE050
junction depth of the Pbody area;
Figure 547916DEST_PATH_IMAGE051
is N + source junction depth;
specific on-resistance of channel contribution in SGT MOSFET devices
Figure 167116DEST_PATH_IMAGE144
Can be controlled by channel resistance
Figure 480155DEST_PATH_IMAGE005
And area of cell
Figure 475792DEST_PATH_IMAGE138
Obtained by multiplication, i.e.
Figure 941409DEST_PATH_IMAGE145
；
For the stripe-shaped cells, the cell area is as follows
Figure 216663DEST_PATH_IMAGE146
；
Wherein the content of the first and second substances,
Figure 767731DEST_PATH_IMAGE147
for the mesa width of an SGT MOSFET device,
Figure 567059DEST_PATH_IMAGE027
is the trench width of the SGT MOSFET device;
in the SGT MOSFET device, two channels exist in the cross section of each structure, and current flows from a source electrode to a drift region, and the specific on-resistance of the channels can be obtained by combining the formula
Figure 139379DEST_PATH_IMAGE148
。
Further, in this embodiment, the calculation process of the specific on-resistance of the drift region is specifically as follows:
firstly, the current flowing out of the channel region is assumed to enter the drift region at a certain divergence angle
Figure 100382DEST_PATH_IMAGE055
Extending toward the drain region, passing through the rectangular drift region and then at the bottom of the trench
Figure 889478DEST_PATH_IMAGE149
The angle is expanded to the substrate and finally straightenedWhen the current flows in the whole drift region, the drift region is divided into the following four parts
(a) The first part
Assuming a channel thickness of
Figure 961339DEST_PATH_IMAGE150
Then there is
Figure 135968DEST_PATH_IMAGE151
；
Wherein the content of the first and second substances,
Figure 48298DEST_PATH_IMAGE041
is unit area gate oxide capacitance;
Figure 308379DEST_PATH_IMAGE042
is the gate-source voltage;
Figure 183931DEST_PATH_IMAGE043
is the device threshold voltage;
Figure 963799DEST_PATH_IMAGE152
is the electron charge amount;
Figure 532184DEST_PATH_IMAGE153
doping concentration of the Pbody area;
current flows from the channel region
Figure 279560DEST_PATH_IMAGE055
The angle is expanded towards the drift region until the drift region is filled with current, and the resistance of the part after flowing out of the channel is
Figure 199281DEST_PATH_IMAGE154
；
Wherein the content of the first and second substances,
Figure 348503DEST_PATH_IMAGE092
is the resistivity of the drift region and,
Figure 838521DEST_PATH_IMAGE066
for the length of the first part of the drift region over which current flows,
Figure 807614DEST_PATH_IMAGE067
is the cross-sectional area of current flow through the first portion of the drift region;
since the partial area is a trapezoid with a narrow upper part and a wide lower part, the cross section area is small
Figure 556127DEST_PATH_IMAGE067
Is carried along
Figure 809123DEST_PATH_IMAGE066
When the partial resistance is obtained, the variable of the change is integrated, and the specific method is as follows:
when current flows through the first part of the drift region, the resistance of the drift region changes with the distance of the current flowing downwards in the current flowing mode, and the depth is
Figure 453731DEST_PATH_IMAGE155
At a position where the current flow cross-sectional width is
Figure 175699DEST_PATH_IMAGE156
；
In a first part of the drift region through which current flows, the depth differential unit
Figure 213057DEST_PATH_IMAGE070
The resistance of the thickness is as follows
Figure 336870DEST_PATH_IMAGE157
；
Wherein the content of the first and second substances,
Figure 404577DEST_PATH_IMAGE023
is the effective width of the channel;
through which current flowsA first partial drift region having a specific on-resistance
Figure 613841DEST_PATH_IMAGE158
And
Figure 438578DEST_PATH_IMAGE073
the resistance integral between and multiplied by the cell area, for a stripe cell, the cell area
Figure 167631DEST_PATH_IMAGE159
Meanwhile, the partial resistance is formed by bilaterally symmetrical parallel connection, so that the specific on-resistance of the first part of the drift region is
Figure 685200DEST_PATH_IMAGE160
；
Wherein, the first and the second end of the pipe are connected with each other,
Figure 365449DEST_PATH_IMAGE026
is the mesa region width of the SGT MOSFET device;
Figure 728297DEST_PATH_IMAGE027
is the trench width of the SGT MOSFET device.
(b) The second part
The current flows in the whole drift region and spreads towards the substrate
Figure 826703DEST_PATH_IMAGE161
；
Wherein the content of the first and second substances,
Figure 265905DEST_PATH_IMAGE077
in order to be the resistivity of the drift region,
Figure 184183DEST_PATH_IMAGE162
for the length of the source field plate region over which current flows after flowing through the first portion of the drift region,
Figure 602919DEST_PATH_IMAGE079
is the cross-sectional area of current flow through the second portion of the drift region;
the length of the current flowing into the source field plate region after the current flows through the first part of the drift region and the cross-sectional area of the current flowing through the second part of the drift region are obtained through the following calculation expressions respectively
Figure 555832DEST_PATH_IMAGE163
；
Figure 149624DEST_PATH_IMAGE164
；
Wherein the content of the first and second substances,
Figure 305930DEST_PATH_IMAGE026
is the mesa region width of the SGT MOSFET device;
Figure 10581DEST_PATH_IMAGE165
junction depth of the Pbody area;
Figure 818000DEST_PATH_IMAGE083
is the depth of the groove;
a second part of drift region through which current flows and the specific on-resistance of which is the cell resistance of the part
Figure 831961DEST_PATH_IMAGE084
And area of cell
Figure 990410DEST_PATH_IMAGE138
Multiplication is carried out to obtain the cell area of the strip-shaped cells
Figure 249484DEST_PATH_IMAGE166
Then the specific on-resistance of the second part of the drift region is
Figure 176989DEST_PATH_IMAGE167
；
Wherein the content of the first and second substances,
Figure 364781DEST_PATH_IMAGE027
is the trench width of an SGT MOSFET device.
(c) Third part
When current flows through the third part of the drift region, the resistance of the drift region changes with the distance of the current flowing downwards in the current flowing mode, and the depth is
Figure 744947DEST_PATH_IMAGE155
At a position where the current flow cross-sectional width is
Figure 56980DEST_PATH_IMAGE168
；
Wherein, the first and the second end of the pipe are connected with each other,
Figure 324144DEST_PATH_IMAGE026
is the mesa region width of the SGT MOSFET device;
in a third part of the drift region through which current flows, the depth differential unit
Figure 430640DEST_PATH_IMAGE070
The resistance of the thickness is as follows
Figure 812949DEST_PATH_IMAGE169
；
A third partial drift region through which current flows and of which the specific on-resistance can be determined by the pair
Figure 928673DEST_PATH_IMAGE170
And
Figure 565190DEST_PATH_IMAGE171
the resistance integral between and multiplied by the cell area, for a stripe cell, the cell area
Figure 124479DEST_PATH_IMAGE090
Then the specific on-resistance of the third part of the drift region is
Figure 805470DEST_PATH_IMAGE172
；
Wherein, the first and the second end of the pipe are connected with each other,
Figure 459305DEST_PATH_IMAGE027
for the trench width of an SGT MOSFET device,
Figure 966641DEST_PATH_IMAGE065
is the drift region resistivity.
(d) Fourth section
Current is supplied to
Figure 946098DEST_PATH_IMAGE056
Flowing towards the substrate after an angular expansion, the partial resistance being
Figure 37420DEST_PATH_IMAGE093
；
Wherein the content of the first and second substances,
Figure 511257DEST_PATH_IMAGE173
in order to be the resistivity of the drift region,
Figure 653526DEST_PATH_IMAGE095
for the length of the rectangular area through which current flows before entering the substrate after flowing through the third portion,
Figure 790502DEST_PATH_IMAGE096
the cross-sectional area of the drift region of the fourth part through which current flows;
the length of the current flowing through the rectangular region and the cross-sectional area of the drift region of the fourth part through which the current flows before the current flows into the substrate after flowing through the third part are respectively obtained through the following calculation expressions
Figure 119853DEST_PATH_IMAGE097
；
Figure 131802DEST_PATH_IMAGE174
；
Wherein the content of the first and second substances,
Figure 394156DEST_PATH_IMAGE175
is the epitaxial layer thickness of the device;
a fourth part drift region through which current flows, the specific on-resistance of which is the cell resistance of the part
Figure 964684DEST_PATH_IMAGE100
And area of cell
Figure 63221DEST_PATH_IMAGE138
Multiplication is carried out to obtain the cell area of the strip-shaped cells
Figure 862550DEST_PATH_IMAGE112
Then the specific on-resistance of the fourth part of the drift region is
Figure 700449DEST_PATH_IMAGE176
；
Finally, the total on-resistance of the drift region is the sum of the on-resistances of the four parts, i.e.
Figure 192610DEST_PATH_IMAGE177
。
Further, in this embodiment, the calculation process of the substrate specific on-resistance is specifically as follows:
when the current passes through the bottom of the drift region and then rapidly diffuses to the whole heavily doped substrate, the current passing through the substrate can be assumed to enter a uniform cross-section area, and the cellular resistance of the substrate
Figure 247285DEST_PATH_IMAGE104
Is composed of
Figure 319146DEST_PATH_IMAGE178
；
Figure 274202DEST_PATH_IMAGE106
；
Figure 406106DEST_PATH_IMAGE107
；
Wherein the content of the first and second substances,
Figure 931765DEST_PATH_IMAGE179
is the resistivity of the substrate and is,
Figure 558049DEST_PATH_IMAGE180
in order for the cell current to flow through the thickness of the substrate,
Figure 118344DEST_PATH_IMAGE110
is the cross-sectional area of the cell current flowing through the substrate;
Figure 938926DEST_PATH_IMAGE111
is the substrate thickness;
the specific on-resistance of the substrate is defined as the cell resistance
Figure 686302DEST_PATH_IMAGE104
And area of cell
Figure 365545DEST_PATH_IMAGE120
Obtained by multiplication, for a stripe-shaped cell, its cell area
Figure 265499DEST_PATH_IMAGE112
Then there is a substrate specific on-resistance of
Figure 270364DEST_PATH_IMAGE113
。
Further, in the present embodiment, the drain contact resistance is obtained by the following calculation expression
Figure 754304DEST_PATH_IMAGE181
；
Wherein the content of the first and second substances,
Figure 971658DEST_PATH_IMAGE130
in order to achieve a contact resistance ratio,
Figure 240966DEST_PATH_IMAGE026
for the mesa width of an SGT MOSFET device,
Figure 901885DEST_PATH_IMAGE027
is the trench width of the SGT MOSFET device;
the specific on-resistance is defined as the drain contact resistance
Figure 889433DEST_PATH_IMAGE182
And area of cell
Figure 150957DEST_PATH_IMAGE138
Are multiplied by each other to obtain
Figure 9192DEST_PATH_IMAGE183
；
For stripe shaped cells, the cell area
Figure 90280DEST_PATH_IMAGE101
Then the drain contact specific on-resistance ends up being
Figure 50277DEST_PATH_IMAGE184
。
In this embodiment, it should be noted that the current needs to pass through the drain contact resistor between the drain metal and the substrate before reaching the drain, and since the drain contact current flows uniformly, a resistance value smaller than that of the drain contact terminal can be obtained
Figure 875014DEST_PATH_IMAGE185
Ideal resistance and therefore drain contact resistance is usually neglected.
And S102, verifying the established specific on-resistance model of the SGT MOSFET device by adopting simulation software.
In the present embodiment, it should be noted that the divergence angle is specifically introduced by the present invention
Figure 102601DEST_PATH_IMAGE055
And
Figure 89012DEST_PATH_IMAGE149
therefore, the method adopts Silvaco software to verify the established specific on-resistance model of the SGT MOSFET device and determine the divergence angle
Figure 51152DEST_PATH_IMAGE055
And
Figure 164732DEST_PATH_IMAGE149
and the value of the angle, thereby determining a calculation expression of the specific on-resistance of the whole drift region, and finally determining a calculation expression of a specific on-resistance model of the whole device.
And S103, drawing a curve chart of the specific on-resistance of the SGT MOSFET device along with the change of the platform area width and the groove width according to a final calculation expression of the specific on-resistance model of the SGT MOSFET device, obtaining the platform area width and the groove width of the SGT MOSFET device at the optimal specific on-resistance according to the drawn chart and by combining process flow conditions (namely within a process condition allowable range) formulated by a chip manufacturer, and taking the platform area width and the groove width as guide parameters during device design.
In this embodiment, the computational expression of the SGT MOSFET device specific on-resistance model is a mathematical relationship relating the device mesa region width and trench width.
In this embodiment, the horizontal axis of the graph is the mesa width of the SGT MOSFET device and the vertical axis is the specific on-resistance of the device. When a curve chart is drawn, the width of a groove of the SGT MOSFET device is fixed to be unchanged, the specific on-resistance of the device is calculated under the condition of different platform area widths, so that a curve is obtained, then the groove width is converted, so that a plurality of curves are obtained in the chart, and the drawing of the curve chart of the SGT MOSFET device specific on-resistance changing along with the platform area width and the groove width is completed; after the chart is drawn, the mesa region width and the trench width corresponding to the value of the lowest point are selected as design structure parameters of the SGT MOSFET device in all curves according to the process flow conditions (i.e., within the allowable range of the device processing process conditions) formulated by the chip manufacturing factory for guiding the production and processing of the device. Therefore, in the present invention, when an SGT MOSFET device is actually designed and produced, the mesa region width and the trench width corresponding to the optimal specific on-resistance of the device need not only meet the requirement of the optimal specific on-resistance of the device, but also the two parameters need to be within the allowable range of the process flow conditions set by the chip manufacturing factory, that is, under the parameter conditions, the device can not only reach the optimal specific on-resistance, but also be successfully manufactured. The process flow conditions established by a chip manufacturing plant are related to the level and capability of the chip manufacturing plant.
Further, according to the SGT MOSFET device specific on-resistance physical model established as above, the specific on-resistance value of the 60V SGT MOSFET is calculated and verified in the further embodiment of the present invention.
Referring to the specification, fig. 4, a device structure with a voltage of 60V is simulated by simulation software, and a current flowing out of a channel region is seen in the figure and enters a drift region at a certain divergence angle
Figure 263138DEST_PATH_IMAGE055
Extend to the drain region in view of
Figure 672648DEST_PATH_IMAGE055
The angle is very small while the SGT MOSFET drift region doping concentration is high, so it can be approximated that current flows throughout the rectangular drift region. The current flowing out of the channel region enters the drift regionThe drain region flows at the bottom of the trench
Figure 856504DEST_PATH_IMAGE056
The angle is expanded towards the substrate and is obtained by simulation and experience
Figure 23043DEST_PATH_IMAGE186
，
Figure 461109DEST_PATH_IMAGE187
And finally directly to the substrate.
The resistance of the whole drift region of the device obtained by combining the analysis can be simplified into three parts for calculation, and the calculation modes of the resistance of other regions of the device are unchanged. When in use
Figure 54901DEST_PATH_IMAGE186
，
Figure 460475DEST_PATH_IMAGE187
When the current flows through the first partial region of the drift region, the first partial region is not trapezoidal any more, but is changed into a rectangular region, the first partial resistance and the second partial resistance of the drift region through which the current flows can be calculated in a combined mode, and the combined resistance calculation expression is as follows
Figure 945552DEST_PATH_IMAGE188
；
Further, the length and area of the current flowing through the merging section are obtained by the following calculation expression
Figure 752971DEST_PATH_IMAGE189
；
Figure 268397DEST_PATH_IMAGE190
；
The specific on-resistance of the combined part is obtained by multiplying the cell resistance by the cell area
Figure 161267DEST_PATH_IMAGE191
；
The specific on-resistance of the original third partial region of the drift region through which the current flows is changed to
Figure 669608DEST_PATH_IMAGE192
；
The specific on-resistance of the original fourth partial region of the drift region through which the current flows is changed to
Figure 583731DEST_PATH_IMAGE193
；
Therefore, the specific on-resistance of the whole drift region is finally added to the above three parts as follows
Figure 784905DEST_PATH_IMAGE195
。
Referring to the specification, fig. 5 is a graph of the specific on-resistance of a 60V SGT MOSFET as a function of trench width and mesa width. As can be seen from fig. 5, under the process flow conditions defined by the chip manufacturing factory (i.e., within the allowable range of the process conditions), the mesa width of the device
Figure 915803DEST_PATH_IMAGE196
Width of trench
Figure 962257DEST_PATH_IMAGE197
There is an optimum value to make the specific on-resistance of the device minimum at this time, so that during design, the mesa region width and the trench width of the device are respectively 1.15 and 0.75, and finally the specific on-resistance value and the percentage of the device in each region are obtained as shown in table 1 below.
Figure 744268DEST_PATH_IMAGE199
Finally, the simulation is performed again through the semiconductorThe tool Silvaco verifies and simulates the structural parameters
Figure 100032DEST_PATH_IMAGE196
And
Figure 233073DEST_PATH_IMAGE197
the structure of the device simulates that 10V starting voltage is added at two ends of a grid source, and the total specific on-resistance of the device is 14 mohm.mm2 when 0.1V bias voltage is added at a drain, which is similar to the specific on-resistance value 13.3 mohm.mm2 obtained by calculation by using a physical model.
The foregoing is directed to the preferred embodiment of the present invention, which is not intended to be exhaustive or to limit the invention to the precise form disclosed, and all modifications and equivalents of the above-described embodiment may be resorted to, falling within the scope of the invention.

Claims (2)

1. An SGT MOSFET device optimization design method is characterized by comprising the following steps:
acquiring the on-resistance of the SGT MOSFET device, and establishing a specific on-resistance model of the SGT MOSFET device according to the acquired on-resistance;
verifying a specific on-resistance model of the SGT MOSFET device by adopting simulation software;
drawing a curve chart of the change of the specific on-resistance of the SGT MOSFET device along with the width of the platform area and the width of the groove, and selecting the width of the platform area and the width of the groove when the device has the optimal specific on-resistance as the structural design parameters of the SGT MOSFET device according to the curve chart;
the obtaining of the on-resistance of the SGT MOSFET device and the establishing of the SGT MOSFET device specific on-resistance model according to the obtained on-resistance comprise:
the on-resistance of an SGT MOSFET device is composed of a source contact resistance, a source body resistance, a channel resistance, a drift region resistance, a substrate resistance and a drain contact resistance, and then
Figure 173443DEST_PATH_IMAGE001
；
Wherein the content of the first and second substances,
Figure 28267DEST_PATH_IMAGE002
is the on-resistance of the SGT MOSFET device,
Figure 296087DEST_PATH_IMAGE003
is a resistance of the source contact, and,
Figure 35504DEST_PATH_IMAGE004
is a body contact resistance of the source region,
Figure 459663DEST_PATH_IMAGE005
in order to be the channel resistance,
Figure 13616DEST_PATH_IMAGE006
is a resistance of the drift region and is,
Figure 624857DEST_PATH_IMAGE007
is a resistance of the substrate and is,
Figure 433545DEST_PATH_IMAGE008
is a drain contact resistance;
defining the on-resistance in unit area as the specific on-resistance of SGT MOSFET device, and the number of cells in unit area
Figure 782050DEST_PATH_IMAGE009
Because each cell is in parallel connection, the specific on-resistance of the SGT MOSFET device is
Figure 244255DEST_PATH_IMAGE010
；
Wherein, the first and the second end of the pipe are connected with each other,
Figure 342792DEST_PATH_IMAGE011
is the cell area;
then, the calculation expression of the specific on-resistance model of the SGT MOSFET device is as follows
Figure 30869DEST_PATH_IMAGE012
；
Wherein the content of the first and second substances,
Figure 757517DEST_PATH_IMAGE013
is the specific on-resistance of the SGT MOSFET device;
Figure 141356DEST_PATH_IMAGE014
source contact specific on-resistance;
Figure 323594DEST_PATH_IMAGE015
the source region specific on-resistance;
Figure 677346DEST_PATH_IMAGE016
is the channel specific on-resistance;
Figure 540391DEST_PATH_IMAGE017
is the drift region specific on-resistance;
Figure 216836DEST_PATH_IMAGE018
substrate specific on-resistance;
Figure 821123DEST_PATH_IMAGE019
drain contact specific on-resistance;
the calculation process of the source contact specific on-resistance is specifically as follows:
the contact resistance to the N + source region in the cell structure of the SGT MOSFET device is determined by the contact resistivity and the junction depth of the N + source region, and the calculation expression is as follows
Figure 634359DEST_PATH_IMAGE020
；
Wherein the content of the first and second substances,
Figure 7702DEST_PATH_IMAGE021
in order to achieve a contact resistance ratio,
Figure 403785DEST_PATH_IMAGE022
is the junction depth of the N + source region,
Figure 964210DEST_PATH_IMAGE023
is the effective width of the channel;
the specific on-resistance is defined as the product of the source contact resistance multiplied by the cell area
Figure 456502DEST_PATH_IMAGE024
；
For the stripe-shaped cells, the cell area is as follows
Figure 684353DEST_PATH_IMAGE025
；
Wherein, the first and the second end of the pipe are connected with each other,
Figure 109124DEST_PATH_IMAGE026
is the mesa region width of the SGT MOSFET device;
Figure 156846DEST_PATH_IMAGE027
is the trench width of the SGT MOSFET device;
in an SGT MOSFET device, the source is formed by two N + source regions connected in parallel, so the source contact specific on-resistance is
Figure 780725DEST_PATH_IMAGE028
；
The calculation process of the source region specific on-resistance is specifically as follows:
current enters the source region from the contact hole and flows through the source region before reaching the channelSquare resistor with body resistor diffused from N + source region
Figure 600432DEST_PATH_IMAGE029
And N + source region lateral length
Figure 589248DEST_PATH_IMAGE030
Deciding, calculating the expression as follows
Figure 124266DEST_PATH_IMAGE031
；
Wherein, the first and the second end of the pipe are connected with each other,
Figure 565218DEST_PATH_IMAGE032
is the effective width of the channel;
the length of the N + source region is determined by the following calculation expression
Figure 236502DEST_PATH_IMAGE033
；
Wherein, the first and the second end of the pipe are connected with each other,
Figure 989694DEST_PATH_IMAGE034
for the mesa width of an SGT MOSFET device,
Figure 746429DEST_PATH_IMAGE035
is the contact hole width;
the specific on-resistance is defined as the product of the contact resistance of the source region and the cell area
Figure 719633DEST_PATH_IMAGE036
；
For the stripe-shaped cells, the cell area is as follows
Figure 776582DEST_PATH_IMAGE037
；
Wherein the content of the first and second substances,
Figure 576042DEST_PATH_IMAGE027
is the trench width of the SGT MOSFET device;
in an SGT MOSFET device, two source regions are included in each cell, so the source region has a body-to-body specific on-resistance of
Figure 82722DEST_PATH_IMAGE038
；
The calculation process of the channel specific on-resistance is specifically as follows:
the channels in the SGT MOSFET device structure are formed on two longitudinal side walls of the gate2 structure, and each channel contributes to the resistance
Figure 524199DEST_PATH_IMAGE039
；
Figure 560288DEST_PATH_IMAGE040
；
Figure 999491DEST_PATH_IMAGE041
；
Wherein the content of the first and second substances,
Figure 874693DEST_PATH_IMAGE042
is the channel length;
Figure 854281DEST_PATH_IMAGE043
electron mobility of the channel region;
Figure 354664DEST_PATH_IMAGE044
is unit area gate oxide capacitance;
Figure 758576DEST_PATH_IMAGE045
is the gate-source voltage;
Figure 101832DEST_PATH_IMAGE046
is the device threshold voltage;
Figure 619533DEST_PATH_IMAGE023
is the effective width of the channel;
Figure 240001DEST_PATH_IMAGE047
is a vacuum dielectric constant;
Figure 442179DEST_PATH_IMAGE048
is the relative dielectric constant of silicon dioxide;
Figure 741574DEST_PATH_IMAGE049
is the thickness of the gate oxide layer;
Figure 62965DEST_PATH_IMAGE050
junction depth of the Pbody area;
Figure 269431DEST_PATH_IMAGE051
n + source junction depth;
is defined by specific on-resistance, which is obtained by multiplying channel resistance by cell area
Figure 627862DEST_PATH_IMAGE052
；
For the stripe-shaped cells, the cell area is as follows
Figure 555498DEST_PATH_IMAGE053
；
Wherein the content of the first and second substances,
Figure 745826DEST_PATH_IMAGE054
for the mesa width of an SGT MOSFET device,
Figure 685095DEST_PATH_IMAGE027
is the trench width of the SGT MOSFET device;
in an SGT MOSFET device, two channels exist in the cross section of each structure, and current flows from a source electrode to a drift region, so that the specific on-resistance of the channel is
Figure 604640DEST_PATH_IMAGE055
；
The calculation process of the specific on-resistance of the drift region is specifically as follows:
assuming that the current flowing out of the channel region enters the drift region at a certain divergence angle
Figure 406855DEST_PATH_IMAGE056
Extending to the drain region, passing through the rectangular drift region and then at the bottom of the trench
Figure 70049DEST_PATH_IMAGE057
The angle is expanded towards the substrate and finally the current directly flows towards the substrate, so that when the current flows in the whole drift region, the drift region is divided into the following four parts
(a) The first part
Assuming a channel thickness of
Figure 254037DEST_PATH_IMAGE058
Then there is
Figure 211061DEST_PATH_IMAGE059
；
Wherein the content of the first and second substances,
Figure 113289DEST_PATH_IMAGE044
is unit area gate oxide capacitance;
Figure 845753DEST_PATH_IMAGE045
is the gate-source voltage;
Figure 149826DEST_PATH_IMAGE060
is the device threshold voltage;
Figure 408245DEST_PATH_IMAGE061
is the electron charge amount;
Figure 328927DEST_PATH_IMAGE062
doping concentration of the Pbody area;
current flows from the channel region
Figure 458557DEST_PATH_IMAGE056
The angle is expanded towards the drift region until the current is filled in the drift region, and the resistance of the part after flowing out of the channel is as follows:
Figure 351558DEST_PATH_IMAGE063
；
wherein, the first and the second end of the pipe are connected with each other,
Figure 396524DEST_PATH_IMAGE064
in order to be the resistivity of the drift region,
Figure 7765DEST_PATH_IMAGE065
for the length of the first part of the drift region over which current flows,
Figure 82032DEST_PATH_IMAGE066
is the cross-sectional area of current flow through the first portion of the drift region;
when current flows through the first portion of the drift region, its resistance changes as the distance the current flows downward increases, at a depth of
Figure 216822DEST_PATH_IMAGE067
At a position where the current flow cross-sectional width is
Figure 85552DEST_PATH_IMAGE068
；
In a first part of the drift region through which current flows, a depth differential unit
Figure 449669DEST_PATH_IMAGE069
The resistance of the thickness is as follows
Figure 967824DEST_PATH_IMAGE070
；
Wherein, the first and the second end of the pipe are connected with each other,
Figure 100996DEST_PATH_IMAGE023
is the effective width of the channel;
a first part of drift region through which current flows and the specific on-resistance of which passes through the pair
Figure 140627DEST_PATH_IMAGE071
And
Figure 851094DEST_PATH_IMAGE072
the product of the resistances is multiplied by the area of the cell, and the resistance is composed of the left and right symmetrical parallel connection, for the strip-shaped cell, the cell area
Figure 998654DEST_PATH_IMAGE073
Then the specific on-resistance of the first part of the drift region is
Figure 251912DEST_PATH_IMAGE074
；
Wherein the content of the first and second substances,
Figure 462445DEST_PATH_IMAGE026
is the mesa region width of the SGT MOSFET device;
Figure 148291DEST_PATH_IMAGE027
is the trench width of the SGT MOSFET device;
(b) The second part
The current flows in the whole drift region and spreads towards the substrate, and the partial resistance is
Figure 430368DEST_PATH_IMAGE075
；
Figure 803711DEST_PATH_IMAGE076
；
Figure 919566DEST_PATH_IMAGE077
；
Wherein the content of the first and second substances,
Figure 742641DEST_PATH_IMAGE078
in order to be the resistivity of the drift region,
Figure 500513DEST_PATH_IMAGE079
for the length of the source field plate region over which current flows after flowing through the first portion of the drift region,
Figure 462784DEST_PATH_IMAGE080
for the current to flow through the cross-sectional area of the second part of the drift region,
Figure 881696DEST_PATH_IMAGE026
is the mesa region width of the SGT MOSFET device;
Figure 929417DEST_PATH_IMAGE081
junction depth of the Pbody area;
Figure 959821DEST_PATH_IMAGE082
is the depth of the groove;
a second part of drift region through which current flows and the specific on-resistance of which is the cell resistance of the part
Figure 901233DEST_PATH_IMAGE083
Multiplied by the cell area, for a stripe cell, the cell area
Figure 355960DEST_PATH_IMAGE084
Then the specific on-resistance of the second part of the drift region is
Figure 890978DEST_PATH_IMAGE085
；
Wherein the content of the first and second substances,
Figure 725073DEST_PATH_IMAGE027
is the trench width of the SGT MOSFET device;
(c) Third part
When current flows through the third portion of the drift region, its resistance changes with increasing distance that the current flows downward, at a depth of
Figure 274653DEST_PATH_IMAGE067
At a position where the current flow cross-sectional width is
Figure 496687DEST_PATH_IMAGE086
；
Wherein the content of the first and second substances,
Figure 519000DEST_PATH_IMAGE026
is the mesa region width of the SGT MOSFET device;
in a third part of the drift region through which current flows, a depth differential unit
Figure 498064DEST_PATH_IMAGE069
The resistance of the thickness is as follows
Figure 289434DEST_PATH_IMAGE087
；
A third part of drift region for passing current, the specific on-resistance of which is passed through
Figure 354473DEST_PATH_IMAGE088
And
Figure 864083DEST_PATH_IMAGE089
the product of resistance between the two is multiplied by the cell area, and for the strip-shaped cells, the cell area is obtained
Figure 913683DEST_PATH_IMAGE090
Then the specific on-resistance of the third part of the drift region is
Figure 559560DEST_PATH_IMAGE091
；
Wherein the content of the first and second substances,
Figure 795500DEST_PATH_IMAGE027
for the trench width of an SGT MOSFET device,
Figure 399263DEST_PATH_IMAGE092
is the drift region resistivity;
(d) Fourth section
Current is supplied to
Figure 378852DEST_PATH_IMAGE093
Flowing towards the substrate after an angular expansion, the partial resistance being
Figure 738289DEST_PATH_IMAGE094
；
Figure 613972DEST_PATH_IMAGE095
；
Figure 507629DEST_PATH_IMAGE096
；
Wherein the content of the first and second substances,
Figure 635116DEST_PATH_IMAGE097
in order to be the resistivity of the drift region,
Figure 987075DEST_PATH_IMAGE098
for the length of the rectangular area through which current flows before entering the substrate after flowing through the third portion,
Figure 564818DEST_PATH_IMAGE099
the cross-sectional area of the drift region of the fourth part through which current flows;
Figure 395371DEST_PATH_IMAGE100
is the epitaxial layer thickness of the device;
a fourth part drift region through which current flows, the specific on-resistance of which is the cell resistance of the part
Figure 185603DEST_PATH_IMAGE101
Multiplied by the cell area, for a stripe cell, the cell area
Figure 917368DEST_PATH_IMAGE102
Then the specific on-resistance of the fourth part of the drift region is
Figure 541379DEST_PATH_IMAGE103
；
Finally, the total on-resistance of the drift region is the sum of the four partial on-resistances, i.e.
Figure 734594DEST_PATH_IMAGE104
；
The calculation process of the substrate specific on-resistance is specifically as follows:
when the current passes through the bottom of the drift region and then rapidly diffuses to the whole heavily doped substrate, the current passing through the substrate can be assumed to enter a uniform cross-section area, and the cell resistance of the substrate
Figure 591167DEST_PATH_IMAGE105
Is composed of
Figure 186228DEST_PATH_IMAGE106
；
Figure 230407DEST_PATH_IMAGE107
；
Figure 645339DEST_PATH_IMAGE108
；
Wherein the content of the first and second substances,
Figure 921249DEST_PATH_IMAGE109
is the resistivity of the substrate and is,
Figure 105237DEST_PATH_IMAGE110
in order for the cell current to flow through the thickness of the substrate,
Figure 195684DEST_PATH_IMAGE111
is the cross-sectional area of the cell current flowing through the substrate;
Figure 219616DEST_PATH_IMAGE112
is the substrate thickness;
the specific on-resistance of the substrate is obtained by multiplying the cell resistance of the substrate by the cell area, and for the strip-shaped cells, the cell area
Figure 686501DEST_PATH_IMAGE113
Then there is a substrate specific on-resistance of
Figure 990574DEST_PATH_IMAGE114
；
The drain contact resistance is obtained by the following calculation expression
Figure 251922DEST_PATH_IMAGE115
；
Wherein the content of the first and second substances,
Figure 797040DEST_PATH_IMAGE021
in order to achieve a contact resistance ratio,
Figure 802037DEST_PATH_IMAGE026
for the mesa width of an SGT MOSFET device,
Figure 960617DEST_PATH_IMAGE027
is the trench width of the SGT MOSFET device;
defined by the specific on-resistance, the drain contact specific on-resistance is the product of the drain contact resistance times the cell area, for a stripe cell, the cell area
Figure 514570DEST_PATH_IMAGE116
Then the drain contact specific on-resistance ends up being
Figure 125811DEST_PATH_IMAGE117
。
2. The SGT MOSFET device optimization design method of claim 1, wherein the verifying the SGT MOSFET device specific on-resistance model by using simulation software is to use Silvaco software to the SGT MOSFET deviceVerifying the specific on-resistance model and finally determining the divergence angle
Figure 278706DEST_PATH_IMAGE118
And
Figure 294722DEST_PATH_IMAGE093
the value of the angle.
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