CN111106161A - MOSFET ideal switch structure with small specific on-resistance - Google Patents
MOSFET ideal switch structure with small specific on-resistance Download PDFInfo
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- 108010075750 P-Type Calcium Channels Proteins 0.000 claims description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 3
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- MCMSPRNYOJJPIZ-UHFFFAOYSA-N cadmium;mercury;tellurium Chemical compound [Cd]=[Te]=[Hg] MCMSPRNYOJJPIZ-UHFFFAOYSA-N 0.000 claims description 2
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- 229910052581 Si3N4 Inorganic materials 0.000 description 3
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
Abstract
A novel MOSFET ideal switch structure with small specific on-resistance relates to a semiconductor device and a related process realization method. The novel MOSFET ideal switch with small specific on-resistance adopts a device structure with longitudinal and four-sided grids. The key technical problems to be solved by the invention are as follows: the novel MOSFET ideal switch structure with small specific on-resistance and the process realization method thereof are provided, the structure of an N-type MOSFET, an N-drift region and four-side channels is adopted, and the selection of semiconductor materials is adopted, so that the on-current density is increased, the on-resistance is reduced, the Moore's law is broken through, a parasitic BJT is eliminated, and the area of a device is greatly reduced; meanwhile, the process implementation flow is optimized, the device implementation process is simplified, and the limitation of photoetching precision is avoided.
Description
Technical Field
The invention relates to microelectronics and semiconductor technology.
Background
Since the 60 s of the last century, the development of integrated circuits has been in three general directions, namely, high speed, low power, and large-scale integration. In terms of speed, the performance of the components as switches plays a decisive role, an ideal switch needs to have no voltage drop when switched on and no current when switched off, and the switching time is zero. The rapid development of integrated circuits capable of processing frequencies from the first tens of hertz to the RF of today has benefited from the beginning of the last 80 th century, MOS devices gradually replaced the role of triodes due to their superior switching characteristics, and MOS transistors have been continuously reduced in size following moore's law while improving the scale and performance of integrated circuits. Therefore, optimizing MOS structure devices is nevertheless a major research direction to improve the processing power of integrated circuits. The MOSFET is divided into an N type and a P type, wherein a carrier of the N type is an electron, a carrier of the P type is a hole, and the speed of the electron is about 3 times that of the hole, so that the N type MOSFET is selected for obtaining a high-speed ideal switch.
Silicon and germanium are the semiconductor materials discovered at the earliest time and are generally accepted as the first-generation semiconductor materials, but the forbidden bandwidth of germanium is smaller than that of silicon, although silicon is the mainstream of the existing semiconductor materials due to abundant resources, low cost and process support, partial use of germanium can enable semiconductor devices to have better performanceGood performance. Patent entitled "narrow forbidden band source drain region metal oxide semiconductor field effect transistor and integrated circuit" in inventor lie teaching "[1]It is proposed that a narrow bandgap hetero-material different from the substrate material of the device is used as the source region or the source and drain regions of the device, so that the parasitic BJT emitter junction in the device is a hetero-junction, and β is provided<<1, can completely eliminate the parasitic BJT pair BV from the deviceDSThe influence of (c).
FinFET, named FinFET in Chinese, is proposed by the formal published paper of around 2000 in the Ministry of California Berkeley[2]. The FinFET is mainly characterized in that a channel region is a fin-shaped semiconductor wrapped by a grid electrode, and the length of a fin along the source-drain direction is the channel length.
The FinFET channel is typically lightly doped or even undoped, avoiding scattering of discrete dopant atoms, and the carrier mobility is greatly improved compared to heavily doped planar devices. In addition, compared with the traditional planar CMOS, the semi-ring gate fin-shaped structure of the FinFET increases the control area of the gate to the channel, so that the gate control capability is greatly enhanced, the short channel effect can be effectively inhibited, and the sub-threshold leakage current is reduced. Because of the suppression of the short channel effect and the enhancement of the gate control capability, the FINFET device can use a thicker gate oxide than conventional ones, so that the gate leakage current of the FINFET device can also be reduced. FINFETs, instead of the traditional planar CMOS after the 20nm technology node, were initially selected by various large chip manufacturers, now mass-produced is the 7nm process, and mesa integration is expected to start mass-producing 5nm process chips at 7 months of the next year. However, the FINFET process still relies on multiple exposures to achieve ultra-small scale processes, i.e., the process still requires more complex processes at small scale.
Reference to the literature
[1] Plum blossom; li Zhaoji, narrow forbidden band source-drain region metal oxide semiconductor field effect transistor and integrated circuit, China, CN96117551.6[ P ].1997.11.19.
[2] The Chinese semiconductor technology lags behind the international industry, and the breakthrough is known first about FinFET and Huzhengming [ N ]. Alias, 2017, month 01, 13.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: a device structure of an ideal MOSFET switch with a smaller specific on-resistance is provided, which provides a smaller specific on-resistance, a larger current, a higher withstand voltage, a smaller area, and a simplified implementation process in a small-sized device.
The structure of the invention adopts the semiconductor materials germanium and germanium-silicon with narrow forbidden band as the source region, so that the parasitic BJT in the device becomes a heterojunction triode with an emitting region and β<<1, can completely eliminate the parasitic BJT pair BV from the deviceDSThe need for a structure to short the substrate and source regions to ground is eliminated, thus saving a significant amount of area required for substrate contact openings. Meanwhile, other materials with narrow forbidden bands besides germanium can be used as the source region, such as GeSi, HgTe, InP and the like, so that the flexibility of device design is increased. And when germanium is used as a source region, a conventional epitaxial or LPCVD process is adopted, and because germanium and silicon have stress per se, single crystals or pseudomorphic crystals or polycrystal crystals can be used to optimize the process flow.
In the structure, the channel semiconductor region is made of Si material, and the source electrode region is made of narrow-gap semiconductor material; or, the channel semiconductor region material is a wide bandgap semiconductor material, and the source region is a narrow bandgap semiconductor material; or, the channel semiconductor region material is a wide bandgap semiconductor material, and the source region is a Si material.
The grid electrode of the structure surrounds the device body area, so when proper bias is applied to the grid electrode, a four-side channel is formed, the grid control capability can be increased through a multi-side grid structure like a FINFET, and the grid control capability is even better than that of the three-side channel of the FINFET, the grid control capability is increased, the current density in conduction is improved, and the specific on resistance is reduced. More faceted surrounding gate structures, such as six-sided, etc., may also be used.
The channel region of the structure of the invention is not completed by a photoetching process, so the channel length is not limited by the photoetching precision any more. The body region of the channel formed in the new structure is completed by an epitaxial process, and the thickness of the epitaxial layer is the length of the channel, so that a large amount of cost required by photoetching and complex process flows such as multiple exposure and the like for achieving required precision are saved. At present, the molecular beam epitaxy process technology can prepare a single crystal film as thin as tens of atomic layers, and can realize an extremely short channel length.
The structure of the invention adopts the structure that the N-doped region is added at the front end of the drain region, so that the voltage resistance is greatly improved, and the short channel effect can be effectively inhibited. Nowadays, in the aspect of an extremely short channel device, a FINFET is mainly used in research or market because the FINFET can effectively suppress short channel effect, but the suppression principle of the short channel effect is that the control capability of a fin-shaped structure gate is strong, so the FINFET still follows moore's law, and under the premise that the electric field strength and the current density are not changed, the voltage and the size need to be reduced in equal proportion, that is, the operating voltage of the device is limited by the size. However, the new structure is mainly resistant to the voltage of the N-drift region, and the breakdown voltage of the device is no longer related to the length of a channel, namely the limitation of Moore's law is broken through. Meanwhile, the N-doped region naturally forms an LDD structure, so that the short-channel effect can be effectively inhibited.
The invention has the beneficial effects that:
1) the structure of the invention uses materials of narrow forbidden bands such as germanium, germanium-silicon and the like as the source region, eliminates the influence of the intrinsic parasitic BJT in the MOS device, does not need the area of an opening due to substrate contact, and greatly reduces the area. The source region and the channel semiconductor region are made of different materials, so that the semiconductor material of the source region can be monocrystalline, pseudomorphic or polycrystalline.
2) The structure of the invention forms channels on four sides when in conduction, thereby effectively increasing the current density and reducing the on-resistance.
3) The channel length of the structure of the invention does not depend on the photoetching process any more, and the process is simplified and the cost is reduced while the extremely short channel length is realized.
4) The structure of the invention adopts an N-drift region structure, breaks through Moore's law, and enables the voltage not to be reduced in proportion to the size. Meanwhile, the LDD structure formed naturally can also effectively inhibit short channel effect in small size.
Drawings
FIG. 1 is a schematic diagram of the three-dimensional structure of a transistor according to the present invention, showing its basic structure;
FIG. 2 is a perspective view of the three-dimensional structure of the transistor of the present invention, showing its basic structure;
FIG. 3 is a schematic plan view of the new structure;
FIG. 4 is a cross-sectional view and a plan view of a (left) conventional TMOS (right) conventional TMOS (without a metal layer and an oxide layer covering the device surface in the plan view, with the gate electrode led out from another direction), illustrating that the structure of the present invention can significantly reduce the area
FIG. 5 is a flow chart of a process implementation of a new structure device;
fig. 6 is a plan view of a plurality of new structures after processing, wherein the source regions are connected by metal layers and oxide layer isolation (not shown) is provided on the gate electrodes.
Reference numbers in fig. 1: the transistor comprises a 1N + drain region, a 2N-lightly doped layer, a 3P type channel semiconductor region, a 4N + source region, a 5 gate dielectric layer and a 6 gate electrode layer.
Detailed Description
An ideal switch structure of MOSFET with small specific on-resistance is provided, wherein the lowest part is an N + drain region, an N-lightly doped layer is arranged above the drain region, a P-type channel semiconductor region is arranged above the N-lightly doped layer, an N + source region is arranged above the P-type channel semiconductor region, and a gate dielectric layer and a gate electrode are surrounded.
The gate electrode may be N + polysilicon, or metal, or a combination of the two.
The source electrode region is made of narrow-gap semiconductor materials such as single crystal Ge, polycrystalline Ge, pseudomorphic Ge, SiGe, mercury cadmium telluride and InP.
The channel semiconductor region is made of Si material, and the source region is made of narrow-gap semiconductor materials such as single crystal Ge, polycrystalline Ge, pseudomorphic Ge, SiGe, tellurium-cadmium-mercury, InP and the like; or, the channel semiconductor region material is a wide bandgap semiconductor material, and the source region is a narrow bandgap semiconductor material; or, the channel semiconductor region material is a wide bandgap semiconductor material, and the source region is a Si material.
The gate dielectric layer and the gate electrode are surrounded.
Referring to fig. 5:
example 1: the process for realizing the new device structure process comprises the following steps
(a) Extending an N-silicon layer on the N + doped silicon substrate;
(b) extending a P silicon layer on the N-epitaxial layer;
(c) extending an N + germanium layer on the P layer;
(d) growing silicon nitride as a protective layer by a deposition process;
(e) etching to form a groove by using an RIE process;
(f) ALD growing a thin gate oxide layer;
(g) filling grid polysilicon or metal or a combination of polysilicon and metal by a deposition process;
(h) the polishing process grinds the surface of the device, but leaves silicon nitride and polysilicon with certain thickness;
(i) oxidizing polysilicon with a certain thickness to form a gate electrode isolation layer;
(j) and etching away the silicon nitride by a wet method.
Example 2: switch with a switch body
This embodiment is a switching device formed using the transistor structure of embodiment 1. The on and off of the device is controlled by controlling the voltage of the grid electrode, so that the switching function is realized.
Claims (6)
1. An ideal switch structure of MOSFET with small specific on-resistance, the lowest part is N + drain region, the N-light doped layer is above the drain region, the P-channel semiconductor region is above the N-light doped layer, the N + source region is above the P-channel semiconductor region, the gate dielectric layer and the gate electrode are surrounded, characterized in that the gate electrode can be N + polysilicon, or metal, or the combination of the two.
2. The ideal switch structure of a MOSFET with small specific on-resistance as claimed in claim 1, wherein the N + source region is a narrow bandgap semiconductor material such as single crystal Ge, poly-crystal Ge, pseudomorphic Ge, SiGe, mercury cadmium telluride, InP.
3. The ideal switch structure of a MOSFET with small specific on-resistance as claimed in claim 1, wherein the material of the channel semiconductor region is Si material, and the material of the source region is narrow bandgap semiconductor material; or, the channel semiconductor region material is a wide bandgap semiconductor material, and the source region is a narrow bandgap semiconductor material; or, the channel semiconductor region material is a wide bandgap semiconductor material, and the source region is a Si material.
4. The ideal switch structure for MOSFET with small specific on-resistance as claimed in claim 1, wherein the P-type channel semiconductor region is not defined by photolithography, and the channel length is not limited by the photolithography precision.
5. The ideal switching structure for a MOSFET with a small specific on-resistance as claimed in claim 1, wherein an N-lightly doped layer is provided, and the withstand voltage of the device is determined by the concentration and thickness of the N-lightly doped layer.
6. The ideal switching configuration for a MOSFET of low specific on-resistance as recited in claim 1, wherein the gate dielectric layer and the gate electrode are surrounded and have a four sided channel when conducting.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113013234A (en) * | 2021-03-08 | 2021-06-22 | 电子科技大学 | Source region self-aligned vertical channel MOS integrated circuit unit and implementation method thereof |
| CN114823861A (en) * | 2022-04-12 | 2022-07-29 | 电子科技大学 | Drain region self-aligned vertical channel MOS integrated circuit unit structure and implementation method thereof |
| CN114880880A (en) * | 2022-07-04 | 2022-08-09 | 成都复锦功率半导体技术发展有限公司 | SGT MOSFET device optimization design method |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5350934A (en) * | 1992-03-05 | 1994-09-27 | Kabushiki Kaisha Toshiba | Conductivity modulation type insulated gate field effect transistor |
| US20050173741A1 (en) * | 2004-02-09 | 2005-08-11 | International Rectifier Corp. | Top drain MOSFET with thickened oxide at trench top |
| US20110018058A1 (en) * | 2001-09-07 | 2011-01-27 | Power Integrations, Inc. | High-voltage vertical transistor with edge termination structure |
| CN104425714A (en) * | 2013-08-19 | 2015-03-18 | 爱思开海力士有限公司 | Semiconductor device having vertical channel, resistive memory device including the same, and method of manufacturing the same |
| CN106206514A (en) * | 2015-01-29 | 2016-12-07 | 台湾积体电路制造股份有限公司 | Top metal pad as the local interlinkage part of vertical transistor |
| US20170323977A1 (en) * | 2016-05-05 | 2017-11-09 | International Business Machines Corporation | Vertical transistor including controlled gate length and a self-aligned junction |
| WO2019139624A1 (en) * | 2018-01-12 | 2019-07-18 | Intel Corporation | Vertical field effect transistors having extended drain regions and methods of manufacturing the same |
-
2019
- 2019-12-18 CN CN201911306118.6A patent/CN111106161A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5350934A (en) * | 1992-03-05 | 1994-09-27 | Kabushiki Kaisha Toshiba | Conductivity modulation type insulated gate field effect transistor |
| US20110018058A1 (en) * | 2001-09-07 | 2011-01-27 | Power Integrations, Inc. | High-voltage vertical transistor with edge termination structure |
| US20050173741A1 (en) * | 2004-02-09 | 2005-08-11 | International Rectifier Corp. | Top drain MOSFET with thickened oxide at trench top |
| CN104425714A (en) * | 2013-08-19 | 2015-03-18 | 爱思开海力士有限公司 | Semiconductor device having vertical channel, resistive memory device including the same, and method of manufacturing the same |
| CN106206514A (en) * | 2015-01-29 | 2016-12-07 | 台湾积体电路制造股份有限公司 | Top metal pad as the local interlinkage part of vertical transistor |
| US20170323977A1 (en) * | 2016-05-05 | 2017-11-09 | International Business Machines Corporation | Vertical transistor including controlled gate length and a self-aligned junction |
| WO2019139624A1 (en) * | 2018-01-12 | 2019-07-18 | Intel Corporation | Vertical field effect transistors having extended drain regions and methods of manufacturing the same |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113013234A (en) * | 2021-03-08 | 2021-06-22 | 电子科技大学 | Source region self-aligned vertical channel MOS integrated circuit unit and implementation method thereof |
| CN114823861A (en) * | 2022-04-12 | 2022-07-29 | 电子科技大学 | Drain region self-aligned vertical channel MOS integrated circuit unit structure and implementation method thereof |
| CN114823861B (en) * | 2022-04-12 | 2023-04-28 | 电子科技大学 | Drain region self-aligned vertical channel MOS integrated circuit unit structure and implementation method thereof |
| CN114880880A (en) * | 2022-07-04 | 2022-08-09 | 成都复锦功率半导体技术发展有限公司 | SGT MOSFET device optimization design method |
| CN114880880B (en) * | 2022-07-04 | 2022-10-11 | 成都复锦功率半导体技术发展有限公司 | SGT MOSFET device optimization design method |
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Application publication date: 20200505 |