CN114899235B - High-integration-level nano-wall integrated circuit structure - Google Patents
High-integration-level nano-wall integrated circuit structure Download PDFInfo
- Publication number
- CN114899235B CN114899235B CN202210413345.4A CN202210413345A CN114899235B CN 114899235 B CN114899235 B CN 114899235B CN 202210413345 A CN202210413345 A CN 202210413345A CN 114899235 B CN114899235 B CN 114899235B
- Authority
- CN
- China
- Prior art keywords
- region
- drain
- drain region
- source
- channel semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000010354 integration Effects 0.000 claims abstract description 13
- 239000004065 semiconductor Substances 0.000 claims description 228
- 229910052710 silicon Inorganic materials 0.000 claims description 69
- 239000010703 silicon Substances 0.000 claims description 69
- 239000013078 crystal Substances 0.000 claims description 67
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 45
- 239000003870 refractory metal Substances 0.000 claims description 32
- 239000011810 insulating material Substances 0.000 claims description 16
- 239000000463 material Substances 0.000 claims description 16
- 229910021332 silicide Inorganic materials 0.000 claims description 16
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 3
- 229910000661 Mercury cadmium telluride Inorganic materials 0.000 claims description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 2
- MCMSPRNYOJJPIZ-UHFFFAOYSA-N cadmium;mercury;tellurium Chemical compound [Cd]=[Te]=[Hg] MCMSPRNYOJJPIZ-UHFFFAOYSA-N 0.000 claims description 2
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 claims description 2
- 238000004377 microelectronic Methods 0.000 abstract description 2
- 238000005516 engineering process Methods 0.000 abstract 1
- 238000004088 simulation Methods 0.000 description 41
- 238000000034 method Methods 0.000 description 38
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 230000000694 effects Effects 0.000 description 8
- 230000008569 process Effects 0.000 description 6
- 239000000377 silicon dioxide Substances 0.000 description 5
- 235000012239 silicon dioxide Nutrition 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 4
- 230000004044 response Effects 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 230000001052 transient effect Effects 0.000 description 3
- 239000008186 active pharmaceutical agent Substances 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical group [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
The invention discloses a high-integration-level nano-wall integrated circuit structure, and relates to the fields of microelectronic technology and Integrated Circuits (ICs). Based on the physical principle of devices different from MOSFETs in the traditional IC, the invention provides a Nano-Wall integrated circuit unit structure (Nano-Wall FET, NWAFET for short) with high integration level. The NWAFET can improve the integration level of the IC, obviously shorten the channel length, improve the flexibility of device channel width-to-length ratio adjustment and save the chip area.
Description
Technical Field
The present invention relates to the field of microelectronics and integrated circuits.
Background
The conventional planar MOSFET structure is gradually replaced by a three-dimensional FINFET after 22 nm. FINFETs were developed by the Hu Zheng Ming et al, university of California, U.S. under the formal published paper around 2000; the channel region of the FINFET is a fin-shaped semiconductor wrapped by three sides of a gate, and the three-side gate structure enhances the gate control capability, effectively inhibits the short channel effect and enables the moore's law to be continued. Along the idea of a three-sided gate structure of a FINFET, after 5nm node, a GAAFET (gate full surrounding field effect transistor) structure of a four-sided gate structure is proposed.
MOSFETs are classified into N-type and P-type, where the channel carriers of the N-type are electrons, the channel carriers of the P-type are holes, and the electron mobility is about 3 times that of the holes, so that in CMOS processes, the channel width of each PMOS is 3 times that of the NMOS under the same channel length conditions in order to form symmetrical complementary electrical characteristics. In the traditional planar MOSFET, a folded gate method is often used for widening a channel, and in the FINFET, most of the channel is realized by a 3 PMOS parallel connection method, so that the area of an integrated circuit is greatly increased, and the improvement of the integration level is limited.
The DIBL (drain induced barrier lowering) effect is a major problem preventing further scaling of planar MOSFETs after they enter the less than 22nm process node. In the last decade, methods such as FDSOI, FINFET and GAAFET have been adopted, in the same proportionOn the basis of shrinking, the method of using MOS grid electrode to make channel region 'fully depleted' overcomes DIBL effect of short channel MOSFET, and FINFET and GAAFET based on fully depleted theory must wrap three or four sides of channel region to implement MOSFET function. Taking NMOSFET as an example, the full depletion principle requires that P-Well be intrinsic or low doped; the negative effects brought by the method are as follows: first, the silicon channel region needs to be wrapped by a grid electrode, so that the integration level is reduced; second, the aspect ratio of the MOSFET is inconvenient to adjust, and in the case of FINFETs, the height and width of Fin are cured by the process, L ch In the minimum condition, only a multi-pipe parallel connection mode can be adopted to increase the width-to-length ratio. Multiple tubes in parallel means that the aspect ratio is achieved in a multiple increase. This is certainly inconvenient for analog ICs that require precise control of the aspect ratio.
Conventional MOSFETs, including planar MOSFET, SOIFET, FINFET and GAAFET, have a structure that determines, for example, NMOSFETs, the doping concentration of P-Well is much lower than the source drain concentration. Even if lightly doped source drain regions (LDDs) are present, this condition cannot be changed substantially. Because "lightly doped source and drain regions" is referred to in the term "lightly doped" as heavily doped source and drain regions. The LDD doping concentration must be higher than the P-Well doping concentration. This is determined by the silicon gate source drain self-aligned ion implantation (including annealing) process. The avalanche breakdown voltage of the PN junction is determined by the side with low doping concentration, namely, the P-Well concentration and the channel length L ch Determines the avalanche breakdown voltage BV of the conventional MOSFET DS . As such, IEEE IRDS predicts: in the future, the forward speed of the moore's law will be slower and slower, and the gate length L of the single transistor will be ch Will shrink slowly until 2028, L ch Shrink to 12nm, thereafter, L ch Will not shrink. Before the 28nm process node, L ch Can always follow the characteristic dimension L f And the integration level of the IC is doubled every 18-24 months. This is the most central content of moore's law. After 2028, L after entering 1.5 nm process node ch Cannot be reduced any more; this means that moore's law ends up sleeping. Due to the operating frequency f of MOSFET o ～1/L ch 2 This isMeaning that existing FINFETs and GAAFET have limited high frequency applications.
Disclosure of Invention
The invention aims to provide a semiconductor device with integration level superior to FinFET and GAAFET and the shortest channel length L ch Significantly shorter than FinFET and GAAFET and the convenience of MOSFET gate width to length ratio adjustment are significantly better than the IC basic structure of FinFET and GAAFET, we call a Nano-Wall integrated circuit cell structure with high integration (Nano-Wall FET, nwfet for short).
The technical scheme 1 of the invention is a high-integration nano-wall integrated circuit structure, as shown in fig. 1. A P-Well silicon single crystal semiconductor region 105 is formed at the lowermost part of the structure, and a silicon single crystal n+ drain region 104 of an nwfet is formed above the P-Well semiconductor region 105; above the n+ drain region 104 is an N-silicon single crystal or narrow bandgap pseudomorphic drain region 103; above the N-drain region 103 is a p+ -type channel semiconductor region 102; above the p+ channel semiconductor region is an n+ narrow bandgap poly-semiconductor source region 101; the n+ drain region 104 includes an upper portion and a lower portion, the lower portion is wider than the upper portion, the lower surface and the side surface of the lower portion are surrounded by the P-Well 105, a trench is formed in the upper portion of the n+ drain region 104, the N-drain region 103, the p+ channel semiconductor region 102, and the side surface of the n+ narrow bandgap polycrystalline semiconductor source region 101, the lower surface of the trench is lower than the interface between the N-drain region 103 and the n+ drain region 104, and higher than the lower surface of the n+ drain region 104; the trench is filled with a gate electrode 106 and an insulated gate dielectric 107. The gate electrode 106 is comprised of a heavily doped poly or refractory metal silicide or refractory metal or a combination thereof. An insulated gate dielectric 107 is used to isolate the gate electrode 106 from other semiconductor regions. The drain electrode 108 is provided on the sides of the n+ narrow bandgap polycrystalline semiconductor source region 101, the p+ channel semiconductor region 102, the N-drain region 103, and the n+ drain region 104. The insulating material 109 isolates the drain electrode 108 from the n+ narrow bandgap poly-semiconductor source region 101, the p+ channel semiconductor region 102, and the N-drain 103 region. Drain electrode 108 is in contact with n+ drain region 104 at a level below the interface of N-drain region 103 and n+ drain region 104.
The invention relates to a high-integration nano-wall integrated circuit structure, as shown in fig. 2. A P-Well silicon single crystal semiconductor region 105 is formed at the lowermost part of the structure, and a silicon single crystal n+ drain region 104 of an nwfet is formed above the P-Well semiconductor region 105; above the n+ drain region 104 is an N-silicon single crystal or narrow bandgap pseudomorphic drain region 103; a p+ -type channel semiconductor region 102 over the N-drain region 103; above the p+ channel semiconductor region 102 is an n+ narrow bandgap poly-semiconductor source region 101; the n+ drain region 104 includes an upper portion and a lower portion, the lower portion is wider than the upper portion, the lower surface and sides of the lower portion are surrounded by the P-Well 105, and trenches are provided on the sides of the n+ drain region 104, the N-drain region 103, the p+ type channel semiconductor region 102 and the n+ source region 101, and the lower surface of the trench is lower than the interface between the p+ type channel semiconductor region 102 and the N-drain region 103 and higher than the interface between the N-drain region 103 and the n+ drain region 104. The trench is filled with a gate electrode 106 and an insulated gate dielectric 107. The gate electrode 106 is comprised of a heavily doped poly or refractory metal silicide or refractory metal or a combination thereof. An insulated gate dielectric 107 is used to isolate the gate electrode 106 from other semiconductor regions. The drain electrode 108 is provided on the sides of the n+ source region 101, the p+ channel semiconductor region 102, the N-drain region 103, and the n+ drain region 104. The insulating material 109 isolates the drain electrode 108 from the n+ source region 101, the p+ channel semiconductor region 102, and the N-drain 103 region. Drain electrode 108 is in contact with n+ drain region 104 at a level below the interface of N-drain region 103 and n+ drain region 104.
The invention discloses a high-integration nano-wall integrated circuit structure in the technical scheme 3, as shown in fig. 3. A P-Well silicon single crystal semiconductor region 105 is formed at the lowermost part of the structure, and a silicon single crystal n+ drain region 104 of an nwfet is formed above the P-Well semiconductor region 105; above the n+ drain region 104 is an N-silicon single crystal or narrow bandgap pseudomorphic drain region 103; above the N-drain region 103 is a p+ -type channel semiconductor region 102; above the p+ channel semiconductor region 102 is an N-silicon single crystal or narrow bandgap pseudomorphic source region 110; above the N-source region 110 is an n+ narrow bandgap polycrystalline semiconductor source region 101; the n+ drain region 104 includes an upper portion and a lower portion, the lower portion is wider than the upper portion, the lower surface and sides of the lower portion are surrounded by the P-Well 105, and trenches are provided in the sides of the n+ drain region 104, the N-drain region 103, the p+ channel semiconductor region 102, the N-source region 110, and the n+ source region 101 above the n+ drain region 104, the lower surface of the trench is lower than the interface between the N-drain region 103 and the n+ drain region 104, and higher than the lower surface of the n+ drain region 104. The trench is filled with a gate electrode 106 and an insulated gate dielectric 107. The gate electrode 106 is comprised of a heavily doped poly or refractory metal silicide or refractory metal or a combination thereof. An insulated gate dielectric 107 is used to isolate the gate electrode 106 from other semiconductor regions. The drain electrode 108 is provided on the side surfaces of the n+ source region 101, the N-source region 110, the p+ channel semiconductor region 102, the N-drain region 103, and the silicon single crystal n+ drain region 104. The insulating material 109 isolates the drain electrode 108 from the n+ source region 101, the p+ channel semiconductor region 102, and the N-drain 103 region. Drain electrode 108 is in contact with n+ drain region 104 at a level below the interface of N-drain region 103 and n+ drain region 104. The N-source region 110 has a lower doping concentration than the n+ source region 101 and the p+ channel semiconductor region 102.
The invention provides a high-integration nano-wall integrated circuit structure as shown in fig. 4. A P-Well silicon single crystal semiconductor region 105 is formed at the lowermost part of the structure, and a silicon single crystal n+ drain region 104 of an nwfet is formed above the P-Well semiconductor region 105; above the n+ drain region 104 is an N-silicon single crystal or narrow bandgap pseudomorphic drain region 103; a p+ -type channel semiconductor region 102 over the N-drain region 103; above the p+ channel semiconductor region 102 is an N-source region 110; above the N-source region 110 is an n+ narrow bandgap polycrystalline semiconductor source region 101; the n+ drain region 104 includes an upper portion and a lower portion wider than the upper portion, the lower surface and sides of the lower portion are surrounded by the P-Well 105, and trenches are provided on the sides of the upper portion of the n+ drain region 104, the N-drain region 103, the p+ type channel semiconductor region 102, the N-source region 110, and the n+ source region 101, and the lower surface of the trench is lower than the interface between the p+ type channel semiconductor region 102 and the N-drain region 103 and higher than the interface between the N-drain region 103 and the n+ drain region 104. The trench is filled with a gate electrode 106 and an insulated gate dielectric 107. The gate electrode 106 is comprised of a heavily doped poly or refractory metal silicide or refractory metal or a combination thereof. An insulated gate dielectric 107 is used to isolate the gate electrode 106 from other semiconductor regions. The drain electrode 108 is provided on the sides of the n+ source region 101, the N-source region 110, the p+ channel semiconductor region 102, the N-drain region 103, and the n+ drain region 104. The insulating material 109 isolates the drain electrode 108 from the n+ source region 101, the p+ channel semiconductor region 102, and the N-drain 103 region. Drain electrode 108 is in contact with n+ drain region 104 at a level below the interface of N-drain region 103 and n+ drain region 104. The N-source region 110 has a lower doping concentration than the n+ source region 101 and the p+ channel semiconductor region 102.
The invention discloses a high-integration nano-wall integrated circuit structure as shown in fig. 5. An N-Well silicon single crystal semiconductor region 115 is formed at the lowermost part of the structure, and a silicon single crystal P+ drain region 114 of an NWAFET is formed at the upper part of the N-Well semiconductor region 115; above the P + drain region 114 is a P-silicon single crystal or narrow bandgap pseudomorphic drain region 113; above the P-drain region 113 is an n+ channel semiconductor region 112; above the n+ channel semiconductor region 112 is a p+ narrow bandgap poly-semiconductor source region 111; the p+ drain region 114 includes an upper portion and a lower portion wider than the upper portion, the lower surface and sides of the lower portion are surrounded by the N-Well 115, and trenches are provided on the sides of the p+ drain region 114, the P-drain region 113, the n+ channel semiconductor region 112, and the p+ source region 111 above the p+ drain region 114, the lower surface of the trench being lower than the interface of the P-drain region 113 and the p+ drain region 114, and higher than the lower surface of the p+ drain region 114. The trench is filled with a gate electrode 106 and an insulated gate dielectric 107. The gate electrode 106 is comprised of a heavily doped poly or refractory metal silicide or refractory metal or a combination thereof. An insulated gate dielectric 107 is used to isolate the gate electrode 106 from other semiconductor regions. The drain electrode 108 is disposed on the sides of the p+ narrow bandgap polycrystalline semiconductor source region 111, the n+ channel semiconductor region 112, the P-drain region 113, and the p+ drain region 114. The insulating material 109 is isolated from the p+ source region 111, the n+ channel semiconductor region 112, and the P-drain 113 region. Drain electrode 108 is in contact with p+ drain region 114 at a level below the interface of P-drain region 113 and p+ drain region 114.
The technical scheme 6 of the invention is a high-integration nano-wall integrated circuit structure, as shown in fig. 6. An N-Well silicon single crystal semiconductor region 115 is formed at the lowermost part of the structure, and a silicon single crystal P+ drain region 114 of an NWAFET is formed at the upper part of the N-Well semiconductor region 115; above the P + drain region 114 is a P-silicon single crystal or narrow bandgap pseudomorphic drain region 113; an n+ channel semiconductor region 112 over the P-drain region 113; above the n+ channel semiconductor region 112 is a p+ narrow bandgap poly-semiconductor source region 111; the p+ drain region 114 includes an upper portion and a lower portion wider than the upper portion, the lower surface and sides of the lower portion are surrounded by the N-Well 115, and trenches are provided on the sides of the p+ drain region 114, the P-drain region 113, the n+ type channel semiconductor region 112, and the p+ source region 111, the lower surface of the trench being lower than the interface of the n+ type channel semiconductor region 112 and the P-drain region 113 and higher than the lower surface of the P-drain region 113. The trench is filled with a gate electrode 106 and an insulated gate dielectric 107. The gate electrode 106 is comprised of a heavily doped poly or refractory metal silicide or refractory metal or a combination thereof. An insulated gate dielectric 107 is used to isolate the gate electrode 106 from other semiconductor regions. The drain electrode 108 is disposed on the sides of the p+ narrow bandgap polycrystalline semiconductor source region 111, the n+ channel semiconductor region 112, the P-drain region 113, and the p+ drain region 114. The insulating material 109 isolates the drain electrode 108 from the p+ source region 111, the n+ channel semiconductor region 112, and the P-drain 113 region. Drain electrode 108 is in contact with p+ drain region 114 at a level below the interface of P-drain region 113 and p+ drain region 114.
The invention relates to a high-integration nano-wall integrated circuit structure, as shown in fig. 7. An N-Well silicon single crystal semiconductor region 115 is formed at the lowermost part of the structure, and a silicon single crystal P+ drain region 114 of an NWAFET is formed at the upper part of the N-Well semiconductor region 115; above the P + drain region 114 is a P-silicon single crystal or narrow bandgap pseudomorphic drain region 113; above the P-drain region 113 is an n+ channel semiconductor region 112; above the n+ channel semiconductor region 112 is a P-silicon single crystal or narrow bandgap pseudomorphic source region 116; above the P-source region 116 is a p+ narrow bandgap polycrystalline semiconductor source region 111; the p+ drain region 114 includes an upper portion and a lower portion wider than the upper portion, the lower surface and sides of the lower portion are surrounded by the N-Well 115, and trenches are provided on sides of the p+ drain region 114, the P-drain region 113, the n+ channel semiconductor region 112, the P-source region 116, and the p+ source region 111 above the p+ drain region 114, the lower surface of the trench being lower than the interface of the P-drain region 113 and the p+ drain region 114, and higher than the lower surface of the p+ drain region 114. The trench is filled with a gate electrode 106 and an insulated gate dielectric 107. The gate electrode 106 is comprised of a heavily doped poly or refractory metal silicide or refractory metal or a combination thereof. An insulated gate dielectric 107 is used to isolate the gate electrode 106 from other semiconductor regions. The drain electrode 108 is disposed on the sides of the p+ narrow bandgap polycrystalline semiconductor source region 111, the P-source region 116, the n+ channel semiconductor region 112, the P-drain region 113, and the p+ drain region 114. The insulating material 109 isolates the drain electrode 108 from the p+ source region 111, the P-source region 116, the n+ channel semiconductor region 112, and the P-drain 113 regions. Drain electrode 108 is in contact with p+ drain region 114 at a level below the interface of P-drain region 113 and p+ drain region 114. The P-source region 116 is doped with a lower concentration than the p+ source region 111 and the n+ channel semiconductor region 112.
The technical scheme 8 of the invention is a high-integration nano-wall integrated circuit structure, as shown in fig. 8. An N-Well silicon single crystal semiconductor region 115 is formed at the lowermost part of the structure, and a silicon single crystal P+ drain region 114 of an NWAFET is formed at the upper part of the N-Well semiconductor region 115; above the P + drain region 114 is a P-silicon single crystal or narrow bandgap pseudomorphic drain region 113; an n+ channel semiconductor region 112 over the P-drain region 113; above the n+ channel semiconductor region 112 is a P-silicon single crystal or narrow bandgap pseudomorphic source region 116; above the P-source region 116 is a p+ narrow bandgap polycrystalline semiconductor source region 111; the p+ drain region 114 includes an upper portion and a lower portion wider than the upper portion, the lower surface and sides of the lower portion are surrounded by the N-Well 115, and trenches are formed in the sides of the p+ drain region 114, the P-drain region 113, the n+ type channel semiconductor region 112, the P-source region 116, and the p+ source region 111, and the lower surface of the trench is lower than the interface between the n+ type channel semiconductor region 112 and the P-drain region 113 and higher than the lower surface of the P-drain region 113. The trench is filled with a gate electrode 106 and an insulated gate dielectric 107. The gate electrode 106 is comprised of a heavily doped poly or refractory metal silicide or refractory metal or a combination thereof. An insulated gate dielectric 107 is used to isolate the gate electrode 106 from other semiconductor regions. The drain electrode 108 is disposed on the sides of the p+ narrow bandgap polycrystalline semiconductor source region 111, the P-source region 116, the n+ channel semiconductor region 112, the P-drain region 113, and the p+ drain region 114. The insulating material 109 isolates the drain electrode 108 from the p+ source region 111, the P-source region 116, the n+ channel semiconductor region 112, and the P-drain 113 regions. Drain electrode 108 is in contact with p+ drain region 114 at a level below the interface of P-drain region 113 and p+ drain region 114. The P-source region 116 is doped with a lower concentration than the p+ source region 111 and the n+ channel semiconductor region 112.
Further, the thickness of the p+ channel semiconductor region 102 is less than 12nm.
Further, the doping concentration of the p+ channel semiconductor region 102 is higher than that of the N-drain region 103 by more than 2 orders of magnitude.
Further, the thickness of the n+ channel semiconductor region 112 is less than 12nm.
Further, the doping concentration of the n+ channel semiconductor region 112 is more than 2 orders of magnitude higher than that of the P-drain region 113.
Further, the gate electrode 106 is provided in the entire region of one side surface of the semiconductor region or in a partial region of one side surface of the semiconductor region, as shown in fig. 13 (a).
Further, the gate electrode 106 is provided in the entire region of both sides of the semiconductor region, or in the entire region of one side and a partial region of the other side of the semiconductor region, as shown in fig. 13 (b).
Further, the gate electrode 106 is provided in all of three side surfaces of the semiconductor region, or in all of two side surfaces and a partial region of the other side surface of the semiconductor region, as shown in fig. 13 (c).
Further, the gate electrode 106 is provided in all regions of four sides of the semiconductor region, or all regions of three sides and a partial region of the last side of the semiconductor region, as shown in fig. 13 (d).
Further, when the channel semiconductor region (102, 112), the heavily doped drain region (104, 114), the semiconductor substrate or the well (105, 115) is monocrystalline silicon, the lightly doped drain region (103, 113), the lightly doped source region (110, 116) is a narrow bandgap pseudomorphic semiconductor material (e.g., siGe pseudomorphic); when the channel semiconductor region (102, 112), the heavily doped drain region (104, 114), the semiconductor substrate or the well (105, 115) is a wide bandgap monocrystalline semiconductor material (such as SiC monocrystalline or GaN monocrystalline), the lightly doped drain region (103, 113) and the lightly doped source region (110, 116) are pseudomorphic Si semiconductor materials. The use of pseudomorphic crystals in the lightly doped drain and lightly doped source regions can introduce stress in the channel semiconductor (102, 112) to increase carrier mobility.
Further, when the channel semiconductor region (102, 112), the heavily doped drain region (104, 114), the semiconductor substrate or the well (105, 115) is monocrystalline silicon, the heavily doped source region (101, 111) is a narrow bandgap semiconductor polycrystalline material such as polycrystalline Ge, polycrystalline SiGe, polycrystalline TWS (mercury cadmium telluride), polycrystalline InP, polycrystalline InSb, or a combination thereof; when the channel semiconductor region (102, 112), the heavily doped drain region (104, 114), the semiconductor substrate or the well (105, 115) is a wide bandgap monocrystalline semiconductor material (e.g., siC monocrystalline or GaN monocrystalline), the heavily doped source region (101, 111) is a polycrystalline Si semiconductor material. If the heavily doped source regions (101, 111) are made of a narrow bandgap pseudomorphic semiconductor material, the thickness of the source regions must be very thin due to stress generated by lattice mismatch, and the source region metal alloy may penetrate the pseudomorphic source region, resulting in device failure. The heavy doping source region is made of polycrystalline materials, and the problem of lattice mismatch is avoided, so that the thickness of the heavy doping source region can be thicker, and the problem caused by pseudomorphic crystals is avoided.
The gate depth may be selected according to different usage requirements. Taking an NMOSFET as an example, under low frequency application, the gate can be deeper, the gate depth is lower than the interface between the N-drain region 103 and the n+ drain region 104, and higher than the lower surface of the n+ drain region 104, and the parasitic capacitance added at this depth does not significantly affect the low frequency application, but can bring about a lower on-resistance R ON The on-state current is increased, and the driving capability of the transistor is improved; in high frequency applications, excessive parasitic capacitance can significantly affect transistor performance, so the gate cannot be too deep, and the gate depth is lower than the interface of N-drain region 103 and n+ drain region 104, and higher than n+ drainThe lower surface of region 104.
The nwfet proposed by the present invention employs a completely different mechanism to the full depletion principle of FINFET and GAAFET to suppress DIBL effects. The channel region of the NWAFET adopts high doping, the concentration of the channel region is higher than that of the N-drain region, and BV of the device DS Is determined by the length and concentration of the N-drain region, and avoids the high field effect of the channel region, so L ch Can be scaled down to a small size. The drain depletion region extends approximately only in the drift region, with the channel region barrier shape being almost unchanged. Therefore, the NWAFET can well inhibit the DIBL effect, the grid electrode does not need to wrap a channel region, and a non-leakage MOSFET can be formed on one side surface of the silicon wall, so that the chip area is saved compared with three-side or four-side channels of the FINFET and the GAAFET, and the integration level of transistors of the IC is remarkably improved.
The invention provides an NWAFET structure capable of realizing a single-sided channel based on a novel principle of inhibiting DIBL effect. Compared with FINFET and GAAFET, the single-sided channel of NWAFET saves chip area compared with three-sided or four-sided channel, and in addition, L thereof ch L can be compared with FINFET and GAAFET ch Much shorter. Compared with the conventional planar MOSFET, the nwfet is a three-dimensional structure, and thus the integration level is significantly improved. In terms of digital ICs, advantages in NWaFET integration and speed will result in better digital IC chip performance and smaller chip area. In the analog IC aspect, the NWAFET can flexibly and conveniently adjust the width-to-length ratio and simultaneously has higher working voltage V dd Under the condition that its channel length L ch Can be further shortened, thus having wide application prospect in the high-frequency field.
Drawings
Fig. 1 is a cross-sectional view of an NMOSFET cell with a high-integration nanowall integrated circuit structure without N-source region deep gate trench according to the present invention.
Fig. 2 is a cross-sectional view of an NMOSFET cell with a high-integration nanowall integrated circuit structure without an N-source region shallow trench.
Fig. 3 is a cross-sectional view of an NMOSFET cell with an N-source region deep gate trench in a high-integration nanowall integrated circuit structure according to the present invention.
Fig. 4 is a cross-sectional view of a high-integration nanowall integrated circuit structure with N-source shallow trench NMOSFET cells in accordance with the present invention.
Fig. 5 is a cross-sectional view of a P-source region free deep gate trench PMOSFET cell of a high-integration nanowall integrated circuit structure according to the invention.
Fig. 6 is a cross-sectional view of a P-source region free shallow trench PMOSFET cell of a high-integration nanowall integrated circuit structure according to the present invention.
Fig. 7 is a cross-sectional view of a PMOSFET cell with a P-source region deep gate trench in a high-integration nanowall integrated circuit structure according to the invention.
Fig. 8 is a cross-sectional view of a high-integration nano-wall integrated circuit structure with P-source region shallow trench PMOSFET cell according to the present invention.
Fig. 9 is a top view of an NMOSFET cell with a high-integration nano-wall integrated circuit structure according to the present invention.
Fig. 10 is a top view of a PMOSFET cell of a high-integration nano-wall integrated circuit structure according to the present invention.
Fig. 11 is a cross-sectional view of an NMOSFET with no N-source region in a high-integration nanowall integrated circuit structure according to the present invention.
FIG. 12 is a cross-sectional view of a P-source region free deep gate trench PMOSFET in a high integration nano-wall integrated circuit structure according to the present invention.
FIG. 13 illustrates the formation of different gate widths (W) for the trench gate electrode 106 of a high-integration-level nanowall integrated circuit structure unit according to the present invention ch ) A top view of the MOSFET.
Fig. 14 is a cross-sectional view of a simulation structure of embodiment 1.
Fig. 15 is a transient response curve obtained by the simulation of example 1.
Fig. 16 is a cross-sectional view of a simulation structure of embodiment 2.
FIG. 17 is a transfer characteristic curve obtained by simulation in example 2.
Fig. 18 is an output characteristic curve obtained by simulation in example 2.
Fig. 19 is a frequency response curve obtained by simulation in example 2.
Fig. 20 is a cross-sectional view of a simulation structure of embodiment 3.
FIG. 21 is a transfer characteristic curve obtained by simulation in example 3.
Fig. 22 is an output characteristic curve obtained by simulation in example 3.
FIG. 23 is a graph showing DIBL values obtained by simulation in example 4 as a function of the doping concentration of the P+ channel region
FIG. 24 is a cross-sectional view of a simulation structure of example 5
FIG. 25 is a transfer characteristic curve obtained by simulation in example 5.
Fig. 26 is an output characteristic curve obtained by simulation in example 5.
Detailed Description
Example 1:
a three-dimensional simulation of a computer was performed for a CMOS inverter constructed using the present invention of claim 3 and claim 7, and the simulation structure is shown in fig. 14. For NMOSFET, its N+ source is silicon, its depth is 20nm, and its doping concentration is 1×10 20 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The depth of the N-source electrode is 20nm, and the doping concentration is 1 multiplied by 10 16 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The depth of the P+ channel is 10nm, and the doping concentration is 1 multiplied by 10 18 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The depth of the N-drain electrode is 20nm, and the doping concentration is 1 multiplied by 10 16 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The depth of the N+ drain electrode is 20nm, and the doping concentration is 1 multiplied by 10 20 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the For PMOSFET, its P+ source depth is 20nm, and doping concentration is 1×10 20 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The depth of the P-source electrode is 20nm, and the doping concentration is 1 multiplied by 10 16 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The depth of the N+ channel is 10nm, and the doping concentration is 1 multiplied by 10 18 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The depth of the P-drain electrode is 20nm, and the doping concentration is 1 multiplied by 10 16 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The depth of the P+ drain electrode is 20nm, and the doping concentration is 1 multiplied by 10 20 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The grid electrode is made of polysilicon material and is deep 2nm below the lower surface of the N-drain electrode; the gate dielectric is silicon dioxide, and the thickness is 1nm; the NMOSFET channel width is 20nm, and the width-to-length ratio is 2:1; the width of the PMOSFET channel is 3 times of that of the NMOSFET channel, namely 60nm, and the width-to-length ratio is 6:1; the drain lead-out metal of the two transistors is titanium and deeply penetrates 10nm below the lower surface of the N-drain. The input voltage of transient simulation is a square wave signal with periodical change, the input low level is 0V, the input high level is 1.5V, and the input voltage is from high to low and from highThe low to high level transition times are all 1×10 -11 s。
Simulation results referring to the drawings in the specification, fig. 15 is a transient response curve obtained by simulation. From the simulation results, it can be seen that the common gate of the NMOSFET and the PMOSFET can realize the function of the CMOS inverter IC. The inverter IC switching times are all less than 10ps achieved with nwfet devices of 10nm channel length without careful optimization.
Example 2:
computer three-dimensional simulation is performed on an NMOSFET structure using the technical scheme 4 of the invention, and a cross-sectional view of the simulation structure is shown in figure 16. Wherein the N+ source is silicon, the depth is 10nm, and the doping concentration is 1×10 20 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The depth of the N-source electrode is 20nm, and the doping concentration is 1 multiplied by 10 17 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The depth of the P+ channel is 0.543nm, and the doping concentration is 2 multiplied by 10 20 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The depth of the N-drain electrode is 20nm, and the doping concentration is 1 multiplied by 10 17 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The depth of the N+ drain electrode is 10nm, and the doping concentration is 1 multiplied by 10 20 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The grid electrode is made of polysilicon material and penetrates deep into the lower surface of the P+ channel region by 2nm; the gate dielectric is silicon dioxide, and the thickness is 1.1nm; the grid electrode is arranged on one side face of the functional region, the corresponding channel width is 5nm, and the width-to-length ratio is about 9.2:1.
Simulation results referring to the drawings of the specification, FIG. 17 is a transfer characteristic curve obtained by simulation, and FIG. 18 is an output characteristic curve obtained by simulation, and from the simulation results, it can be seen that the NMOSFET structure using the technical scheme 4 of the present invention can obtain transistor characteristics as expected under the condition that the channel length is 0.543nm, and the source-drain voltage V ds The calculated threshold voltage is 0.36V at 0.05V; the switching ratio can reach 1e6. Fig. 19 is a frequency response curve obtained by simulation, and it can be seen from the simulation result that the cut-off frequency ft of the device is 2.33THz.
Example 3:
computer three-dimensional simulation is performed on an NMOSFET structure using the technical scheme 2 of the invention, and a cross-sectional view of the simulation structure is shown in figure 20. Wherein the N+ source is germanium-silicon, the depth is 10nm, and the doping concentration is 1×10 20 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the P+ channel depth of 7nm, doping concentration of 5×10 19 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The depth of the N-drain electrode is 10nm, and the doping concentration is 1 multiplied by 10 15 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The depth of the N+ drain electrode is 10nm, and the doping concentration is 1 multiplied by 10 20 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The grid electrode is made of polycrystalline silicon material, and the depth of the grid electrode is flush with the lower surface of the P+ channel region; the gate dielectric is silicon dioxide, and the thickness is 2nm; the grid electrodes are arranged on three sides of the functional region, the corresponding channel width is 21nm, and the width-to-length ratio is 3:1.
Simulation results referring to the drawings of the specification, FIG. 21 is a transfer characteristic curve obtained by simulation, FIG. 22 is an output characteristic curve obtained by simulation, and from the simulation results, it can be seen that the NMOSFET using the technical scheme 2 of the present invention can obtain transistor characteristics as expected, at the source-drain voltage V ds The calculated threshold voltage is 0.7V at 1.2V; the switching ratio can reach 1e8.
Example 4:
computer three-dimensional simulation is performed on an NMOSFET structure using the technical scheme 4 of the invention, and a cross-sectional view of the simulation structure is shown in figure 16. Wherein the N+ source is silicon, the depth is 10nm, and the doping concentration is 1×10 20 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The depth of the N-source electrode is 10nm, and the doping concentration is 1 multiplied by 10 17 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The depth of the P+ channel is 0.543nm; the depth of the N-drain electrode is 10nm, and the doping concentration is 1 multiplied by 10 17 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The depth of the N+ drain electrode is 10nm, and the doping concentration is 1 multiplied by 10 20 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The grid electrode is made of polysilicon material and penetrates deep into the lower surface of the P+ channel region by 2nm; the gate dielectric is silicon dioxide, and the thickness is 1.1nm; the grid electrodes are arranged on four sides of the functional region, the corresponding channel width is 20nm, and the width-to-length ratio is about 36.8:1.
FIG. 23 shows that the P+ channel region doping concentration is from 1×10 19 cm -3 To 3X 10 20 cm -3 Change in DIBL value. As the doping concentration of the p+ channel region increases, a gradual decrease in DIBL value is observed, indicating that the highly doped channel region of the nwfet structure is effective in suppressing DIBL effects.
Example 5:
the PMOSFET structure adopting the technical scheme 8 of the invention is subjected to computer three-dimensional simulation, and the section of the simulation structure isThe diagram is shown in fig. 24. Wherein the P+ source is silicon, the depth is 10nm, and the doping concentration is 1×10 20 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The depth of the P-source electrode is 20nm, and the doping concentration is 1 multiplied by 10 16 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The depth of the N+ channel is 10nm; the depth of the P-drain electrode is 20nm, and the doping concentration is 1 multiplied by 10 16 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The depth of the P+ drain electrode is 10nm, and the doping concentration is 1 multiplied by 10 20 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The grid electrode is made of polysilicon material and is deep under the lower surface of the N+ channel region by 5nm; the gate dielectric is silicon dioxide, and the thickness is 3nm; the grid electrodes are arranged on four sides of the functional region, the corresponding channel width is 40nm, and the width-to-length ratio is about 4:1.
Simulation results referring to the drawings of the specification, FIG. 25 is a transfer characteristic curve obtained by simulation, FIG. 26 is an output characteristic curve obtained by simulation, and from the simulation results, it can be seen that the PMOSFET using the technical scheme 8 of the present invention can obtain transistor characteristics as expected, at the source-drain voltage V ds The threshold voltage calculated at-2V is-0.9V; the switching ratio can reach 1e8.
Claims (14)
1. A high-integration nanowall integrated circuit (nwfet) structure, characterized in that a P-Well silicon single crystal semiconductor region (105) is arranged at the lowest part of the structure, and a silicon single crystal n+ drain region (104) of the nwfet is formed at the upper part of the P-Well silicon single crystal semiconductor region (105); an N-silicon single crystal or narrow bandgap pseudomorphic drain region (103) over the n+ drain region (104); above the N-drain region (103) is a p+ channel semiconductor region (102); above the p+ channel semiconductor region (102) is an n+ narrow bandgap polycrystalline semiconductor source region (101); the N+ drain region 104 comprises an upper part and a lower part, the lower part is wider than the upper part, the lower surface and the side surface of the lower part are surrounded by a P-Well (105), grooves are formed in the upper part of the N+ drain region (104), the N-drain region (103), the P+ channel semiconductor region (102) and the side surface of the N+ narrow bandgap polycrystalline semiconductor source region (101), and the lower surface of the grooves is lower than the interface of the N-drain region (103) and the N+ drain region (104) and higher than the lower surface of the N+ drain region (104); filling a gate electrode (106) and an insulated gate dielectric (107) in the trench; the gate electrode (106) is composed of a heavily doped polycrystalline or refractory metal silicide or refractory metal or a combination thereof; the insulated gate dielectric (107) is used for isolating the gate electrode (106) from other semiconductor regions; the drain electrode (108) is arranged on the side surfaces of the N+ narrow bandgap polycrystalline semiconductor source region (101), the P+ channel semiconductor region (102), the N-drain region (103) and the N+ drain region (104); an insulating material (109) isolates the drain electrode (108) from the n+ source (101), the p+ channel semiconductor region (102) and the N-drain (103) region; the drain electrode (108) is in contact with the N+ drain region (104), and the contact surface is lower than the interface between the N-drain region (103) and the N+ drain region (104).
2. A high-integration nanowall integrated circuit structure, characterized in that a P-Well silicon single crystal semiconductor region (105) is arranged at the lowest part of the structure, and an n+ silicon single crystal drain region (104) of an nwfet is formed at the upper part of the P-Well silicon single crystal semiconductor region (105); an N-silicon single crystal or narrow bandgap pseudomorphic drain region (103) over the n+ drain region (104); a p+ channel semiconductor region (102) over the N-drain region (103); above the p+ channel semiconductor region (102) is an n+ narrow bandgap polycrystalline semiconductor source region (101); the silicon single crystal N+ drain region (104) comprises an upper part and a lower part, the lower part is wider than the upper part, the lower surface and the side surface of the lower part are surrounded by a P-Well (105), grooves are formed in the upper part of the N+ drain region (104), the N-drain region (103), the P+ type channel semiconductor region (102) and the side surface of the N+ narrow forbidden band polycrystalline semiconductor source region (101), and the lower surface of the grooves is lower than the interface of the P+ type channel semiconductor region (102) and the N-drain region (103) and higher than the interface of the N-drain region (103) and the N+ drain region (104); filling a gate electrode (106) and an insulated gate dielectric (107) in the trench; the gate electrode (106) is composed of a heavily doped polycrystalline or refractory metal silicide or refractory metal or a combination thereof; the insulated gate dielectric (107) is used for isolating the gate electrode (106) from other semiconductor regions; the drain electrode (108) is arranged on the side surfaces of the N+ source electrode region (101), the P+ channel semiconductor region (102), the N-drain electrode region (103) and the N+ drain electrode region (104); an insulating material (109) isolates the drain electrode (108) from the n+ source region (101), the p+ channel semiconductor region (102) and the N-drain (103) region; the drain electrode (108) is in contact with the N+ drain region (104), and the contact surface is lower than the interface between the N-drain region (103) and the N+ drain region (104).
3. A high-integration nanowall integrated circuit structure, characterized in that a P-Well silicon single crystal semiconductor region (105) is arranged at the lowest part of the structure, and a silicon single crystal n+ drain region (104) of an nwfet is formed at the upper part of the P-Well silicon single crystal semiconductor region (105); an N-silicon single crystal or narrow bandgap pseudomorphic drain region (103) over the n+ drain region (104); above the N-drain region (103) is a p+ channel semiconductor region (102); above the p+ channel semiconductor region (102) is an N-silicon single crystal or narrow bandgap pseudomorphic source region (110); above the N-source region (110) is an n+ narrow bandgap polycrystalline semiconductor source region (101); the N+ drain region (104) comprises an upper part and a lower part, the lower part is wider than the upper part, the lower surface and the side surface of the lower part are surrounded by the P-Well (105), grooves are formed in the upper part of the N+ drain region (104), the N-drain region (103), the P+ type channel semiconductor region (102), the N-source region (110) and the side surface of the N+ source region (101), and the lower surface of the grooves is lower than the interface between the N-drain region (103) and the N+ drain region (104) and higher than the lower surface of the N+ drain region (104); filling a gate electrode (106) and an insulated gate dielectric (107) in the trench; the gate electrode (106) is composed of a heavily doped polycrystalline or refractory metal silicide or refractory metal or a combination thereof; the insulated gate dielectric (107) is used for isolating the gate electrode (106) from other semiconductor regions; the drain electrode (108) is arranged on the side surface of the N+ narrow band gap polycrystalline semiconductor source region (101), the N-source region (110), the P+ channel semiconductor region (102), the N-drain region (103) and the N+ drain region (104); an insulating material (109) isolates the drain electrode (108) from the n+ source region (101), the p+ channel semiconductor region (102) and the N-drain (103) region; the drain electrode (108) is in contact with the N+ drain region (104), and the contact surface is lower than the interface between the N-drain region (103) and the N+ drain region (104); the N-source region (110) has a lower doping concentration than the N+ source region (101) and the P+ channel semiconductor region (102).
4. A high-integration nanowall integrated circuit structure, characterized in that a P-Well silicon single crystal semiconductor region (105) is arranged at the lowest part of the structure, and a silicon single crystal n+ drain region (104) of an nwfet is formed at the upper part of the P-Well silicon single crystal semiconductor region (105); an N-silicon single crystal or narrow bandgap pseudomorphic drain region (103) over the n+ drain region (104); a p+ channel semiconductor region (102) over the N-drain region (103); above the p+ channel semiconductor region (102) is an N-silicon single crystal or narrow bandgap pseudomorphic source region (110); above the N-source region (110) is an n+ narrow bandgap polycrystalline semiconductor source region (101); the N+ drain region (104) comprises an upper part and a lower part, the lower part is wider than the upper part, the lower surface and the side surface of the lower part are surrounded by the P-Well (105), grooves are formed in the upper part of the N+ drain region (104), the N-drain region (103), the P+ type channel semiconductor region (102), the N-source region (110) and the side surface of the N+ source region (101), and the lower surface of the grooves is lower than the interface of the P+ type channel semiconductor region (102) and the N-drain region (103) and higher than the interface of the N-drain region (103) and the N+ drain region (104); filling a gate electrode (106) and an insulated gate dielectric (107) in the trench; the gate electrode (106) is composed of a heavily doped polycrystalline or refractory metal silicide or refractory metal or a combination thereof; the insulated gate dielectric (107) is used for isolating the gate electrode (106) from other semiconductor regions; a drain electrode (108) provided on the side surfaces of the N+ source region (101), the N-source region (110), the P+ channel semiconductor region (102), the N-drain region (103), and the N+ drain region (104); an insulating material (109) isolates the drain electrode (108) from the n+ narrow bandgap polycrystalline semiconductor source region (101), the p+ channel semiconductor region (102) and the N-drain (103) region; the drain electrode (108) is in contact with the N+ drain region (104), and the contact surface is lower than the interface between the N-drain region (103) and the N+ drain region (104); the N-source region (110) has a lower doping concentration than the N+ source region (101) and the P+ channel semiconductor region (102).
5. The high-integration nanowall integrated circuit structure of any of claims 1-4, wherein the p+ channel semiconductor region (102) has a thickness of less than 12nm.
6. The high integration nanowall integrated circuit structure of any of claims 1-4, wherein the p+ channel semiconductor region (102) has a doping concentration greater than 2 orders of magnitude higher than the N-drain region (103).
7. A high-integration nanowall integrated circuit structure, characterized in that an N-Well silicon single crystal semiconductor region (115) is arranged at the lowest part of the structure, and a silicon single crystal p+ drain region (114) of an nwfet is formed at the upper part of the N-Well semiconductor region (115); a P-silicon single crystal or narrow bandgap pseudomorphic drain region (113) above the p+ drain region (114); above the P-drain region (113) is an n+ channel semiconductor region (112); above the n+ channel semiconductor region (112) is a p+ narrow bandgap polycrystalline semiconductor source region (111); the P+ drain region (114) comprises an upper part and a lower part, the lower part is wider than the upper part, the lower surface and the side surface of the lower part are surrounded by an N-Well (115), grooves are formed in the upper part of the P+ drain region (114), the side surfaces of the P-drain region (113), the N+ channel semiconductor region (112) and the P+ source region (111), and the lower surface of the grooves is lower than the interface between the P-drain region (113) and the P+ drain region (114) and higher than the lower surface of the P+ drain region (114); filling a gate electrode (106) and an insulated gate dielectric (107) in the trench; the gate electrode (106) is composed of a heavily doped polycrystalline or refractory metal silicide or refractory metal or a combination thereof; the insulated gate dielectric (107) is used for isolating the gate electrode (106) from other semiconductor regions; the drain electrode (108) is arranged on the side surface of the upper parts of the P+ source electrode region (111), the N+ channel semiconductor region (112), the P-drain electrode region (113) and the P+ drain electrode region (114); the insulating material (109) isolates the drain electrode (108) from the p+ narrow bandgap polycrystalline semiconductor source region (111), the n+ channel semiconductor region (112) and the P-drain (113) region; the drain electrode (108) is in contact with the P+ drain region (114), the contact surface being lower than the interface of the P-drain region (113) and the P+ drain region (114).
8. A high-integration nanowall integrated circuit structure, characterized in that an N-Well silicon single crystal semiconductor region (115) is arranged at the lowest part of the structure, and a silicon single crystal p+ drain region (114) of an nwfet is formed at the upper part of the N-Well semiconductor region (115); a P-silicon single crystal or narrow bandgap pseudomorphic drain region (113) above the p+ drain region (114); an N+ channel semiconductor region (112) over the P-drain region (113); above the n+ channel semiconductor region (112) is a p+ narrow bandgap polycrystalline semiconductor source region (111); the P+ drain region (114) comprises an upper part and a lower part, the lower part is wider than the upper part, the lower surface and the side surface of the lower part are surrounded by an N-Well (115), grooves are formed in the upper part of the P+ drain region (114), the side surfaces of the P-drain region (113), the N+ type channel semiconductor region (112) and the P+ source region (111), and the lower surface of the grooves is lower than the interface of the N+ type channel semiconductor region (112) and the P-drain region (113) and higher than the lower surface of the P-drain region (113); filling a gate electrode (106) and an insulated gate dielectric (107) in the trench; the gate electrode (106) is composed of a heavily doped polycrystalline or refractory metal silicide or refractory metal or a combination thereof; the insulated gate dielectric (107) is used for isolating the gate electrode (106) from other semiconductor regions; the drain electrode (108) is arranged on the side surfaces of the P+ narrow bandgap polycrystalline semiconductor source region (111), the N+ channel semiconductor region (112), the P-drain region (113) and the P+ drain region (114); an insulating material (109) isolates the drain electrode (108) from the p+ source region (111), the n+ channel semiconductor region (112), and the P-drain (113) region; the drain electrode (108) is in contact with the P+ drain region (114), the contact surface being lower than the interface of the P-drain region (113) and the P+ drain region (114).
9. A high-integration nanowall integrated circuit structure, characterized in that an N-Well silicon single crystal semiconductor region (115) is arranged at the lowest part of the structure, and a silicon single crystal p+ drain region (114) of an nwfet is formed at the upper part of the N-Well semiconductor region (115); a P-silicon single crystal or narrow bandgap pseudomorphic drain region (113) above the p+ drain region (114); above the P-drain region (113) is an n+ channel semiconductor region (112); above the n+ channel semiconductor region (112) is a P-silicon single crystal or narrow bandgap pseudomorphic source region (116); above the P-source region (116) is a p+ narrow bandgap polycrystalline semiconductor source region (111); the P+ drain region (114) comprises an upper part and a lower part, the lower part is wider than the upper part, the lower surface and the side surface of the lower part are surrounded by an N-Well (115), grooves are formed in the upper part of the P+ drain region (114), the P-drain region (113), the N+ type channel semiconductor region (112), the P-source region (116) and the side surface of the P+ source region (111), and the lower surface of the grooves is lower than the interface of the P-drain region (113) and the P+ drain region (114) and higher than the lower surface of the P+ drain region (114); filling a gate electrode (106) and an insulated gate dielectric (107) in the trench; the gate electrode (106) is composed of a heavily doped polycrystalline or refractory metal silicide or refractory metal or a combination thereof; the insulated gate dielectric (107) is used for isolating the gate electrode (106) from other semiconductor regions; the drain electrode (108) is arranged on the side surfaces of the P+ source electrode region (111), the P-source electrode region (116), the N+ channel semiconductor region (112), the P-drain electrode region (113) and the P+ drain electrode region (114); the insulating material (109) isolates the drain electrode (108) from the p+ narrow bandgap polycrystalline semiconductor source region (111), the P-silicon single crystal or narrow bandgap pseudomorphic source region (116), the n+ channel semiconductor region (112) and the P-drain (113) region; the drain electrode (108) is in contact with the P+ drain region (114), and the contact surface is lower than the interface between the P-drain region (113) and the P+ drain region (114); the P-source region (116) has a lower doping concentration than the P+ source region (111) and the N+ channel semiconductor region (112).
10. A high-integration nanowall integrated circuit structure, characterized in that an N-Well silicon single crystal semiconductor region (115) is arranged at the lowest part of the structure, and a silicon single crystal p+ drain region (114) of an nwfet is formed at the upper part of the N-Well semiconductor region (115); -a P-drain region (113) above the p+ drain region (114); an N+ channel semiconductor region (112) over the P-drain region (113); above the n+ channel semiconductor region (112) is a P-silicon single crystal or narrow bandgap pseudomorphic source region (116); above the P-source region (116) is a p+ narrow bandgap polycrystalline semiconductor source region (111); the P+ drain region (114) comprises an upper part and a lower part, the lower part is wider than the upper part, the lower surface and the side surface of the lower part are surrounded by an N-Well (115), grooves are formed in the upper part of the P+ drain region (114), the P-drain region (113), the N+ type channel semiconductor region (112), the P-source region (116) and the side surface of the P+ source region (111), and the lower surface of the grooves is lower than the interface of the N+ type channel semiconductor region (112) and the P-drain region (113) and higher than the lower surface of the P-drain region (113); filling a gate electrode (106) and an insulated gate dielectric (107) in the trench; the gate electrode (106) is composed of a heavily doped polycrystalline or refractory metal silicide or refractory metal or a combination thereof; the insulated gate dielectric (107) is used for isolating the gate electrode (106) from other semiconductor regions; the drain electrode (108) is arranged on the side surfaces of the P+ source electrode region (111), the P-source electrode region (116), the N+ channel semiconductor region (112), the P-drain electrode region (113) and the P+ drain electrode region (114); the insulating material (109) isolates the drain electrode (108) from the p+ narrow bandgap polycrystalline semiconductor source region (111), the P-silicon single crystal or narrow bandgap pseudomorphic source region (116), the n+ channel semiconductor region (112) and the P-drain (113) region; the drain electrode (108) is in contact with the P+ drain region (114), and the contact surface is lower than the interface between the P-drain region (113) and the P+ drain region (114); the P-source region (116) has a lower doping concentration than the P+ source region (111) and the N+ channel semiconductor region (112).
11. The high-integration nanowall integrated circuit structure of any one of claims 7-10, wherein said n+ channel semiconductor region (112) has a thickness of less than 12nm.
12. The high integration nanowall integrated circuit structure of any of claims 7-10, wherein said n+ channel semiconductor region (112) has a doping concentration greater than 2 orders of magnitude higher than that of P-drain region (113).
13. The high-integration nanowall integrated circuit structure according to any of claims 1-4 and 7-10, wherein when the channel semiconductor region (102, 112), the n+ drain region (104), the p+ drain region (114), the P-Well semiconductor region (105), the N-Well semiconductor region (115) are monocrystalline silicon, the N-drain region (103), the P-drain region (113), the N-source region (110), the P-source region (116) are narrow bandgap pseudomorphic semiconductor materials (e.g., siGe pseudomorphic), the n+ source region (101), the p+ source region (111) are polycrystalline Ge, polycrystalline SiGe, polycrystalline TWS (mercury cadmium telluride), polycrystalline InP, polycrystalline InSb, or a combination thereof; when the channel semiconductor regions (102, 112), the N+ drain region (104), the P+ drain region (114), the P-Well semiconductor region (105) and the N-Well semiconductor region (115) are made of a wide band gap single crystal semiconductor material (such as SiC single crystal or GaN single crystal), the N-drain region (103), the P-drain region (113), the N-source region (110) and the P-source region (116) are made of pseudomorphic Si semiconductor material, and the N+ source region (101) and the P+ source region (111) are made of polycrystalline Si semiconductor material.
14. The high-integration nanowall integrated circuit structure according to any one of claims 1-4 and 7-10, wherein the gate electrode (106) is disposed in a full area of one side of the channel semiconductor region or in a partial area of one side of the channel semiconductor region; further, the gate electrode (106) is provided in the entire region of both sides of the channel semiconductor region, or in the entire region of one side and a partial region of the other side of the channel semiconductor region; further, the gate electrode (106) is provided in all of three side surfaces of the channel semiconductor region, or in all of two side surfaces of the channel semiconductor region and in a partial region with the other side surface; further, the gate electrode (106) is provided in all regions of four sides of the channel semiconductor region, or all regions of three sides and a partial region of the last side of the channel semiconductor region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210413345.4A CN114899235B (en) | 2022-04-20 | 2022-04-20 | High-integration-level nano-wall integrated circuit structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210413345.4A CN114899235B (en) | 2022-04-20 | 2022-04-20 | High-integration-level nano-wall integrated circuit structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114899235A CN114899235A (en) | 2022-08-12 |
| CN114899235B true CN114899235B (en) | 2023-06-13 |
Family
ID=82717491
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210413345.4A Active CN114899235B (en) | 2022-04-20 | 2022-04-20 | High-integration-level nano-wall integrated circuit structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114899235B (en) |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111048579A (en) * | 2019-12-18 | 2020-04-21 | 电子科技大学 | Novel digital gate integrated circuit structure |
| CN111668220A (en) * | 2020-06-23 | 2020-09-15 | 电子科技大学 | Vertical channel SRAM integrated circuit structure |
| CN112366204B (en) * | 2020-11-10 | 2023-08-11 | 电子科技大学 | High-integration SRAM |
| CN113013234A (en) * | 2021-03-08 | 2021-06-22 | 电子科技大学 | Source region self-aligned vertical channel MOS integrated circuit unit and implementation method thereof |
-
2022
- 2022-04-20 CN CN202210413345.4A patent/CN114899235B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN114899235A (en) | 2022-08-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9472615B2 (en) | Super junction LDMOS finFET devices | |
| US7569873B2 (en) | Integrated circuit using complementary junction field effect transistor and MOS transistor in silicon and silicon alloys | |
| US20090095981A1 (en) | Complementary metal oxide semiconductor device and method of manufacturing the same | |
| KR20140083964A (en) | Accumulation type finfet, circuits and fabrication method thereof | |
| US7709311B1 (en) | JFET device with improved off-state leakage current and method of fabrication | |
| KR20110033033A (en) | Germanium finfets with metal gates and stressors | |
| JP2004241755A (en) | Semiconductor device | |
| US9716169B2 (en) | Lateral double diffused metal oxide semiconductor field-effect transistor | |
| US8299509B2 (en) | Asymmetric source/drain junctions for low power silicon on insulator devices | |
| JP5925740B2 (en) | Tunnel field effect transistor | |
| KR20130095611A (en) | Dual gate lateral mosfet | |
| US7951680B2 (en) | Integrated circuit system employing an elevated drain | |
| JP2014038898A (en) | Semiconductor device | |
| US8415720B2 (en) | Vertically pinched junction field effect transistor | |
| US20080308842A1 (en) | Forming silicides with reduced tailing on silicon germanium and silicon | |
| CN110828459A (en) | Novel DRAM integrated circuit structure | |
| CN114899235B (en) | High-integration-level nano-wall integrated circuit structure | |
| JP2012146817A (en) | Semiconductor device and method of manufacturing the same | |
| KR20240038102A (en) | Method of forming bottom dielectric isolation layers | |
| KR101846991B1 (en) | SiGe P-CHANNEL TRI-GATE TRANSISTOR BASED ON BULK SILICON AND FABRICATION METHOD THEREOF | |
| US11183591B2 (en) | Lateral double-diffused metal-oxide-semiconductor (LDMOS) fin field effect transistor with enhanced capabilities | |
| US11621349B2 (en) | Nano-wall integrated circuit structure with high integrated density | |
| KR101229187B1 (en) | Vertically pinched junction field effect transistor | |
| US8969164B2 (en) | Semiconductor structure and method for manufacturing the same | |
| CN116632006A (en) | Longitudinally stacked grid self-aligned inverter integrated circuit structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |