CN111668220A - Vertical channel SRAM integrated circuit structure - Google Patents
Vertical channel SRAM integrated circuit structure Download PDFInfo
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- CN111668220A CN111668220A CN202010580478.1A CN202010580478A CN111668220A CN 111668220 A CN111668220 A CN 111668220A CN 202010580478 A CN202010580478 A CN 202010580478A CN 111668220 A CN111668220 A CN 111668220A
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- 239000004065 semiconductor Substances 0.000 claims abstract description 31
- 239000000463 material Substances 0.000 claims abstract description 19
- 229910052751 metal Inorganic materials 0.000 claims abstract description 13
- 239000002184 metal Substances 0.000 claims abstract description 13
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 11
- 229920005591 polysilicon Polymers 0.000 claims description 11
- 239000013078 crystal Substances 0.000 claims description 5
- 229910044991 metal oxide Inorganic materials 0.000 claims description 5
- 150000004706 metal oxides Chemical class 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 235000012239 silicon dioxide Nutrition 0.000 claims description 2
- 239000000377 silicon dioxide Substances 0.000 claims description 2
- 229910000661 Mercury cadmium telluride Inorganic materials 0.000 claims 1
- MCMSPRNYOJJPIZ-UHFFFAOYSA-N cadmium;mercury;tellurium Chemical compound [Cd]=[Te]=[Hg] MCMSPRNYOJJPIZ-UHFFFAOYSA-N 0.000 claims 1
- 229910052681 coesite Inorganic materials 0.000 claims 1
- 229910052906 cristobalite Inorganic materials 0.000 claims 1
- 239000003989 dielectric material Substances 0.000 claims 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims 1
- 229910052682 stishovite Inorganic materials 0.000 claims 1
- 229910052905 tridymite Inorganic materials 0.000 claims 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 abstract description 12
- 238000000034 method Methods 0.000 abstract description 8
- 238000005516 engineering process Methods 0.000 abstract description 6
- 238000004377 microelectronic Methods 0.000 abstract description 2
- 238000001259 photo etching Methods 0.000 abstract description 2
- 238000000407 epitaxy Methods 0.000 abstract 1
- 239000000758 substrate Substances 0.000 description 27
- 229910052732 germanium Inorganic materials 0.000 description 7
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 7
- 230000000694 effects Effects 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000015654 memory Effects 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 4
- 239000008186 active pharmaceutical agent Substances 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 229910004262 HgTe Inorganic materials 0.000 description 1
- 206010027439 Metal poisoning Diseases 0.000 description 1
- 241000037831 Polygonatum sibiricum Species 0.000 description 1
- 210000000746 body region Anatomy 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- LFQCEHFDDXELDD-UHFFFAOYSA-N tetramethyl orthosilicate Chemical compound CO[Si](OC)(OC)OC LFQCEHFDDXELDD-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
- H10B10/125—Static random access memory [SRAM] devices comprising a MOSFET load element the MOSFET being a thin film transistor [TFT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
A vertical channel SRAM integrated circuit structure relates to microelectronic technology and semiconductor technology. The SRAM is composed of 6 novel MOS tubes, each MOS tube is of a longitudinal structure and is provided with a silicon germanium material source electrode, a channel, a lightly doped drain electrode and an annular grid. The key technical problems to be solved by the invention are as follows: an SRAM basic unit is designed by utilizing a novel MOS tube. The novel MOS tube is provided with a common grid, and the germanium-silicon is used as a source electrode, so that the areas of metal through holes and interconnection lines can be saved. The lightly doped drain can improve the withstand voltage without depending on the feature size. The four-side annular grid increases the control capability of a channel and reduces the resistance. The longitudinal structure is grown through epitaxy, multiple times of photoetching are avoided, and the process flow and the cost are saved.
Description
Technical Field
The invention relates to microelectronics and semiconductor technology.
Background
As one of the most important memories, a Static Random Access Memory (SRAM) is a critical part of a modern SoC, and performance of the SoC in various aspects such as power consumption and stability is a critical factor of the performance of the whole chip. As shown in fig. 3, the most basic SRAM cell structure at present is composed of 6-transistor CMOS transistors, and a standard 6-transistor SRAM cell is widely used due to its advantages of simple structure, small number of transistors, and small area. It adopts a symmetrical design, the core structure is composed of two pairs of inverters (M1 and M2, M3 and M4), and the data '0' or '1' stored in the unit is kept through the action of anti-muddlehead "[1]。
After the semiconductor technology enters the nanometer level, the parameter fluctuation is larger and larger, the leakage current power consumption is also larger and larger, and the design of the SRAM faces new problems in the aspects of stability, power consumption and the like.
Silicon and germanium are the semiconductor materials discovered at the earliest time and are generally accepted as the first-generation semiconductor materials, the properties of the two semiconductor materials are similar, but the forbidden bandwidth of germanium is smaller than that of silicon, although silicon is the mainstream of the existing semiconductor materials due to abundant resources, low cost and process support, partial use of germanium can enable semiconductor devices to have better performance[2]In the patent "narrow forbidden band source and drain region metal oxide semiconductor field effect transistor and integrated circuit" which has been successfully applied by the inventor of lie flat teaching and lie Zhaoji teaching, it is proposed to use a narrow forbidden band hetero-material different from the substrate material of the device as the source region or the source and drain regions of the device, so that the parasitic BJT emitter junction in the device becomes a hetero-junction, and β is provided<<1, can completely eliminate the parasitic BJT pair BV from the deviceDSInfluence of (2)[3]。
Reference documents:
[1]Sergei Skorobogatov.Low temperature data remanence in staticRAM.University of Cambridge,Computer Laboratory.June 2002[2008-02-27].
[2] design and fabrication of high-speed NPN sige heterojunction bipolar transistor [ J ]. qiansheng, liudonghua, chenfan, chenxiong bin, stone crystal, segmenting, hujun, huangjing feng, research and development of solid electronics 2012(05)
[3] Plum blossom; lenzhige, narrow bandgap source drain to mosfet level integrated circuit: china, CN96117551.6[ P ].1997.11.19.
Disclosure of Invention
The key technical problem to be solved by the invention is the integration level of the SRAM, the bistable structure of the SRAM disclosed by the invention utilizes a novel MOS tube structure, and the bistable circuit unit of the SRAM comprises 4 MOS tubes which are marked as M1, M2, M3 and M4, as shown in FIG. 5. The structure of the M1 tube is: the lowest N + doped substrate is positioned above the N + doped substrate, and an N-epitaxial layer is used as a drain electrode. And a P epitaxial layer is arranged above the N-epitaxial layer and used as a channel. And an N + germanium-silicon epitaxial layer is arranged above the P epitaxial layer and is used as a source. Another lead hole is formed in the SiGe layer and connected to VGND. The structure of the M2 tube is: the lowest P + doped substrate is used as a drain, a P-epitaxial layer is positioned above the P + doped substrate, and the two layers are used as substrates. An N epitaxial layer is arranged above the P-epitaxial layer and used as a channel. And a P + germanium-silicon epitaxial layer is arranged above the N epitaxial layer and is used as a source. The Ge-Si layer has a via hole connected to VDD. The outer rings of the two columnar structures are respectively an oxide layer and a polysilicon layer. A lead hole is arranged on the polysilicon and connected with the input end V of the NOT gatein1. The substrates of M1 and M2 are also connected by metal, and lead out from the lead hole as the output end V of NOT gateout1. The structure of the M3 tube is: the lowest P + doped substrate is used as a drain, a P-epitaxial layer is positioned above the P + doped substrate, and the two layers are used as substrates. An N epitaxial layer is arranged above the P-epitaxial layer and used as a channel. And a P + germanium-silicon epitaxial layer is arranged above the N epitaxial layer and is used as a source. On the SiGe layer is a leadLine hole, connect VDD. The structure of the M4 tube is: the lowest N + doped substrate is positioned above the N + doped substrate, and an N-epitaxial layer is used as a drain electrode. And a P epitaxial layer is arranged above the N-epitaxial layer and used as a channel. And an N + germanium-silicon epitaxial layer is arranged above the P epitaxial layer and is used as a source. Another lead hole is formed in the SiGe layer and connected to VGND. The outer rings of the two columnar structures are respectively an oxide layer and a polysilicon layer. A lead hole is arranged on the polysilicon and connected with the input end V of the NOT gatein2. The substrates of M1 and M2 are also connected by metal, and lead out from the lead hole as the output end V of NOT gateout2. For connecting two NOT gates end to end, Vin1Connected to V by metal interconnection wiresout2，Vin2Connected to V by metal interconnection wiresout1. As shown in fig. 6. As shown in fig. 3, M5 and M6 are respectively connected to the input terminals of the two not gates. Thereby forming an SRAM base cell.
Furthermore, the new structure adopts a narrow-gap semiconductor material germanium as a source region, so that a parasitic BJT (bipolar junction transistor) emitter junction in the device is a heterojunction, and β is formed<<1, can completely eliminate the parasitic BJT pair BV from the deviceDSThe influence of (c). It is no longer necessary to short the substrate and source regions to ground (V for P-type MOSFETs)DD) Thus saving a large amount of area required for substrate contact openings, as shown in fig. 8. Meanwhile, other materials with narrow forbidden bands besides germanium can be used as the source region, such as GeSi, HgTe, InP and the like, so that the flexibility of device design is increased. And when the germanium is used as a source region, a conventional epitaxial or LPCVD process is adopted, and because germanium and silicon have stress, a single crystal or pseudomorphic crystal is not required to be prepared specially, and polycrystal is directly used for optimizing the process flow.
Furthermore, the gate of the structure surrounds the device body area, so that when the gate is applied with proper bias, a four-side channel is formed, and thus, the gate control capability can be increased by the multi-side gate structure like a FINFET (like in FIG. 9), and the four-side channel is even better than the four-side channel of the FINFET, so that the gate control capability is increased, the current density during conduction is improved, and the on-resistance is reduced.
Further, the channel region of the new structure is not completed by the photolithography process, so the channel length is not limited by the photolithography precision. As shown in fig. 1, the body region for forming the channel in the new structure is completed by an epitaxial process, and the thickness of the epitaxial layer is the length of the channel, so that a great deal of cost required by photolithography and complicated process flows such as multiple exposures and the like for achieving the required precision are saved. At present, the molecular beam epitaxy process technology can prepare a single crystal film as thin as tens of atomic layers, and can realize an extremely short channel length.
Furthermore, as the new structure shown in fig. 1 adopts a power MOS structure, that is, an N-drift region structure is added at the front end of the drain region, so that the withstand voltage is greatly improved, and the short channel effect can be effectively suppressed. In the aspect of an ultra-short channel device, because the FINFET can effectively suppress the short channel effect, the FINFET is mainly used in research or market, but the suppression principle of the short channel effect is that the control capability of a fin-shaped structure gate is strong, so the FINFET still follows moore's law, and on the premise that the electric field strength and the current density are not changed, the voltage and the size need to be reduced in equal proportion, that is, the working voltage of the device is limited by the size. However, the novel structure mainly comprises an N-drift region for resisting voltage, the breakdown voltage of the device is not related to the channel length any more, namely the limitation of Moore's law is broken through, and meanwhile, the N-region naturally forms a low-doped drain structure, so that the short-channel effect can be effectively inhibited.
The device structure has the advantages that
1) By using the novel MOS tube structure, the germanium-silicon source can avoid BJT to BVDSThe area of the lead hole is saved;
2) the drain electrode is low doped, so that the short channel effect is inhibited;
3) the PMOS tube and the NMOS tube which form the NOT gate share the grid, so that the area required by a grid interconnection line is saved;
4) the longitudinal structure is grown by using an epitaxial or PECVD technology, so that the photoetching step is saved;
5) longitudinal structure was used, 30% area.
The invention is further described with reference to the following figures and detailed description.
Drawings
FIGS. 1, 2, 3, 4, 5, 6, 7 are drawings in the claims;
FIG. 1 is a cross-sectional view and a perspective view of a novel PMOS tube;
FIG. 2 is a cross-sectional view and a perspective view of a novel NMOS transistor;
FIG. 3 is a circuit diagram of an SRAM;
FIG. 4 is a circuit diagram of a bistable circuit cell;
FIG. 5 is a cross-sectional view of a bistable circuit cell;
fig. 6 is a perspective view of a bistable circuit cell;
FIG. 7 is a top view of a bistable circuit cell;
FIG. 8 is a cross-sectional view and a top view of a conventional TMOS;
FIG. 9 is a device structure of a FINFET;
FIG. 10 is a diagram of an embodiment illustrating a memory circuit comprising an SRAM.
In each figure, 101 is a silicon germanium layer, 102 is a dielectric layer silicon dioxide, 103 is silicon, 104 is a metal electrode, 105 is polysilicon, and 106 is a metal lead.
Detailed Description
A vertical channel SRAM integrated circuit structure is composed of a novel MOS tube structure, the structure is a longitudinal structure, and a source electrode region, a semiconductor channel region and a drain electrode region are respectively arranged in the longitudinal direction; the grid electrode region is surrounded on the periphery in the horizontal direction, a grid medium layer is arranged between the grid electrode and the channel semiconductor region, the drain electrode region at the bottom can be led out from the outer side through a lead hole, a PMOS (P-channel metal oxide semiconductor) tube and an NMOS (N-channel metal oxide semiconductor) tube are connected in series, the grid electrode is connected with the NMOS tube as input, the drain electrode is connected with the PMOS tube as outputDDNMOS is connected to VGNDThereby forming an inverter. And then two inverters are connected end to form a bistable structure unit which is used as a core unit of the SRAM storage.
See fig. 3, 4, 5, 6, 7. Embodiment 1, a vertical channel SRAM integrated circuit structure.
As shown in the circuit diagram of fig. 4, the memory core of the SRAM is a bistable circuit, which is composed of 4 new MOS transistors, which are denoted as M1, M2, M3, and M4, and the internal structure thereof is shown in fig. 5.The structure of the M1 tube is: the lowest N + doped substrate is positioned above the N + doped substrate, and an N-epitaxial layer is used as a drain electrode. And a P epitaxial layer is arranged above the N-epitaxial layer and used as a channel. And an N + germanium-silicon epitaxial layer is arranged above the P epitaxial layer and is used as a source. Another lead hole is formed in the SiGe layer and connected to VGND. The structure of the M2 tube is: the lowest P + doped substrate is used as a drain, a P-epitaxial layer is positioned above the P + doped substrate, and the two layers are used as substrates. An N epitaxial layer is arranged above the P-epitaxial layer and used as a channel. And a P + germanium-silicon epitaxial layer is arranged above the N epitaxial layer and is used as a source. The Ge-Si layer has a via hole connected to VDD. The outer rings of the two columnar structures are respectively an oxide layer and a polysilicon layer. A lead hole is arranged on the polysilicon and connected with the input end V of the NOT gatein1. The substrates of M1 and M2 are also connected by metal, and lead out from the lead hole as the output end V of NOT gateout1. The structure of the M3 tube is: the lowest P + doped substrate is used as a drain, a P-epitaxial layer is positioned above the P + doped substrate, and the two layers are used as substrates. An N epitaxial layer is arranged above the P-epitaxial layer and used as a channel. And a P + germanium-silicon epitaxial layer is arranged above the N epitaxial layer and is used as a source. The Ge-Si layer has a via hole connected to VDD. The structure of the M4 tube is: the lowest N + doped substrate is positioned above the N + doped substrate, and an N-epitaxial layer is used as a drain electrode. And a P epitaxial layer is arranged above the N-epitaxial layer and used as a channel. And an N + germanium-silicon epitaxial layer is arranged above the P epitaxial layer and is used as a source. Another lead hole is formed in the SiGe layer and connected to VGND. The outer rings of the two columnar structures are respectively an oxide layer and a polysilicon layer. A lead hole is arranged on the polysilicon and connected with the input end V of the NOT gatein2. The substrates of M1 and M2 are also connected by metal, and lead out from the lead hole as the output end V of NOT gateout2. For connecting two NOT gates end to end, Vin1Connected to V by metal interconnection wiresout2，Vin2Connected to V by metal interconnection wiresout1As shown in fig. 6 (a). As shown in fig. 3, the drain of M5 is connected to the output terminals of M1 and M2, and the drain of M6 is connected to the output terminals of M3 and M4, so as to form a basic structure of a novel SRAM (the structure is shown in fig. 6 (b)).
See fig. 10. Embodiment 2, a memory circuit overall structure.
The SRAM basic unit is used for storing data repeatedly, the bit selection circuit and the word selection circuit are used for positioning each SRAM unit, the time sequence control circuit is used for controlling the time sequence of the whole storage unit, the write driver is used for controlling the writing of data into the specific SRAM storage unit, the sense amplifier control signal and other units form an integral storage circuit together.
Claims (7)
1. A vertical channel SRAM integrated circuit structure is composed of a novel MOS tube structure, the structure is a longitudinal structure, and a source electrode region, a semiconductor channel region and a drain electrode region are respectively arranged in the longitudinal direction; the grid electrode region is surrounded on the periphery in the horizontal direction, a grid medium layer is arranged between the grid electrode and the channel semiconductor region, the drain electrode region at the bottom can be led out from the outer side through a lead hole, a PMOS (P-channel metal oxide semiconductor) tube and an NMOS (N-channel metal oxide semiconductor) tube are connected in series, the grid electrode is connected with the NMOS tube as input, the drain electrode is connected with the PMOS tube as outputDDNMOS is connected to VGNDThereby forming an inverter. And then two inverters are connected end to form a bistable structure unit as a core unit of the SRAM storage, and the bistable structure unit is characterized in that an oxide layer and a polysilicon layer are respectively arranged on four sides of the outer ring of each MOS tube, so that channels on four sides can be provided, the grid control capability is enhanced, the on-resistance is reduced, and the current density is increased.
2. The vertical channel SRAM integrated circuit structure of claim 1, wherein the gate dielectric layer is a conventional gate dielectric material such as SiO2, HfO2, and the like.
3. The vertical channel SRAM integrated circuit structure of claim 1, wherein the source region is formed from a narrow bandgap semiconductor material such as single crystal Ge, polycrystalline Ge, pseudomorphic Ge, SiGe, mercury cadmium telluride, InP.
4. The vertical channel SRAM integrated circuit structure of claim 1, wherein the channel semiconductor region material is a Si material, and the source region is a narrow bandgap semiconductor material; or, the channel semiconductor region material is a wide bandgap semiconductor material, and the source region is a narrow bandgap semiconductor material; or, the channel semiconductor region material is a wide bandgap semiconductor material, and the source region is a Si material.
5. The vertical channel SRAM integrated circuit structure of claim 1, wherein the source and drain are metal electrodes and the gate electrode is N + polysilicon or a metal electrode or a combination thereof.
6. The vertical channel SRAM integrated circuit structure of claim 1, wherein the channel semiconductor region comprises two first-conductivity-type regions and a second-conductivity-type region, one first-conductivity-type region is disposed between the source and the second-conductivity-type region, the other first-conductivity-type region is disposed between the drain and the second-conductivity-type region, and a lightly-doped first-conductivity-type region is disposed as a drift region on a side close to the second conductivity type; the first conductive type region is made of a P-type semiconductor, and the second conductive type region is made of an N-type semiconductor; or the first conductive type region is made of an N-type semiconductor, and the second conductive type region is made of a P-type semiconductor.
7. The vertical channel SRAM integrated circuit structure of claim 1, wherein the PMOS transistor P-lightly doped layer and the NMOS transistor N-lightly doped layer serve as lightly doped drains.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112366204A (en) * | 2020-11-10 | 2021-02-12 | 电子科技大学 | High-integration-level nano-wall structure SRAM and implementation method |
| CN113013234A (en) * | 2021-03-08 | 2021-06-22 | 电子科技大学 | Source region self-aligned vertical channel MOS integrated circuit unit and implementation method thereof |
| CN114823861A (en) * | 2022-04-12 | 2022-07-29 | 电子科技大学 | Drain region self-aligned vertical channel MOS integrated circuit unit structure and implementation method thereof |
| CN114899235A (en) * | 2022-04-20 | 2022-08-12 | 电子科技大学 | High-integration-level nanometer wall integrated circuit structure |
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| CN110828459A (en) * | 2019-12-18 | 2020-02-21 | 电子科技大学 | Novel DRAM integrated circuit structure |
| CN111048579A (en) * | 2019-12-18 | 2020-04-21 | 电子科技大学 | Novel digital gate integrated circuit structure |
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2020
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| CN103515435A (en) * | 2012-06-26 | 2014-01-15 | 中芯国际集成电路制造(上海)有限公司 | MOS transistor and formation method thereof, and SRAM memory cell circuit |
| CN110828459A (en) * | 2019-12-18 | 2020-02-21 | 电子科技大学 | Novel DRAM integrated circuit structure |
| CN111048579A (en) * | 2019-12-18 | 2020-04-21 | 电子科技大学 | Novel digital gate integrated circuit structure |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112366204A (en) * | 2020-11-10 | 2021-02-12 | 电子科技大学 | High-integration-level nano-wall structure SRAM and implementation method |
| CN112366204B (en) * | 2020-11-10 | 2023-08-11 | 电子科技大学 | High-integration SRAM |
| CN113013234A (en) * | 2021-03-08 | 2021-06-22 | 电子科技大学 | Source region self-aligned vertical channel MOS integrated circuit unit and implementation method thereof |
| CN114823861A (en) * | 2022-04-12 | 2022-07-29 | 电子科技大学 | Drain region self-aligned vertical channel MOS integrated circuit unit structure and implementation method thereof |
| CN114823861B (en) * | 2022-04-12 | 2023-04-28 | 电子科技大学 | Drain region self-aligned vertical channel MOS integrated circuit unit structure and implementation method thereof |
| CN114899235A (en) * | 2022-04-20 | 2022-08-12 | 电子科技大学 | High-integration-level nanometer wall integrated circuit structure |
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Application publication date: 20200915 |