JP3722046B2 - Semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a current control type power element having a U-shaped insulating electrode.
[0002]
[Prior art]
As a prior art as the background of the present invention, one described in Japanese Patent Application Laid-Open No. 8-46192 (hereinafter referred to as a conventional example) filed by the present applicant is known. 7 and 8 are structural views of the semiconductor device cited from the conventional example. In addition, the code | symbol described in a figure, the name of a site | part, etc. are changed suitably and described for convenience of explanation. FIG. 7 is a perspective view for explaining the basic structure, and FIG. 8 is a sectional view thereof.
[0003]
In the figure, reference numeral 51 denotes an n + type substrate region, 52 denotes an n type drain region, 53 denotes an n + type source region, 54 denotes a MOS type electrode, and 55 denotes an insulating film. The MOS type electrode 54 is made of high concentration p + type polysilicon. Reference numeral 61 denotes a drain electrode which is in ohmic contact with the substrate region 51. Reference numeral 63 shown in FIG. 8 denotes a source electrode, which is in ohmic contact with the source region 53 and further with the MOS electrode 54. That is, the MOS type electrode 54 is fixed at the source potential. Therefore, the MOS type electrode 54 and the insulating film 55 are collectively referred to as a fixed potential insulating electrode 56. The cross-sectional structure of the fixed potential insulating electrode is formed in a stripe shape, for example, as shown by a letter “U”, in which the side wall is formed in a substantially vertical groove.
[0004]
The “broken line” in FIG. 8 indicates the presence of the fixed potential insulating electrode 56 in the depth direction of the paper as can be seen from the relationship with FIG. Further, the drain region 52 sandwiched between the fixed potential insulating electrodes 56 is referred to as a channel region 57.
[0005]
Further, a p-type gate region 58 exists at a position away from the source region 53 in contact with the insulating film 55. In FIG. 8, 68 is an electrode that is in ohmic contact with the gate region 58 and is called a gate electrode. In the unit cell region surrounded by the two gate regions 58 and the two fixed potential insulating electrodes 56, two source regions 53 are formed. These two source regions 53 are symmetrically arranged so as to be a predetermined distance from a portion that is equidistant from the two gate regions 58. Reference numeral 60 denotes an interlayer insulating film.
[0006]
This element is used, for example, by setting the source potential to ground (0 V) and applying an appropriate positive potential to the drain electrode 61 via an inductive load such as a motor. Hereinafter, a mechanism in which a positive potential is applied to the gate electrode 68 and the element is turned on to shift to a cut-off state will be described.
[0007]
When the potential of the gate electrode 68 is set to ground (0 V) or a negative potential in order to turn off from the conductive state, excess holes existing in the drain region 52 and the channel region 57 flow into the gate region 58, The concentration decreases sequentially from the vicinity of the gate region 58. In the drain region 52, excessive holes located relatively far from the gate region 58 also move to the channel region 57 having a low potential, and the holes in the drain region 52 are depleted.
[0008]
Then, the resistance of the drain region 52 gradually increases, but when an inductive load such as a motor is connected to the drain electrode 61, the inductive load itself has a property of trying to hold a current value. As the resistance of the drain region 52 increases, the potential of the drain electrode 61 also increases. Then, when a depletion region spreads in the drain region 52 and a carrier travels through a high electric field applied to the drain region 52, a pair of carriers is newly generated.
[0009]
Of the carriers generated in the drain region 52, electrons constitute an electron flow as it is. On the other hand, the holes move to the channel region 57 (FIG. 7) in the direction opposite to the electron flow path, and are discharged to the gate region 58 through the interface of the fixed potential insulating electrode 56. At this time, when the amount of holes generated in the drain region 52 that increases in response to the rise in the drain potential becomes equal to the amount of holes discharged to the gate region 58, a sustain operation occurs at the drain potential. .
[0010]
However, in the conventional element structure, instantaneous breakdown does not occur due to the sustain operation as known in a normal bipolar transistor. This is because a semiconductor chip in which a plurality of conventional element structures are formed has a property that a main current flows in the entire region where the conventional element structure is formed during a sustain operation. When this conventional element structure is used in an inductive load circuit for driving a motor or the like, this property is such as a guard ring or the like formed in the same semiconductor chip due to an increase in drain voltage generated by an induced electromotive force at turn-off. The advantage is that the burden on the pressure-resistant structure can be avoided.
[0011]
Furthermore, by appropriately setting the unit cell size of the conventional structure, the sustain voltage can be obtained from a predetermined voltage applied to the drain electrode 61 when the conventional element is in a cut-off state, and the breakdown voltage of the withstand voltage structure such as a guard ring. Can be designed to any voltage between. For example, in the conventional device structure, when the unit cell size is reduced, the density of the source region 53 per unit area is increased, so that the density of the electron current flowing through the source region 53 is decreased and the drain region 52 is Among these, since the distance from the gate region 58 to the farthest part is shortened, the hole extraction speed is increased.
[0012]
That is, when the unit cell size is reduced, the generation of hole pairs is suppressed, and the generated holes are promoted to discharge, so the sustain voltage becomes higher.
[0013]
However, if the unit cell size of the conventional structure is too small, the current gain is reduced. Thus, in the conventional structure, it was not easy to increase the sustain voltage while maintaining other characteristics.
[0014]
[Problems to be solved by the invention]
As described above, in the conventional element, when the drain electrode 61 is connected to an inductive load such as a motor, the inductive load itself has a property of maintaining a current value. As the resistance increases, the potential of the drain electrode 61 increases. The electron flow that flows from the source region 53 in which the current value is maintained by the inductive load to the substrate region 51 always flows through a path with a small resistance, so that a hole is discharged from the vicinity of the gate region 58. , The drain region 52 flows through a portion farthest from the two gate regions 58 where holes remain until the end, that is, a portion equidistant from the two gate regions 58. From this, in the conductive state, the electron flow was flowing from the two source regions surrounded by the two gate regions 58 and the two fixed potential insulating electrodes 56 to the substrate region 51 through different paths. In the transient state at the time of turn-off, both current paths are concentrated at a portion that is equidistant from the two gate regions 58, so that the current density at this point is higher than that during steady conduction. That is, in the conventional device, since the density of the electron flow flowing through the drain region 52 to which a high electric field is applied becomes high, new carrier pairs are likely to be generated.
[0015]
Further, holes generated by the generation of carrier pairs move to the surface channel region 57 in the direction opposite to the electron flow path, and are discharged to the gate region 58 through the interface of the fixed potential insulating electrode 56. At this time, in the conventional structure, holes are generated in the portion of the drain region 52 that is farthest from the two gate regions 58, so that the resistance of the extraction path when extracting holes from this portion is large.
[0016]
From the above, in the conventional element, since the current density is increased due to the concentration of the electron current path immediately before turning off, holes are easily generated, and the resistance of the hole extraction path is large. The generated holes were difficult to be discharged.
[0017]
The present invention has been made to solve such a conventional problem, and an object of the present invention is to provide a semiconductor device capable of improving the sustain voltage without changing the cell size of the basic structure. There is.
[0018]
[Means for Solving the Problems]
In order to achieve the above object, according to the first aspect of the present invention, there is provided at least two second conductivity type formed at a predetermined interval on one main surface of a semiconductor substrate of the first conductivity type as a drain region. The gate region and a plurality of first grooves arranged in parallel with each other at equal intervals so as to be in contact with the gate region between the gate region and the main surface of the semiconductor substrate, and adjacent to the gate region One main surface of the semiconductor substrate sandwiched between first grooves, at least two first conductivity type source regions formed at an equal distance from the adjacent gate region, and one main surface of the semiconductor substrate A plurality of second grooves formed between the adjacent source regions substantially orthogonal to the first trench, and the drain region and the gate region formed by an insulating film inside the first trench. Is formed to be insulated from the source region. A fixed potential insulated electrode which is kept at the same potential, a part of the drain region in contact with the source region, and having a channel region sandwiched by the fixed potential insulated electrode.
[0022]
【The invention's effect】
In the first aspect of the invention, for example, when the source region is grounded and an appropriate positive potential is applied to the drain region via an inductive load, the gate region is grounded to turn off from the conductive state, or When the potential is negative, excess minority carriers in the drain region and the channel region flow into the gate region, and the minority carrier concentration decreases sequentially from the vicinity of the gate region. In addition, excessive minority carriers existing in a position relatively distant from the gate region in the drain region also move to the main region on the main surface having a low potential, and the minority carriers in the drain region are depleted.
[0023]
At this time, the main region surrounded by the two gate regions and the two fixed potential insulating electrodes is divided by the second groove, and the minority carriers that have moved to the main region are extracted from the vicinity of the gate region, and the source region Since the minority carriers present immediately below are finally extracted, the path of the majority carriers flowing from the source region to the drain region is maintained immediately below the source region, as in the conductive state. That is, in this configuration, the density of majority carriers in the drain region does not change even in a transient state at the turn-off time.
[0024]
Then, as the minority carriers in the drain region are depleted, the drain potential rises, and when a high electric field is applied to the drain region, the minority carriers generated in the drain region are opposite to the majority carrier path, It moves to the main region, passes through the first fixed potential insulating electrode interface, and is discharged to the gate region. In this configuration, the position where minority carriers are generated is close to the gate region because it is close to the source region, so that the generated minority carriers do not stay and are quickly discharged in a short period.
[0025]
From the above, since the amount of minority carriers generated in the drain region is reduced and the amount of minority carriers discharged to the gate region is increased, these amounts can be changed without changing the cell size of the device. The equal sustain voltage is increased. In addition, since minority carriers are discharged quickly at turn-off, the switching speed and the reverse recovery speed during reverse conduction are also improved.
[0027]
Further, since the width of the second groove can be made equal to the width of the first groove, a step formed on the surface on the main surface side can be minimized by the same process. From this, it is possible to make it difficult for the electrode to be disconnected or short-circuited when the surface electrode structure is formed.
[0028]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. 1 to 4 are configuration diagrams of a semiconductor device according to the first embodiment of the present invention.
[0029]
FIG. 1 is a perspective view for explaining a basic structure of the semiconductor device. 2 is an explanatory view showing the surface portion of FIG. 1, and FIG. 3 is a cross-sectional view showing the side portion of FIG. 4 is a cross-sectional view taken along a line AA in the surface view of FIG. Further, FIGS. 1 and 2 depict a state in which the metal film as the surface electrode and the surface protective film are removed for the sake of explanation. In this embodiment, the semiconductor is described as silicon.
[0030]
First, the element structure will be described. 1 to 4, reference numeral 1 denotes an n + type substrate region, 2 denotes an n type drain region, 3 denotes an n + type source region, 4 denotes a first MOS type electrode, and 5 denotes a first insulating film. It is. The first MOS type electrode 4 is made of high concentration p + type polysilicon. Reference numeral 11 denotes a drain electrode which is in ohmic contact with the substrate region 1.
[0031]
Reference numeral 13 (FIG. 3) denotes a source electrode that is in ohmic contact with the source region 3 and the MOS type electrode 4. That is, the first MOS electrode 4 is fixed at the source potential. Therefore, the first MOS type electrode 4 and the first insulating film 5 are collectively referred to as a first fixed potential insulating electrode 6. As shown in FIG. 2, the cross-sectional structure of the first fixed potential insulating electrode 6 is formed in a groove a1 (first groove) whose side walls are substantially vertical, for example, as shown in a “U” shape. .
[0032]
Further, in FIG. 1, the source region 3 is drawn so as to be in contact with the first insulating film 5, but if the source region 3 is disposed so as to be sandwiched between the first fixed potential insulating electrodes 6. It is not necessary to touch. Further, in FIG. 4, a portion of the drain region 2 sandwiched between the first fixed potential insulating electrodes 6 is referred to as a channel region 7. Further, as shown in FIGS. 1 and 3, a p-type gate region 8 exists at a position away from the source region 3 in contact with the first insulating film 5.
[0033]
Reference numeral 18 in FIG. 3 denotes an electrode that is in ohmic contact with the gate region 8 and is referred to as a gate electrode. Reference numeral 10 denotes an interlayer insulating film. Up to this point, the structure is the same as that shown in the conventional example.
[0034]
In the present invention, two source regions 3 are further formed in a unit cell region (b1 shown in FIG. 2) surrounded by two gate regions 8 (8a, 8b) and two first fixed potential insulating electrodes 6. The source regions 3 are arranged so that the distances from the closer gate regions 8 are equal. As shown in FIG. 3, a groove a2 (second groove) is formed between the two source regions 3. The groove a2 is adjacent to the source region 3 and has a first fixed shape. A second fixed potential insulating electrode 16 is disposed so as to be in contact with the potential insulating electrode 6. The second fixed potential insulating electrode 16 includes a second insulating film 15 and a second MOS type electrode 14. In the present embodiment, the second insulating film 15 is the same as the first insulating film 5. It is formed of the same material, and the second MOS type electrode 14 is formed of the same material as the first MOS type electrode 4.
[0035]
In the first embodiment, as an example, a structure in which the manufacturing method can be easily realized is illustrated, but the second fixed potential insulating electrode 16 may have only a groove, for example. Alternatively, the second insulating film 15 and the second MOS type electrode 14 may be partially formed.
[0036]
Further, the second insulating film 15 is drawn so as to be in contact with the source region 3, but the source region 3 is sandwiched between the first fixed potential insulating electrode 6 and the second fixed potential insulating electrode 16. As long as the second insulating film 15 is disposed, the second insulating film 15 may not be in contact with the source electrode 3.
[0037]
Next, the operation of the semiconductor device according to this embodiment configured as described above will be described. In this semiconductor device, for example, the source electrode 13 is grounded (0 V), and an appropriate positive potential is applied to the drain electrode 11 via an inductive load such as a motor.
[0038]
First, when the gate electrode 18 (FIG. 3) is grounded, the device is in a cut-off state. This will be described with reference to FIG. 4. A depletion layer associated with the built-in potential of the first MOS type electrode 4 is formed around the first fixed potential insulating electrode 6. If the distance between the two first fixed potential insulating electrodes 6 facing each other in the channel region 7 (hereinafter referred to as channel thickness H) is sufficiently narrow, the channel region 7 includes the depletion region. This forms a sufficient potential barrier for conduction electrons. At this time, the smaller the channel thickness H, the better the blocking performance.
[0039]
Next, regarding the conductive state, when the potential of the gate electrode 18 (FIG. 3), that is, the potential of the p-type gate region 8 is set to a positive potential of, for example, +0.5 V, the holes are reversed to the p-type gate region. 8 flows into the interface of the first insulating film 5 to form an inversion layer, shields the lines of electric force from the first MOS type electrode 4 forming the potential barrier to the channel region 7, and 7 lowers the potential barrier to the conduction electrons in 7. That is, the drain region 2 and the source region 3 are in a conductive state.
[0040]
When the potential of the gate electrode 18 is further increased, the pn junction composed of the p-type gate region 8 and the surrounding n-type region is forward-biased, and holes are directly injected into the drain region 2 and the channel region 7. . Then, the conductivity of these n-type regions, which have been made low in impurity concentration and high resistance in order to maintain the device breakdown voltage, is increased, and the electron current that is the component of the drain current flows from the source region 3 to the substrate region 1. And it will flow with low resistance.
[0041]
The electron current flowing from the source region 3 spreads radially according to the thickness of the drain region 2 as it moves in the drain region 2, so that the path through which the electron current flows is just in contact with the drain region 2 with the source region 3 as a vertex. It has a conical shape with the substrate region 1 as the bottom surface. At this time, in the configuration of the present embodiment, since the two source regions 3 in the unit cell region are arranged at an appropriate distance, the electron flow paths in the drain region do not substantially overlap.
[0042]
Next, when the gate electrode 18 is set to ground (0 V) or a negative potential in order to turn off the device, excess holes existing in the drain region 2 and the channel region 7 flow into the gate region 8. The hole concentration gradually decreases from the vicinity of the gate region 8. In addition, excessive holes existing in a portion of the drain region 2 away from the gate region 8 also move to the channel region 7 on the surface having a low potential, and the holes in the drain region 2 are depleted.
[0043]
At this time, in this embodiment, since the unit cell region surrounded by the two gate regions 8 and the first fixed potential insulating electrode 6 is divided by the second fixed potential insulating electrode 16, it moves to the surface. The holes thus transferred move to the closer gate region 8. That is, the holes that have moved to the surface are also discharged from the vicinity of the gate region 8 and the holes that existed immediately below the source region 3 are discharged last, so that the electron flow that flows from the source region 3 to the substrate region 1 The path is maintained immediately below the source region 3 as in the conductive state.
[0044]
For this reason, the electron flow paths in the drain region 2 do not substantially overlap as in the steady conduction state, so that the electron flow density in the drain region 2 does not increase even in the transient state.
[0045]
In addition, the potential of the drain electrode 11 rises and a depletion layer spreads in the drain region 2, whereby carriers in a high electric field in the drain region 2 travel, thereby newly generating carrier pairs. Of the carriers generated in the drain region 2, electrons constitute an electron flow as it is.
[0046]
On the other hand, holes move to the channel region 7 on the surface in the direction opposite to the electron flow path, and are discharged to the gate region 8 through the interface of the first fixed potential insulating electrode 6. At this time, in the present embodiment, the position where holes are generated in pairs is the drain region 2 immediately below the source region 3, so that the position where holes are generated is close to the gate region 8, and is closer to the gate region 8 than in the prior art. The resistance of the hole extraction path is small.
[0047]
As described above, the semiconductor device according to the present embodiment has a structure in which generation of a pair of holes is suppressed and resistance of a discharge path of generated holes is small in a transient state at the time of turn-off. The sustain voltage in which the amount of holes generated in the region 2 and the amount of holes extracted in the gate region 8 is equal can be improved as compared with the conventional case.
[0048]
In the present embodiment, as in the conventional element structure, there is no instantaneous breakdown caused by the sustain operation as is known in normal bipolar transistors. This is because the semiconductor chip in which a plurality of element structures according to the present embodiment are formed has the property that the main current flows in the entire region where the element structure according to the present embodiment is formed during the sustain operation.
[0049]
This characteristic is that when the semiconductor device of this embodiment is used in an inductive load circuit that drives a motor or the like, a guard ring formed in the same semiconductor chip due to an increase in drain voltage caused by an induced electromotive force at turn-off. This is an advantage of avoiding the burden on the pressure-resistant structure.
[0050]
Further, in this embodiment, since the hole extraction path from the channel region 7 is short and the hole does not stay easily, the blocking speed of the channel region 7, that is, the turn-off speed is also higher than the conventional one. improves.
[0051]
Furthermore, in this embodiment, for example, the source electrode 13 is grounded (0 V), and has a bidirectional conduction characteristic in which a current flows when a negative potential is applied to the drain electrode 11. For example, the gate electrode 18 is grounded. In this state, when a negative potential of −0.7 V or less is applied to the drain electrode 11, current flows between the source electrode 13 and the drain electrode 11 and between the gate electrode 18 and the drain electrode 11.
[0052]
Even when turning off from this state, the holes spreading in the drain region 2 and the channel region 7 are extracted from the gate region 8 and depleted of the holes to be turned off. The turn-off speed when conducting is also improved. That is, the reverse recovery speed at the time of reverse direction conduction improves.
[0053]
Next, a second embodiment of the present invention will be described using FIG. 5 and FIG. FIG. 5 is a perspective view corresponding to FIG. 1, and FIG. 6 is a cross-sectional view corresponding to FIG. In the second embodiment, in addition to the first embodiment described above, two second fixed potential insulating electrodes 16 are formed so as to be close to one source region 3, respectively. With this configuration, the second fixed potential insulating electrode 16 can be formed with a width substantially equal to that of the first fixed potential insulating electrode 6.
[0054]
Therefore, for example, when the MOS type electrode is formed by a method of depositing high-concentration p-type poly-Si and etching so that p-type polysilicon remains only in the groove, the width of the groove is wide. However, in the second embodiment, the surface step can be minimized.
[0055]
As a result, in the actual process, since the surface electrode structure can be formed more flatly, the disconnection or short circuit of the electrode can be made less likely to occur.
[Brief description of the drawings]
FIG. 1 is a perspective view showing a configuration of a semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a cross-sectional view showing a surface structure of the semiconductor device according to the first embodiment of the present invention.
FIG. 3 is a cross-sectional view showing a side structure of the semiconductor device according to the first embodiment of the present invention.
4 is a cross-sectional view taken along line AA shown in FIG.
FIG. 5 is a perspective view showing a configuration of a semiconductor device according to a second embodiment of the present invention.
FIG. 6 is a cross-sectional view showing a side structure of a semiconductor device according to a second embodiment of the present invention.
FIG. 7 is a perspective view showing a configuration of a conventional semiconductor device.
FIG. 8 is a cross-sectional view showing a side structure of a conventional semiconductor device.
[Explanation of symbols]
1 substrate region 2 drain region 3 source region 4 first MOS type electrode 5 first insulating film 6 first fixed potential insulating electrode 7 channel region 8 (8a, 8b) gate region 10 interlayer insulating film 11 drain electrode 13 source Electrode 14 Second MOS type electrode 15 Second insulating film 16 Second fixed potential insulating electrode 18 Gate electrode 51 Substrate region 52 Drain region 53 Source region 54 MOS type electrode 55 Insulating film 56 Fixed potential insulating electrode 57 Channel region 58 Gate region 60 Interlayer insulating film 61 Drain electrode 63 Source electrode 68 Gate electrode a1 First groove a2 Second groove b1 Unit cell region H Channel thickness

Claims (1)

At least two second conductivity type gate regions formed at predetermined intervals on one main surface of the first conductivity type semiconductor substrate which is a drain region;
A plurality of first grooves arranged in parallel to each other at equal intervals so as to be in contact with the gate region between the gate regions on the main surface of the semiconductor substrate,
At least two source regions of the first conductivity type formed at a position equidistant from the adjacent gate region on one main surface of the semiconductor substrate sandwiched between the adjacent first grooves;
A plurality of second grooves formed between the adjacent source regions on one main surface of the semiconductor substrate, substantially orthogonal to the first groove,
A fixed potential insulating electrode formed in the first trench by being insulated from the drain region and the gate region by an insulating film, and maintained at the same potential as the source region;
A channel region that is part of the drain region in contact with the source region and is sandwiched by the fixed potential insulating electrode;
A semiconductor device comprising:

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