JP3991803B2

JP3991803B2 - Semiconductor device

Info

Publication number: JP3991803B2
Application number: JP2002213890A
Authority: JP
Inventors: 哲也林
Original assignee: Nissan Motor Co Ltd
Current assignee: Nissan Motor Co Ltd
Priority date: 2002-07-23
Filing date: 2002-07-23
Publication date: 2007-10-17
Anticipated expiration: 2022-07-23
Also published as: JP2004055968A

Description

【０００１】
【発明の属する技術分野】
本発明は半導体装置に係り、特にＵ字型絶縁電極を有する電流制御型パワー半導体デバイスに関する。
【０００２】
【従来の技術】
本発明の背景となる従来技術として本出願人が出願した特開平９−３２１２９２号公開特許公報がある。
【０００３】
この従来技術では、例えばｎ^＋型の基板領域、ｎ型のドレイン領域、ｎ^＋型のソース領域、ｐ型のゲート領域、それぞれ例えば高濃度のｐ^＋型ポリシリコン等の導電性材料からなり、第１、第２の絶縁膜を有する第１、第２のＭＯＳ型電極からなっている。
【０００４】
ドレイン領域に設けられたドレイン電極は、基板領域とオーミックコンタクトしている。ソース領域並びに第１のＭＯＳ型電極はソース電極に接続されており、第１のＭＯＳ型電極と第１の絶縁膜を合わせて「固定電位絶縁電極」と呼ぶ。また、ゲート領域並びに第２のＭＯＳ型電極はゲート電極に接続されており、第２のＭＯＳ型電極と第２の絶縁膜を合わせて「可変電位絶縁電極」６０と呼ぶ。固定電位絶縁電極と可変電位絶縁電極は、互いに平行で等間隔にかつ交互に配置されており、両者の断面構造は例えば「Ｕ」の字のように側壁がほぼ垂直な溝の中に形成されている。ソース領域は固定電位絶縁電極と可変電位絶縁電極の間に挟み込まれるように形成されており、ゲート領域は固定電位絶縁電極と可変電位絶縁電極の端部を覆うようにそれらより深く形成されている。また、固定電位絶縁電極並びに可変電位絶縁電極の間に挟まれたドレイン領域をチャネル領域と呼ぶ。
【０００５】
【発明が解決しようとする課題】
ここでは、素子が遮断状態にある場合について説明する。すなわち、ソース電位並びにゲート電位を共に接地（０Ｖ）電位とし、ドレイン電極にしかるべき正の電位を印加すると、ｐ型のゲート領域とｎ型のドレイン領域の接合間と、第１の絶縁膜並びに第２の絶縁膜を介したｐ型の第１のＭＯＳ型電極並びに第２のＭＯＳ型電極とｎ型のドレイン領域間と、に逆バイアスがかかる。すると、高耐圧を得るために低不純物濃度で形成されているドレイン領域にはそれぞれの接合部から空乏層が広がる。さらに、ドレイン電極に印加する正電位を高めていくと、ゲート領域もしくは固定電位絶縁電極もしくは可変電位絶縁電極のいずれかのドレイン領域との接合部における電界強度が臨界電界に到達し、そこでアバランシェ降伏が起こる。アバランシェ降伏が起こるドレイン電圧はドレイン領域の厚みに依存しているため、各接合部においてドレイン領域の厚みが最も小さい部分でアバランシェ降伏が起こり、従来の素子ではゲート領域直下のドレイン領域の厚みが最も小さく、その接合部でアバランシェ降伏が起こる。このことから、さらにアバランシェ降伏電圧を効率よく高めるためには、ゲート領域と固定電位絶縁電極と可変電位絶縁電極の深さは同程度とするのが良い。
【０００６】
しかし、従来構造においては上述のとおり、ゲート領域は固定電位絶縁電極と可変電位絶縁電極の端部を覆うようにそれらより深く形成されているため、ゲート領域を固定電位絶縁電極および可変電位絶縁電極と同程度の深さに形成することが難しい。なぜなら、ゲート領域を固定電位絶縁電極および可変電位絶縁電極と同程度の深さとした場合、３次元状の突起となる固定電位絶縁電極および可変電位絶縁電極の端部がドレイン電界にさらされ電界集中が起こるため、かえって低いドレイン電圧でアバランシェ降伏が生じてしまうからである。
【０００７】
このことから、本発明は上記のような問題点に着目し、アバランシェ降伏電圧とトレードオフ関係にあるオン抵抗、電流増幅率、スイッチング速度などの半導体装置の諸特性を向上する構造を提供することを目的としている。
【０００８】
【課題を解決するための手段】
上記の目的を達成するため、本発明においては、ドレイン領域である一導電型の半導体基体の一主面に、互いに平行にかつ交互に配置された複数の第１、第２の溝を有し、第１、第２の溝に挟まれた主面には同一導電型のソース領域と反対導電型のゲート領域が形成され、第１の溝内には、第１の絶縁膜によってドレイン領域とは絶縁され、ソース領域と同電位に保たれた固定電位絶縁電極を有し、固定電位絶縁電極は隣接するドレイン領域に空乏領域を形成するような仕事関数の導電性材料から成り、第２の溝内には、第２の絶縁膜によってドレイン領域とは絶縁され、ゲート領域と同電位に保たれた可変電位絶縁電極を有し、可変電位絶縁電極は隣接するドレイン領域に空乏領域を形成するような仕事関数の導電性材料から成り、固定電位絶縁電極と可変電位絶縁電極によって挟み込まれたチャネル領域を有し、ドレイン領域、ソース領域、ゲート領域、固定電位絶縁電極および可変電位絶縁電極を含んでなる複数の基本構造を有し、隣接する該基本構造の固定電位絶縁電極どうし、および可変電位絶縁電極どうしがつながっており、チャネル領域には空乏領域によって多数キャリアの移動を阻止するポテンシャル障壁が形成され、ゲート領域から少数キャリアが導入されると、チャネル領域に形成されたポテンシャル障壁を減少もしくは消滅させてチャネルが開くようになっている。
【０００９】
【発明の効果】
本発明によれば、アバランシェ降伏電圧とトレードオフ関係にあるオン抵抗、電流増幅率、スイッチング速度などの半導体装置の諸特性を従来以上に向上することができる。
【００１０】
【発明の実施の形態】
以下、本発明を各実施の形態によって詳細に説明する。
【００１１】
第１の実施の形態
本発明の第１の実施の形態について、図１〜図５を用いて説明する。図１は素子の基本構造を説明する斜視図である。図２は図１の前面と同じ部分を示す断面図。図３は図１の後面と同じ部分を示す断面図である。図４は図１の上面と同じ部分を示す表面図である。図５は図１の側面と同じ断面図である。つまり、図４の表面図中の線分Ａ−Ａに沿って紙面に垂直に切った断面図が図２であり、同じく線分Ｂ−Ｂに沿って切った断面図が図３であり、同じく線分Ｃ−Ｃに沿って切った断面図が図５である。なお図４と図５は、ともに図１に示した基本構造の２単位分を示している。また、上記図１〜図３においては、説明のため表面の電極である金属膜ならびに表面保護膜を除去した様子を描いている。なお、この実施の形態では半導体をシリコンとして説明する。
【００１２】
初めに素子構造を説明する。まず図１〜図５中において、番号１はｎ^＋型の基板領域、２はｎ型のドレイン領域、３はｎ^＋型のソース領域、４はｐ型のゲート領域である。５は第１のＭＯＳ型電極、６は第１の絶縁膜、８は第２のＭＯＳ型電極、９は第２の絶縁膜である。第１のＭＯＳ型電極５並びに第２のＭＯＳ型電極８はそれぞれ導電性材料からなっており、本実施の形態においては容易に製造ができる共に同じ材料（例えば高濃度のｐ^＋型ポリシリコン）で形成した場合を例示している。また、第１の絶縁膜６並びに第２の絶縁膜９についても、本実施の形態においては容易に製造ができる共に同じ材料（例えばシリコン酸化物）で形成した場合を例示している。本実施の形態においては、一例として製造方法が容易に実現できる構造を示しているが、第２のＭＯＳ型電極８や第２の絶縁膜９が第１のＭＯＳ型電極５や第１の絶縁膜６と別の材料で構成されていてもかまわない。
【００１３】
１１はドレイン電極で基板領域１とオーミックコンタクトしている。図２、図５に示す１３はソース電極で、層間絶縁膜１２に穿たれた各ソースコンタクトホール１５（図４）を介して、それぞれ第１のＭＯＳ型電極５とそれを挟んで隣りあう２つのソース領域３に同時に接続している。これにより、ソース電極１３は第１のＭＯＳ型電極５並びに島状に孤立している各ソース領域３全てとオーミックコンタクトしている。このことから、第１のＭＯＳ型電極５はソース電位に固定されているため、この第１のＭＯＳ型電極５と第１の絶縁膜６を合わせて「固定電位絶縁電極」７と呼ぶ。図３、図５に示す１４はゲート電極で、層間絶縁膜１２に穿たれた各ゲートコンタクトホール１６（図４）を介して、それぞれ第２のＭＯＳ型電極８とそれを挟んで隣りあう２つのゲート領域４に同時に接続している。これにより、ゲート電極１４は第２のＭＯＳ型電極８並びに島状に孤立している各ゲート領域４全てとオーミックコンタクトしている。このことから、第２のＭＯＳ型電極８はゲート電位に固定されているため、この第２のＭＯＳ型電極８と第２の絶縁膜９を合わせて「可変電位絶縁電極」１０と呼ぶ。
【００１４】
固定電位絶縁電極７と可変電位絶縁電極１０は、図１〜図４に示すように、互いに平行で等間隔にかつ交互に配置され、両者の断面構造は例えば「Ｕ」の字のように側壁がほぼ垂直な溝の中に形成されている。そして、固定電位絶縁電極７と可変電位絶縁電極１０の間に挟み込まれるように、ソース領域３並びにゲート領域４が互いに接しないように配置されている。このことから、図４に示す基本構造２単位分が左右に鏡像関係で繰り返し配置される場合、本実施の形態においては固定電位絶縁電極７並びに可変電位絶縁電極１０には端部が生じない構造となっている。なお、本実施の形態においてはゲート領域４が固定電位絶縁電極７並びに可変電位絶縁電極１０の深さより浅く形成された場合で説明しているが、それらの深さと同等もしくはそれ以上深く形成されていてもかまわない。また、図１及び図２において固定電位絶縁電極７並びに可変電位絶縁電極１０の間に挟まれたドレイン領域２をチャネル領域１７と呼ぶ。
【００１５】
次に動作を説明する。本実施の形態においてはソース電極１３を接地しドレイン電極１１に正電位を印加した状態で、ゲート電極１４に制御信号を与えて動作させる順方向動作と、ドレイン電極１１を接地しソース電極１３並びにゲート電極１４に正電位を与えて動作させる逆方向動作の両方の動作が可能な双方向導通特性を有している。
【００１６】
先ず、順方向動作について説明する。例えばソース電極１３（図２）を接地し、ドレイン電極１１にしかるべき正電位を印加した状態において、ゲート電極１４が接地もしくは負電位とした場合、この素子は遮断状態を維持する。固定電位絶縁電極７並びに可変電位絶縁電極１０の周囲には仕事関数差による第１のＭＯＳ型電極５並びに第２のＭＯＳ型電極８のビルトイン電位に伴う空乏層が形成されているが、チャネル領域１７内で対向する２つの固定電位絶縁電極７並びに可変電位絶縁電極１０間の距離（以下、これをチャネル厚みＨと呼ぶことにする）が充分狭ければ、チャネル領域１７にはこの空乏領域によって伝導電子に対する充分なポテンシャル障壁が形成されている。また、本実施の形態においては、各基本構造において固定電位絶縁電極７並びに可変電位絶縁電極１０に端部が生じないため、ゲート領域４が浅く形成されていても固定電位絶縁電極７並びに可変電位絶縁電極１０底部の電界分布はほぼ同様となっている。つまり、固定電位絶縁電極７並びに可変電位絶縁電極１０の底部とドレイン領域２の距離を従来に比べて小さく設定しても従来と同等のアバランシェ降伏電圧となる。このことから、本実施の形態においては固定電位絶縁電極７並びに可変電位絶縁電極１０の底部とドレイン領域５２との距離を、従来構造のゲート領域５４の底部とドレイン領域５２との距離と同等に設定することで同等の耐圧性能を得ることができる。つまり、従来に比べてドレイン領域２の厚みを小さくすることができる。
【００１７】
次に導通状態であるが、ゲート電極１４（図３）の電位すなわちｐ型ゲート領域４ならびに可変電位絶縁電極１０にたとえば＋０．５Ｖの電圧を印加すると、チャネル領域１７のポテンシャル障壁が低下し主電流が流れ始める。すなわち、固定電位絶縁電極７の第１の絶縁膜６界面にはｐ型ゲート領域４から少数キャリアである正孔が流れ込んで反転層を形成し、第１のＭＯＳ型電極５からチャネル領域１７への電気力線を遮蔽するため、界面の電位を上昇させる。また可変電位絶縁電極１０の第２の絶縁膜９界面においては正電位を印加したことにより電位が上昇する。よって、第１の絶縁膜６および第２の絶縁膜９界面の伝導電子に対するポテンシャル障壁は低下する。すなわち、これによってドレイン領域２とソース領域３は導通状態となる。さらに、ゲート電極１４の電位を上げていくと、ｐ型ゲート領域４と周辺のｎ型領域からなるｐｎ接合が順バイアスされ、正孔は直接ドレイン領域２ならびにチャネル領域１７へと注入される。すると、耐圧を保つために不純物濃度を薄く、高抵抗に作られていたこれらｎ型の領域は伝導度が高められ、電流は低い抵抗で流れるようになる。このとき、本実施の形態においては、ドレイン領域２の厚みが従来構造に比べて小さくできるためオン抵抗を低減することができる。また、ｎ型領域の伝導度を高めるために必要な正孔の量自体を減らすことができるため電流増幅率を向上することができる。
【００１８】
また、従来構造においては、ゲート領域は固定電位絶縁電極及び可変電位絶縁電極の端部を覆うように深く形成しなければならなかったため、ドレイン領域の厚みによって変化する導通特性にあわせて、基本構造を最適化することが難しかった。つまり、従来構造においてはゲート領域を小さく形成できないばかりか、ゲート領域の横方向の広がりを考慮した基本構造設計を必要としているためである。それに対して、本実施の形態においてはゲート領域４の深さを自由に設定できるため、ドレイン領域２の厚みによって変化する導通特性にあわせて、基本構造を最適化することができる。
【００１９】
次に、ターンオフについて説明する。まず、導通状態からターンオフさせるために、ゲート電極１４の電位を負電位に転じると、ドレイン領域２およびチャネル領域１７における正孔はゲート領域４近傍から順次減少する。このときチャネル領域１７内においては、高水準注入状態は解除される。可変電位絶縁電極１０は固定電位絶縁電極７より負電位になるので、チャネル領域１７内の正孔は負電位を印加された可変電位絶縁電極１０の第２の絶縁膜９界面に強い反転層を形成し、チャネル領域１７内の正孔はこれを伝ってゲート領域４へと流れる。このとき本実施の形態においては、ドレイン領域２が小さく、そこに注入されていた正孔自体の量が小さくなるため、従来に比べて正孔は速やかに排出され、ターンオフ速度が向上する。
【００２０】
次に、逆方向動作について説明する。例えばドレイン電極１１を接地し、ソース電極１３並びにゲート電極１４それぞれしかるべき正電位を印加した場合逆方向に導通する。この逆導通状態においても、上述した順方向の動作と同じように、固定電位絶縁電極７の第１の絶縁膜６界面にはｐ型ゲート領域４から正孔が流れ込んで反転層を形成し、第１のＭＯＳ型電極５からチャネル領域１７への電気力線を遮蔽するため、界面の電位を上昇させる。また可変電位絶縁電極１０の第２の絶縁膜９界面においては正電位を印加したことにより電位が上昇する。よって、第１の絶縁膜６および第２の絶縁膜９界面の多数キャリアである伝導電子に対するポテンシャル障壁は低下する。すなわち、ソース領域３ドレイン領域２は導通状態となる。また、ｐ型ゲート領域４と周辺のｎ型領域からなるｐｎ接合も順バイアスされ、正孔はドレイン領域２ならびにチャネル領域１７に直接注入されるため、基板領域１からソース領域３に向けて電子流が低い抵抗で流れるようになる。さらに、ｐ型のゲート領域４とｎ型のドレイン領域２のｐｎダイオードもオンするため、ゲート領域４とドレイン領域２との間でも電流が流れる。このとき、本実施の形態においては順方向導通時と同様に、ドレイン領域２の厚みが従来構造に比べて小さくできるため逆導通時のオン抵抗も低減することができる。また、ｎ型領域に注入される正孔の量自体も減らすことができるため逆方向導通時の電流増幅率も向上することができる。
【００２１】
次に、この状態から遮断状態に移行すべく、ソース領域３並びにゲート領域４に接地（０Ｖ）もしくは負電位を印加すると、順方向導通時と同様に、ドレイン領域２およびチャネル領域１７における正孔はゲート領域４近傍から順次減少すると共に、可変電位絶縁電極１０は固定電位絶縁電極７より負電位になるので、チャネル領域１７内の正孔は負電位を印加された可変電位絶縁電極１０の第２の絶縁膜９界面に強い反転層を形成し、チャネル領域１７内の正孔はこれを伝ってゲート領域４へと流れる。このとき本実施の形態においては順方向導通時と同様に、ドレイン領域２が小さくドレイン領域２に注入されていた正孔自体の量が小さいため、従来に比べて速やかに正孔を排出できるため逆方向導通時のターンオフ速度を向上することができる。
【００２２】
上記のように、本実施の形態では、ドレイン領域２である一導電型の半導体基体の一主面に、互いに平行にかつ交互に配置された複数の第１の溝と第２の溝を有している。これら第１の溝と第２の溝に挟まれた主面には同一導電型のソース領域３と反対導電型のゲート領域４が互いに接しないように形成されている。第１の溝の内部には、第１の絶縁膜６によってドレイン領域２とは絶縁され、かつ、ソース領域３と同電位に保たれた固定電位絶縁電極７を有し、固定電位絶縁電極７は第１の絶縁膜６を介して隣接するドレイン領域２に空乏領域を形成するような仕事関数の導電性材料から成っている。第２の溝の内部には、第２の絶縁膜９によってドレイン領域２とは絶縁され、かつ、ゲート領域４と同電位に保たれた可変電位絶縁電極１０を有し、可変電位絶縁電極１０は第２の絶縁膜９を介して隣接するドレイン領域２に空乏領域を形成するような仕事関数の導電性材料から成っている。また、ドレイン領域２の一部であって固定電位絶縁電極７と可変電位絶縁電極１０によって挟み込まれたチャネル領域１７を有し、ドレイン領域２、ソース領域３、ゲート領域４、固定電位絶縁電極７および可変電位絶縁電極１０を含んでなる複数の基本構造を有し、隣接する該基本構造の固定電位絶縁電極７どうし、および可変電位絶縁電極１０どうしがつながっており、チャネル領域１７には固定電位絶縁電極７並びに可変電位絶縁電極１０の周囲に形成された空乏領域によって多数キャリアの移動を阻止するポテンシャル障壁が形成されていて、ゲート領域４から少数キャリアが導入されると、第１の絶縁膜６並びに第２の絶縁膜９の界面に反転層を形成し、固定電位絶縁電極７並びに可変電位絶縁電極１０からドレイン領域２への電界を遮蔽してチャネル領域１７に形成されたポテンシャル障壁を減少もしくは消滅させてチャネルが開くようになっている。
【００２３】
また、主面を覆うように形成された層間絶縁膜１２と、層間絶縁膜１２に接しかつ互いに接しないように形成されたソース電極１３及びゲート電極１４を有する。層間絶縁膜１２には、固定電位絶縁電極７を挟んで隣り合う２つのソース領域３並びに固定電位絶縁電極７が同時にソース電極１３と接続するためのソースコンタクトホール１５が穿たれている。また、層間絶縁膜１２には、可変電位絶縁電極１０を挟んで隣り合う２つのゲート領域４並びに可変電位絶縁電極１０が同時にゲート電極１４と接続するためのゲートコンタクトホールが穿たれている。これにより、本発明による半導体装置を容易に具現化することができる。
【００２４】
以上のように本実施の形態によれば、固定電位絶縁電極７並びに可変電位絶縁電極１０に端部が生じず、ゲート領域４を浅く形成することができることから、固定電位絶縁電極７並びに可変電位絶縁電極１０直下のドレイン領域２の厚みを従来と同等にした場合は、従来以上にアバランシェ降伏電圧を向上することができ、また従来と同等のアバランシェ降伏電圧とした場合は、固定電位絶縁電極７並びに可変電位絶縁電極１０直下のドレイン領域２の厚みを小さくすることができるため、アバランシェ降伏電圧とトレードオフ関係にあるオン抵抗、電流増幅率、スイッチング速度などの諸特性を従来以上に向上することができる。
【００２５】
第２の実施の形態
次に、図６を用いて第２の実施の形態を説明する。図６は図４に対応する表面図であり、第１の実施の形態で示した半導体装置の基本構造が複数形成された場合の最外部の構造を示している。第２の実施の形態においては第１の実施の形態の構成に加えて、第３のＭＯＳ型電極１８と第３の絶縁膜１９からなる絶縁電極２０を有している。絶縁電極２０は固定電位絶縁電極７並びに可変電位絶縁電極１０の端部の近傍に形成されており、例えば固定電位絶縁電極７と可変電位絶縁電極１０の距離となるチャネル厚みＨと同程度の距離にある。
【００２６】
次に動作について説明する。ソース電極並びにゲート電極を共に接地（０Ｖ）電位としドレイン電極１１に正電位を印加した遮断状態において、最外部の基本構造における固定電位絶縁電極７もしくは可変電位絶縁電極１０の端部に電界集中が起こるのを緩和することができる。つまり、第２の実施の形態においては、第１の絶縁膜６並びに第２の絶縁膜９を介して第１のＭＯＳ型電極５並びに第２のＭＯＳ型電極８とｎ型のドレイン領域間に逆バイアスがかかるのと同時に、第３の絶縁膜１９を介して第３のＭＯＳ型電極１８とドレイン領域間にも逆バイアスがかかる。すると、絶縁電極２０とドレイン領域の接合からもドレイン領域側に空乏層が広がるため、絶縁電極２０の近傍に形成されている固定電位絶縁電極７並びに可変電位絶縁電極１０の端部に生じるドレイン電界の集中を緩和することができる。このように、本実施の形態では、第１の溝の端部並びに第２の溝の端部の近傍に第３の溝を有しており、この第３の溝の内部には、第３の絶縁膜１９によってドレイン領域とは絶縁された絶縁電極２０を有し、この絶縁電極２０は固定電位絶縁電極７の端部並びに可変電位絶縁電極１０の端部におけるドレイン領域からの電界集中を緩和している。
【００２７】
このことから本実施の形態にすることによって、基本構造の最外部に生じる固定電位絶縁電極７並びに可変電位絶縁電極１０の端部においてアバランシェ降伏電圧が低下するのを抑えることができる。
【００２８】
第３の実施の形態
次に、図７および図８を用いて第３の実施の形態を説明する。図７並びに図８は図６の第２の実施の形態に対応する表面図である。図７は、絶縁電極２０が可変電位絶縁電極１０と接続された場合を示しており、可変電位絶縁電極１０は最外部でも端部が生じず、かつ固定電位絶縁電極７の端部は周囲を絶縁電極２０並びに可変電位絶縁電極１０にて囲まれるように形成されている。また図８は、絶縁電極２０が固定電位絶縁電極７と接続された場合を示しており、固定電位絶縁電極７は最外部でも端部が生じず、かつ可変電位絶縁電極１０の端部は周囲を絶縁電極２０並びに固定電位絶縁電極７にて囲まれるように形成されている。
【００２９】
このように、絶縁電極２０は図８に示すように固定電位絶縁電極７の端部もしくは図７に示すように可変電位絶縁電極１０の端部のどちらか一方と接続されている。
【００３０】
次に動作について説明する。絶縁電極２０はソース電位もしくはゲート電位に固定されるため、遮断状態における絶縁電極２０からドレイン領域側に伸びる空乏層が固定電位絶縁電極７もしくは可変電位絶縁電極１０の端部から伸びる空乏層と同程度となり、さらには端部が残る一方の電極を絶縁電極と接続された他方の電極で取り囲むため、固定電位絶縁電極７もしくは可変電位絶縁電極１０の端部に生じるドレイン電界の集中を第２の実施の形態よりもさらに緩和することができ、アバランシェ降伏電圧が低下するのをさらに抑えることができる。
【００３１】
第４の実施の形態
次に、図９および図１０を用いて第４の実施の形態を説明する。図９並びに図１０は図６の第２の実施の形態に対応する表面図である。図９並びに図１０は、第１の実施の形態で示した半導体装置の基本構造を複数用いた場合の四隅の構造を示している。図９においては、絶縁電極２０が固定電位絶縁電極７並びに可変電位絶縁電極１０の端部と近接して、かつ所定の曲率で湾曲している。また、図１０では湾曲した絶縁電極２０が可変電位絶縁電極１０と接続された場合を例示しているが、絶縁電極２０は固定電位絶縁電極７と接続されていてもかまわない（図８参照）。
【００３２】
このように、絶縁電極２０は、ドレイン領域からの電界が集中するような端部もしくは角部が生じないように、当該半導体装置の隅部において湾曲している。
【００３３】
本実施の形態では、ソース電極並びにゲート電極を共に接地（０Ｖ）電位としドレイン領域に正電位を印加した遮断状態において、第１の実施の形態の半導体装置を複数配置した際に、四隅における絶縁電極２０が固定電位絶縁電極７並びに可変電位絶縁電極１０の端部と近接し、かつ所定の曲率で湾曲しているため絶縁電極２０に３次元状の突起となる端部が生じない。このため、絶縁電極２０にかかるドレイン電界を緩和することができるため、絶縁電極２０でのアバランシェ降伏電圧が低下するのを抑えることができる。
【００３４】
以上、本発明を前記実施の形態に基づいて具体的に説明したが、前記実施の形態はあくまで一例であって、本発明はこれらに限定されるものではもちろんなく、その要旨を逸脱しない範囲において種々変更可能であることは言うまでもない。
【図面の簡単な説明】
【図１】本発明の第１の実施の形態の斜視図
【図２】本発明の第１の実施の形態の断面図
【図３】本発明の第１の実施の形態の別の断面図
【図４】本発明の第１の実施の形態の表面図
【図５】本発明の第１の実施の形態の側面図
【図６】本発明の第２の実施の形態の表面図
【図７】本発明の第３の実施の形態の表面図
【図８】本発明の第３の別の実施の形態の表面図
【図９】本発明の第４の実施の形態の表面図
【図１０】本発明の第４の別の実施の形態の表面図
【符号の説明】
１…基板領域
２…ドレイン領域
３…ソース領域
４…ゲート領域
５…第１のＭＯＳ型電極
６…第１の絶縁膜
７…固定電位絶縁電極
８…第２のＭＯＳ型電極
９…第２の絶縁膜
１０…可変電位絶縁電極
１１…ドレイン電極
１２…層間絶縁膜
１３…ソース電極
１４…ゲート電極
１５…ソースコンタクトホール
１６…ゲートコンタクトホール
１７…チャネル領域
１８…第３のＭＯＳ型電極
１９…第３の絶縁膜
２０…絶縁電極[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly to a current control type power semiconductor device having a U-shaped insulating electrode.
[0002]
[Prior art]
As a prior art which is the background of the present invention, there is Japanese Patent Application Laid-Open No. 9-32292 filed by the present applicant.
[0003]
In this prior art, for example, n ⁺ Type substrate region, n type drain region, n ⁺ Type source region and p type gate region, for example, high concentration p ⁺ The first and second MOS electrodes are made of a conductive material such as type polysilicon and have first and second insulating films.
[0004]
The drain electrode provided in the drain region is in ohmic contact with the substrate region. The source region and the first MOS type electrode are connected to the source electrode, and the first MOS type electrode and the first insulating film are collectively referred to as a “fixed potential insulating electrode”. The gate region and the second MOS type electrode are connected to the gate electrode, and the second MOS type electrode and the second insulating film are collectively referred to as a “variable potential insulating electrode” 60. The fixed potential insulating electrodes and the variable potential insulating electrodes are arranged in parallel with each other at equal intervals and alternately, and the cross-sectional structure of both is formed in a groove whose side walls are substantially vertical, for example, "U". ing. The source region is formed so as to be sandwiched between the fixed potential insulating electrode and the variable potential insulating electrode, and the gate region is formed deeper so as to cover the end portions of the fixed potential insulating electrode and the variable potential insulating electrode. . A drain region sandwiched between the fixed potential insulating electrode and the variable potential insulating electrode is referred to as a channel region.
[0005]
[Problems to be solved by the invention]
Here, a case where the element is in a cut-off state will be described. That is, when both the source potential and the gate potential are set to the ground (0 V) potential and an appropriate positive potential is applied to the drain electrode, the junction between the p-type gate region and the n-type drain region, the first insulating film, A reverse bias is applied to the p-type first MOS type electrode and the second MOS type electrode and the n-type drain region via the second insulating film. Then, a depletion layer spreads from each junction in the drain region formed with a low impurity concentration in order to obtain a high breakdown voltage. Furthermore, when the positive potential applied to the drain electrode is increased, the electric field strength at the junction with the drain region of either the gate region or the fixed potential insulating electrode or the variable potential insulating electrode reaches a critical electric field, where an avalanche breakdown occurs. Happens. Since the drain voltage at which avalanche breakdown occurs depends on the thickness of the drain region, avalanche breakdown occurs at the portion where the drain region is the smallest at each junction, and in the conventional device, the drain region immediately below the gate region has the largest thickness. Small and avalanche breakdown occurs at the junction. Therefore, in order to further increase the avalanche breakdown voltage more efficiently, it is preferable that the depths of the gate region, the fixed potential insulating electrode, and the variable potential insulating electrode be approximately the same.
[0006]
However, in the conventional structure, as described above, the gate region is formed deeper than the fixed potential insulating electrode and the variable potential insulating electrode so as to cover the end portions of the fixed potential insulating electrode and the variable potential insulating electrode. It is difficult to form at the same depth. This is because when the gate region has the same depth as the fixed potential insulating electrode and the variable potential insulating electrode, the end portions of the fixed potential insulating electrode and the variable potential insulating electrode, which are three-dimensional projections, are exposed to the drain electric field and the electric field is concentrated. This is because avalanche breakdown occurs at a low drain voltage.
[0007]
Accordingly, the present invention focuses on the above problems and provides a structure for improving various characteristics of a semiconductor device such as on-resistance, current amplification factor, and switching speed that are in a trade-off relationship with an avalanche breakdown voltage. It is an object.
[0008]
[Means for Solving the Problems]
In order to achieve the above object, the present invention has a plurality of first and second grooves arranged alternately and parallel to each other on one main surface of a semiconductor substrate of one conductivity type as a drain region. A gate region of the opposite conductivity type to the source region of the same conductivity type is formed on the main surface sandwiched between the first and second trenches, and a drain region and a drain region are formed in the first trench by a first insulating film. Has a fixed potential insulating electrode that is insulated and maintained at the same potential as the source region, and the fixed potential insulating electrode is made of a conductive material having a work function that forms a depletion region in the adjacent drain region. The trench has a variable potential insulating electrode insulated from the drain region by the second insulating film and maintained at the same potential as the gate region, and the variable potential insulating electrode forms a depletion region in the adjacent drain region. Made of conductive material with a work function like Has a channel region sandwiched by the insulated electrode and the variable potential insulated electrodes, It has a plurality of basic structures including a drain region, a source region, a gate region, a fixed potential insulating electrode and a variable potential insulating electrode, and adjacent fixed potential insulating electrodes of the basic structure and variable potential insulating electrodes are connected to each other. And In the channel region, a potential barrier is formed to block the movement of majority carriers by the depletion region, and when minority carriers are introduced from the gate region, the potential barrier formed in the channel region is reduced or eliminated so that the channel opens. It has become.
[0009]
【The invention's effect】
According to the present invention, various characteristics of a semiconductor device such as on-resistance, current amplification factor, and switching speed that are in a trade-off relationship with an avalanche breakdown voltage can be improved more than ever.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described in detail by embodiments.
[0011]
First embodiment
A first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a perspective view for explaining the basic structure of the element. 2 is a cross-sectional view showing the same part as the front surface of FIG. 3 is a cross-sectional view showing the same portion as the rear surface of FIG. 4 is a surface view showing the same portion as the upper surface of FIG. FIG. 5 is the same cross-sectional view as the side view of FIG. That is, FIG. 2 is a cross-sectional view taken along the line AA in the surface view of FIG. 4 perpendicular to the paper surface, and FIG. 3 is a cross-sectional view taken along the line BB. FIG. 5 is a cross-sectional view taken along the line C-C. 4 and 5 both show two units of the basic structure shown in FIG. 1 to 3 show a state where the metal film and the surface protective film, which are electrodes on the surface, are removed for the sake of explanation. In this embodiment, the semiconductor is described as silicon.
[0012]
First, the element structure will be described. First, in FIG. 1 to FIG. ⁺ Type substrate region, 2 is an n-type drain region, 3 is n ⁺ The source region 4 is a p-type gate region. Reference numeral 5 denotes a first MOS type electrode, 6 denotes a first insulating film, 8 denotes a second MOS type electrode, and 9 denotes a second insulating film. The first MOS type electrode 5 and the second MOS type electrode 8 are each made of a conductive material. In the present embodiment, the same material (for example, high concentration p) can be easily manufactured. ⁺ The case where it forms with a type | mold polysilicon) is illustrated. Further, the first insulating film 6 and the second insulating film 9 are also exemplified in the present embodiment when they can be easily manufactured and are formed of the same material (for example, silicon oxide). In the present embodiment, a structure in which the manufacturing method can be easily realized is shown as an example. However, the second MOS type electrode 8 and the second insulating film 9 are the first MOS type electrode 5 and the first insulating film. The film 6 may be made of a different material.
[0013]
A drain electrode 11 is in ohmic contact with the substrate region 1. Reference numerals 13 shown in FIGS. 2 and 5 denote source electrodes which are adjacent to the first MOS type electrode 5 with the source contact holes 15 (FIG. 4) formed in the interlayer insulating film 12 interposed therebetween. Two source regions 3 are connected simultaneously. Thus, the source electrode 13 is in ohmic contact with the first MOS type electrode 5 and all the source regions 3 isolated in an island shape. Therefore, since the first MOS type electrode 5 is fixed at the source potential, the first MOS type electrode 5 and the first insulating film 6 are collectively referred to as a “fixed potential insulating electrode” 7. 3 and 5 is a gate electrode, which is adjacent to the second MOS-type electrode 8 and sandwiches the second MOS-type electrode 8 through each gate contact hole 16 (FIG. 4) formed in the interlayer insulating film 12. Two gate regions 4 are connected simultaneously. Thereby, the gate electrode 14 is in ohmic contact with the second MOS type electrode 8 and all the gate regions 4 isolated in an island shape. Therefore, since the second MOS type electrode 8 is fixed at the gate potential, the second MOS type electrode 8 and the second insulating film 9 are collectively referred to as a “variable potential insulating electrode” 10.
[0014]
As shown in FIGS. 1 to 4, the fixed potential insulating electrode 7 and the variable potential insulating electrode 10 are alternately arranged in parallel with each other at equal intervals, and the cross-sectional structure of both is a side wall such as a letter “U”, for example. Is formed in a substantially vertical groove. The source region 3 and the gate region 4 are arranged so as not to contact each other so as to be sandwiched between the fixed potential insulating electrode 7 and the variable potential insulating electrode 10. Therefore, when two units of the basic structure shown in FIG. 4 are repeatedly arranged in a mirror image relationship on the left and right, in the present embodiment, the fixed potential insulating electrode 7 and the variable potential insulating electrode 10 have no end portions. It has become. In the present embodiment, the gate region 4 is described as being formed shallower than the fixed potential insulating electrode 7 and the variable potential insulating electrode 10, but it is formed to be equal to or deeper than those depths. It doesn't matter. 1 and 2, the drain region 2 sandwiched between the fixed potential insulating electrode 7 and the variable potential insulating electrode 10 is referred to as a channel region 17.
[0015]
Next, the operation will be described. In this embodiment, the source electrode 13 is grounded and a positive potential is applied to the drain electrode 11, and a forward operation is performed by supplying a control signal to the gate electrode 14, and the drain electrode 11 is grounded, the source electrode 13 and It has a bidirectional conduction characteristic that enables both reverse operation in which the gate electrode 14 is operated by applying a positive potential.
[0016]
First, the forward operation will be described. For example, in the state where the source electrode 13 (FIG. 2) is grounded and an appropriate positive potential is applied to the drain electrode 11, when the gate electrode 14 is grounded or a negative potential, the element maintains the cutoff state. A depletion layer is formed around the fixed potential insulating electrode 7 and the variable potential insulating electrode 10 due to the built-in potential of the first MOS type electrode 5 and the second MOS type electrode 8 due to the work function difference. If the distance between the two fixed potential insulating electrodes 7 and the variable potential insulating electrode 10 facing each other within 17 (hereinafter referred to as the channel thickness H) is sufficiently narrow, the channel region 17 has a depletion region. A sufficient potential barrier for conduction electrons is formed. In the present embodiment, the fixed potential insulating electrode 7 and the variable potential insulating electrode 10 do not have ends in each basic structure. Therefore, even if the gate region 4 is shallow, the fixed potential insulating electrode 7 and the variable potential insulating electrode 10 The electric field distribution at the bottom of the insulating electrode 10 is substantially the same. That is, even if the distance between the bottom of the fixed potential insulating electrode 7 and the variable potential insulating electrode 10 and the drain region 2 is set smaller than the conventional one, the avalanche breakdown voltage is the same as the conventional one. Therefore, in the present embodiment, the distance between the bottom of the fixed potential insulating electrode 7 and the variable potential insulating electrode 10 and the drain region 52 is equal to the distance between the bottom of the gate region 54 and the drain region 52 of the conventional structure. Equivalent pressure resistance can be obtained by setting. That is, the thickness of the drain region 2 can be reduced as compared with the conventional case.
[0017]
Next, in the conductive state, when a voltage of, for example, +0.5 V is applied to the potential of the gate electrode 14 (FIG. 3), that is, the p-type gate region 4 and the variable potential insulating electrode 10, the potential barrier of the channel region 17 is lowered. Current begins to flow. That is, minority carrier holes flow from the p-type gate region 4 into the interface of the first insulating film 6 of the fixed potential insulating electrode 7 to form an inversion layer, and the first MOS type electrode 5 to the channel region 17. In order to shield the electric field lines, the potential at the interface is increased. In addition, at the interface of the second insulating film 9 of the variable potential insulating electrode 10, the potential rises due to the application of a positive potential. Therefore, the potential barrier against conduction electrons at the interface between the first insulating film 6 and the second insulating film 9 is lowered. That is, as a result, the drain region 2 and the source region 3 become conductive. When the potential of the gate electrode 14 is further increased, the pn junction composed of the p-type gate region 4 and the surrounding n-type region is forward biased, and holes are directly injected into the drain region 2 and the channel region 17. Then, the conductivity of these n-type regions, which have been made low in impurity concentration and high resistance in order to maintain the breakdown voltage, is increased, and current flows with low resistance. At this time, in the present embodiment, since the thickness of the drain region 2 can be reduced as compared with the conventional structure, the on-resistance can be reduced. Further, since the amount of holes necessary for increasing the conductivity of the n-type region can be reduced, the current amplification factor can be improved.
[0018]
In the conventional structure, the gate region had to be deeply formed so as to cover the ends of the fixed potential insulating electrode and the variable potential insulating electrode. Therefore, the basic structure is adapted to the conduction characteristics that change depending on the thickness of the drain region. It was difficult to optimize. That is, the conventional structure requires not only a small gate region but also a basic structure design that takes into account the lateral extension of the gate region. In contrast, in the present embodiment, the depth of the gate region 4 can be freely set, so that the basic structure can be optimized in accordance with the conduction characteristics that change depending on the thickness of the drain region 2.
[0019]
Next, turn-off will be described. First, when the potential of the gate electrode 14 is changed to a negative potential in order to turn off the conductive state, holes in the drain region 2 and the channel region 17 are sequentially decreased from the vicinity of the gate region 4. At this time, the high-level injection state is canceled in the channel region 17. Since the variable potential insulating electrode 10 has a negative potential more than the fixed potential insulating electrode 7, holes in the channel region 17 form a strong inversion layer at the interface of the second insulating film 9 of the variable potential insulating electrode 10 to which a negative potential is applied. The holes in the channel region 17 are formed and flow to the gate region 4 through this. At this time, in this embodiment, since the drain region 2 is small and the amount of holes injected therein becomes small, the holes are expelled more quickly than before, and the turn-off speed is improved.
[0020]
Next, the reverse operation will be described. For example, when the drain electrode 11 is grounded and an appropriate positive potential is applied to each of the source electrode 13 and the gate electrode 14, the drain electrode 11 conducts in the opposite direction. Even in this reverse conduction state, as in the forward operation described above, holes flow from the p-type gate region 4 into the interface of the first insulating film 6 of the fixed potential insulating electrode 7 to form an inversion layer, In order to shield electric lines of force from the first MOS type electrode 5 to the channel region 17, the interface potential is raised. In addition, at the interface of the second insulating film 9 of the variable potential insulating electrode 10, the potential rises due to the application of a positive potential. Therefore, the potential barrier against conduction electrons that are majority carriers at the interface between the first insulating film 6 and the second insulating film 9 is lowered. That is, the source region 3 and the drain region 2 become conductive. Further, the pn junction composed of the p-type gate region 4 and the surrounding n-type region is also forward-biased, and the holes are directly injected into the drain region 2 and the channel region 17, so that electrons are transferred from the substrate region 1 toward the source region 3. The flow begins to flow with low resistance. Further, since the pn diodes of the p-type gate region 4 and the n-type drain region 2 are also turned on, a current flows between the gate region 4 and the drain region 2. At this time, in this embodiment, similarly to the forward conduction, the thickness of the drain region 2 can be made smaller than that of the conventional structure, so that the on-resistance during the reverse conduction can also be reduced. In addition, since the amount of holes injected into the n-type region itself can be reduced, the current amplification factor during reverse conduction can also be improved.
[0021]
Next, when ground (0 V) or a negative potential is applied to the source region 3 and the gate region 4 in order to shift from this state to the cut-off state, holes in the drain region 2 and the channel region 17 are formed as in forward conduction. Gradually decreases from the vicinity of the gate region 4 and the variable potential insulating electrode 10 becomes a negative potential from the fixed potential insulating electrode 7. A strong inversion layer is formed at the interface between the two insulating films 9 and the holes in the channel region 17 flow to the gate region 4 through this. At this time, in the present embodiment, the drain region 2 is small and the amount of holes injected into the drain region 2 is small as in the case of forward conduction. The turn-off speed at the time of reverse conduction can be improved.
[0022]
As described above, in the present embodiment, one main surface of the one-conductivity-type semiconductor substrate that is the drain region 2 has a plurality of first grooves and second grooves arranged alternately and parallel to each other. is doing. A source region 3 of the same conductivity type and a gate region 4 of the opposite conductivity type are formed on the main surface sandwiched between the first groove and the second groove so as not to contact each other. Inside the first trench, there is a fixed potential insulating electrode 7 which is insulated from the drain region 2 by the first insulating film 6 and kept at the same potential as the source region 3. Is made of a conductive material having a work function that forms a depletion region in the adjacent drain region 2 via the first insulating film 6. Inside the second trench, there is a variable potential insulating electrode 10 insulated from the drain region 2 by the second insulating film 9 and kept at the same potential as the gate region 4. Is made of a conductive material having a work function that forms a depletion region in the adjacent drain region 2 via the second insulating film 9. Further, it has a channel region 17 that is a part of the drain region 2 and is sandwiched between the fixed potential insulating electrode 7 and the variable potential insulating electrode 10. It has a plurality of basic structures including a drain region 2, a source region 3, a gate region 4, a fixed potential insulating electrode 7 and a variable potential insulating electrode 10, adjacent fixed potential insulating electrodes 7 of the basic structure, and variable The potential insulating electrodes 10 are connected to each other. In the channel region 17, a potential barrier that prevents movement of majority carriers is formed by a depletion region formed around the fixed potential insulating electrode 7 and the variable potential insulating electrode 10, and minority carriers are introduced from the gate region 4. Then, an inversion layer is formed at the interface between the first insulating film 6 and the second insulating film 9, and the electric field from the fixed potential insulating electrode 7 and the variable potential insulating electrode 10 to the drain region 2 is shielded to form the channel region 17. The channel is opened by reducing or eliminating the formed potential barrier.
[0023]
In addition, the semiconductor device includes an interlayer insulating film 12 formed so as to cover the main surface, and a source electrode 13 and a gate electrode 14 formed so as to be in contact with the interlayer insulating film 12 but not in contact with each other. The interlayer insulating film 12 is provided with two source regions 3 adjacent to each other with the fixed potential insulating electrode 7 interposed therebetween, and a source contact hole 15 for connecting the fixed potential insulating electrode 7 to the source electrode 13 at the same time. The interlayer insulating film 12 has two gate regions 4 adjacent to each other with the variable potential insulating electrode 10 interposed therebetween and a gate contact hole for connecting the variable potential insulating electrode 10 to the gate electrode 14 at the same time. Thereby, the semiconductor device according to the present invention can be easily realized.
[0024]
As described above, according to the present embodiment, the fixed potential insulating electrode 7 and the variable potential insulating electrode 10 do not have end portions, and the gate region 4 can be formed shallow. When the thickness of the drain region 2 directly below the insulating electrode 10 is made equal to the conventional one, the avalanche breakdown voltage can be improved more than before, and when the avalanche breakdown voltage equivalent to the conventional one is used, the fixed potential insulating electrode 7 In addition, since the thickness of the drain region 2 immediately below the variable potential insulating electrode 10 can be reduced, various characteristics such as on-resistance, current amplification factor, and switching speed, which are in a trade-off relationship with the avalanche breakdown voltage, are improved more than before. Can do.
[0025]
Second embodiment
Next, a second embodiment will be described with reference to FIG. FIG. 6 is a surface view corresponding to FIG. 4 and shows the outermost structure when a plurality of basic structures of the semiconductor device shown in the first embodiment are formed. In the second embodiment, in addition to the configuration of the first embodiment, an insulating electrode 20 including a third MOS type electrode 18 and a third insulating film 19 is provided. The insulating electrode 20 is formed in the vicinity of the end portions of the fixed potential insulating electrode 7 and the variable potential insulating electrode 10. It is in.
[0026]
Next, the operation will be described. When the source electrode and the gate electrode are both grounded (0 V) potential and a positive potential is applied to the drain electrode 11, electric field concentration occurs at the end of the fixed potential insulating electrode 7 or the variable potential insulating electrode 10 in the outermost basic structure. Can alleviate what happens. That is, in the second embodiment, the first MOS type electrode 5 and the second MOS type electrode 8 and the n-type drain region are interposed via the first insulating film 6 and the second insulating film 9. At the same time as the reverse bias is applied, the reverse bias is also applied between the third MOS type electrode 18 and the drain region via the third insulating film 19. Then, since the depletion layer also spreads to the drain region side from the junction between the insulating electrode 20 and the drain region, the drain electric field generated at the ends of the fixed potential insulating electrode 7 and the variable potential insulating electrode 10 formed in the vicinity of the insulating electrode 20. Can be relaxed. As described above, in the present embodiment, the third groove is provided in the vicinity of the end of the first groove and the end of the second groove, and the third groove includes the third groove. The insulating electrode 20 is insulated from the drain region by the insulating film 19, and the insulating electrode 20 reduces the electric field concentration from the drain region at the end of the fixed potential insulating electrode 7 and the end of the variable potential insulating electrode 10. is doing.
[0027]
Therefore, by using this embodiment, it is possible to suppress the avalanche breakdown voltage from being lowered at the ends of the fixed potential insulating electrode 7 and the variable potential insulating electrode 10 that are generated at the outermost part of the basic structure.
[0028]
Third embodiment
Next, a third embodiment will be described with reference to FIGS. 7 and 8 are surface views corresponding to the second embodiment of FIG. FIG. 7 shows a case where the insulating electrode 20 is connected to the variable potential insulating electrode 10. The variable potential insulating electrode 10 does not have an end even at the outermost portion, and the end of the fixed potential insulating electrode 7 surrounds the periphery. It is formed so as to be surrounded by the insulating electrode 20 and the variable potential insulating electrode 10. Further, FIG. 8 shows a case where the insulating electrode 20 is connected to the fixed potential insulating electrode 7. The fixed potential insulating electrode 7 does not have an end portion even at the outermost part, and the end portion of the variable potential insulating electrode 10 is the periphery. Is surrounded by the insulating electrode 20 and the fixed potential insulating electrode 7.
[0029]
In this way, the insulating electrode 20 is connected to either the end of the fixed potential insulating electrode 7 as shown in FIG. 8 or the end of the variable potential insulating electrode 10 as shown in FIG.
[0030]
Next, the operation will be described. Since the insulating electrode 20 is fixed to the source potential or the gate potential, the depletion layer extending from the insulating electrode 20 to the drain region side in the cutoff state is the same as the depletion layer extending from the end of the fixed potential insulating electrode 7 or the variable potential insulating electrode 10. In addition, since one electrode having the end portion is surrounded by the other electrode connected to the insulating electrode, the concentration of the drain electric field generated at the end portion of the fixed potential insulating electrode 7 or the variable potential insulating electrode 10 is reduced to the second level. This can be further relaxed than in the embodiment, and the avalanche breakdown voltage can be further suppressed from decreasing.
[0031]
Fourth embodiment
Next, a fourth embodiment will be described with reference to FIGS. 9 and 10. 9 and 10 are surface views corresponding to the second embodiment of FIG. 9 and 10 show the structures of the four corners when a plurality of basic structures of the semiconductor device shown in the first embodiment are used. In FIG. 9, the insulating electrode 20 is curved close to the fixed potential insulating electrode 7 and the ends of the variable potential insulating electrode 10 and with a predetermined curvature. Further, FIG. 10 illustrates the case where the curved insulating electrode 20 is connected to the variable potential insulating electrode 10, but the insulating electrode 20 may be connected to the fixed potential insulating electrode 7 (see FIG. 8). .
[0032]
As described above, the insulating electrode 20 does not have an end portion or a corner portion where the electric field from the drain region is concentrated. Curved at the corner of the semiconductor device .
[0033]
In this embodiment, when a plurality of semiconductor devices according to the first embodiment are arranged in a cut-off state in which both the source electrode and the gate electrode are grounded (0 V) potential and a positive potential is applied to the drain region, insulation at four corners is performed. Since the electrode 20 is close to the ends of the fixed potential insulating electrode 7 and the variable potential insulating electrode 10 and is curved with a predetermined curvature, the insulating electrode 20 does not have a three-dimensional protrusion. For this reason, since the drain electric field concerning the insulating electrode 20 can be relieved, it can suppress that the avalanche breakdown voltage in the insulating electrode 20 falls.
[0034]
The present invention has been specifically described above based on the above embodiment, but the above embodiment is merely an example, and the present invention is not limited to the above, and the scope of the present invention is not deviated. It goes without saying that various changes can be made.
[Brief description of the drawings]
FIG. 1 is a perspective view of a first embodiment of the present invention.
FIG. 2 is a sectional view of the first embodiment of the present invention.
FIG. 3 is another sectional view of the first embodiment of the present invention.
FIG. 4 is a surface view of the first embodiment of the present invention.
FIG. 5 is a side view of the first embodiment of the present invention.
FIG. 6 is a surface view of a second embodiment of the present invention.
FIG. 7 is a surface view of a third embodiment of the present invention.
FIG. 8 is a surface view of a third alternative embodiment of the present invention.
FIG. 9 is a surface view of a fourth embodiment of the present invention.
FIG. 10 is a surface view of a fourth alternative embodiment of the present invention.
[Explanation of symbols]
1 ... Board area
2 ... Drain region
3 ... Source area
4 ... Gate area
5. First MOS type electrode
6 ... 1st insulating film
7 ... Fixed potential insulated electrode
8 ... Second MOS type electrode
9: Second insulating film
10 ... Variable potential insulated electrode
11 ... Drain electrode
12 ... Interlayer insulating film
13 ... Source electrode
14 ... Gate electrode
15 ... Source contact hole
16 ... Gate contact hole
17 ... Channel region
18 ... Third MOS type electrode
19 ... Third insulating film
20 ... Insulated electrode

Claims

One main surface of a semiconductor substrate of one conductivity type that is a drain region has a plurality of first grooves and second grooves arranged alternately and parallel to each other, and the first groove and the second groove A source region of the same conductivity type and a gate region of the opposite conductivity type are formed on the main surface sandwiched between the grooves so as not to contact each other,
The first trench has a fixed potential insulating electrode insulated from the drain region by the first insulating film and kept at the same potential as the source region, and the fixed potential insulating electrode is A work function conductive material that forms a depletion region in the drain region adjacent via the first insulating film,
Inside the second trench, there is a variable potential insulating electrode insulated from the drain region by a second insulating film and kept at the same potential as the gate region, and the variable potential insulating electrode is A conductive material having a work function that forms a depletion region in the drain region adjacent via the second insulating film;
A channel region that is part of the drain region and sandwiched between the fixed potential insulating electrode and the variable potential insulating electrode ;
The drain region, the source region, the gate region, the fixed potential insulating electrode and a plurality of basic structures including the variable potential insulating electrode, the fixed potential insulating electrodes of the basic structure adjacent to each other, and The variable potential insulation electrodes are connected
In the channel region, a potential barrier that prevents movement of majority carriers by the depletion region formed around the fixed potential insulating electrode and the variable potential insulating electrode is formed,
When minority carriers are introduced from the gate region, an inversion layer is formed at the interface between the first insulating film and the second insulating film, and from the fixed potential insulating electrode and the variable potential insulating electrode to the drain region. A semiconductor device in which a channel is opened by reducing or eliminating a potential barrier formed in the channel region by shielding the electric field.

An interlayer insulating film formed so as to cover the main surface, and a source electrode and a gate electrode formed so as to be in contact with the interlayer insulating film and not in contact with each other,
In the interlayer insulating film, two source regions adjacent to each other with the fixed potential insulating electrode interposed therebetween and a source contact hole for connecting the fixed potential insulating electrode to the source electrode at the same time are formed,
Further, the interlayer insulating film has two gate regions adjacent to each other with the variable potential insulating electrode interposed therebetween and a gate contact hole for connecting the variable potential insulating electrode to the gate electrode at the same time. The semiconductor device according to claim 1.

A third groove is provided in the vicinity of the end portion of the first groove and the end portion of the second groove, and the drain region and the drain region are formed inside the third groove by a third insulating film. 2 has an insulated insulating electrode, and the insulating electrode relaxes electric field concentration from the drain region at an end portion of the fixed potential insulating electrode and an end portion of the variable potential insulating electrode. Item 3. The semiconductor device according to Item 1 or 2.

The isolated electrodes are the fixed potential insulated end or said variable potential is connected to either end of the insulated electrode, wherein the has claim 3 Symbol mounting semiconductor device of the electrode.

The semiconductor device according to claim 3 , wherein the insulating electrode is curved at a corner of the semiconductor device.