JP3588671B2 - Semiconductor device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a bipolar vertical power element.
[0002]
[Prior art]
Japanese Patent Application Laid-Open No. 6-252408 filed by the present applicant is cited as a prior art as the background of the present invention. 8 and 9 are structural diagrams of the semiconductor device cited from the above publication. It should be noted that the numbers and the names of parts in the drawings are appropriately changed and described for explanation. FIG. 8 is a perspective view illustrating the basic structure, and FIG. 9 is a sectional view of the same side as FIG. FIG. 9 shows two units of the basic structure shown in FIG.
[0003]
The number 51 in the above figure is n ⁺ Substrate region, 52 is an n-type drain region, 53 is n-type ⁺ A source region, 54 is a MOS electrode, and 55 is an insulating film. The MOS type electrode 54 has a high concentration of p ⁺ Molded polysilicon. Reference numeral 61 denotes a drain electrode, which is in ohmic contact with the substrate region 51. A source electrode 63 is in ohmic contact with the source region 53 and the MOS electrode 54. That is, the MOS electrode 54 is fixed at the source potential. Therefore, the MOS electrode 54 and the insulating film 55 are collectively referred to as a “fixed potential insulating electrode” 56. The cross-sectional structure of the fixed potential insulating electrode has a side wall formed in a substantially vertical groove like a letter "U", for example. Further, the drain region 52 sandwiched between the fixed potential insulating electrodes 56 is called a channel region 57.
[0004]
Further, a p-type gate region 58 exists in contact with the insulating film 55 and away from the source region 53. In FIG. 9, reference numeral 68 denotes an electrode in ohmic contact with the gate region 58, which is called a "gate electrode". Reference numeral 60 denotes an interlayer insulating film.
The "dashed line" in the figure indicates the presence of the fixed potential insulating electrode 56 in the depth direction of the paper as can be seen from the relationship with FIG.
[0005]
In this element, for example, the source electrode 63 is grounded (to 0 V), and the drain electrode 61 is used by giving an appropriate positive potential via a load. When the gate electrode 68 is grounded or a negative potential is applied, a depletion layer associated with the built-in potential of the MOS electrode 54 is formed around the fixed potential insulating electrode 56, and the depletion layer is formed in the channel region 57. Since the region forms a sufficient potential barrier for conduction electrons, the device is in a cutoff state. When a positive potential is applied to the gate electrode 68, the potential of the p-type gate region 58 rises, holes flow into the interface of the insulating film 55, and an inversion layer is formed. The inversion layer is p ⁺ Since the lines of electric force from the MOS-type electrode 54 to the channel region 57 are shielded, the depletion region shrinks or disappears, the channel is opened, and the channel is opened. Further, when the potential applied to the gate electrode 68 is increased, the pn junction composed of the gate region 58 and the surrounding n-type region is in a forward bias state, and holes are directly injected into the drain region 52 and the channel region 57. Since these n-type regions are formed with a low impurity concentration in order to maintain the breakdown voltage or the blocking property of the channel, the conductivity is improved when a large amount of holes are injected, and the electrons emitted from the source region 53 It moves to the substrate region 51 with high conductivity. That is, the n-type region is in a high level injection state, and the drain current flows with a low resistance.
[0006]
[Problems to be solved by the invention]
In order to switch the device from the conductive state to the cutoff state, the potential of the gate electrode 68 is changed from a positive potential to a negative (or ground) potential. In particular, the negative potential applied to the gate electrode 68 Is the gate potential at which avalanche breakdown occurs between the gate and the source when the source electrode 63 is grounded and a negative potential is applied to the gate electrode 68 (hereinafter, this is referred to as “gate / source reverse bias withstand voltage”). ), The “gate / source reverse bias withstand voltage” should be as large as possible.
In this conventional structure, when a reverse bias is applied between the gate electrode 68 and the source electrode 63, the fixed potential insulating electrode 56 fixed to the source electrode 63 is in contact with the gate region 58. The lines of electric force are dense near the insulating film 55 where the insulating electrode 56 and the gate region 58 are in contact, and when the electric field near the insulating film 55 reaches a critical electric field even if the magnitude of the reverse bias voltage is small, Avalanche surrender occurs. That is, in this conventional structure, there is a limit in improving the "gate / source reverse bias withstand voltage".
[0007]
An object of the present invention is to provide a semiconductor device having a high "gate / source reverse bias withstand voltage" by focusing on the above problems.
[0008]
[Means for Solving the Problems]
In order to achieve the above object, the present invention has a configuration as described in the claims. That is, according to the first aspect of the present invention, the semiconductor device has a source region of the same conductivity type (here, n type) in contact with one main surface of a semiconductor substrate of one conductivity type (for example, n type) which is a drain region, A first groove disposed in contact with the main surface and sandwiching the source region; Generally, two grooves are required to sandwich the source region, but they may be sandwiched by a single U-shaped groove.
[0009]
Inside the first groove, there is a fixed potential insulating electrode that is insulated from the drain region by a first insulating film and that is kept at the same potential as the source region. It is made of a conductive material (for example, p-type polysilicon) having a work function such that a depletion region is formed in the drain region adjacent via the first insulating film. And a channel region that is part of the drain region that is in contact with the source region and that is sandwiched between the fixed potential insulating electrodes. Furthermore, the semiconductor device has a gate region of the opposite conductivity type (for example, p-type) facing the main surface and not in contact with the source region. Further, in a state where the drain region and the source region are cut off, in order to reduce concentration of an electric field from the drain region at the end of the first groove, the drain region and the source region are in contact with the gate region facing the main surface. A second groove not in contact with the first groove and the source region, and inside the second groove, the drain region and the gate region are formed by a second insulating film. Electrically Insulated first No electricity very (Floating structure electrode) It has composition which has. Note that the above configuration corresponds to, for example, FIGS.
[0010]
The operation of such a configuration will be described. When a voltage near the voltage at which avalanche breakdown occurs is applied between the gate region and the source region in a reverse bias state, the potential of the first floating electrode becomes (1) the potential of the first floating electrode and the gate. And (2) the capacitance between the first floating electrode and the fixed potential insulating electrode, and (3) the capacitance between the first floating electrode and the drain region. (4) the potential of the second insulating film interface in contact with the drain region, (5) the potential of the source region, and (6) the potential of the gate region. The first floating electrode has a potential between the potential of the gate region and the potential of the source region. Then, portions where the lines of electric force become dense between the gate region and the source region are: (a) the second insulating film of the first floating electrode in contact with the gate region; and (b) the second insulating film. One floating electrode, a second insulating film facing the fixed potential insulating electrode, (c) a first insulating film, and (d) the drain region sandwiched therebetween. That is, since there are a plurality of portions where the lines of electric force are dense between the gate region and the source region, the breakdown voltage between the gate region and the source region is improved.
Further, at the time of turn-off, a strong inversion layer is formed at the interface of the first floating electrode with the second insulating film, and the mobility of minority carriers is improved, so that the switching speed is improved.
[0011]
According to the second aspect of the present invention, in the configuration of the first aspect, in the cutoff state, concentration of an electric field from the drain region at an end of the first groove and an end of the second groove. A third groove facing the main surface and not in contact with the first groove and the second groove and the source region and the gate region; A second insulating film insulated from the drain region by a third insulating film. No electricity very (Floating structure electrode) It has composition which has. This configuration corresponds to, for example, FIG. 5 described later.
[0012]
The operation of such a configuration will be described. When a reverse bias state is applied between the gate region and the source region and a voltage near a voltage at which avalanche breakdown occurs is applied, the potential of the first floating electrode and the potential of the second floating electrode become (7) (8) capacitance between the first floating electrode and the second floating electrode and (9) capacitance between the first floating electrode and the gate region and (9) capacitance between the first floating electrode and the second floating electrode. (10) the capacitance between the electrode and the fixed potential insulating electrode, and (10) the capacitance between the first floating electrode and the interface of the second insulating film in contact with the drain region. (12) the capacitance relationship between the second floating electrode and the interface of the third insulating film in contact with the drain region; (13) the potential of the third insulating film interface in contact with the drain region, (14) the potential of the source region, and (15) the potential of the gate region. In this configuration, the potential of the first floating electrode is a potential between the potential of the gate region and the potential of the second floating electrode, and the potential of the second floating electrode is the first potential. Of the floating electrode and the potential of the source region. Then, between the source region and the gate region, a portion where the lines of electric force are dense is (e) the second insulating film of the first floating electrode in contact with the gate region, and (f) the second insulating film. One floating electrode, a second insulating film facing the fixed potential insulating electrode, (g) a first insulating film, (h) the drain region interposed therebetween, and (i) the second floating electrode. A third insulating film facing the first floating electrode, (j) a second insulating film, (k) the drain region sandwiched between the third insulating film, and (l) the second floating electrode and the fixed potential insulation. The second insulating film facing the electrode, (m) the first insulating film, and (n) the drain region sandwiched therebetween, and the portion where electric lines of force are denser further increases, so that the gate region and the source Resistance between areas There is further improved.
[0013]
According to the third aspect of the present invention, Has two floating structure electrodes, a first electrode and a second electrode In the configuration, First electrode Is connected to the gate region. This configuration corresponds to, for example, FIG. 6 described later.
[0014]
The operation of such a configuration will be described. first No electricity The potential of the pole becomes the same as the potential of the gate region, No electricity Pole and said second No electricity The shape of the poles facing each other and the second No electricity Since the pole and the shape of the fixed potential insulating electrode facing each other are equal, the first No electricity Pole and said second No electricity The capacitance between the pole and the second No electricity The capacitance between the pole and the fixed potential insulating electrode is equal. That is, the second No electricity Poles and said first No electricity Distribution of electric lines of force in the region where the pole faces, No electricity The distribution of lines of electric force in the region where the pole and the fixed potential insulating electrode face each other is equalized, and the withstand voltage is improved.
[0015]
Also, in the invention according to claim 4, in the configuration of claims 1 to 4, Of the first groove and the second groove in claim 1, or the first groove, the second groove, and the third groove in claim 2 or claim 3, from the main surface direction. A structure in which grooves adjacent to each other in the longitudinal direction of the groove are arranged so that they are not aligned on the straight line in the longitudinal direction of the groove That is, the configuration is such that the ends of the two adjacent grooves do not face each other, but are arranged so as to face the drain region, respectively. This configuration corresponds to, for example, FIG. 7 described later.
[0016]
The operation of such a configuration will be described. In this structure, the facing area of the two electrodes in the vicinity of the fixed potential insulating electrode, the first floating electrode, and the second floating electrode increases, so that the capacitance between the electrodes increases. The potential of one floating electrode is not affected by the drain potential and becomes more stable.
[0017]
【The invention's effect】
According to the configuration of the first aspect, the “gate / source reverse bias withstand voltage” is improved. Further, the turn-off speed is improved.
In the configuration of claim 2, the "gate / source reverse bias withstand voltage" is further improved as compared with claim 1.
According to the configuration of the third aspect, the “gate / source reverse bias withstand voltage” is further improved as compared with the second aspect.
According to the configuration of the fourth aspect, the potentials of the first floating electrode and the second floating electrode are less likely to be affected by the potential of the drain region, and the reliability is improved.
[0018]
BEST MODE FOR CARRYING OUT THE INVENTION
(First embodiment)
1 to 4 are views showing a first embodiment of the present invention. This corresponds to claim 1. 1 is a perspective view illustrating the basic structure of the device, FIG. 2 is a cross-sectional view showing the same portion as the front surface of FIG. 1, FIG. 3 is a surface view showing the same portion as the front surface of FIG. 1, and FIG. It is the same sectional view as. FIG. 2 is a cross-sectional view taken along a line AA in the front view of FIG. 3 and perpendicular to the paper surface, and FIG. 4 is a cross-sectional view taken along a line BB in the same manner. 3 and 4 both show two units of the basic structure shown in FIG. FIGS. 1 and 3 show a state in which the metal film (the source electrode 13 and the gate electrode 18) and the surface protection film (the interlayer insulating film 60), which are the electrodes on the surface, are removed for explanation. In this embodiment, a semiconductor is described as silicon.
[0019]
First, the element structure will be described. First, in FIG. 1 to FIG. ⁺ Substrate area of the mold, 2 is n ⁻ Type drain region, 3 is n ⁺ The source region 4 is a first MOS type electrode, and the first insulating film 5 is. The first MOS type electrode 4 has a high concentration of p ⁺ Molded polysilicon. Reference numeral 11 denotes a drain electrode, which is in ohmic contact with the substrate region 1. Reference numeral 13 denotes a source electrode, which is in ohmic contact with the source region 3 and the first MOS type electrode 4. That is, the first MOS electrode 4 is fixed at the source potential. Therefore, the first MOS type electrode 4 and the first insulating film 5 are collectively referred to as “fixed potential insulating electrode” 6. As shown in FIG. 2, the cross-sectional structure of the fixed potential insulating electrode 6 is such that, for example, a side wall is formed in a substantially vertical groove like a letter "U". Although the source region 3 is drawn in contact with the first insulating film 5 in the drawing, the source region 3 may not be in contact if the source region 3 is arranged so as to be sandwiched between the fixed potential insulating electrodes 6. . Further, in FIG. 2, the drain region 2 sandwiched between the fixed potential insulating electrodes 6 is called a channel region 7. The configuration up to here is the same as that of the above-described conventional example.
[0020]
Further, in the present invention, as shown in FIGS. 1 and 4, a p-type gate region 8 exists at a position away from the source region 3. In FIG. 4, reference numeral 18 denotes an electrode in ohmic contact with the gate region 8 and is called a “gate electrode”. Then, as shown in FIGS. 1 and 3, a second MOS-type electrode 14 which is in contact with the gate region 8 but not with the source region 3 and the fixed potential insulating electrode 6 is insulated from the drain region 2. The first floating electrode 16 formed by the second insulating film 15 for forming the first floating electrode 16. The surface of the first floating electrode 16 is also insulated by the interlayer insulating film 10.
[0021]
The cross-sectional structure of the first floating electrode 16 is similar to that of the fixed potential insulating electrode 6, and the side wall is formed in a substantially vertical groove like a letter "U". The second MOS type electrode 14 is made of the same conductive material as the first MOS type electrode 4, that is, for example, a high-concentration p-type. ⁺ Type polysilicon may be used. Further, the second insulating film 15 may be the same as the first insulating film 5. Also, the “dashed line” in FIG. 4 indicates the presence of the fixed potential insulating electrode 6 and the first floating electrode 16 in the depth direction of the paper as can be seen from the relationship with FIG. 1 and 4, the ends of the fixed potential insulating electrode 6 and the first floating electrode 16 are drawn at right angles, but the shape of the end may be polygonal or curved. .
[0022]
The potential of the first floating electrode 16 is determined by the potential distribution around the first floating electrode 16 and the magnitude of the capacitance with the periphery. That is, for example, the potential of the interface of the second insulating film 15 in contact with the gate region 8 is V1, the potential of the fixed potential insulating electrode 6 is V2, and the second insulating film in contact with the drain region 2 and facing the drain electrode 11. The potential at the interface of the film 15 is V3, the capacitance between the first floating electrode 16 and the interface of the second insulating film 15 in contact with the gate region 8 is C1, the first floating electrode 16 and the fixed potential insulating electrode 6 When the capacitance between the first floating electrode 16 and the interface of the second insulating film 15 in contact with the drain region 2 is C3, the capacitance between the first floating electrode 16 and the drain field 2 is C3. Is the potential of the floating electrode 16 of
C1 × (V−V1) + C2 × (V−V2) + C3 × (V−V3) = 0 (Equation 1)
Is a potential to satisfy the relational expression.
[0023]
Next, the operation will be described.
In this element, for example, the source electrode 13 is grounded (0 V), and the drain electrode 11 is used by applying an appropriate positive potential via a load. First, when a negative potential is applied to the gate electrode 18, the element is in a cutoff state. Referring to FIG. 2, a depletion layer is formed around the fixed potential insulating electrode 6 due to the built-in potential of the first MOS type electrode 4. If the distance between the potential insulating electrodes 6 (hereinafter referred to as “channel thickness H”) is sufficiently small, a sufficient potential barrier for conduction electrons is formed in the channel region 7 by the depletion region. For example, the thickness of the first insulating film 5 is 100 nm or less, and the impurity concentration of the channel region 7 is 1 × 10 ¹⁴ cm￣ ³ Hereinafter, if the “channel thickness H” is set to 2 μm or less, it is possible to form a sufficient potential barrier for preventing conduction electrons in the source region 3 from moving to the drain region 2 through the channel region 7. The distance from the source region 3 to the bottom of the fixed potential insulating electrode 6 (hereinafter referred to as “channel length L”) so that the potential barrier does not decrease due to the influence of the electric field from the drain region 2. Is set to be 2 to 3 times or more of the channel thickness H.
[0024]
In the present embodiment, further, a voltage at which avalanche breakdown occurs between the gate and the source when a reverse bias is applied between the gate electrode 18 and the source electrode 13 (this is referred to as “gate / source reverse bias withstand voltage”) In order to improve the drain potential as compared with the conventional structure, under the condition that a voltage close to the “gate / source reverse bias withstand voltage” is applied between the gate electrode 18 and the source electrode 13, Regardless, at least the potential of the first floating electrode 16 is set to be between the gate potential and the source potential. That is, under the condition that the source electrode 13 is grounded, the drain electric field affects the first floating electrode 16 so that the potential of the first floating electrode 16 does not become a positive potential. The capacitance C3 between the insulating film 15 and the interface is set.
[0025]
By the way, in the present embodiment, the drain region 2 is made to have high resistance, and in the cut-off state, a potential distribution is generated in the depletion layer extending to the drain region 2. The potential V3 at the interface of the second insulating film 15 is smaller than the potential applied to the drain electrode 11. For example, suppose that the second insulating film 15 is formed of an oxide film, and its dielectric constant is ε. _OX , The electric field spreading to the second insulating film 15 is represented by E _OX And the dielectric constant of the drain region 2 at the interface of the first floating electrode 16 is ε _SI The electric field spreading to the drain region 2 at the interface of the first floating electrode 16 is represented by E _SI Then, the following equation (Equation 2) is established from the electric flux continuity equation.
[0026]
ε _OX × E _OX = Ε _SI × E _SI ... (Equation 2)
For example, if the impurity concentration of the drain region 2 is 1 × 10 ¹⁴ cm￣ ³ When the gate region 8 and the source region 3 are grounded and a predetermined voltage is applied to the drain electrode 11 and avalanche breakdown occurs at the junction surface between the drain region 2 and the gate region 8, the electric field at the portion where the avalanche breakdown occurs The strength is about 2.4 × 10 ⁵ V / cm. At this time, for example, when the depth of the first floating electrode 16 is set to be equal to the depth at which the avalanche breakdown has occurred, the electric field spreading to the drain region 2 at the interface of the first floating electrode 16 in the equation (2) E _SI Is about 2.4 × 10 avalanche electric field ⁵ V / cm, the electric field E spread over the second insulating film 15 _OX Is approximately 7.4 × 10 ⁵ V / cm. Further, assuming that the thickness of the second insulating film 15 is, for example, 1000 ° and the potential of the second MOS type electrode 14 is 0 V, the potential of the drain region 2 at the interface of the first floating electrode 16 is at most 7 It becomes about 4V.
[0027]
From this, for example, the potential V1 at the interface of the second insulating film 15 in contact with the gate region 8 is about -5 V, the potential V2 of the fixed potential insulating electrode 6 grounded is about 0 V, and the drain electrode 11 Assuming that the potential V3 at the interface of the second insulating film 15 facing the surface is about 8 V, from the equation (1)
(C1 + C2 + C3) × V = 8 × C3-5 × C1
It becomes. That is, in the case where the potential V1 at the interface of the second insulating film 15 in contact with the gate region 8 is set to about −5 V, the first floating is performed if the capacitance C1 is at least 1.6 times the capacitance C3 or more. The potential of the electrode 16 becomes a negative potential and becomes a potential between the gate potential and the source potential. That is, under the condition that the fixed potential insulating electrode 6 is grounded,
C1> (C3 × V3) / V1
What is necessary is just to design so that it may become C1 and C3 which satisfy | fill.
[0028]
By optimally designing the structure of the first floating electrode 16, it is easy to change the ratio of the capacitance to each region. For example, if the thickness of the second insulating film 15 of the first floating electrode 16 is uniform on the side wall and the bottom surface, the first floating electrode 16 and the interface of the second insulating film 15 in contact with the gate region 8 can be formed. The ratio between the capacitance C1 between the first floating electrode 16 and the capacitance C3 between the interface of the second insulating film 15 in contact with the drain region 2 and the magnitude of the capacitance C3 between the first floating electrode 16 and the drain region 2 is given by The ratio of the area of the bottom surface of the first floating electrode 16 in contact with the drain region 2 to the surface area of the first floating electrode 16 in contact with the gate region 8 is substantially equal. As described above, under the condition that the reverse bias voltage is applied between the gate and the source, under the condition that the potential of the first floating electrode 16 becomes a potential between the gate potential and the source potential, the gate region 8 and the source region 3 Between the electric field lines caused by the potential difference between the gate region 8 and the first floating electrode 16 and the electric potential lines between the fixed potential insulating electrode 6 connected to the first floating electrode 16 and the source region. It can be broadly divided into the lines of electric force caused. In the former case, the lines of electric force of the second insulating film 15 where the gate region 8 and the first floating electrode 16 are in contact with each other become dense. Regarding the latter, of the region where the first floating electrode 16 and the fixed potential insulating electrode 6 face each other, the second insulating film 15, the first insulating film 5, and the drain region 2 sandwiched between the two insulating films are formed. The lines of electric force become dense. As described above, in this embodiment, even when a reverse bias is applied between the gate and the source, there are a plurality of portions where the lines of electric force are dense without being concentrated on a part. That is, since a reverse bias voltage can be applied between the gate and the source until some portion of the region where the electric flux lines are dense reaches the critical electric field, an element having a high “gate / source reverse bias withstand voltage” can be used. can get.
[0029]
Next, in the conductive state, when a positive potential of, for example, +0.5 V is applied as the potential of the gate electrode 18, that is, the potential of the p-type gate region 8, holes are conveyed from the p-type gate region 8 to the The inversion layer is formed by flowing into the interface of the one insulating film 5 to block the lines of electric force from the first MOS type electrode 4 forming the potential barrier to the channel region 7, and the conduction electrons in the channel region 7 are blocked. Lower the potential barrier to At this time, since the first floating electrode 16 is always at a positive potential, the potential barrier at the interface of the second insulating film 15 has disappeared, and there is no difference from the operation in the conventional structure. That is, the drain region 2 and the source region 3 are brought into conduction. When the potential of the gate electrode 18 is further increased, the pn junction formed by the p-type gate region 8 and the surrounding n-type region is forward-biased, and holes are directly injected into the drain region 2 and the channel region 7. Then, the n-type region, which has been formed to have a low impurity concentration and a high resistance in order to maintain the withstand voltage of the element, has an increased conductivity, and a current flows with a low resistance.
[0030]
Next, turn-off will be described. When a negative potential is applied to the gate electrode 18 to turn off the conductive element, excess holes in the drain region 2 and the channel region 7 begin to flow into the p-type gate region 8. Eventually, the excess holes in the channel region 7 disappear, and the potential barrier for electrons is restored. At this time, the potential V of the first floating electrode 16 becomes a negative potential as in the cutoff state. That is, since a strong inversion layer is formed at the interface between the first floating electrode 16 and the second insulating film 15 and the mobility of minority carriers is improved, the switching speed is improved.
[0031]
(Second embodiment)
FIG. 5 is a diagram showing a second embodiment. This is a front view of the element corresponding to FIG. 3, and the same numbers in the figure indicate the same elements. As shown in FIG. 5, a second floating electrode 26 exists between the fixed potential insulating electrode 6 and the first floating electrode 16. The second floating electrode 26 includes a third MOS type electrode 24 and a third insulating film 25, and has basically the same structure as the fixed potential insulating electrode 6 and the first floating electrode 16. However, FIG. 5 illustrates a case where the surface shape is T-shaped.
[0032]
When the source electrode 13 is grounded and a negative potential is applied to the gate electrode 18 so that the gate region 8 and the source region 3 are in a reverse bias state, the potential of the first floating electrode 16 and the second floating electrode The potential of 26 is the potential of the interface of the second insulating film 15 in contact with the gate region 8, the potential of the fixed potential insulating electrode 6, the potential of the interface of the second insulating film 15 in contact with the drain region 2, and the potential of the drain region. 2, the potential at the interface of the third insulating film 25 in contact with the second floating electrode 16, the capacitance between the first floating electrode 16 and the gate region 8, and the potential between the first floating electrode 16 and the second floating electrode 26. , The capacitance between the second floating electrode 26 and the fixed potential insulating electrode 6, and the second insulating film 15 in contact with the drain region 2 and facing the drain electrode 11. Capacitance and the capacitance of the third insulating film 25 that faces the drain electrode 11, a naturally determined potential from the relationship. Then, each potential of the first floating electrode and the second floating electrode is
At least the capacitance between the first floating electrode 16 and the gate region 8 is set to the drain region so that the relationship of source potential <potential of the second floating electrode 26 <potential of the first floating electrode 16 <gate potential is satisfied. 2 and larger than the capacitance of the second insulating film 15 facing the drain electrode 11, and the capacitance between the second floating electrode 26 and the first floating electrode 16 is The third insulating film 25 facing the drain electrode 11 has a structure larger than the capacitance of the third insulating film 25.
[0033]
As a result, the portion where the lines of electric force between the gate region 8 and the source region 3 become denser is the portion where the second insulating film 15 of the first floating electrode 16 in contact with the gate region 8 and the second floating electrode 26 The third insulating film 25 facing the first floating electrode 16, the second insulating film 15, and the drain region 2 interposed therebetween, and the second insulating film facing the first floating electrode 16 and the fixed potential insulating electrode 6. The insulating film 15 and the first insulating film 5 and the drain region 2 interposed therebetween are formed. That is, the number of places where the lines of electric force are denser between the gate region 8 and the source region 3 is further increased as compared with the first embodiment, so that the “gate / source reverse bias breakdown voltage” is further improved.
[0034]
By the way, in FIG. 5, the shape of the second floating electrode 26 is T-shaped, but by doing so, the capacitance between the first floating electrode and the second floating electrode is increased. effective.
[0035]
Next, FIG. 6 is a diagram showing a third embodiment. This is a front view of the device corresponding to FIG. 5, and the same reference numerals in the drawing indicate the same elements. In FIG. 6, the first floating electrode 16 is connected to the gate electrode 18 (not shown in FIG. 6, but present above the gate region 8), and the potential of the first floating electrode 16 is the same as the gate potential. Potential.
[0036]
With this structure, the source electrode 13 is grounded and a negative potential is applied to the gate electrode 18 so that the gate region 8 and the source region 3 are in a reverse bias state, as in the second embodiment. The portion where the lines of electric force between the gate and the source are dense is sandwiched between the third insulating film 25 and the second insulating film 15 where the second floating electrode 26 and the first floating electrode 16 face each other. The drain region 2, the first floating electrode 16, and the fixed potential insulating electrode 6 face the second insulating film 15, the first insulating film 5, and the drain region 2 sandwiched therebetween. At this time, when the shape of the region where the second floating electrode 26 and the first floating electrode 16 face and the shape of the region where the first floating electrode 16 and the fixed potential insulating electrode 6 face are the same, the respective capacitances are Become equal. That is, the electric field distribution in the region where the second floating electrode 26 and the first floating electrode 16 face each other is almost equal to the electric field distribution in the region where the first floating electrode 16 and the fixed potential insulating electrode 6 face each other. / Reverse bias withstand voltage between sources ”is further improved.
[0037]
Next, FIG. 7 is a diagram showing a fourth embodiment. This is a surface view of the device corresponding to FIG. 6, and the same reference numerals in the drawing indicate the same elements. In the fourth embodiment, the first floating electrode 16 is not arranged on the same straight line as the fixed potential insulating electrode 6 and faces the channel region 7 with respect to the first embodiment. Structure.
[0038]
With such a structure, the facing area between the first floating electrode 16 and the fixed potential insulating electrode 6 can be increased up to √2 times at the maximum. The capacitance between them can be increased up to √2 times at the maximum. This makes the potential of the first floating electrode more stable without being affected by the drain potential.
[Brief description of the drawings]
FIG. 1 is a perspective view of a first embodiment of the present invention.
FIG. 2 is a cross-sectional view of the first embodiment of the present invention.
FIG. 3 is a sectional view showing a surface structure according to the first embodiment of the present invention.
FIG. 4 is a sectional view of the first embodiment of the present invention viewed from another angle.
FIG. 5 is a front view of the second embodiment of the present invention.
FIG. 6 is a front view of a third embodiment of the present invention.
FIG. 7 is a front view of a fourth embodiment of the present invention.
FIG. 8 is a perspective view of a conventional example of the present invention.
FIG. 9 is a sectional view of a conventional example of the present invention.
[Explanation of symbols]
1: substrate area 2: drain area
3. Source region 4. First MOS type electrode
5: First insulating film 6: Fixed potential insulating electrode
7 channel region 8 gate region
10 interlayer insulating film 11 drain electrode
13: source electrode 14: second MOS type electrode
15: second insulating film 16: first floating electrode
18 ... gate electrode 24 ... third MOS type electrode
25 ... third insulating film 26 ... second floating electrode
51 ... n ⁺ Substrate region 52... N-type drain region
53 ... n ⁺ Type source region 54 ... MOS type electrode
55: insulating film 56: fixed potential insulating electrode
57: channel region 58: p-type gate region
60: interlayer insulating film 61: drain electrode
63: Source electrode 68: Gate electrode
H: Channel thickness L: Channel length

Claims (4)

Having a source region of the same conductivity type in contact with one main surface of a semiconductor substrate of one conductivity type which is a drain region,
Having a first groove arranged in contact with the main surface to sandwich the source region,
Inside the first groove, a fixed potential insulating electrode that is insulated from the drain region by a first insulating film and that is kept at the same potential as the source region,
The fixed potential insulating electrode is made of a conductive material having a work function such as forming a depletion region in the drain region adjacent to the drain region via the first insulating film,
A part of the drain region in contact with the source region, having a channel region sandwiched by the fixed potential insulating electrode,
Facing the main surface, not having contact with the source region, having a gate region of the opposite conductivity type,
Further, in a state where the drain region and the source region are cut off, in order to reduce concentration of an electric field from the drain region at an end of the first groove, the drain region and the source region are in contact with the gate region facing the main surface. A second groove that is not in contact with the first groove and the source region, and is electrically connected to the drain region and the gate region by a second insulating film inside the second groove. having a first electrodes that are insulated,
A semiconductor device characterized by the above-mentioned. In the cutoff state, in order to reduce the concentration of the electric field from the drain region at the end of the first groove and the end of the second groove, facing the main surface, the first groove and the A third groove that does not contact the second groove and the source region and the gate region, and is electrically insulated from the drain region by a third insulating film inside the third groove; having a second electrodes,
The semiconductor device according to claim 1, wherein: Having a source region of the same conductivity type in contact with one main surface of a semiconductor substrate of one conductivity type which is a drain region,
Having a first groove arranged in contact with the main surface to sandwich the source region,
Inside the first groove, a fixed potential insulating electrode that is insulated from the drain region by a first insulating film and that is kept at the same potential as the source region,
The fixed potential insulating electrode is made of a conductive material having a work function such as forming a depletion region in the drain region adjacent to the drain region via the first insulating film,
A part of the drain region in contact with the source region, having a channel region sandwiched by the fixed potential insulating electrode,
Facing the main surface, not having contact with the source region, having a gate region of the opposite conductivity type,
Further, in a state where the drain region and the source region are cut off, in order to reduce concentration of an electric field from the drain region at an end of the first groove, the drain region and the source region are in contact with the gate region facing the main surface. A second groove that is not in contact with the first groove and the source region, and is electrically connected to the drain region and the gate region by a second insulating film inside the second groove. Having an insulated first electrode;
In the cutoff state, in order to reduce the concentration of the electric field from the drain region at the end of the first groove and the end of the second groove, facing the main surface, the first groove and the A third groove that does not contact the second groove and the source region and the gate region, and is electrically insulated from the drain region by a third insulating film inside the third groove; Having a second electrode,
And semi-conductor device you characterized in that said first electrode is connected to the gate region. Among the first grooves and the second grooves or the first grooves definitive to claim 2 or claim 3 and wherein the second groove and the third groove, in claim 1, wherein the main surface direction A semiconductor device, wherein grooves adjacent to each other in the longitudinal direction of the groove as viewed from above are arranged so as not to be aligned on a straight line in the longitudinal direction of the groove .

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